From nobody Sun Feb 8 06:54:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CCA8C41513 for ; Sun, 23 Jul 2023 16:24:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229766AbjGWQYS (ORCPT ); Sun, 23 Jul 2023 12:24:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229537AbjGWQYL (ORCPT ); Sun, 23 Jul 2023 12:24:11 -0400 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FE9CE7F; Sun, 23 Jul 2023 09:23:45 -0700 (PDT) Received: by mail-pg1-x52d.google.com with SMTP id 41be03b00d2f7-53fa455cd94so1848120a12.2; Sun, 23 Jul 2023 09:23:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1690129418; x=1690734218; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nC80tf2Fqm9NV1HkrgmsaoEnP1GJqadflAYCzRO4B1o=; b=ocjCaFiKtIzplKvPtoFuX6XwXSSF7vAO3+JLcljBsiqsRF941PjtOQYeAcUw38T3p4 ymth6n3JivTbjphSrZY7Ld/pQLahaiRI0jW2wAlGPW4yAr/AFsnuD+uKSoPCmCrtmYLd HT4kMHJj+TZxvEteuUfdf2rJXJ2VIL+CwdNQYri5KXIHndzS4wwAC/Zvl9xPZwlBD+GW bMqWYYm/yxS7VuB8u2yctHWRizsJM/4QVlhf5DoXngtocWGWNLjVwwgeFO0VAc8RDfku wLkCAmMpvKiHc5eR4KaqJsyDXI/6dgpg8Yl001uOZaUTVhyHwQIOCpt4vXU0LalgyM5j ke9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690129418; x=1690734218; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nC80tf2Fqm9NV1HkrgmsaoEnP1GJqadflAYCzRO4B1o=; b=GskJGMh/4se3MBUP0Uwz3BdkNqHM6fbjk0sWS8WolFKnV1LEnFKNntCFryVthi3Uaw NbYiPDp/5OLfhOHX0YWVZf1hs64Z71w6sgJD4VtAzHvg1NuMX71zw2u6vOIq1yKon893 NuEkrKuxfMIaKV/kzuCQjL8+bEt+V8fLDlitjfg01H2L+ZOS+b/Xqcn8KjF4K/PXG4fQ +FcdDspVu0ByN8k9MNGAcgr2W7VIEIIbNvkiW14I0yj72hzFf0wqOv6jE4hGVsqV03Q0 q6LLkViCc9hnzjcXm58pn4vTxHkahNMuMgnsnXcHcDez2J/E3/QHouMGT3UHi0UEnldI fVpQ== X-Gm-Message-State: ABy/qLZ4oeqKwMtDi3/DfZRIfXO0KO6p8iVCIJCJ2tt7siHFr/6RSO6a rnWQYM1c+KdaBQkWFTdNuhPrrhyqQps0eBWg X-Google-Smtp-Source: APBJJlEsvD9LPSoZWZiXuYzYb60vSPCNoY0ctpEPAFsnrJFO54xpYFLgT6dM3ZSCq7T0LpEK2WkM3A== X-Received: by 2002:a17:90a:8a13:b0:263:661e:e0dc with SMTP id w19-20020a17090a8a1300b00263661ee0dcmr5930107pjn.25.1690129418604; Sun, 23 Jul 2023 09:23:38 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.245.199]) by smtp.gmail.com with ESMTPSA id u3-20020a17090aae8300b00265a7145fe5sm6883787pjq.41.2023.07.23.09.23.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Jul 2023 09:23:38 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH v5 01/13] clk: hisilicon: Add helper functions for platform driver Date: Mon, 24 Jul 2023 00:22:26 +0800 Message-Id: <20230723162245.35033-2-mmyangfl@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230723162245.35033-1-mmyangfl@gmail.com> References: <20230723162245.35033-1-mmyangfl@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Helper functions extract common operations on platform drivers. During migration to devm APIs, (virtual) fixed clocks were found hard on devm APIs, since they often depended by crucial peripherals, thus require early initialization before device probing, and cannot use devm APIs. One solution to this problem is to add a "fixed-clock" node to device tree, independent to clock device, and make those peripherals depend on that. However, there is also some devices that do use fixed clocks provided by drivers, for example clk-hi3660.c . To simplify codes, we migrate clocks of other types to devm APIs, while keep fixed clocks self-managed, alongside with struct hisi_clock_data, and remove devm-managed hisi_clock_data. hisi_clk_alloc() will be removed in the following patch. Signed-off-by: David Yang --- drivers/clk/hisilicon/clk.c | 157 ++++++++++++++++++++++++++++++++++ drivers/clk/hisilicon/clk.h | 46 +++++++++- drivers/clk/hisilicon/crg.h | 5 ++ drivers/clk/hisilicon/reset.c | 42 +++++++++ 4 files changed, 248 insertions(+), 2 deletions(-) diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c index 54d9fdc93599..aa8908714cd0 100644 --- a/drivers/clk/hisilicon/clk.c +++ b/drivers/clk/hisilicon/clk.c @@ -88,6 +88,25 @@ struct hisi_clock_data *hisi_clk_init(struct device_node= *np, } EXPORT_SYMBOL_GPL(hisi_clk_init); =20 +void hisi_clk_free(struct device_node *np, struct hisi_clock_data *data) +{ + if (data->clks) { + if (data->clks->fixed_rate_clks_num) + hisi_clk_unregister_fixed_rate(data->clks->fixed_rate_clks, + data->clks->fixed_rate_clks_num, + data); + if (data->clks->fixed_factor_clks_num) + hisi_clk_unregister_fixed_factor(data->clks->fixed_factor_clks, + data->clks->fixed_factor_clks_num, + data); + } + + of_clk_del_provider(np); + kfree(data->clk_data.clks); + kfree(data); +} +EXPORT_SYMBOL_GPL(hisi_clk_free); + int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks, int nums, struct hisi_clock_data *data) { @@ -341,3 +360,141 @@ void __init hi6220_clk_register_divider(const struct = hi6220_divider_clock *clks, data->clk_data.clks[clks[i].id] =3D clk; } } + +static size_t hisi_clocks_get_nr(const struct hisi_clocks *clks) +{ + if (clks->nr) + return clks->nr; + + return clks->fixed_rate_clks_num + clks->fixed_factor_clks_num + + clks->mux_clks_num + clks->phase_clks_num + + clks->divider_clks_num + clks->gate_clks_num + + clks->gate_sep_clks_num + clks->customized_clks_num; +} + +int hisi_clk_early_init(struct device_node *np, const struct hisi_clocks *= clks) +{ + struct hisi_clock_data *data; + int ret; + + data =3D hisi_clk_init(np, hisi_clocks_get_nr(clks)); + if (!data) + return -ENOMEM; + data->clks =3D clks; + + ret =3D hisi_clk_register_fixed_rate(clks->fixed_rate_clks, + clks->fixed_rate_clks_num, data); + if (ret) + goto err; + + ret =3D hisi_clk_register_fixed_factor(clks->fixed_factor_clks, + clks->fixed_factor_clks_num, data); + if (ret) + goto err; + + np->data =3D data; + return 0; + +err: + hisi_clk_free(np, data); + return ret; +} +EXPORT_SYMBOL_GPL(hisi_clk_early_init); + +static int hisi_clk_register(struct device *dev, const struct hisi_clocks = *clks, + struct hisi_clock_data *data) +{ + int ret; + + if (clks->mux_clks_num) { + ret =3D hisi_clk_register_mux(clks->mux_clks, + clks->mux_clks_num, data); + if (ret) + return ret; + } + + if (clks->phase_clks_num) { + ret =3D hisi_clk_register_phase(dev, clks->phase_clks, + clks->phase_clks_num, data); + if (ret) + return ret; + } + + if (clks->divider_clks_num) { + ret =3D hisi_clk_register_divider(clks->divider_clks, + clks->divider_clks_num, data); + if (ret) + return ret; + } + + if (clks->gate_clks_num) { + ret =3D hisi_clk_register_gate(clks->gate_clks, + clks->gate_clks_num, data); + if (ret) + return ret; + } + + if (clks->gate_sep_clks_num) { + hisi_clk_register_gate_sep(clks->gate_sep_clks, + clks->gate_sep_clks_num, data); + } + + if (clks->clk_register_customized && clks->customized_clks_num) { + ret =3D clks->clk_register_customized(dev, clks->customized_clks, + clks->customized_clks_num, data); + if (ret) + return ret; + } + + return 0; +} + +int hisi_clk_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + const struct hisi_clocks *clks; + struct hisi_clock_data *data; + int ret; + + clks =3D of_device_get_match_data(dev); + if (!clks) + return -ENOENT; + + if (!np->data) { + ret =3D hisi_clk_early_init(np, clks); + if (ret) + return ret; + } + + data =3D np->data; + np->data =3D NULL; + + if (clks->prologue) { + ret =3D clks->prologue(dev, data); + if (ret) + goto err; + } + + ret =3D hisi_clk_register(dev, clks, data); + if (ret) + goto err; + + platform_set_drvdata(pdev, data); + return 0; + +err: + hisi_clk_free(np, data); + return ret; +} +EXPORT_SYMBOL_GPL(hisi_clk_probe); + +void hisi_clk_remove(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + struct hisi_clock_data *data =3D platform_get_drvdata(pdev); + + hisi_clk_free(np, data); +} +EXPORT_SYMBOL_GPL(hisi_clk_remove); diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index 7a9b42e1b027..87b17e9b79a3 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h @@ -17,10 +17,12 @@ #include =20 struct platform_device; +struct hisi_clocks; =20 struct hisi_clock_data { - struct clk_onecell_data clk_data; - void __iomem *base; + struct clk_onecell_data clk_data; + void __iomem *base; + const struct hisi_clocks *clks; }; =20 struct hisi_fixed_rate_clock { @@ -103,6 +105,39 @@ struct hisi_gate_clock { const char *alias; }; =20 +struct hisi_clocks { + /* if 0, sum all *_num */ + size_t nr; + + int (*prologue)(struct device *dev, struct hisi_clock_data *data); + + const struct hisi_fixed_rate_clock *fixed_rate_clks; + size_t fixed_rate_clks_num; + + const struct hisi_fixed_factor_clock *fixed_factor_clks; + size_t fixed_factor_clks_num; + + const struct hisi_mux_clock *mux_clks; + size_t mux_clks_num; + + const struct hisi_phase_clock *phase_clks; + size_t phase_clks_num; + + const struct hisi_divider_clock *divider_clks; + size_t divider_clks_num; + + const struct hisi_gate_clock *gate_clks; + size_t gate_clks_num; + + const struct hisi_gate_clock *gate_sep_clks; + size_t gate_sep_clks_num; + + const void *customized_clks; + size_t customized_clks_num; + int (*clk_register_customized)(struct device *dev, const void *clks, + size_t num, struct hisi_clock_data *data); +}; + struct clk *hisi_register_clkgate_sep(struct device *, const char *, const char *, unsigned long, void __iomem *, u8, @@ -113,6 +148,7 @@ struct clk *hi6220_register_clkdiv(struct device *dev, = const char *name, =20 struct hisi_clock_data *hisi_clk_alloc(struct platform_device *, int); struct hisi_clock_data *hisi_clk_init(struct device_node *, int); +void hisi_clk_free(struct device_node *np, struct hisi_clock_data *data); int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *, int, struct hisi_clock_data *); int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *, @@ -154,4 +190,10 @@ hisi_clk_unregister(mux) hisi_clk_unregister(divider) hisi_clk_unregister(gate) =20 +/* helper functions for platform driver */ + +int hisi_clk_early_init(struct device_node *np, const struct hisi_clocks *= clks); +int hisi_clk_probe(struct platform_device *pdev); +void hisi_clk_remove(struct platform_device *pdev); + #endif /* __HISI_CLK_H */ diff --git a/drivers/clk/hisilicon/crg.h b/drivers/clk/hisilicon/crg.h index 803f6ba6d7a2..bd8e76b1f6d7 100644 --- a/drivers/clk/hisilicon/crg.h +++ b/drivers/clk/hisilicon/crg.h @@ -22,4 +22,9 @@ struct hisi_crg_dev { const struct hisi_crg_funcs *funcs; }; =20 +/* helper functions for platform driver */ + +int hisi_crg_probe(struct platform_device *pdev); +void hisi_crg_remove(struct platform_device *pdev); + #endif /* __HISI_CRG_H */ diff --git a/drivers/clk/hisilicon/reset.c b/drivers/clk/hisilicon/reset.c index 93cee17db8b1..c7d4c9ea7183 100644 --- a/drivers/clk/hisilicon/reset.c +++ b/drivers/clk/hisilicon/reset.c @@ -6,11 +6,15 @@ */ =20 #include +#include #include #include #include #include #include + +#include "clk.h" +#include "crg.h" #include "reset.h" =20 #define HISI_RESET_BIT_MASK 0x1f @@ -116,3 +120,41 @@ void hisi_reset_exit(struct hisi_reset_controller *rst= c) reset_controller_unregister(&rstc->rcdev); } EXPORT_SYMBOL_GPL(hisi_reset_exit); + +int hisi_crg_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct hisi_crg_dev *crg; + int ret; + + crg =3D devm_kmalloc(dev, sizeof(*crg), GFP_KERNEL); + if (!crg) + return -ENOMEM; + + ret =3D hisi_clk_probe(pdev); + if (ret) + return ret; + + crg->rstc =3D hisi_reset_init(pdev); + if (!crg->rstc) { + ret =3D -ENOMEM; + goto err; + } + + platform_set_drvdata(pdev, crg); + return 0; + +err: + hisi_clk_remove(pdev); + return ret; +} +EXPORT_SYMBOL_GPL(hisi_crg_probe); + +void hisi_crg_remove(struct platform_device *pdev) +{ + struct hisi_crg_dev *crg =3D platform_get_drvdata(pdev); + + hisi_reset_exit(crg->rstc); + hisi_clk_remove(pdev); +} +EXPORT_SYMBOL_GPL(hisi_crg_remove); --=20 2.40.1