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[83.9.31.203]) by smtp.gmail.com with ESMTPSA id u1-20020ac24c21000000b004fb881e5c23sm2168977lfq.47.2023.07.24.04.39.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jul 2023 04:40:00 -0700 (PDT) From: Konrad Dybcio Date: Mon, 24 Jul 2023 13:39:57 +0200 Subject: [PATCH v2 2/3] pinctrl: qcom: Introduce SM6115 LPI pinctrl driver MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230722-topic-6115_lpasstlmm-v2-2-d4883831a858@linaro.org> References: <20230722-topic-6115_lpasstlmm-v2-0-d4883831a858@linaro.org> In-Reply-To: <20230722-topic-6115_lpasstlmm-v2-0-d4883831a858@linaro.org> To: Andy Gross , Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Catalin Marinas , Will Deacon Cc: Marijn Suijten , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Konrad Dybcio , Krzysztof Kozlowski X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1690198796; l=8504; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Zw8UvjQG3+97GKJdeN+OeSPueUgh+BdXUwb4Ji0YFKg=; b=TNb0hLM5i6dmYFqxva5Xqk6btzWxppIIS76cys2/elCuMeYugzKhdbYVCYlQvqcmj/Me6/ZOC Kejr/X/N3NkCsdxw1kIQ+NhyRvpUb/iekNkxNPQvUTqU+se6OpnzD6m X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for the pin controller block on SM6115's Low Power Island. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- drivers/pinctrl/qcom/Kconfig | 9 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c | 175 ++++++++++++++++++++= ++++ 3 files changed, 185 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 634c75336983..c6ef38032c05 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -68,6 +68,15 @@ config PINCTRL_SC7280_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platfo= rm. =20 +config PINCTRL_SM6115_LPASS_LPI + tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller drive= r" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SM6115 platfo= rm. + config PINCTRL_SM8250_LPASS_LPI tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller drive= r" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 426ddbf35f32..d1179d8b2c42 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_PINCTRL_SDX55) +=3D pinctrl-sdx55.o obj-$(CONFIG_PINCTRL_SDX65) +=3D pinctrl-sdx65.o obj-$(CONFIG_PINCTRL_SDX75) +=3D pinctrl-sdx75.o obj-$(CONFIG_PINCTRL_SM6115) +=3D pinctrl-sm6115.o +obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) +=3D pinctrl-sm6115-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM6125) +=3D pinctrl-sm6125.o obj-$(CONFIG_PINCTRL_SM6350) +=3D pinctrl-sm6350.o obj-$(CONFIG_PINCTRL_SM6375) +=3D pinctrl-sm6375.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm6115-lpass-lpi.c new file mode 100644 index 000000000000..2b09bf171a2c --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, 2023 Linaro Ltd. + */ + +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic01_clk, + LPI_MUX_dmic01_data, + LPI_MUX_dmic23_clk, + LPI_MUX_dmic23_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_i2s3_clk, + LPI_MUX_i2s3_data, + LPI_MUX_i2s3_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_mclk, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static int gpio0_pins[] =3D { 0 }; +static int gpio1_pins[] =3D { 1 }; +static int gpio2_pins[] =3D { 2 }; +static int gpio3_pins[] =3D { 3 }; +static int gpio4_pins[] =3D { 4 }; +static int gpio5_pins[] =3D { 5 }; +static int gpio6_pins[] =3D { 6 }; +static int gpio7_pins[] =3D { 7 }; +static int gpio8_pins[] =3D { 8 }; +static int gpio9_pins[] =3D { 9 }; +static int gpio10_pins[] =3D { 10 }; +static int gpio11_pins[] =3D { 11 }; +static int gpio12_pins[] =3D { 12 }; +static int gpio13_pins[] =3D { 13 }; +static int gpio14_pins[] =3D { 14 }; +static int gpio15_pins[] =3D { 15 }; +static int gpio16_pins[] =3D { 16 }; +static int gpio17_pins[] =3D { 17 }; +static int gpio18_pins[] =3D { 18 }; + +static const struct pinctrl_pin_desc sm6115_lpi_pins[] =3D { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), +}; + +static const char * const dmic01_clk_groups[] =3D { "gpio6" }; +static const char * const dmic01_data_groups[] =3D { "gpio7" }; +static const char * const dmic23_clk_groups[] =3D { "gpio8" }; +static const char * const dmic23_data_groups[] =3D { "gpio9" }; +static const char * const i2s1_clk_groups[] =3D { "gpio6" }; +static const char * const i2s1_data_groups[] =3D { "gpio8", "gpio9" }; +static const char * const i2s1_ws_groups[] =3D { "gpio7" }; +static const char * const i2s2_clk_groups[] =3D { "gpio10" }; +static const char * const i2s2_data_groups[] =3D { "gpio12", "gpio13" }; +static const char * const i2s2_ws_groups[] =3D { "gpio11" }; +static const char * const i2s3_clk_groups[] =3D { "gpio14" }; +static const char * const i2s3_data_groups[] =3D { "gpio16", "gpio17" }; +static const char * const i2s3_ws_groups[] =3D { "gpio15" }; +static const char * const qua_mi2s_data_groups[] =3D { "gpio2", "gpio3", "= gpio4", "gpio5" }; +static const char * const qua_mi2s_sclk_groups[] =3D { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] =3D { "gpio1" }; +static const char * const swr_rx_clk_groups[] =3D { "gpio3" }; +static const char * const swr_rx_data_groups[] =3D { "gpio4", "gpio5" }; +static const char * const swr_tx_clk_groups[] =3D { "gpio0" }; +static const char * const swr_tx_data_groups[] =3D { "gpio1", "gpio2" }; +static const char * const wsa_mclk_groups[] =3D { "gpio18" }; + +static const struct lpi_pingroup sm6115_groups[] =3D { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, _, qua_mi2s_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic01_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic01_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic23_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic23_data, i2s1_data, _, _), + LPI_PINGROUP(10, LPI_NO_SLEW, i2s2_clk, _, _, _), + LPI_PINGROUP(11, LPI_NO_SLEW, i2s2_ws, _, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, _, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, _, i2s2_data, _, _), + LPI_PINGROUP(14, LPI_NO_SLEW, i2s3_clk, _, _, _), + LPI_PINGROUP(15, LPI_NO_SLEW, i2s3_ws, _, _, _), + LPI_PINGROUP(16, LPI_NO_SLEW, i2s3_data, _, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, i2s3_data, _, _, _), + LPI_PINGROUP(18, 14, wsa_mclk, _, _, _), +}; + +static const struct lpi_function sm6115_functions[] =3D { + LPI_FUNCTION(dmic01_clk), + LPI_FUNCTION(dmic01_data), + LPI_FUNCTION(dmic23_clk), + LPI_FUNCTION(dmic23_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(i2s3_clk), + LPI_FUNCTION(i2s3_data), + LPI_FUNCTION(i2s3_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_mclk), +}; + +static const struct lpi_pinctrl_variant_data sm6115_lpi_data =3D { + .pins =3D sm6115_lpi_pins, + .npins =3D ARRAY_SIZE(sm6115_lpi_pins), + .groups =3D sm6115_groups, + .ngroups =3D ARRAY_SIZE(sm6115_groups), + .functions =3D sm6115_functions, + .nfunctions =3D ARRAY_SIZE(sm6115_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] =3D { + { .compatible =3D "qcom,sm6115-lpass-lpi-pinctrl", .data =3D &sm6115_lpi_= data }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver =3D { + .driver =3D { + .name =3D "qcom-sm6115-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + }, + .probe =3D lpi_pinctrl_probe, + .remove =3D lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("QTI SM6115 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); --=20 2.41.0