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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT003.mail.protection.outlook.com (10.13.173.162) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6609.28 via Frontend Transport; Fri, 21 Jul 2023 21:47:53 +0000 Received: from ethanolx50f7host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 21 Jul 2023 16:47:52 -0500 From: Smita Koralahalli To: , , CC: Bjorn Helgaas , , Lukas Wunner , Kuppuswamy Sathyanarayanan , Mahesh J Salgaonkar , Alison Schofield , "Vishal Verma" , Ira Weiny , "Ben Widawsky" , Dan Williams , Jonathan Cameron , Yazen Ghannam , Terry Bowman , Robert Richter , Smita Koralahalli Subject: [PATCH v2 1/3] cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS registers Date: Fri, 21 Jul 2023 21:47:38 +0000 Message-ID: <20230721214740.256602-2-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230721214740.256602-1-Smita.KoralahalliChannabasappa@amd.com> References: <20230721214740.256602-1-Smita.KoralahalliChannabasappa@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT003:EE_|MW4PR12MB6778:EE_ X-MS-Office365-Filtering-Correlation-Id: 40f10c06-8b07-4f54-f42a-08db8a34230f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jul 2023 21:47:53.2675 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 40f10c06-8b07-4f54-f42a-08db8a34230f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT003.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6778 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" According to Section 9.17.2, Table 9-26 of CXL Specification [1], owner of AER should also own CXL Protocol Error Management as there is no explicit control of CXL Protocol error. And the CXL RAS Cap registers reported on Protocol errors should check for AER _OSC rather than CXL Memory Error Reporting Control _OSC. The CXL Memory Error Reporting Control _OSC specifically highlights handling Memory Error Logging and Signaling Enhancements. These kinds of errors are reported through a device's mailbox and can be managed independently from CXL Protocol Errors. This change fixes handling and reporting CXL Protocol Errors and RAS registers natively with native AER and FW-First CXL Memory Error Reporting Control. [1] Compute Express Link (CXL) Specification, Revision 3.1, Aug 1 2022. Fixes: 248529edc86f ("cxl: add RAS status unmasking for CXL") Signed-off-by: Smita Koralahalli Reviewed-by: Robert Richter --- v2: Added fixes tag. Included what the patch fixes in commit message. --- drivers/cxl/pci.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 1cb1494c28fe..2323169b6e5f 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -541,9 +541,9 @@ static int cxl_pci_ras_unmask(struct pci_dev *pdev) return 0; } =20 - /* BIOS has CXL error control */ - if (!host_bridge->native_cxl_error) - return -ENXIO; + /* BIOS has PCIe AER error control */ + if (!host_bridge->native_aer) + return 0; =20 rc =3D pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap); if (rc) --=20 2.17.1