From nobody Fri Sep 20 14:30:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9D6AC41513 for ; Fri, 21 Jul 2023 21:12:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229711AbjGUVMH (ORCPT ); Fri, 21 Jul 2023 17:12:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229763AbjGUVMD (ORCPT ); Fri, 21 Jul 2023 17:12:03 -0400 X-Greylist: delayed 344 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Fri, 21 Jul 2023 14:11:57 PDT Received: from mx.skole.hr (mx1.hosting.skole.hr [161.53.165.185]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D39E359D; Fri, 21 Jul 2023 14:11:57 -0700 (PDT) Received: from mx1.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id 80C4986D18; Fri, 21 Jul 2023 23:06:10 +0200 (CEST) From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= To: Greg Kroah-Hartman , Jiri Slaby , linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, afaerber@suse.com, =?UTF-8?q?Duje=20Mihanovi=C4=87?= Subject: [PATCH 01/10] tty: serial: 8250: Define earlycon for mrvl,mmp-uart Date: Fri, 21 Jul 2023 22:37:43 +0200 Message-ID: <20230721210042.21535-2-duje.mihanovic@skole.hr> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230721210042.21535-1-duje.mihanovic@skole.hr> References: <20230721210042.21535-1-duje.mihanovic@skole.hr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org mrvl,pxa-uart already supports earlycon and both compatible strings use the same driver, so there's no reason for mmp-uart to not have earlycon as well. Signed-off-by: Duje Mihanovi=C4=87 --- drivers/tty/serial/8250/8250_pxa.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/tty/serial/8250/8250_pxa.c b/drivers/tty/serial/8250/8= 250_pxa.c index 28b341f602c6..a5b3ea27fc90 100644 --- a/drivers/tty/serial/8250/8250_pxa.c +++ b/drivers/tty/serial/8250/8250_pxa.c @@ -183,6 +183,7 @@ static int __init early_serial_pxa_setup(struct earlyco= n_device *device, return early_serial8250_setup(device, NULL); } OF_EARLYCON_DECLARE(early_pxa, "mrvl,pxa-uart", early_serial_pxa_setup); +OF_EARLYCON_DECLARE(mmp, "mrvl,mmp-uart", early_serial_pxa_setup); #endif =20 MODULE_AUTHOR("Sergei Ianovich"); --=20 2.41.0 From nobody Fri Sep 20 14:30:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56A22EB64DD for ; Fri, 21 Jul 2023 21:14:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230466AbjGUVN7 (ORCPT ); Fri, 21 Jul 2023 17:13:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229866AbjGUVNp (ORCPT ); Fri, 21 Jul 2023 17:13:45 -0400 Received: from mx.skole.hr (mx2.hosting.skole.hr [161.53.165.186]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EFAC30E2; Fri, 21 Jul 2023 14:13:16 -0700 (PDT) Received: from mx2.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id 2EFD888092; Fri, 21 Jul 2023 23:06:11 +0200 (CEST) From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= To: Robert Jarzmik , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, afaerber@suse.com, =?UTF-8?q?Duje=20Mihanovi=C4=87?= Subject: [PATCH 02/10] gpio: pxa: use dynamic allocation of base Date: Fri, 21 Jul 2023 22:37:44 +0200 Message-ID: <20230721210042.21535-3-duje.mihanovic@skole.hr> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230721210042.21535-1-duje.mihanovic@skole.hr> References: <20230721210042.21535-1-duje.mihanovic@skole.hr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fixes the warning in dmesg that static allocation of the base is deprecated. Signed-off-by: Duje Mihanovi=C4=87 --- drivers/gpio/gpio-pxa.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c index a1630ed4b741..076ee6dff4d5 100644 --- a/drivers/gpio/gpio-pxa.c +++ b/drivers/gpio/gpio-pxa.c @@ -350,6 +350,7 @@ static int pxa_init_gpio_chip(struct pxa_gpio_chip *pch= ip, int ngpio, void __iom =20 pchip->chip.parent =3D pchip->dev; pchip->chip.label =3D "gpio-pxa"; + pchip->chip.base =3D -1; pchip->chip.direction_input =3D pxa_gpio_direction_input; pchip->chip.direction_output =3D pxa_gpio_direction_output; pchip->chip.get =3D pxa_gpio_get; --=20 2.41.0 From nobody Fri Sep 20 14:30:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36488C001DE for ; Fri, 21 Jul 2023 21:12:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231204AbjGUVMM (ORCPT ); Fri, 21 Jul 2023 17:12:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230078AbjGUVMD (ORCPT ); Fri, 21 Jul 2023 17:12:03 -0400 X-Greylist: delayed 344 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Fri, 21 Jul 2023 14:11:57 PDT Received: from mx.skole.hr (mx1.hosting.skole.hr [161.53.165.185]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D26E359C; Fri, 21 Jul 2023 14:11:57 -0700 (PDT) Received: from mx1.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id 8B8B486D1B; Fri, 21 Jul 2023 23:06:11 +0200 (CEST) From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= To: Robert Jarzmik , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, afaerber@suse.com, =?UTF-8?q?Duje=20Mihanovi=C4=87?= Subject: [PATCH 03/10] gpio: pxa: make pxa_gpio_has_pinctrl return false for MMP_GPIO Date: Fri, 21 Jul 2023 22:37:45 +0200 Message-ID: <20230721210042.21535-4-duje.mihanovic@skole.hr> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230721210042.21535-1-duje.mihanovic@skole.hr> References: <20230721210042.21535-1-duje.mihanovic@skole.hr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fixes the incorrect assumption that mmp-gpio needs a pinctrl handle, causing devices consuming GPIO to be indefinitely deferred. Signed-off-by: Duje Mihanovi=C4=87 --- drivers/gpio/gpio-pxa.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c index 076ee6dff4d5..b48d142b736d 100644 --- a/drivers/gpio/gpio-pxa.c +++ b/drivers/gpio/gpio-pxa.c @@ -238,6 +238,7 @@ static bool pxa_gpio_has_pinctrl(void) switch (gpio_type) { case PXA3XX_GPIO: case MMP2_GPIO: + case MMP_GPIO: return false; =20 default: --=20 2.41.0 From nobody Fri Sep 20 14:30:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0513EB64DD for ; Fri, 21 Jul 2023 21:14:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230386AbjGUVOB (ORCPT ); Fri, 21 Jul 2023 17:14:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230128AbjGUVNr (ORCPT ); Fri, 21 Jul 2023 17:13:47 -0400 Received: from mx.skole.hr (mx2.hosting.skole.hr [161.53.165.186]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F01B359F; Fri, 21 Jul 2023 14:13:16 -0700 (PDT) Received: from mx2.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id DF505880BF; Fri, 21 Jul 2023 23:06:12 +0200 (CEST) From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= To: Michael Turquette , Stephen Boyd , =?UTF-8?q?Duje=20Mihanovi=C4=87?= , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, afaerber@suse.com Subject: [PATCH 04/10] clk: mmp: Add Marvell PXA1908 clock driver Date: Fri, 21 Jul 2023 22:37:46 +0200 Message-ID: <20230721210042.21535-5-duje.mihanovic@skole.hr> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230721210042.21535-1-duje.mihanovic@skole.hr> References: <20230721210042.21535-1-duje.mihanovic@skole.hr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add driver for Marvell PXA1908 clock controller blocks. The SoC has numerous clock controller blocks, currently supporting APBC, APBCP, MPMU and APMU. Signed-off-by: Duje Mihanovi=C4=87 --- drivers/clk/mmp/Makefile | 2 +- drivers/clk/mmp/clk-of-pxa1908.c | 282 +++++++++++++++++++++++++++++++ 2 files changed, 283 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/mmp/clk-of-pxa1908.c diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile index cbcc2f8430a2..feacddb28fc4 100644 --- a/drivers/clk/mmp/Makefile +++ b/drivers/clk/mmp/Makefile @@ -15,4 +15,4 @@ obj-$(CONFIG_CPU_PXA168) +=3D clk-pxa168.o obj-$(CONFIG_CPU_PXA910) +=3D clk-pxa910.o obj-$(CONFIG_CPU_MMP2) +=3D clk-mmp2.o =20 -obj-y +=3D clk-of-pxa1928.o +obj-$(CONFIG_ARCH_MMP) +=3D clk-of-pxa1928.o clk-of-pxa1908.o diff --git a/drivers/clk/mmp/clk-of-pxa1908.c b/drivers/clk/mmp/clk-of-pxa1= 908.c new file mode 100644 index 000000000000..58b3beca7b02 --- /dev/null +++ b/drivers/clk/mmp/clk-of-pxa1908.c @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include + +#include + +#include "clk.h" + +#define APBC_INDEX_TO_OFFSET(n) ((n - 1) * 4) + +#define APMU_CLK_GATE_CTRL 0x40 +#define MPMU_UART_PLL 0x14 + +struct pxa1908_clk_unit { + struct mmp_clk_unit unit; + void __iomem *mpmu_base; + void __iomem *apmu_base; + void __iomem *apbc_base; + void __iomem *apbcp_base; + void __iomem *apbs_base; + void __iomem *ciu_base; +}; + +static struct mmp_param_fixed_rate_clk fixed_rate_clks[] =3D { + {PXA1908_CLK_CLK32, "clk32", NULL, 0, 32768}, + {PXA1908_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000}, + {PXA1908_CLK_PLL1_624, "pll1_624", NULL, 0, 624000000}, + {PXA1908_CLK_PLL1_416, "pll1_416", NULL, 0, 416000000}, + {PXA1908_CLK_PLL1_499, "pll1_499", NULL, 0, 499000000}, + {PXA1908_CLK_PLL1_832, "pll1_832", NULL, 0, 832000000}, + {PXA1908_CLK_PLL1_1248, "pll1_1248", NULL, 0, 1248000000}, +}; + +static struct mmp_param_fixed_factor_clk fixed_factor_clks[] =3D { + {PXA1908_CLK_PLL1_D2, "pll1_d2", "pll1_624", 1, 2, 0}, + {PXA1908_CLK_PLL1_D4, "pll1_d4", "pll1_d2", 1, 2, 0}, + {PXA1908_CLK_PLL1_D6, "pll1_d6", "pll1_d2", 1, 3, 0}, + {PXA1908_CLK_PLL1_D8, "pll1_d8", "pll1_d4", 1, 2, 0}, + {PXA1908_CLK_PLL1_D12, "pll1_d12", "pll1_d6", 1, 2, 0}, + {PXA1908_CLK_PLL1_D13, "pll1_d13", "pll1_624", 1, 13, 0}, + {PXA1908_CLK_PLL1_D16, "pll1_d16", "pll1_d8", 1, 2, 0}, + {PXA1908_CLK_PLL1_D24, "pll1_d24", "pll1_d12", 1, 2, 0}, + {PXA1908_CLK_PLL1_D48, "pll1_d48", "pll1_d24", 1, 2, 0}, + {PXA1908_CLK_PLL1_D96, "pll1_d96", "pll1_d48", 1, 2, 0}, + {PXA1908_CLK_PLL1_32, "pll1_32", "pll1_d13", 2, 3, 0}, + {PXA1908_CLK_PLL1_208, "pll1_208", "pll1_d2", 2, 3, 0}, + {PXA1908_CLK_PLL1_117, "pll1_117", "pll1_624", 3, 16, 0}, +}; + +static struct mmp_clk_factor_masks uart_factor_masks =3D { + .factor =3D 2, + .num_mask =3D 0x1fff, + .den_mask =3D 0x1fff, + .num_shift =3D 16, + .den_shift =3D 0, +}; + +static struct mmp_clk_factor_tbl uart_factor_tbl[] =3D { + {.num =3D 8125, .den =3D 1536}, /* 14.745MHz */ +}; + +static DEFINE_SPINLOCK(pll1_lock); +static struct mmp_param_general_gate_clk pll1_gate_clks[] =3D { + {PXA1908_CLK_PLL1_D2_GATE, "pll1_d2_gate", "pll1_d2", 0, APMU_CLK_GATE_CT= RL, 29, 0, &pll1_lock}, + {PXA1908_CLK_PLL1_416_GATE, "pll1_416_gate", "pll1_416", 0, APMU_CLK_GATE= _CTRL, 27, 0, &pll1_lock}, + {PXA1908_CLK_PLL1_624_GATE, "pll1_624_gate", "pll1_624", 0, APMU_CLK_GATE= _CTRL, 26, 0, &pll1_lock}, + {PXA1908_CLK_PLL1_832_GATE, "pll1_832_gate", "pll1_832", 0, APMU_CLK_GATE= _CTRL, 30, 0, &pll1_lock}, + {PXA1908_CLK_PLL1_1248_GATE, "pll1_1248_gate", "pll1_1248", 0, APMU_CLK_G= ATE_CTRL, 28, 0, &pll1_lock}, +}; + +static void pxa1908_pll_init(struct pxa1908_clk_unit *pxa_unit) +{ + struct mmp_clk_unit *unit =3D &pxa_unit->unit; + + mmp_register_fixed_rate_clks(unit, fixed_rate_clks, + ARRAY_SIZE(fixed_rate_clks)); + + mmp_register_fixed_factor_clks(unit, fixed_factor_clks, + ARRAY_SIZE(fixed_factor_clks)); + + mmp_clk_register_factor("uart_pll", "pll1_d4", + CLK_SET_RATE_PARENT, + pxa_unit->mpmu_base + MPMU_UART_PLL, + &uart_factor_masks, uart_factor_tbl, + ARRAY_SIZE(uart_factor_tbl), NULL); + +} + +static DEFINE_SPINLOCK(pwm0_lock); +static DEFINE_SPINLOCK(pwm2_lock); + +static DEFINE_SPINLOCK(uart0_lock); +static DEFINE_SPINLOCK(uart1_lock); +static DEFINE_SPINLOCK(uart2_lock); + +static const char * const uart_parent_names[] =3D {"pll1_117", "uart_pll"}; +static const char * const ssp_parent_names[] =3D {"pll1_d16", "pll1_d48", = "pll1_d24", "pll1_d12"}; + +static struct mmp_param_gate_clk apbc_gate_clks[] =3D { + {PXA1908_CLK_TWSI0, "twsi0_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_IND= EX_TO_OFFSET(PXA1908_CLK_TWSI0), 0x7, 3, 0, 0, NULL}, + {PXA1908_CLK_TWSI1, "twsi1_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_IND= EX_TO_OFFSET(PXA1908_CLK_TWSI1), 0x7, 3, 0, 0, NULL}, + {PXA1908_CLK_TWSI3, "twsi3_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_IND= EX_TO_OFFSET(PXA1908_CLK_TWSI3), 0x7, 3, 0, 0, NULL}, + {PXA1908_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_INDEX_= TO_OFFSET(PXA1908_CLK_GPIO), 0x7, 3, 0, 0, NULL}, + {PXA1908_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_INDEX_TO_= OFFSET(PXA1908_CLK_KPC), 0x7, 3, 0, MMP_CLK_GATE_NEED_DELAY, NULL}, + {PXA1908_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_INDEX_TO_= OFFSET(PXA1908_CLK_RTC), 0x87, 0x83, 0, MMP_CLK_GATE_NEED_DELAY, NULL}, + {PXA1908_CLK_PWM0, "pwm0_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, AP= BC_INDEX_TO_OFFSET(PXA1908_CLK_PWM0), 0x2, 2, 0, 0, &pwm0_lock}, + {PXA1908_CLK_PWM1, "pwm1_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, AP= BC_INDEX_TO_OFFSET(PXA1908_CLK_PWM1), 0x6, 2, 0, 0, NULL}, + {PXA1908_CLK_PWM2, "pwm2_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, AP= BC_INDEX_TO_OFFSET(PXA1908_CLK_PWM2), 0x2, 2, 0, 0, NULL}, + {PXA1908_CLK_PWM3, "pwm3_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, AP= BC_INDEX_TO_OFFSET(PXA1908_CLK_PWM3), 0x6, 2, 0, 0, NULL}, + {PXA1908_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_I= NDEX_TO_OFFSET(PXA1908_CLK_UART0), 0x7, 3, 0, 0, &uart0_lock}, + {PXA1908_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_I= NDEX_TO_OFFSET(PXA1908_CLK_UART1), 0x7, 3, 0, 0, &uart1_lock}, +}; + +static struct mmp_param_mux_clk apbc_mux_clks[] =3D { + {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SE= T_RATE_PARENT, APBC_INDEX_TO_OFFSET(PXA1908_CLK_UART0), 4, 3, 0, &uart0_loc= k}, + {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SE= T_RATE_PARENT, APBC_INDEX_TO_OFFSET(PXA1908_CLK_UART1), 4, 3, 0, &uart1_loc= k}, + {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), 0, APBC_I= NDEX_TO_OFFSET(PXA1908_CLK_SSP0), 4, 3, 0, NULL}, + {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), 0, APBC_I= NDEX_TO_OFFSET(PXA1908_CLK_SSP2), 4, 3, 0, NULL}, +}; + +static void pxa1908_apb_periph_clk_init(struct pxa1908_clk_unit *pxa_unit) +{ + struct mmp_clk_unit *unit =3D &pxa_unit->unit; + + mmp_clk_register_gate(NULL, "pwm01_apb_share", "pll1_d48", + CLK_SET_RATE_PARENT, + pxa_unit->apbc_base + PXA1908_CLK_PWM0 * 4, + 0x5, 1, 0, 0, &pwm0_lock); + mmp_clk_register_gate(NULL, "pwm23_apb_share", "pll1_d48", + CLK_SET_RATE_PARENT, + pxa_unit->apbc_base + PXA1908_CLK_PWM2 * 4, + 0x5, 1, 0, 0, &pwm2_lock); + mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base, + ARRAY_SIZE(apbc_mux_clks)); + mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base, + ARRAY_SIZE(apbc_gate_clks)); +} + +static struct mmp_param_gate_clk apbcp_gate_clks[] =3D { + {PXA1908_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, PXA190= 8_CLK_UART2 * 4, 0x7, 0x3, 0x0, 0, &uart2_lock}, + {PXA1908_CLK_TWSI2, "twsi2_clk", "pll1_32", CLK_SET_RATE_PARENT, PXA1908_= CLK_TWSI2 * 4, 0x7, 0x3, 0x0, 0, NULL}, + {PXA1908_CLK_AICER, "ripc_clk", NULL, 0, PXA1908_CLK_AICER * 4, 0x7, 0x2,= 0x0, 0, NULL}, +}; + +static struct mmp_param_mux_clk apbcp_mux_clks[] =3D { + {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SE= T_RATE_PARENT, PXA1908_CLK_UART2 * 4, 4, 3, 0, &uart2_lock}, +}; + +static void pxa1908_apb_p_periph_clk_init(struct pxa1908_clk_unit *pxa_uni= t) +{ + struct mmp_clk_unit *unit =3D &pxa_unit->unit; + + mmp_register_mux_clks(unit, apbcp_mux_clks, pxa_unit->apbcp_base, + ARRAY_SIZE(apbcp_mux_clks)); + mmp_register_gate_clks(unit, apbcp_gate_clks, pxa_unit->apbcp_base, + ARRAY_SIZE(apbcp_gate_clks)); +} + +static DEFINE_SPINLOCK(sdh0_lock); +static DEFINE_SPINLOCK(sdh1_lock); +static DEFINE_SPINLOCK(sdh2_lock); + +static const char * const sdh_parent_names[] =3D {"pll1_416", "pll1_624"}; + +static struct mmp_clk_mix_config sdh_mix_config =3D { + .reg_info =3D DEFINE_MIX_REG_INFO(3, 8, 2, 6, 11), +}; + +static struct mmp_param_gate_clk apmu_gate_clks[] =3D { + {PXA1908_CLK_USB, "usb_clk", NULL, 0, PXA1908_CLK_USB * 4, 0x9, 0x9, 0x1,= 0, NULL}, + {PXA1908_CLK_SDH0, "sdh0_clk", "sdh0_mix_clk", CLK_SET_RATE_PARENT | CLK_= SET_RATE_UNGATE, PXA1908_CLK_SDH0 * 4, 0x12, 0x12, 0x0, 0, &sdh0_lock}, + {PXA1908_CLK_SDH1, "sdh1_clk", "sdh1_mix_clk", CLK_SET_RATE_PARENT | CLK_= SET_RATE_UNGATE, PXA1908_CLK_SDH1 * 4, 0x12, 0x12, 0x0, 0, &sdh1_lock}, + {PXA1908_CLK_SDH2, "sdh2_clk", "sdh2_mix_clk", CLK_SET_RATE_PARENT | CLK_= SET_RATE_UNGATE, PXA1908_CLK_SDH2 * 4, 0x12, 0x12, 0x0, 0, &sdh2_lock} +}; + +static void pxa1908_axi_periph_clk_init(struct pxa1908_clk_unit *pxa_unit) +{ + struct mmp_clk_unit *unit =3D &pxa_unit->unit; + + mmp_register_general_gate_clks(unit, pll1_gate_clks, + pxa_unit->apmu_base, ARRAY_SIZE(pll1_gate_clks)); + + sdh_mix_config.reg_info.reg_clk_ctrl =3D pxa_unit->apmu_base + PXA1908_CL= K_SDH0 * 4; + mmp_clk_register_mix(NULL, "sdh0_mix_clk", sdh_parent_names, + ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, + &sdh_mix_config, &sdh0_lock); + sdh_mix_config.reg_info.reg_clk_ctrl =3D pxa_unit->apmu_base + PXA1908_CL= K_SDH1 * 4; + mmp_clk_register_mix(NULL, "sdh1_mix_clk", sdh_parent_names, + ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, + &sdh_mix_config, &sdh1_lock); + sdh_mix_config.reg_info.reg_clk_ctrl =3D pxa_unit->apmu_base + PXA1908_CL= K_SDH2 * 4; + mmp_clk_register_mix(NULL, "sdh2_mix_clk", sdh_parent_names, + ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, + &sdh_mix_config, &sdh2_lock); + + mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base, + ARRAY_SIZE(apmu_gate_clks)); +} + +static void __init pxa1908_apbc_clk_init(struct device_node *np) +{ + struct pxa1908_clk_unit *pxa_unit; + + pxa_unit =3D kzalloc(sizeof(*pxa_unit), GFP_KERNEL); + if (!pxa_unit) + return; + + pxa_unit->apbc_base =3D of_iomap(np, 0); + if (!pxa_unit->apbc_base) { + pr_err("failed to map apbc registers\n"); + kfree(pxa_unit); + return; + } + + mmp_clk_init(np, &pxa_unit->unit, PXA1908_APBC_NR_CLKS); + + pxa1908_apb_periph_clk_init(pxa_unit); +} +CLK_OF_DECLARE(pxa1908_apbc, "marvell,pxa1908-apbc", pxa1908_apbc_clk_init= ); + +static void __init pxa1908_apbcp_clk_init(struct device_node *np) +{ + struct pxa1908_clk_unit *pxa_unit; + + pxa_unit =3D kzalloc(sizeof(*pxa_unit), GFP_KERNEL); + if (!pxa_unit) + return; + + pxa_unit->apbcp_base =3D of_iomap(np, 0); + if (!pxa_unit->apbcp_base) { + pr_err("failed to map apbcp registers\n"); + kfree(pxa_unit); + return; + } + + mmp_clk_init(np, &pxa_unit->unit, PXA1908_APBCP_NR_CLKS); + + pxa1908_apb_p_periph_clk_init(pxa_unit); +} +CLK_OF_DECLARE(pxa1908_apbcp, "marvell,pxa1908-apbcp", pxa1908_apbcp_clk_i= nit); + +static void __init pxa1908_mpmu_clk_init(struct device_node *np) +{ + struct pxa1908_clk_unit *pxa_unit; + + pxa_unit =3D kzalloc(sizeof(*pxa_unit), GFP_KERNEL); + if (!pxa_unit) + return; + + pxa_unit->mpmu_base =3D of_iomap(np, 0); + if (!pxa_unit->mpmu_base) { + pr_err("failed to map mpmu registers\n"); + kfree(pxa_unit); + return; + } + + mmp_clk_init(np, &pxa_unit->unit, PXA1908_MPMU_NR_CLKS); + + pxa1908_pll_init(pxa_unit); +} +CLK_OF_DECLARE(pxa1908_mpmu, "marvell,pxa1908-mpmu", pxa1908_mpmu_clk_init= ); + +static void __init pxa1908_apmu_clk_init(struct device_node *np) +{ + struct pxa1908_clk_unit *pxa_unit; + + pxa_unit =3D kzalloc(sizeof(*pxa_unit), GFP_KERNEL); + if (!pxa_unit) + return; + + pxa_unit->apmu_base =3D of_iomap(np, 0); + if (!pxa_unit->apmu_base) { + pr_err("failed to map apmu registers\n"); + kfree(pxa_unit); + return; + } + + mmp_clk_init(np, &pxa_unit->unit, PXA1908_APMU_NR_CLKS); + + pxa1908_axi_periph_clk_init(pxa_unit); +} +CLK_OF_DECLARE(pxa1908_apmu, "marvell,pxa1908-apmu", pxa1908_apmu_clk_init= ); --=20 2.41.0 From nobody Fri Sep 20 14:30:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D87BC0015E for ; Fri, 21 Jul 2023 21:12:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230453AbjGUVMK (ORCPT ); Fri, 21 Jul 2023 17:12:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229766AbjGUVMD (ORCPT ); Fri, 21 Jul 2023 17:12:03 -0400 X-Greylist: delayed 340 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Fri, 21 Jul 2023 14:11:57 PDT Received: from mx.skole.hr (mx1.hosting.skole.hr [161.53.165.185]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D19B30ED; Fri, 21 Jul 2023 14:11:57 -0700 (PDT) Received: from mx1.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id D31C586D1D; Fri, 21 Jul 2023 23:06:12 +0200 (CEST) From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= To: =?UTF-8?q?Duje=20Mihanovi=C4=87?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, afaerber@suse.com Subject: [PATCH 05/10] dt-bindings: clock: Add Marvell PXA1908 clock bindings Date: Fri, 21 Jul 2023 22:37:47 +0200 Message-ID: <20230721210042.21535-6-duje.mihanovic@skole.hr> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230721210042.21535-1-duje.mihanovic@skole.hr> References: <20230721210042.21535-1-duje.mihanovic@skole.hr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the dt bindings for Marvell PXA1908 clock controller. Signed-off-by: Duje Mihanovi=C4=87 --- include/dt-bindings/clock/marvell,pxa1908.h | 93 +++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 include/dt-bindings/clock/marvell,pxa1908.h diff --git a/include/dt-bindings/clock/marvell,pxa1908.h b/include/dt-bindi= ngs/clock/marvell,pxa1908.h new file mode 100644 index 000000000000..da9c5d499ae4 --- /dev/null +++ b/include/dt-bindings/clock/marvell,pxa1908.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __DTS_MARVELL_PXA1908_CLOCK_H +#define __DTS_MARVELL_PXA1908_CLOCK_H + +/* plls */ +#define PXA1908_CLK_CLK32 0x1 +#define PXA1908_CLK_VCTCXO 0x2 +#define PXA1908_CLK_PLL1_624 0x3 +#define PXA1908_CLK_PLL1_416 0x4 +#define PXA1908_CLK_PLL1_499 0x5 +#define PXA1908_CLK_PLL1_832 0x6 +#define PXA1908_CLK_PLL1_1248 0x7 +#define PXA1908_CLK_PLL1_D2 0x8 +#define PXA1908_CLK_PLL1_D4 0x9 +#define PXA1908_CLK_PLL1_D8 0xa +#define PXA1908_CLK_PLL1_D16 0xb +#define PXA1908_CLK_PLL1_D6 0xc +#define PXA1908_CLK_PLL1_D12 0xd +#define PXA1908_CLK_PLL1_D24 0xe +#define PXA1908_CLK_PLL1_D48 0xf +#define PXA1908_CLK_PLL1_D96 0x10 +#define PXA1908_CLK_PLL1_D13 0x11 +#define PXA1908_CLK_PLL1_32 0x12 +#define PXA1908_CLK_PLL1_208 0x13 +#define PXA1908_CLK_PLL1_117 0x14 +#define PXA1908_CLK_PLL1_416_GATE 0x15 +#define PXA1908_CLK_PLL1_624_GATE 0x16 +#define PXA1908_CLK_PLL1_832_GATE 0x17 +#define PXA1908_CLK_PLL1_1248_GATE 0x18 +#define PXA1908_CLK_PLL1_D2_GATE 0x19 +#define PXA1908_CLK_PLL1_499_EN 0x1a +#define PXA1908_CLK_PLL2VCO 0x1b +#define PXA1908_CLK_PLL2 0x1c +#define PXA1908_CLK_PLL2P 0x1d +#define PXA1908_CLK_PLL2VCODIV3 0x1e +#define PXA1908_CLK_PLL3VCO 0x1f +#define PXA1908_CLK_PLL3 0x20 +#define PXA1908_CLK_PLL3P 0x21 +#define PXA1908_CLK_PLL3VCODIV3 0x22 +#define PXA1908_CLK_PLL4VCO 0x23 +#define PXA1908_CLK_PLL4 0x24 +#define PXA1908_CLK_PLL4P 0x25 +#define PXA1908_CLK_PLL4VCODIV3 0x26 +#define PXA1908_MPMU_NR_CLKS 38 + +/* apb (apbc) peripherals */ +#define PXA1908_CLK_UART0 0x1 +#define PXA1908_CLK_UART1 0x2 +#define PXA1908_CLK_GPIO 0x3 +#define PXA1908_CLK_PWM0 0x4 +#define PXA1908_CLK_PWM1 0x5 +#define PXA1908_CLK_PWM2 0x6 +#define PXA1908_CLK_PWM3 0x7 +#define PXA1908_CLK_SSP0 0x8 +#define PXA1908_CLK_SSP1 0x9 +#define PXA1908_CLK_IPC_RST 0xa +#define PXA1908_CLK_RTC 0xb +#define PXA1908_CLK_TWSI0 0xc +#define PXA1908_CLK_KPC 0xd +#define PXA1908_CLK_SWJTAG 0x11 +#define PXA1908_CLK_SSP2 0x14 +#define PXA1908_CLK_TWSI1 0x19 +#define PXA1908_CLK_THERMAL 0x1c +#define PXA1908_CLK_TWSI3 0x1d +#define PXA1908_APBC_NR_CLKS 0x30 + +/* apb (apbcp) peripherals */ +#define PXA1908_CLK_UART2 0x7 +#define PXA1908_CLK_TWSI2 0xa +#define PXA1908_CLK_AICER 0xe +#define PXA1908_APBCP_NR_CLKS 0xe + +/* axi (apmu) peripherals */ +#define PXA1908_CLK_CCIC1 0x9 +#define PXA1908_CLK_ISP 0xe +#define PXA1908_CLK_GATE_CTRL 0x10 +#define PXA1908_CLK_DSI1 0x11 +#define PXA1908_CLK_DISP1 0x13 +#define PXA1908_CLK_CCIC0 0x14 +#define PXA1908_CLK_SDH0 0x15 +#define PXA1908_CLK_SDH1 0x16 +#define PXA1908_CLK_SDH2 0x38 +#define PXA1908_CLK_USB 0x17 +#define PXA1908_CLK_NF 0x18 +#define PXA1908_CLK_CORE_DEBUG 0x24 +#define PXA1908_CLK_VPU 0x29 +#define PXA1908_CLK_GC 0x51 +#define PXA1908_CLK_GC2D 0x3d +#define PXA1908_CLK_TRACE 0x42 +#define PXA1908_CLK_DVC_DFC_DEBUG 0x50 +#define PXA1908_APMU_NR_CLKS 0x60 + +#endif --=20 2.41.0 From nobody Fri Sep 20 14:30:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 093B7C04FE1 for ; Fri, 21 Jul 2023 21:12:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231150AbjGUVMF (ORCPT ); Fri, 21 Jul 2023 17:12:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229451AbjGUVMD (ORCPT ); Fri, 21 Jul 2023 17:12:03 -0400 X-Greylist: delayed 343 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Fri, 21 Jul 2023 14:11:57 PDT Received: from mx.skole.hr (mx1.hosting.skole.hr [161.53.165.185]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D08330E2; Fri, 21 Jul 2023 14:11:57 -0700 (PDT) Received: from mx1.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id C2ED386D1E; Fri, 21 Jul 2023 23:06:13 +0200 (CEST) From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?q?=87?= , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, afaerber@suse.com Subject: [PATCH 06/10] dt-bindings: clock: Add documentation for Marvell PXA1908 Date: Fri, 21 Jul 2023 22:37:48 +0200 Message-ID: <20230721210042.21535-7-duje.mihanovic@skole.hr> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230721210042.21535-1-duje.mihanovic@skole.hr> References: <20230721210042.21535-1-duje.mihanovic@skole.hr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add dt bindings and documentation for Marvell PXA1908's clock controller blocks. Signed-off-by: Duje Mihanovi=C4=87 --- .../bindings/clock/marvell,pxa1908.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/marvell,pxa1908= .yaml diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b= /Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml new file mode 100644 index 000000000000..3fa6f00a26f7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,pxa1908.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell PXA1908 Clock Controllers + +maintainers: + - Duje Mihanovi=C4=87 + +description: | + The PXA1908 clock subsystem generates and supplies clock to various + controllers within the PXA1908 SoC. The PXA1908 contains numerous clock + controller blocks, with the ones currently supported being APBC, APBCP, = MPMU + and APMU roughly corresponding to internal buses. + + Each clock is assigned an identifier and client nodes use this identifie= r to + specify the clock which they consume. + + All these identifiers could be found in . + +properties: + compatible: + enum: + - marvell,pxa1908-apbc + - marvell,pxa1908-apbcp + - marvell,pxa1908-mpmu + - marvell,pxa1908-apmu + reg: + maxItems: 1 + description: | + Physical address of the clock controller and length of the memory ma= pped + region. + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # APMU block: + - | + clock-controller@d4282800 { + compatible =3D "marvell,pxa1908-apmu"; + reg =3D <0xd4282800 0x400>; + #clock-cells =3D <1>; + }; --=20 2.41.0 From nobody Fri Sep 20 14:30:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3ED3EC001DE for ; Fri, 21 Jul 2023 21:13:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231176AbjGUVN4 (ORCPT ); Fri, 21 Jul 2023 17:13:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229844AbjGUVNp (ORCPT ); Fri, 21 Jul 2023 17:13:45 -0400 Received: from mx.skole.hr (mx2.hosting.skole.hr [161.53.165.186]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39B1F3A81; Fri, 21 Jul 2023 14:13:17 -0700 (PDT) Received: from mx2.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id D069C880C3; Fri, 21 Jul 2023 23:06:13 +0200 (CEST) From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= To: Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, afaerber@suse.com, =?UTF-8?q?Duje=20Mihanovi=C4=87?= Subject: [PATCH 07/10] arm64: Kconfig.platforms: Add config for Marvell PXA1908 platform Date: Fri, 21 Jul 2023 22:37:49 +0200 Message-ID: <20230721210042.21535-8-duje.mihanovic@skole.hr> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230721210042.21535-1-duje.mihanovic@skole.hr> References: <20230721210042.21535-1-duje.mihanovic@skole.hr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add ARCH_MMP configuration option for Marvell PXA1908 SoC. Signed-off-by: Duje Mihanovi=C4=87 --- arch/arm64/Kconfig.platforms | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6069120199bb..b417cae42c84 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -89,6 +89,17 @@ config ARCH_BERLIN help This enables support for Marvell Berlin SoC Family =20 +config ARCH_MMP + bool "Marvell MMP SoC Family" + select ARM_GIC + select ARM_ARCH_TIMER + select ARM_SMMU + select MMP_PDMA + select PINCTRL_SINGLE + help + This enables support for Marvell MMP SoC family, currently + supporting PXA1908 aka IAP140. + config ARCH_BITMAIN bool "Bitmain SoC Platforms" help --=20 2.41.0 From nobody Fri Sep 20 14:30:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB20DEB64DD for ; Fri, 21 Jul 2023 21:12:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230394AbjGUVMQ (ORCPT ); Fri, 21 Jul 2023 17:12:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230252AbjGUVME (ORCPT ); Fri, 21 Jul 2023 17:12:04 -0400 X-Greylist: delayed 334 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Fri, 21 Jul 2023 14:11:57 PDT Received: from mx.skole.hr (mx1.hosting.skole.hr [161.53.165.185]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D504359F; Fri, 21 Jul 2023 14:11:57 -0700 (PDT) Received: from mx1.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id 9401986D1F; Fri, 21 Jul 2023 23:06:15 +0200 (CEST) From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?q?Duje=20Mihanovi=C4=87?= , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-hardening@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, afaerber@suse.com Subject: [PATCH 08/10] arm64: dts: Add DTS for Marvell PXA1908 and samsung,coreprimevelte Date: Fri, 21 Jul 2023 22:37:50 +0200 Message-ID: <20230721210042.21535-9-duje.mihanovic@skole.hr> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230721210042.21535-1-duje.mihanovic@skole.hr> References: <20230721210042.21535-1-duje.mihanovic@skole.hr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DTS for Marvell PXA1908 SoC and Samsung Galaxy Core Prime Value Edition LTE, a smartphone based on said SoC. Signed-off-by: Duje Mihanovi=C4=87 --- arch/arm64/boot/dts/marvell/Makefile | 1 + .../pxa1908-samsung-coreprimevelte.dts | 321 ++++++++++++++++++ arch/arm64/boot/dts/marvell/pxa1908.dtsi | 298 ++++++++++++++++ 3 files changed, 620 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimeve= lte.dts create mode 100644 arch/arm64/boot/dts/marvell/pxa1908.dtsi diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/mar= vell/Makefile index 79ac09b58a89..0e277a0d368b 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -27,3 +27,4 @@ dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9132-db-B.dtb dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9130-crb-A.dtb dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9130-crb-B.dtb dtb-$(CONFIG_ARCH_MVEBU) +=3D ac5-98dx35xx-rd.dtb +dtb-$(CONFIG_ARCH_MMP) +=3D pxa1908-samsung-coreprimevelte.dtb diff --git a/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts= b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts new file mode 100644 index 000000000000..3e10a77a106e --- /dev/null +++ b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "pxa1908.dtsi" +#include +#include + +/ { + pxa,rev-id =3D <3928 2>; + model =3D "Samsung Galaxy Core Prime VE LTE"; + compatible =3D "samsung,coreprimevelte", "marvell,pxa1908"; + + /* Bootloader fills this in */ + memory { + device_type =3D "memory"; + reg =3D <0 0 0 0>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + framebuffer@17000000 { + reg =3D <0 0x17000000 0 0x1800000>; + no-map; + }; + + gpu@9000000 { + reg =3D <0 0x9000000 0 0x1000000>; + }; + + /* Communications processor, aka modem */ + cp@3000000 { + reg =3D <0 0x3000000 0 0x5000000>; + }; + + cm3@a000000 { + reg =3D <0 0xa000000 0 0x80000>; + }; + + seclog@8000000 { + reg =3D <0 0x8000000 0 0x100000>; + }; + + ramoops@8100000 { + compatible =3D "ramoops"; + reg =3D <0 0x8100000 0 0x40000>; + record-size =3D <0x8000>; + console-size =3D <0x20000>; + max-reason =3D <5>; + }; + }; + + fb0: framebuffer@17177000 { + compatible =3D "simple-framebuffer"; + reg =3D <0 0x17177000 0 (480 * 800 * 4)>; + width =3D <480>; + height =3D <800>; + stride =3D <(480 * 4)>; + format =3D "a8r8g8b8"; + }; + + muic-i2c { + compatible =3D "i2c-gpio"; + sda-gpios =3D <&gpio 30 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios =3D <&gpio 29 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us =3D <3>; + i2c-gpio,timeout-ms =3D <100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&muic_i2c_pins>; + + muic: extcon@14 { + compatible =3D "siliconmitus,sm5504-muic"; + reg =3D <0x14>; + interrupt-parent =3D <&gpio>; + interrupts =3D <0 IRQ_TYPE_EDGE_FALLING>; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio_keys_pins>; + autorepeat; + + key-home { + label =3D "Home"; + linux,code =3D ; + gpios =3D <&gpio 50 GPIO_ACTIVE_LOW>; + }; + + key-volup { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&gpio 16 GPIO_ACTIVE_LOW>; + }; + + key-voldown { + label =3D "Volume Down"; + linux,code =3D ; + gpios =3D <&gpio 17 GPIO_ACTIVE_LOW>; + }; + }; + + chosen {}; +}; + +&smmu { + status =3D "okay"; +}; + +&pmx { + pinctrl-single,gpio-range =3D <&range 55 55 0>, + <&range 110 32 0>, + <&range 52 1 0>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&board_pins_1 &board_pins_2 &board_pins_3>; + + board_pins_1: pinmux_board_1 { + pinctrl-single,pins =3D < + 0x160 0 + 0x164 0 + 0x168 0 + 0x16c 0 + >; + pinctrl-single,drive-strength =3D <0x1000 0x1800>; + pinctrl-single,bias-pullup =3D <0x8000 0x8000 0 0xc000>; + pinctrl-single,bias-pulldown =3D <0x8000 0x8000 0 0xa000>; + pinctrl-single,input-schmitt =3D <0 0x30>; + pinctrl-single,input-schmitt-enable =3D <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode =3D <0x288 0x388>; + }; + + board_pins_2: pinmux_board_2 { + pinctrl-single,pins =3D < + 0x44 1 + 0x48 1 + 0x20 1 + 0x18 1 + 0x14 1 + 0x10 1 + 0xc 1 + 0x8 1 + 0x68 1 + 0x58 0 + 0x54 0 + 0x7c 0 + 0x6c 0 + 0x70 0 + 0x4c 1 + 0x50 1 + 0xac 0 + 0x90 0 + 0x8c 0 + 0x88 0 + 0x84 0 + 0xc8 0 + 0x128 0 + 0x190 0 + 0x194 0 + 0x1a0 0 + 0x114 0 + 0x118 0 + 0x1d8 0 + 0x1e4 0 + 0xe8 0 + 0x100 0 + 0x204 0 + 0x210 0 + 0x218 0 + >; + pinctrl-single,bias-pullup =3D <0xc000 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown =3D <0x8000 0xa000 0x8000 0xc000>; + pinctrl-single,low-power-mode =3D <0x288 0x388>; + }; + + board_pins_3: pinmux_board_3 { + pinctrl-single,pins =3D < + 0x260 0 + 0x264 0 + 0x268 0 + 0x26c 0 + 0x270 0 + 0x274 0 + 0x78 0 + 0x74 0 + 0xb0 1 + >; + pinctrl-single,drive-strength =3D <0x1000 0x1800>; + pinctrl-single,bias-pullup =3D <0 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown =3D <0 0xa000 0 0xa000>; + pinctrl-single,input-schmitt =3D <0 0x30>; + pinctrl-single,input-schmitt-enable =3D <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode =3D <0 0x388>; + }; + + uart0_pins: pinmux_uart0 { + pinctrl-single,pins =3D < + 0x198 6 + 0x19c 6 + >; + pinctrl-single,drive-strength =3D <0x1000 0x1800>; + pinctrl-single,bias-pullup =3D <0 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown =3D <0 0xa000 0 0xa000>; + pinctrl-single,input-schmitt =3D <0 0x30>; + pinctrl-single,input-schmitt-enable =3D <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode =3D <0 0x388>; + }; + + gpio_keys_pins: pinmux_gpio_keys { + pinctrl-single,pins =3D < + 0x11c 0 + 0x120 0 + 0x1a4 0 + >; + pinctrl-single,drive-strength =3D <0x1000 0x1800>; + pinctrl-single,bias-pullup =3D <0xc000 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown =3D <0x8000 0xa0000 0x8000 0xa000>; + pinctrl-single,input-schmitt =3D <0 0x30>; + pinctrl-single,input-schmitt-enable =3D <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode =3D <0 0x388>; + }; + + muic_i2c_pins: pinmux_muic_i2c { + pinctrl-single,pins =3D < + 0x154 0 + 0x150 0 + >; + pinctrl-single,drive-strength =3D <0x1000 0x1800>; + pinctrl-single,bias-pullup =3D <0 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown =3D <0 0xa000 0 0xa000>; + pinctrl-single,input-schmitt =3D <0 0x30>; + pinctrl-single,input-schmitt-enable =3D <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode =3D <0x288 0x388>; + }; + + sdh0_pins_1: pinmux_sdh0_1 { + pinctrl-single,pins =3D < + 0x108 0 + >; + pinctrl-single,drive-strength =3D <0x1000 0x1800>; + pinctrl-single,bias-pullup =3D <0xc000 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown =3D <0x8000 0xa000 0x8000 0xa000>; + pinctrl-single,input-schmitt =3D <0 0x30>; + pinctrl-single,input-schmitt-enable =3D <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode =3D <0 0x388>; + }; + + sdh0_pins_2: pinmux_sdh0_2 { + pinctrl-single,pins =3D < + 0x94 0 + 0x98 0 + 0x9c 0 + 0xa0 0 + 0xa4 0 + >; + pinctrl-single,drive-strength =3D <0x800 0x1800>; + pinctrl-single,bias-pullup =3D <0xc000 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown =3D <0x8000 0xa000 0x8000 0xa000>; + pinctrl-single,input-schmitt =3D <0 0x30>; + pinctrl-single,input-schmitt-enable =3D <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode =3D <0 0x388>; + }; + + sdh0_pins_3: pinmux_sdh0_3 { + pinctrl-single,pins =3D < + 0xa8 0 + >; + pinctrl-single,drive-strength =3D <0x1000 0x1800>; + pinctrl-single,bias-pullup =3D <0 0xc000 0 0xc000>; + pinctrl-single,bias-pulldown =3D <0 0xa000 0 0xa000>; + pinctrl-single,input-schmitt =3D <0 0x30>; + pinctrl-single,input-schmitt-enable =3D <0x40 0 0x40 0x40>; + pinctrl-single,low-power-mode =3D <0x208 0x388>; + }; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pins>; +}; + +&twsi0 { + status =3D "okay"; +}; + +&twsi1 { + status =3D "okay"; +}; + +&twsi2 { + status =3D "okay"; +}; + +&twsi3 { + status =3D "okay"; +}; + +&usb { + extcon =3D <&muic>, <&muic>; +}; + +&sdh2 { + /* Disabled for now because initialization fails with -ETIMEDOUT. */ + status =3D "disabled"; + bus-width =3D <8>; + non-removable; + broken-cd; + mmc-ddr-1_8v; +}; + +&sdh0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdh0_pins_1 &sdh0_pins_2 &sdh0_pins_3>; + cd-gpios =3D <&gpio 11 0>; + cd-inverted; + bus-width =3D <4>; + wp-inverted; +}; diff --git a/arch/arm64/boot/dts/marvell/pxa1908.dtsi b/arch/arm64/boot/dts= /marvell/pxa1908.dtsi new file mode 100644 index 000000000000..7131b2070b72 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/pxa1908.dtsi @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; + +#include +#include + +/ { + model =3D "Marvell Armada PXA1908"; + compatible =3D "marvell,pxa1908"; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53", "arm,armv8"; + reg =3D <0 0>; + enable-method =3D "psci"; + }; + + cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53", "arm,armv8"; + reg =3D <0 1>; + enable-method =3D "psci"; + }; + + cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53", "arm,armv8"; + reg =3D <0 2>; + enable-method =3D "psci"; + }; + + cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53", "arm,armv8"; + reg =3D <0 3>; + enable-method =3D "psci"; + }; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + smmu: iommu@c0010000 { + compatible =3D "arm,mmu-400"; + reg =3D <0 0xc0010000 0 0x10000>; + #global-interrupts =3D <1>; + #iommu-cells =3D <1>; + interrupts =3D , + ; + status =3D "disabled"; + }; + + gic: interrupt-controller@d1df9000 { + compatible =3D "arm,gic-400"; + reg =3D <0 0xd1df9000 0 0x1000>, + <0 0xd1dfa000 0 0x2000>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + }; + + apb@d4000000 { + compatible =3D "simple-bus"; + reg =3D <0 0xd4000000 0 0x200000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0 0xd4000000 0x200000>; + + pdma: dma-controller@0 { + compatible =3D "marvell,pdma-1.0"; + reg =3D <0 0x10000>; + interrupts =3D ; + dma-channels =3D <30>; + #dma-cells =3D <2>; + }; + + twsi1: i2c@10800 { + compatible =3D "mrvl,mmp-twsi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x10800 0x64>; + interrupts =3D ; + clocks =3D <&apbc PXA1908_CLK_TWSI1>; + mrvl,i2c-fast-mode; + status =3D "disabled"; + }; + + twsi0: i2c@11000 { + compatible =3D "mrvl,mmp-twsi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x11000 0x64>; + interrupts =3D ; + clocks =3D <&apbc PXA1908_CLK_TWSI0>; + mrvl,i2c-fast-mode; + status =3D "disabled"; + }; + + twsi3: i2c@13800 { + compatible =3D "mrvl,mmp-twsi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x13800 0x64>; + interrupts =3D ; + clocks =3D <&apbc PXA1908_CLK_TWSI3>; + mrvl,i2c-fast-mode; + status =3D "disabled"; + }; + + apbc: clock-controller@15000 { + compatible =3D "marvell,pxa1908-apbc"; + reg =3D <0x15000 0x1000>; + #clock-cells =3D <1>; + }; + + uart0: serial@17000 { + compatible =3D "mrvl,mmp-uart"; + reg =3D <0x17000 0x1000>; + interrupts =3D ; + dmas =3D <&pdma 21 1>, + <&pdma 22 1>; + dma-names =3D "rx", "tx"; + clocks =3D <&apbc PXA1908_CLK_UART0>; + }; + + uart1: serial@18000 { + compatible =3D "mrvl,mmp-uart"; + reg =3D <0x18000 0x1000>; + interrupts =3D ; + dmas =3D <&pdma 23 1>, + <&pdma 24 1>; + dma-names =3D "rx", "tx"; + clocks =3D <&apbc PXA1908_CLK_UART1>; + }; + + gpio: gpio@19000 { + compatible =3D "marvell,mmp-gpio"; + reg =3D <0x19000 0x800>; + #address-cells =3D <1>; + #size-cells =3D <1>; + gpio-controller; + #gpio-cells =3D <2>; + clocks =3D <&apbc PXA1908_CLK_GPIO>; + interrupts =3D ; + interrupt-names =3D "gpio_mux"; + interrupt-controller; + #interrupt-cells =3D <2>; + ranges =3D <0 0x19000 0x800>; + + gpio@0 { + reg =3D <0x0 0x4>; + }; + + gpio@4 { + reg =3D <0x4 0x4>; + }; + + gpio@8 { + reg =3D <0x8 0x4>; + }; + + gpio@100 { + reg =3D <0x100 0x4>; + }; + }; + + pmx: pinmux@1e000 { + compatible =3D "pinconf-single"; + reg =3D <0x1e000 0x330>; + #address-cells =3D <1>; + #size-cells =3D <1>; + #gpio-range-cells =3D <3>; + ranges; + + #pinctrl-cells =3D <1>; + pinctrl-single,register-width =3D <32>; + pinctrl-single,function-mask =3D <7>; + + range: gpio-range { + #pinctrl-single,gpio-range-cells =3D <3>; + }; + }; + + uart2: serial@36000 { + compatible =3D "mrvl,mmp-uart"; + reg =3D <0x36000 0x1000>; + interrupts =3D ; + dmas =3D <&pdma 4 1>, + <&pdma 5 1>; + dma-names =3D "rx", "tx"; + clocks =3D <&apbcp PXA1908_CLK_UART2>; + }; + + twsi2: i2c@37000 { + compatible =3D "mrvl,mmp-twsi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x37000 0x64>; + interrupts =3D ; + clocks =3D <&apbcp PXA1908_CLK_TWSI2>; + mrvl,i2c-fast-mode; + status =3D "disabled"; + }; + + apbcp: clock-controller@3b000 { + compatible =3D "marvell,pxa1908-apbcp"; + reg =3D <0x3b000 0x1000>; + #clock-cells =3D <1>; + }; + + mpmu: clock-controller@50000 { + compatible =3D "marvell,pxa1908-mpmu"; + reg =3D <0x50000 0x1000>; + #clock-cells =3D <1>; + }; + }; + + axi@d4200000 { + compatible =3D "simple-bus"; + reg =3D <0 0xd4200000 0 0x200000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0 0xd4200000 0x200000>; + + usbphy: phy@7000 { + compatible =3D "marvell,pxa1928-usb-phy"; + reg =3D <0x7000 0x200>; + clocks =3D <&apmu PXA1908_CLK_USB>; + #phy-cells =3D <0>; + }; + + usb: usb@8000 { + compatible =3D "chipidea,usb2"; + reg =3D <0x8000 0x200>; + interrupts =3D ; + clocks =3D <&apmu PXA1908_CLK_USB>; + phys =3D <&usbphy>; + phy-names =3D "usb-phy"; + }; + + sdh0: mmc@80000 { + compatible =3D "mrvl,pxav3-mmc"; + reg =3D <0x80000 0x120>; + interrupts =3D ; + clocks =3D <&apmu PXA1908_CLK_SDH0>; + clock-names =3D "io"; + mrvl,clk-delay-cycles =3D <31>; + }; + + sdh1: mmc@80800 { + compatible =3D "mrvl,pxav3-mmc"; + reg =3D <0x80800 0x120>; + interrupts =3D ; + clocks =3D <&apmu PXA1908_CLK_SDH1>; + clock-names =3D "io"; + mrvl,clk-delay-cycles =3D <31>; + }; + + sdh2: mmc@81000 { + compatible =3D "mrvl,pxav3-mmc"; + reg =3D <0x81000 0x120>; + interrupts =3D ; + clocks =3D <&apmu PXA1908_CLK_SDH2>; + clock-names =3D "io"; + mrvl,clk-delay-cycles =3D <31>; + }; + + apmu: clock-controller@82800 { + compatible =3D "marvell,pxa1908-apmu"; + reg =3D <0x82800 0x400>; + #clock-cells =3D <1>; + }; + }; + }; +}; --=20 2.41.0 From nobody Fri Sep 20 14:30:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBA9DC0015E for ; Fri, 21 Jul 2023 21:13:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230133AbjGUVNx (ORCPT ); Fri, 21 Jul 2023 17:13:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37576 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229689AbjGUVNp (ORCPT ); Fri, 21 Jul 2023 17:13:45 -0400 Received: from mx.skole.hr (mx2.hosting.skole.hr [161.53.165.186]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F5B83A80; Fri, 21 Jul 2023 14:13:16 -0700 (PDT) Received: from mx2.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id A0D21880C6; Fri, 21 Jul 2023 23:06:15 +0200 (CEST) From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= To: =?UTF-8?q?Duje=20Mihanovi=C4=87?= , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, afaerber@suse.com Subject: [PATCH 09/10] dt-bindings: marvell: Document PXA1908 SoC Date: Fri, 21 Jul 2023 22:37:51 +0200 Message-ID: <20230721210042.21535-10-duje.mihanovic@skole.hr> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230721210042.21535-1-duje.mihanovic@skole.hr> References: <20230721210042.21535-1-duje.mihanovic@skole.hr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add dt bindings and documentation for Marvell PXA1908 SoC. Signed-off-by: Duje Mihanovi=C4=87 --- .../bindings/arm/marvell/marvell,pxa1908.yaml | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,p= xa1908.yaml diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.= yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml new file mode 100644 index 000000000000..085d238129ad --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/pxa1908.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell PXA1908 Platforms + +maintainers: + - Duje Mihanovi=C4=87 + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - samsung,coreprimevelte + - const: marvell,pxa1908 + + pxa,rev-id: + $ref: /schemas/types.yaml#/definitions/uint32-array + oneOf: + - items: + - description: Board ID + - description: Board revision + description: | + Some bootloaders use this property to determine whether the provided= dt + blob is compatible with a specific device. For example, Samsung's S-= Boot + is known to require this property. + +additionalProperties: false --=20 2.41.0 From nobody Fri Sep 20 14:30:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6549C00528 for ; Fri, 21 Jul 2023 21:12:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229663AbjGUVMT (ORCPT ); Fri, 21 Jul 2023 17:12:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35598 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231142AbjGUVMF (ORCPT ); Fri, 21 Jul 2023 17:12:05 -0400 Received: from mx.skole.hr (mx1.hosting.skole.hr [161.53.165.185]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB148359C; Fri, 21 Jul 2023 14:12:03 -0700 (PDT) Received: from mx1.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id D413086D15; Fri, 21 Jul 2023 23:06:15 +0200 (CEST) From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= To: linux-kernel@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, afaerber@suse.com, =?UTF-8?q?Duje=20Mihanovi=C4=87?= Subject: [PATCH 10/10] MAINTAINERS: add myself as Marvell PXA1908 maintainer Date: Fri, 21 Jul 2023 22:37:52 +0200 Message-ID: <20230721210042.21535-11-duje.mihanovic@skole.hr> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230721210042.21535-1-duje.mihanovic@skole.hr> References: <20230721210042.21535-1-duje.mihanovic@skole.hr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add myself as the maintainer for Marvell PXA1908 SoC support. Signed-off-by: Duje Mihanovi=C4=87 --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index aee340630eca..263fd6db0f7b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2297,6 +2297,16 @@ F: drivers/irqchip/irq-mvebu-* F: drivers/pinctrl/mvebu/ F: drivers/rtc/rtc-armada38x.c =20 +ARM/Marvell PXA1908 SOC support +M: Duje Mihanovi=C4=87 +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +T: git https://gitlab.com/LegoLivesMatter/linux +F: Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml +F: arch/arm64/boot/dts/marvell/pxa1908* +F: drivers/clk/mmp/clk-of-pxa1908.c +F: include/dt-bindings/clock/marvell,pxa1908.h + ARM/Mediatek RTC DRIVER M: Eddie Huang M: Sean Wang --=20 2.41.0