From nobody Thu May 16 05:09:41 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7C38C0015E for ; Thu, 20 Jul 2023 11:15:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229808AbjGTLPY (ORCPT ); Thu, 20 Jul 2023 07:15:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230305AbjGTLPT (ORCPT ); Thu, 20 Jul 2023 07:15:19 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 543DE2690; Thu, 20 Jul 2023 04:15:15 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 4A21824E0DF; Thu, 20 Jul 2023 19:15:12 +0800 (CST) Received: from EXMBX062.cuchost.com (172.16.6.62) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 20 Jul 2023 19:15:12 +0800 Received: from starfive-sdk.starfivetech.com (171.223.208.138) by EXMBX062.cuchost.com (172.16.6.62) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 20 Jul 2023 19:15:10 +0800 From: Samin Guo To: , , , Peter Geis , Frank CC: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Andrew Lunn , Heiner Kallweit , "Russell King" , Samin Guo , "Yanhong Wang" Subject: [PATCH v5 1/2] dt-bindings: net: motorcomm: Add pad driver strength cfg Date: Thu, 20 Jul 2023 19:15:08 +0800 Message-ID: <20230720111509.21843-2-samin.guo@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230720111509.21843-1-samin.guo@starfivetech.com> References: <20230720111509.21843-1-samin.guo@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX062.cuchost.com (172.16.6.62) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The motorcomm phy (YT8531) supports the ability to adjust the drive strength of the rx_clk/rx_data. The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage can be configured with hardware pull-up resistors to match the SOC voltage (usually 1.8V). The software can read the registers 0xA001 obtain the current LDO voltage value. Reviewed-by: Hal Feng Signed-off-by: Samin Guo Reviewed-by: Andrew Lunn Reviewed-by: Conor Dooley --- .../bindings/net/motorcomm,yt8xxx.yaml | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml b/= Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml index 157e3bbcaf6f..605be74f8556 100644 --- a/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml +++ b/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml @@ -52,6 +52,40 @@ properties: for a timer. type: boolean =20 + motorcomm,rx-clk-drv-microamp: + description: | + drive strength of rx_clk rgmii pad. + The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage= can + be configured with hardware pull-up resistors to match the SOC volta= ge + (usually 1.8V). + The software can read the registers to obtain the LDO voltage and co= nfigure + the legal drive strength(curren). + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D + | voltage | curren Available (uA) | + | 1.8v | 1200 2100 2700 2910 3110 3600 3970 4350 | + | 3.3v | 3070 4080 4370 4680 5020 5450 5740 6140 | + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D + enum: [ 1200, 2100, 2700, 2910, 3070, 3110, 3600, 3970, + 4080, 4350, 4370, 4680, 5020, 5450, 5740, 6140 ] + default: 2910 + + motorcomm,rx-data-drv-microamp: + description: | + drive strength of rx_data/rx_ctl rgmii pad. + The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage= can + be configured with hardware pull-up resistors to match the SOC volta= ge + (usually 1.8V). + The software can read the registers to obtain the LDO voltage and co= nfigure + the legal drive strength(curren). + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D + | voltage | curren Available (uA) | + | 1.8v | 1200 2100 2700 2910 3110 3600 3970 4350 | + | 3.3v | 3070 4080 4370 4680 5020 5450 5740 6140 | + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D + enum: [ 1200, 2100, 2700, 2910, 3070, 3110, 3600, 3970, + 4080, 4350, 4370, 4680, 5020, 5450, 5740, 6140 ] + default: 2910 + motorcomm,tx-clk-adj-enabled: description: | This configuration is mainly to adapt to VF2 with JH7110 SoC. --=20 2.17.1 From nobody Thu May 16 05:09:41 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5682AEB64DA for ; Thu, 20 Jul 2023 11:15:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230370AbjGTLPg (ORCPT ); Thu, 20 Jul 2023 07:15:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230292AbjGTLP1 (ORCPT ); Thu, 20 Jul 2023 07:15:27 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE45426B2; Thu, 20 Jul 2023 04:15:21 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 1DB0524E16E; Thu, 20 Jul 2023 19:15:13 +0800 (CST) Received: from EXMBX062.cuchost.com (172.16.6.62) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 20 Jul 2023 19:15:13 +0800 Received: from starfive-sdk.starfivetech.com (171.223.208.138) by EXMBX062.cuchost.com (172.16.6.62) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 20 Jul 2023 19:15:11 +0800 From: Samin Guo To: , , , Peter Geis , Frank CC: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Andrew Lunn , Heiner Kallweit , "Russell King" , Samin Guo , "Yanhong Wang" Subject: [PATCH v5 2/2] net: phy: motorcomm: Add pad drive strength cfg support Date: Thu, 20 Jul 2023 19:15:09 +0800 Message-ID: <20230720111509.21843-3-samin.guo@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230720111509.21843-1-samin.guo@starfivetech.com> References: <20230720111509.21843-1-samin.guo@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX062.cuchost.com (172.16.6.62) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The motorcomm phy (YT8531) supports the ability to adjust the drive strength of the rx_clk/rx_data, and the default strength may not be suitable for all boards. So add configurable options to better match the boards.(e.g. StarFive VisionFive 2) When we configure the drive strength, we need to read the current LDO voltage value to ensure that it is a legal value at that LDO voltage. Reviewed-by: Hal Feng Signed-off-by: Samin Guo Reviewed-by: Andrew Lunn --- drivers/net/phy/motorcomm.c | 118 ++++++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index 2fa5a90e073b..7a11fdb687cc 100644 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -163,6 +163,10 @@ =20 #define YT8521_CHIP_CONFIG_REG 0xA001 #define YT8521_CCR_SW_RST BIT(15) +#define YT8531_RGMII_LDO_VOL_MASK GENMASK(5, 4) +#define YT8531_LDO_VOL_3V3 0x0 +#define YT8531_LDO_VOL_1V8 0x2 + /* 1b0 disable 1.9ns rxc clock delay *default* * 1b1 enable 1.9ns rxc clock delay */ @@ -236,6 +240,12 @@ */ #define YTPHY_WCR_TYPE_PULSE BIT(0) =20 +#define YTPHY_PAD_DRIVE_STRENGTH_REG 0xA010 +#define YT8531_RGMII_RXC_DS_MASK GENMASK(15, 13) +#define YT8531_RGMII_RXD_DS_HI_MASK BIT(12) /* Bit 2 of rxd_ds */ +#define YT8531_RGMII_RXD_DS_LOW_MASK GENMASK(5, 4) /* Bit 1/0 of rxd_ds */ +#define YT8531_RGMII_RX_DS_DEFAULT 0x3 + #define YTPHY_SYNCE_CFG_REG 0xA012 #define YT8521_SCR_SYNCE_ENABLE BIT(5) /* 1b0 output 25m clock @@ -834,6 +844,110 @@ static int ytphy_rgmii_clk_delay_config_with_lock(str= uct phy_device *phydev) return ret; } =20 +/** + * struct ytphy_ldo_vol_map - map a current value to a register value + * @vol: ldo voltage + * @ds: value in the register + * @cur: value in device configuration + */ +struct ytphy_ldo_vol_map { + u32 vol; + u32 ds; + u32 cur; +}; + +static const struct ytphy_ldo_vol_map yt8531_ldo_vol[] =3D { + {.vol =3D YT8531_LDO_VOL_1V8, .ds =3D 0, .cur =3D 1200}, + {.vol =3D YT8531_LDO_VOL_1V8, .ds =3D 1, .cur =3D 2100}, + {.vol =3D YT8531_LDO_VOL_1V8, .ds =3D 2, .cur =3D 2700}, + {.vol =3D YT8531_LDO_VOL_1V8, .ds =3D 3, .cur =3D 2910}, + {.vol =3D YT8531_LDO_VOL_1V8, .ds =3D 4, .cur =3D 3110}, + {.vol =3D YT8531_LDO_VOL_1V8, .ds =3D 5, .cur =3D 3600}, + {.vol =3D YT8531_LDO_VOL_1V8, .ds =3D 6, .cur =3D 3970}, + {.vol =3D YT8531_LDO_VOL_1V8, .ds =3D 7, .cur =3D 4350}, + {.vol =3D YT8531_LDO_VOL_3V3, .ds =3D 0, .cur =3D 3070}, + {.vol =3D YT8531_LDO_VOL_3V3, .ds =3D 1, .cur =3D 4080}, + {.vol =3D YT8531_LDO_VOL_3V3, .ds =3D 2, .cur =3D 4370}, + {.vol =3D YT8531_LDO_VOL_3V3, .ds =3D 3, .cur =3D 4680}, + {.vol =3D YT8531_LDO_VOL_3V3, .ds =3D 4, .cur =3D 5020}, + {.vol =3D YT8531_LDO_VOL_3V3, .ds =3D 5, .cur =3D 5450}, + {.vol =3D YT8531_LDO_VOL_3V3, .ds =3D 6, .cur =3D 5740}, + {.vol =3D YT8531_LDO_VOL_3V3, .ds =3D 7, .cur =3D 6140}, +}; + +static u32 yt8531_get_ldo_vol(struct phy_device *phydev) +{ + u32 val; + + val =3D ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); + val =3D FIELD_GET(YT8531_RGMII_LDO_VOL_MASK, val); + + return val <=3D YT8531_LDO_VOL_1V8 ? val : YT8531_LDO_VOL_1V8; +} + +static int yt8531_get_ds_map(struct phy_device *phydev, u32 cur) +{ + u32 vol; + int i; + + vol =3D yt8531_get_ldo_vol(phydev); + for (i =3D 0; i < ARRAY_SIZE(yt8531_ldo_vol); i++) { + if (yt8531_ldo_vol[i].vol =3D=3D vol && yt8531_ldo_vol[i].cur =3D=3D cur) + return yt8531_ldo_vol[i].ds; + } + + return -EINVAL; +} + +static int yt8531_set_ds(struct phy_device *phydev) +{ + struct device_node *node =3D phydev->mdio.dev.of_node; + u32 ds_field_low, ds_field_hi, val; + int ret, ds; + + /* set rgmii rx clk driver strength */ + if (!of_property_read_u32(node, "motorcomm,rx-clk-drv-microamp", &val)) { + ds =3D yt8531_get_ds_map(phydev, val); + if (ds < 0) + return dev_err_probe(&phydev->mdio.dev, ds, + "No matching current value was found.\n"); + } else { + ds =3D YT8531_RGMII_RX_DS_DEFAULT; + } + + ret =3D ytphy_modify_ext_with_lock(phydev, + YTPHY_PAD_DRIVE_STRENGTH_REG, + YT8531_RGMII_RXC_DS_MASK, + FIELD_PREP(YT8531_RGMII_RXC_DS_MASK, ds)); + if (ret < 0) + return ret; + + /* set rgmii rx data driver strength */ + if (!of_property_read_u32(node, "motorcomm,rx-data-drv-microamp", &val)) { + ds =3D yt8531_get_ds_map(phydev, val); + if (ds < 0) + return dev_err_probe(&phydev->mdio.dev, ds, + "No matching current value was found.\n"); + } else { + ds =3D YT8531_RGMII_RX_DS_DEFAULT; + } + + ds_field_hi =3D FIELD_GET(BIT(2), ds); + ds_field_hi =3D FIELD_PREP(YT8531_RGMII_RXD_DS_HI_MASK, ds_field_hi); + + ds_field_low =3D FIELD_GET(GENMASK(1, 0), ds); + ds_field_low =3D FIELD_PREP(YT8531_RGMII_RXD_DS_LOW_MASK, ds_field_low); + + ret =3D ytphy_modify_ext_with_lock(phydev, + YTPHY_PAD_DRIVE_STRENGTH_REG, + YT8531_RGMII_RXD_DS_LOW_MASK | YT8531_RGMII_RXD_DS_HI_MASK, + ds_field_low | ds_field_hi); + if (ret < 0) + return ret; + + return 0; +} + /** * yt8521_probe() - read chip config then set suitable polling_mode * @phydev: a pointer to a &struct phy_device @@ -1518,6 +1632,10 @@ static int yt8531_config_init(struct phy_device *phy= dev) return ret; } =20 + ret =3D yt8531_set_ds(phydev); + if (ret < 0) + return ret; + return 0; } =20 --=20 2.17.1