From nobody Fri Sep 20 14:44:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C306EB64DA for ; Thu, 20 Jul 2023 08:26:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231723AbjGTI0J (ORCPT ); Thu, 20 Jul 2023 04:26:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231617AbjGTI0F (ORCPT ); Thu, 20 Jul 2023 04:26:05 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D93132686; Thu, 20 Jul 2023 01:26:03 -0700 (PDT) X-UUID: 0e4addd626d711ee9cb5633481061a41-20230720 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=x3Ef2HXAMqtZCcHsQB0m7y6VJp+SmT8fZ8z5MnEgAEo=; b=myAoEOP6zzVpJrsuN0V6Rj6/JaKVz7fURFpK9Ifj58uLnwbfPZ4rgOgfKbiH4Q9g8KfRzhRC3z3oVaqn2Vs6OhZpxBowGzfFpsxjbGvkQy3C21P+FqUjs4ksQzvuo3mqHoKVdsmYH/tOcHV/tvVcYZbddE91WZbbNWDFUhzfJMs=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.28,REQID:0fcc76b0-74bd-46a0-9c94-9952dd5c21c8,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:176cd25,CLOUDID:f039d0dc-dc79-4898-9235-1134b97257a8,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_ULN,TF_CID_SPAM_SNR X-UUID: 0e4addd626d711ee9cb5633481061a41-20230720 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 9689820; Thu, 20 Jul 2023 16:25:59 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 20 Jul 2023 16:25:58 +0800 Received: from mszsdhlt06.gcn.mediatek.inc (10.16.6.206) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 20 Jul 2023 16:25:57 +0800 From: Shuijing Li To: , , , , , , , , , CC: , , , , , , Shuijing Li Subject: [PATCH v3,3/3] drm/mediatek: dp: Add the audio divider to mtk_dp_data struct Date: Thu, 20 Jul 2023 16:26:04 +0800 Message-ID: <20230720082604.18618-4-shuijing.li@mediatek.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230720082604.18618-1-shuijing.li@mediatek.com> References: <20230720082604.18618-1-shuijing.li@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Due to the difference of HW, different dividers need to be set. Signed-off-by: Shuijing Li Signed-off-by: Jitao Shi Reviewed-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno --- Changes in v3: Separate these two things into two different patches. per suggestion from the previous thread: https://lore.kernel.org/lkml/e2ad22bcba31797f38a12a488d4246a01bf0cb2e.camel= @mediatek.com/ Changes in v2: - change the variables' name to be more descriptive - add a comment that describes the function of mtk_dp_audio_sample_arrange - reduce indentation by doing the inverse check - add a definition of some bits - add support for mediatek, mt8188-edp-tx per suggestion from the previous thread: https://lore.kernel.org/lkml/ac0fcec9-a2fe-06cc-c727-189ef7babe9c@collabora= .com/ --- drivers/gpu/drm/mediatek/mtk_dp.c | 7 ++++++- drivers/gpu/drm/mediatek/mtk_dp_reg.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/m= tk_dp.c index d8cda83d6fef..8e1a13ab2ba2 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -140,6 +140,7 @@ struct mtk_dp_data { const struct mtk_dp_efuse_fmt *efuse_fmt; bool audio_supported; bool audio_pkt_in_hblank_area; + u16 audio_m_div2_bit; }; =20 static const struct mtk_dp_efuse_fmt mt8195_edp_efuse_fmt[MTK_DP_CAL_MAX] = =3D { @@ -648,7 +649,7 @@ static void mtk_dp_audio_sdp_asp_set_channels(struct mt= k_dp *mtk_dp, static void mtk_dp_audio_set_divider(struct mtk_dp *mtk_dp) { mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30BC, - AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, + mtk_dp->data->audio_m_div2_bit, AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK); } =20 @@ -2636,6 +2637,7 @@ static const struct mtk_dp_data mt8188_edp_data =3D { .efuse_fmt =3D mt8195_edp_efuse_fmt, .audio_supported =3D false, .audio_pkt_in_hblank_area =3D false, + .audio_m_div2_bit =3D MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, }; =20 static const struct mtk_dp_data mt8188_dp_data =3D { @@ -2644,6 +2646,7 @@ static const struct mtk_dp_data mt8188_dp_data =3D { .efuse_fmt =3D mt8195_dp_efuse_fmt, .audio_supported =3D true, .audio_pkt_in_hblank_area =3D true, + .audio_m_div2_bit =3D MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, }; =20 static const struct mtk_dp_data mt8195_edp_data =3D { @@ -2652,6 +2655,7 @@ static const struct mtk_dp_data mt8195_edp_data =3D { .efuse_fmt =3D mt8195_edp_efuse_fmt, .audio_supported =3D false, .audio_pkt_in_hblank_area =3D false, + .audio_m_div2_bit =3D AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, }; =20 static const struct mtk_dp_data mt8195_dp_data =3D { @@ -2660,6 +2664,7 @@ static const struct mtk_dp_data mt8195_dp_data =3D { .efuse_fmt =3D mt8195_dp_efuse_fmt, .audio_supported =3D true, .audio_pkt_in_hblank_area =3D false, + .audio_m_div2_bit =3D AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, }; =20 static const struct of_device_id mtk_dp_of_match[] =3D { diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediat= ek/mtk_dp_reg.h index f38d6ff12afe..6d7f0405867e 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h @@ -162,6 +162,7 @@ #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << 8) #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4 (2 << 8) #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8 (3 << 8) +#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (4 << 8) #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (5 << 8) #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4 (6 << 8) #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8 (7 << 8) --=20 2.40.1