From nobody Mon Feb 9 04:29:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 749A9C0015E for ; Wed, 19 Jul 2023 11:37:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229797AbjGSLhX (ORCPT ); Wed, 19 Jul 2023 07:37:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230094AbjGSLhU (ORCPT ); Wed, 19 Jul 2023 07:37:20 -0400 Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F2582681 for ; Wed, 19 Jul 2023 04:36:56 -0700 (PDT) Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-6686c74183cso6769077b3a.1 for ; Wed, 19 Jul 2023 04:36:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1689766598; x=1690371398; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SmhrC0bwxM+FgEIaLxjftU83GlCxoN1AibJYYkq1R/U=; b=lp2DZv5IgjB3gdal4giL1P9E0hSEwJaOZu3pdCE4vHillC5p9QPCUJEAXfPNlBeCuF HPAUkexFRLL/IHBiaWqQ3JwdZ2kJDHMpoE9fe0/s+d6tiGzmIQGO1aky4dvENamr9sHt DzMPTfF3fI//gdFiOYQpCLdQT+XEJ9LibfP9Xu8afbIpEMKaxCpOP2KYyiRAN3vQgqVo yBLyzI6Y+mGxhc19a0iQbjKlaB6Fe7mSZPNyk1PFdkCG1y1AhsAl7K/GBrbDl9r3ICS5 AMb9StivjA1m7kDkexQgA6Wn2EUDAePd1sNeYB7TSugUco4EEl3BPyG1O9WcRMtLhZDY sXVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689766598; x=1690371398; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SmhrC0bwxM+FgEIaLxjftU83GlCxoN1AibJYYkq1R/U=; b=FR7r4z4ty2BCPFbrAShtNAgJaXIIUGuuoMf+ed2dxsCLZ248ImfTAVsKgF8tYfAVr0 1FyWNoXOBknMZQLg/K510nrDfPLZCI9vBgFwwHNere1hHTkeBEqx276Hwcn7BvyzQyDh hPPui9Xs1ZLJvmZJywecNvdr4LHfL5REDvmTljlT5vaAOcEGOH0h50tFHawxVahi45IZ 0AyBhSWX24Gn0GXhgF2QH3AOERSnUN+73qhOrJ1zh1U3iiES/oUs5D127eakmJHiBeZm x0VeBhxBkR48tCUv0hq8hORz0DvOqwMbpSPvGXmcGXCvXbxMxnV/jp03kKQBVZ/8iw53 MAJg== X-Gm-Message-State: ABy/qLbKLhqZQbzASeXftd8RGLkEP0Bk+7InYvPv+5/+gto4DXffNlkS GiHnGo/aP51zsgf6dpwpSgE/JA== X-Google-Smtp-Source: APBJJlGvpSFmoDtt4AekGZiAmwsfK05xLAsO9n1vYhmfozZlBCZoZsjyw9FqGOyglUcx+lO0ZkkWUw== X-Received: by 2002:a05:6a00:997:b0:66c:a45:f00b with SMTP id u23-20020a056a00099700b0066c0a45f00bmr24803863pfg.23.1689766597626; Wed, 19 Jul 2023 04:36:37 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.86.130]) by smtp.gmail.com with ESMTPSA id j10-20020aa783ca000000b00669c99d05fasm3050408pfn.150.2023.07.19.04.36.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jul 2023 04:36:37 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v6 08/14] irqchip/riscv-imsic: Add support for platform MSI irqdomain Date: Wed, 19 Jul 2023 17:05:36 +0530 Message-Id: <20230719113542.2293295-9-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230719113542.2293295-1-apatel@ventanamicro.com> References: <20230719113542.2293295-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Linux platform MSI support requires a platform MSI irqdomain so let us add a platform irqchip driver for RISC-V IMSIC which provides a base IRQ domain and platform MSI domain. This driver assumes that the IMSIC state is already initialized by the IMSIC early driver. Signed-off-by: Anup Patel --- drivers/irqchip/Makefile | 2 +- drivers/irqchip/irq-riscv-imsic-platform.c | 280 +++++++++++++++++++++ 2 files changed, 281 insertions(+), 1 deletion(-) create mode 100644 drivers/irqchip/irq-riscv-imsic-platform.c diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index d714724387ce..abca445a3229 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -95,7 +95,7 @@ obj-$(CONFIG_QCOM_MPM) +=3D irq-qcom-mpm.o obj-$(CONFIG_CSKY_MPINTC) +=3D irq-csky-mpintc.o obj-$(CONFIG_CSKY_APB_INTC) +=3D irq-csky-apb-intc.o obj-$(CONFIG_RISCV_INTC) +=3D irq-riscv-intc.o -obj-$(CONFIG_RISCV_IMSIC) +=3D irq-riscv-imsic-state.o irq-riscv-imsic-ea= rly.o +obj-$(CONFIG_RISCV_IMSIC) +=3D irq-riscv-imsic-state.o irq-riscv-imsic-ea= rly.o irq-riscv-imsic-platform.o obj-$(CONFIG_SIFIVE_PLIC) +=3D irq-sifive-plic.o obj-$(CONFIG_IMX_IRQSTEER) +=3D irq-imx-irqsteer.o obj-$(CONFIG_IMX_INTMUX) +=3D irq-imx-intmux.o diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/i= rq-riscv-imsic-platform.c new file mode 100644 index 000000000000..db896b6e51ff --- /dev/null +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "irq-riscv-imsic-state.h" + +static int imsic_cpu_page_phys(unsigned int cpu, + unsigned int guest_index, + phys_addr_t *out_msi_pa) +{ + struct imsic_global_config *global; + struct imsic_local_config *local; + + global =3D &imsic->global; + local =3D per_cpu_ptr(global->local, cpu); + + if (BIT(global->guest_index_bits) <=3D guest_index) + return -EINVAL; + + if (out_msi_pa) + *out_msi_pa =3D local->msi_pa + + (guest_index * IMSIC_MMIO_PAGE_SZ); + + return 0; +} + +static int imsic_get_cpu(const struct cpumask *mask_val, bool force, + unsigned int *out_target_cpu) +{ + unsigned int cpu; + + if (force) + cpu =3D cpumask_first(mask_val); + else + cpu =3D cpumask_any_and(mask_val, cpu_online_mask); + + if (cpu >=3D nr_cpu_ids) + return -EINVAL; + + if (out_target_cpu) + *out_target_cpu =3D cpu; + + return 0; +} + +static void imsic_irq_mask(struct irq_data *d) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&imsic->ids_lock, flags); + bitmap_clear(imsic->ids_enabled_bimap, d->hwirq, 1); + __imsic_id_disable(d->hwirq); + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); + + imsic_ids_remote_sync(); +} + +static void imsic_irq_unmask(struct irq_data *d) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&imsic->ids_lock, flags); + bitmap_set(imsic->ids_enabled_bimap, d->hwirq, 1); + __imsic_id_enable(d->hwirq); + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); + + imsic_ids_remote_sync(); +} + +static void imsic_irq_compose_msi_msg(struct irq_data *d, + struct msi_msg *msg) +{ + phys_addr_t msi_addr; + unsigned int cpu; + int err; + + cpu =3D imsic_id_get_target(d->hwirq); + if (WARN_ON(cpu =3D=3D UINT_MAX)) + return; + + err =3D imsic_cpu_page_phys(cpu, 0, &msi_addr); + if (WARN_ON(err)) + return; + + msg->address_hi =3D upper_32_bits(msi_addr); + msg->address_lo =3D lower_32_bits(msi_addr); + msg->data =3D d->hwirq; +} + +#ifdef CONFIG_SMP +static int imsic_irq_set_affinity(struct irq_data *d, + const struct cpumask *mask_val, + bool force) +{ + unsigned int target_cpu; + int rc; + + rc =3D imsic_get_cpu(mask_val, force, &target_cpu); + if (rc) + return rc; + + imsic_id_set_target(d->hwirq, target_cpu); + irq_data_update_effective_affinity(d, cpumask_of(target_cpu)); + + return IRQ_SET_MASK_OK; +} +#endif + +static struct irq_chip imsic_irq_base_chip =3D { + .name =3D "IMSIC-BASE", + .irq_mask =3D imsic_irq_mask, + .irq_unmask =3D imsic_irq_unmask, +#ifdef CONFIG_SMP + .irq_set_affinity =3D imsic_irq_set_affinity, +#endif + .irq_compose_msi_msg =3D imsic_irq_compose_msi_msg, + .flags =3D IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND, +}; + +static int imsic_irq_domain_alloc(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs, + void *args) +{ + int i, hwirq, err =3D 0; + unsigned int cpu; + + err =3D imsic_get_cpu(cpu_online_mask, false, &cpu); + if (err) + return err; + + hwirq =3D imsic_ids_alloc(get_count_order(nr_irqs)); + if (hwirq < 0) + return hwirq; + + for (i =3D 0; i < nr_irqs; i++) { + imsic_id_set_target(hwirq + i, cpu); + irq_domain_set_info(domain, virq + i, hwirq + i, + &imsic_irq_base_chip, imsic, + handle_simple_irq, NULL, NULL); + irq_set_noprobe(virq + i); + irq_set_affinity(virq + i, cpu_online_mask); + /* + * IMSIC does not implement irq_disable() so Linux interrupt + * subsystem will take a lazy approach for disabling an IMSIC + * interrupt. This means IMSIC interrupts are left unmasked + * upon system suspend and interrupts are not processed + * immediately upon system wake up. To tackle this, we disable + * the lazy approach for all IMSIC interrupts. + */ + irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY); + } + + return 0; +} + +static void imsic_irq_domain_free(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs) +{ + struct irq_data *d =3D irq_domain_get_irq_data(domain, virq); + + imsic_ids_free(d->hwirq, get_count_order(nr_irqs)); + irq_domain_free_irqs_parent(domain, virq, nr_irqs); +} + +static const struct irq_domain_ops imsic_base_domain_ops =3D { + .alloc =3D imsic_irq_domain_alloc, + .free =3D imsic_irq_domain_free, +}; + +static struct irq_chip imsic_plat_irq_chip =3D { + .name =3D "IMSIC-PLAT", +}; + +static struct msi_domain_ops imsic_plat_domain_ops =3D { +}; + +static struct msi_domain_info imsic_plat_domain_info =3D { + .flags =3D (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), + .ops =3D &imsic_plat_domain_ops, + .chip =3D &imsic_plat_irq_chip, +}; + +static int __init imsic_irq_domains_init(struct device *dev) +{ + /* Create Base IRQ domain */ + imsic->base_domain =3D irq_domain_create_tree(dev->fwnode, + &imsic_base_domain_ops, imsic); + if (!imsic->base_domain) { + dev_err(dev, "failed to create IMSIC base domain\n"); + return -ENOMEM; + } + irq_domain_update_bus_token(imsic->base_domain, DOMAIN_BUS_NEXUS); + + /* Create Platform MSI domain */ + imsic->plat_domain =3D platform_msi_create_irq_domain(dev->fwnode, + &imsic_plat_domain_info, + imsic->base_domain); + if (!imsic->plat_domain) { + dev_err(dev, "failed to create IMSIC platform domain\n"); + irq_domain_remove(imsic->base_domain); + return -ENOMEM; + } + + return 0; +} + +static int imsic_platform_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct imsic_global_config *global; + int rc; + + if (!imsic) { + dev_err(dev, "early driver not probed\n"); + return -ENODEV; + } + + if (imsic->base_domain) { + dev_err(dev, "irq domain already created\n"); + return -ENODEV; + } + + global =3D &imsic->global; + + /* Initialize IRQ and MSI domains */ + rc =3D imsic_irq_domains_init(dev); + if (rc) { + dev_err(dev, "failed to initialize IRQ and MSI domains\n"); + return rc; + } + + dev_info(dev, " hart-index-bits: %d, guest-index-bits: %d\n", + global->hart_index_bits, global->guest_index_bits); + dev_info(dev, " group-index-bits: %d, group-index-shift: %d\n", + global->group_index_bits, global->group_index_shift); + dev_info(dev, " mapped %d interrupts at base PPN %pa\n", + global->nr_ids, &global->base_addr); + + return 0; +} + +static const struct of_device_id imsic_platform_match[] =3D { + { .compatible =3D "riscv,imsics" }, + {} +}; + +static struct platform_driver imsic_platform_driver =3D { + .driver =3D { + .name =3D "riscv-imsic", + .of_match_table =3D imsic_platform_match, + }, + .probe =3D imsic_platform_probe, +}; + +static int __init imsic_platform_init(void) +{ + /* + * Register IMSIC driver as early as possible so that IMSIC + * platform device is probed as soon as it is created. + */ + return platform_driver_register(&imsic_platform_driver); +} +core_initcall(imsic_platform_init); --=20 2.34.1