From nobody Mon Feb 9 05:53:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26E7CC001DC for ; Wed, 19 Jul 2023 11:36:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230201AbjGSLgn (ORCPT ); Wed, 19 Jul 2023 07:36:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230200AbjGSLgl (ORCPT ); Wed, 19 Jul 2023 07:36:41 -0400 Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06A922102 for ; Wed, 19 Jul 2023 04:36:21 -0700 (PDT) Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-666ecb21f86so6814002b3a.3 for ; Wed, 19 Jul 2023 04:36:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1689766580; x=1690371380; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VKnkNq9mHXbpDqEgJF2mGpUUpQc6aLvqIlFOdqDcBBw=; b=b3x814OpmNemfwa/7a3EGRZg969RSlCcs7g7n0QHErcUHcI/qwHXOVhkdAR57aPLyh gvHRbNxAD3dfrHtEQr182Nix3YX2loXOLz5U2PFCReqGYBEiTY9sisoFZGrV1WqGWVtr vIRFh78M8pxcpDjTDSubtz1IgTLO7ttGlOTsuzjOwiWT52IiOD1QRaEHJykjntxg9kRE yF7l/yqKBaAv/UlefQzJ3PUjhZF30Drc1Ni3Yu8M9hPmaX9TYL7xLSBKAdWNLrKxDie6 Ke4SZaj5seCPaEpc5vtyR/bAR9pDhkNrfNEzsMqA/WX0gymxa0457Ixht/2Spma9jsag j7nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689766580; x=1690371380; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VKnkNq9mHXbpDqEgJF2mGpUUpQc6aLvqIlFOdqDcBBw=; b=DostSxd/ln6tP+DFu45OqFP5UfVnpUTz4rA59sX1ziN+6WEiDYkl9dwEnZgSx0/bwX 2w5N64jV0WCofupBjiGd+TRr68nNqDzckVH00RIK2vSkDZ+ZEC+jMgq8n4Sg3usonXjG gWa0ryBv8NMgUVBWlkP6VNs2VKxcPoXjUEUu5O8BtamIWz20iUxbThSKPdc1M4MQwiUu d2hcvyvCFEb40JgueuNS2g9NdSLSev5NTTlDkteKTl4HKy2QHszCOOkmsY1RlAwBmfgd JRYIPOXt6lpLyW+oFteOyZKev4jPbZIkYAd8icI4H5AXG2hLd3Cl9Vk1g8/m6qW5OTW/ vV7Q== X-Gm-Message-State: ABy/qLbn2iCscX/4Iz3quXFgWM8XSNZly0GeF1ZyM582hSOpJ4TKHVKf wsAo7D+SUH1xM1/SeTeuDvNG2A== X-Google-Smtp-Source: APBJJlEUFsEUJxWRlJHucN1R1tmPLW7mhk8SNC7U14u9x7fB9RKS928Q5C0M9ztl7YwretBf2Q+dbg== X-Received: by 2002:a05:6a00:2d1d:b0:682:5a68:9846 with SMTP id fa29-20020a056a002d1d00b006825a689846mr22089750pfb.16.1689766580537; Wed, 19 Jul 2023 04:36:20 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.86.130]) by smtp.gmail.com with ESMTPSA id j10-20020aa783ca000000b00669c99d05fasm3050408pfn.150.2023.07.19.04.36.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jul 2023 04:36:19 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v6 05/14] irqchip/riscv-intc: Add support for RISC-V AIA Date: Wed, 19 Jul 2023 17:05:33 +0530 Message-Id: <20230719113542.2293295-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230719113542.2293295-1-apatel@ventanamicro.com> References: <20230719113542.2293295-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The RISC-V advanced interrupt architecture (AIA) extends the per-HART local interrupts in following ways: 1. Minimum 64 local interrupts for both RV32 and RV64 2. Ability to process multiple pending local interrupts in same interrupt handler 3. Priority configuration for each local interrupts 4. Special CSRs to configure/access the per-HART MSI controller We add support for #1 and #2 described above in the RISC-V intc driver. Signed-off-by: Anup Patel --- drivers/irqchip/irq-riscv-intc.c | 34 ++++++++++++++++++++++++++------ 1 file changed, 28 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index 4e2704bc25fb..1a0fc87152c5 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -17,6 +17,7 @@ #include #include #include +#include =20 static struct irq_domain *intc_domain; =20 @@ -30,6 +31,15 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *re= gs) generic_handle_domain_irq(intc_domain, cause); } =20 +static asmlinkage void riscv_intc_aia_irq(struct pt_regs *regs) +{ + unsigned long topi; + + while ((topi =3D csr_read(CSR_TOPI))) + generic_handle_domain_irq(intc_domain, + topi >> TOPI_IID_SHIFT); +} + /* * On RISC-V systems local interrupts are masked or unmasked by writing * the SIE (Supervisor Interrupt Enable) CSR. As CSRs can only be written @@ -39,12 +49,18 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *r= egs) =20 static void riscv_intc_irq_mask(struct irq_data *d) { - csr_clear(CSR_IE, BIT(d->hwirq)); + if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >=3D BITS_PER_LONG) + csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); + else + csr_clear(CSR_IE, BIT(d->hwirq)); } =20 static void riscv_intc_irq_unmask(struct irq_data *d) { - csr_set(CSR_IE, BIT(d->hwirq)); + if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >=3D BITS_PER_LONG) + csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); + else + csr_set(CSR_IE, BIT(d->hwirq)); } =20 static void riscv_intc_irq_eoi(struct irq_data *d) @@ -115,16 +131,20 @@ static struct fwnode_handle *riscv_intc_hwnode(void) =20 static int __init riscv_intc_init_common(struct fwnode_handle *fn) { - int rc; + int rc, nr_irqs =3D riscv_isa_extension_available(NULL, SxAIA) ? + 64 : BITS_PER_LONG; =20 - intc_domain =3D irq_domain_create_linear(fn, BITS_PER_LONG, + intc_domain =3D irq_domain_create_linear(fn, nr_irqs, &riscv_intc_domain_ops, NULL); if (!intc_domain) { pr_err("unable to add IRQ domain\n"); return -ENXIO; } =20 - rc =3D set_handle_irq(&riscv_intc_irq); + if (riscv_isa_extension_available(NULL, SxAIA)) + rc =3D set_handle_irq(&riscv_intc_aia_irq); + else + rc =3D set_handle_irq(&riscv_intc_irq); if (rc) { pr_err("failed to set irq handler\n"); return rc; @@ -132,7 +152,9 @@ static int __init riscv_intc_init_common(struct fwnode_= handle *fn) =20 riscv_set_intc_hwnode_fn(riscv_intc_hwnode); =20 - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); + pr_info("%d local interrupts mapped%s\n", + nr_irqs, riscv_isa_extension_available(NULL, SxAIA) ? + " using AIA" : ""); =20 return 0; } --=20 2.34.1