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[2.34.27.228]) by smtp.gmail.com with ESMTPSA id h18-20020a05620a10b200b00765ab6d3e81sm550221qkk.122.2023.07.18.06.03.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jul 2023 06:03:21 -0700 (PDT) From: Marco Pagani To: Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix Cc: Marco Pagani , linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org Subject: [PATCH v10 1/4] fpga: add an initial KUnit suite for the FPGA Manager Date: Tue, 18 Jul 2023 15:03:01 +0200 Message-ID: <20230718130304.87048-2-marpagan@redhat.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230718130304.87048-1-marpagan@redhat.com> References: <20230718130304.87048-1-marpagan@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The suite tests the basic behaviors of the FPGA Manager including programming using a single contiguous buffer and a scatter gather table. Signed-off-by: Marco Pagani Acked-by: Xu Yilun --- drivers/fpga/tests/fpga-mgr-test.c | 327 +++++++++++++++++++++++++++++ 1 file changed, 327 insertions(+) create mode 100644 drivers/fpga/tests/fpga-mgr-test.c diff --git a/drivers/fpga/tests/fpga-mgr-test.c b/drivers/fpga/tests/fpga-m= gr-test.c new file mode 100644 index 000000000000..6acec55b60ce --- /dev/null +++ b/drivers/fpga/tests/fpga-mgr-test.c @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * KUnit test for the FPGA Manager + * + * Copyright (C) 2023 Red Hat, Inc. + * + * Author: Marco Pagani + */ + +#include +#include +#include +#include +#include +#include + +#define HEADER_FILL 'H' +#define IMAGE_FILL 'P' +#define IMAGE_BLOCK 1024 + +#define HEADER_SIZE IMAGE_BLOCK +#define IMAGE_SIZE (IMAGE_BLOCK * 4) + +struct mgr_stats { + bool header_match; + bool image_match; + u32 seq_num; + u32 op_parse_header_seq; + u32 op_write_init_seq; + u32 op_write_seq; + u32 op_write_sg_seq; + u32 op_write_complete_seq; + enum fpga_mgr_states op_parse_header_state; + enum fpga_mgr_states op_write_init_state; + enum fpga_mgr_states op_write_state; + enum fpga_mgr_states op_write_sg_state; + enum fpga_mgr_states op_write_complete_state; +}; + +struct mgr_ctx { + struct fpga_image_info *img_info; + struct fpga_manager *mgr; + struct platform_device *pdev; + struct mgr_stats stats; +}; + +/** + * init_test_buffer() - Allocate and initialize a test image in a buffer. + * @test: KUnit test context object. + * @count: image size in bytes. + * + * Return: pointer to the newly allocated image. + */ +static char *init_test_buffer(struct kunit *test, size_t count) +{ + char *buf; + + KUNIT_ASSERT_GE(test, count, HEADER_SIZE); + + buf =3D kunit_kzalloc(test, count, GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf); + + memset(buf, HEADER_FILL, HEADER_SIZE); + memset(buf + HEADER_SIZE, IMAGE_FILL, count - HEADER_SIZE); + + return buf; +} + +/* + * Check the image header. Do not return an error code if the image check = fails + * since, in this case, it is a failure of the FPGA manager itself, not th= is + * op that tests it. + */ +static int op_parse_header(struct fpga_manager *mgr, struct fpga_image_inf= o *info, + const char *buf, size_t count) +{ + struct mgr_stats *stats =3D mgr->priv; + size_t i; + + stats->op_parse_header_state =3D mgr->state; + stats->op_parse_header_seq =3D stats->seq_num++; + + /* Set header_size and data_size for later */ + info->header_size =3D HEADER_SIZE; + info->data_size =3D info->count - HEADER_SIZE; + + stats->header_match =3D true; + for (i =3D 0; i < info->header_size; i++) { + if (buf[i] !=3D HEADER_FILL) { + stats->header_match =3D false; + break; + } + } + + return 0; +} + +static int op_write_init(struct fpga_manager *mgr, struct fpga_image_info = *info, + const char *buf, size_t count) +{ + struct mgr_stats *stats =3D mgr->priv; + + stats->op_write_init_state =3D mgr->state; + stats->op_write_init_seq =3D stats->seq_num++; + + return 0; +} + +/* + * Check the image data. As with op_parse_header, do not return an error c= ode + * if the image check fails. + */ +static int op_write(struct fpga_manager *mgr, const char *buf, size_t coun= t) +{ + struct mgr_stats *stats =3D mgr->priv; + size_t i; + + stats->op_write_state =3D mgr->state; + stats->op_write_seq =3D stats->seq_num++; + + stats->image_match =3D true; + for (i =3D 0; i < count; i++) { + if (buf[i] !=3D IMAGE_FILL) { + stats->image_match =3D false; + break; + } + } + + return 0; +} + +/* + * Check the image data, but first skip the header since write_sg will get + * the whole image in sg_table. As with op_parse_header, do not return an + * error code if the image check fails. + */ +static int op_write_sg(struct fpga_manager *mgr, struct sg_table *sgt) +{ + struct mgr_stats *stats =3D mgr->priv; + struct sg_mapping_iter miter; + char *img; + size_t i; + + stats->op_write_sg_state =3D mgr->state; + stats->op_write_sg_seq =3D stats->seq_num++; + + stats->image_match =3D true; + sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG); + + if (!sg_miter_skip(&miter, HEADER_SIZE)) { + stats->image_match =3D false; + goto out; + } + + while (sg_miter_next(&miter)) { + img =3D miter.addr; + for (i =3D 0; i < miter.length; i++) { + if (img[i] !=3D IMAGE_FILL) { + stats->image_match =3D false; + goto out; + } + } + } +out: + sg_miter_stop(&miter); + return 0; +} + +static int op_write_complete(struct fpga_manager *mgr, struct fpga_image_i= nfo *info) +{ + struct mgr_stats *stats =3D mgr->priv; + + stats->op_write_complete_state =3D mgr->state; + stats->op_write_complete_seq =3D stats->seq_num++; + + return 0; +} + +/* + * Fake FPGA manager that implements all ops required to check the program= ming + * sequence using a single contiguous buffer and a scatter gather table. + */ +static const struct fpga_manager_ops fake_mgr_ops =3D { + .skip_header =3D true, + .parse_header =3D op_parse_header, + .write_init =3D op_write_init, + .write =3D op_write, + .write_sg =3D op_write_sg, + .write_complete =3D op_write_complete, +}; + +static void fpga_mgr_test_get(struct kunit *test) +{ + struct mgr_ctx *ctx =3D test->priv; + struct fpga_manager *mgr; + + mgr =3D fpga_mgr_get(&ctx->pdev->dev); + KUNIT_EXPECT_PTR_EQ(test, mgr, ctx->mgr); + + fpga_mgr_put(ctx->mgr); +} + +static void fpga_mgr_test_lock(struct kunit *test) +{ + struct mgr_ctx *ctx =3D test->priv; + int ret; + + ret =3D fpga_mgr_lock(ctx->mgr); + KUNIT_EXPECT_EQ(test, ret, 0); + + ret =3D fpga_mgr_lock(ctx->mgr); + KUNIT_EXPECT_EQ(test, ret, -EBUSY); + + fpga_mgr_unlock(ctx->mgr); +} + +/* Check the programming sequence using an image in a buffer */ +static void fpga_mgr_test_img_load_buf(struct kunit *test) +{ + struct mgr_ctx *ctx =3D test->priv; + char *img_buf; + int ret; + + img_buf =3D init_test_buffer(test, IMAGE_SIZE); + + ctx->img_info->count =3D IMAGE_SIZE; + ctx->img_info->buf =3D img_buf; + + ret =3D fpga_mgr_load(ctx->mgr, ctx->img_info); + KUNIT_EXPECT_EQ(test, ret, 0); + + KUNIT_EXPECT_TRUE(test, ctx->stats.header_match); + KUNIT_EXPECT_TRUE(test, ctx->stats.image_match); + + KUNIT_EXPECT_EQ(test, ctx->stats.op_parse_header_state, FPGA_MGR_STATE_PA= RSE_HEADER); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_state, FPGA_MGR_STATE_WRIT= E_INIT); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_state, FPGA_MGR_STATE_WRITE); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_state, FPGA_MGR_STATE_= WRITE_COMPLETE); + + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_seq, ctx->stats.op_parse_h= eader_seq + 1); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_seq, ctx->stats.op_parse_header= _seq + 2); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_seq, ctx->stats.op_par= se_header_seq + 3); +} + +/* Check the programming sequence using an image in a scatter gather table= */ +static void fpga_mgr_test_img_load_sgt(struct kunit *test) +{ + struct mgr_ctx *ctx =3D test->priv; + struct sg_table *sgt; + char *img_buf; + int ret; + + img_buf =3D init_test_buffer(test, IMAGE_SIZE); + + sgt =3D kunit_kzalloc(test, sizeof(*sgt), GFP_KERNEL); + ret =3D sg_alloc_table(sgt, 1, GFP_KERNEL); + KUNIT_ASSERT_EQ(test, ret, 0); + sg_init_one(sgt->sgl, img_buf, IMAGE_SIZE); + + ctx->img_info->sgt =3D sgt; + + ret =3D fpga_mgr_load(ctx->mgr, ctx->img_info); + KUNIT_EXPECT_EQ(test, ret, 0); + + KUNIT_EXPECT_TRUE(test, ctx->stats.header_match); + KUNIT_EXPECT_TRUE(test, ctx->stats.image_match); + + KUNIT_EXPECT_EQ(test, ctx->stats.op_parse_header_state, FPGA_MGR_STATE_PA= RSE_HEADER); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_state, FPGA_MGR_STATE_WRIT= E_INIT); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_sg_state, FPGA_MGR_STATE_WRITE); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_state, FPGA_MGR_STATE_= WRITE_COMPLETE); + + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_seq, ctx->stats.op_parse_h= eader_seq + 1); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_sg_seq, ctx->stats.op_parse_hea= der_seq + 2); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_seq, ctx->stats.op_par= se_header_seq + 3); + + sg_free_table(ctx->img_info->sgt); +} + +static int fpga_mgr_test_init(struct kunit *test) +{ + struct mgr_ctx *ctx; + + ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx); + + ctx->pdev =3D platform_device_register_simple("mgr_pdev", PLATFORM_DEVID_= AUTO, NULL, 0); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->pdev); + + ctx->mgr =3D devm_fpga_mgr_register(&ctx->pdev->dev, "Fake FPGA Manager",= &fake_mgr_ops, + &ctx->stats); + KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->mgr)); + + ctx->img_info =3D fpga_image_info_alloc(&ctx->pdev->dev); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->img_info); + + test->priv =3D ctx; + + return 0; +} + +static void fpga_mgr_test_exit(struct kunit *test) +{ + struct mgr_ctx *ctx =3D test->priv; + + fpga_image_info_free(ctx->img_info); + platform_device_unregister(ctx->pdev); +} + +static struct kunit_case fpga_mgr_test_cases[] =3D { + KUNIT_CASE(fpga_mgr_test_get), + KUNIT_CASE(fpga_mgr_test_lock), + KUNIT_CASE(fpga_mgr_test_img_load_buf), + KUNIT_CASE(fpga_mgr_test_img_load_sgt), + {} +}; + +static struct kunit_suite fpga_mgr_suite =3D { + .name =3D "fpga_mgr", + .init =3D fpga_mgr_test_init, + .exit =3D fpga_mgr_test_exit, + .test_cases =3D fpga_mgr_test_cases, +}; + +kunit_test_suite(fpga_mgr_suite); + +MODULE_LICENSE("GPL"); --=20 2.41.0