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[2.34.27.228]) by smtp.gmail.com with ESMTPSA id h18-20020a05620a10b200b00765ab6d3e81sm550221qkk.122.2023.07.18.06.03.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jul 2023 06:03:21 -0700 (PDT) From: Marco Pagani To: Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix Cc: Marco Pagani , linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org Subject: [PATCH v10 1/4] fpga: add an initial KUnit suite for the FPGA Manager Date: Tue, 18 Jul 2023 15:03:01 +0200 Message-ID: <20230718130304.87048-2-marpagan@redhat.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230718130304.87048-1-marpagan@redhat.com> References: <20230718130304.87048-1-marpagan@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The suite tests the basic behaviors of the FPGA Manager including programming using a single contiguous buffer and a scatter gather table. Signed-off-by: Marco Pagani Acked-by: Xu Yilun --- drivers/fpga/tests/fpga-mgr-test.c | 327 +++++++++++++++++++++++++++++ 1 file changed, 327 insertions(+) create mode 100644 drivers/fpga/tests/fpga-mgr-test.c diff --git a/drivers/fpga/tests/fpga-mgr-test.c b/drivers/fpga/tests/fpga-m= gr-test.c new file mode 100644 index 000000000000..6acec55b60ce --- /dev/null +++ b/drivers/fpga/tests/fpga-mgr-test.c @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * KUnit test for the FPGA Manager + * + * Copyright (C) 2023 Red Hat, Inc. + * + * Author: Marco Pagani + */ + +#include +#include +#include +#include +#include +#include + +#define HEADER_FILL 'H' +#define IMAGE_FILL 'P' +#define IMAGE_BLOCK 1024 + +#define HEADER_SIZE IMAGE_BLOCK +#define IMAGE_SIZE (IMAGE_BLOCK * 4) + +struct mgr_stats { + bool header_match; + bool image_match; + u32 seq_num; + u32 op_parse_header_seq; + u32 op_write_init_seq; + u32 op_write_seq; + u32 op_write_sg_seq; + u32 op_write_complete_seq; + enum fpga_mgr_states op_parse_header_state; + enum fpga_mgr_states op_write_init_state; + enum fpga_mgr_states op_write_state; + enum fpga_mgr_states op_write_sg_state; + enum fpga_mgr_states op_write_complete_state; +}; + +struct mgr_ctx { + struct fpga_image_info *img_info; + struct fpga_manager *mgr; + struct platform_device *pdev; + struct mgr_stats stats; +}; + +/** + * init_test_buffer() - Allocate and initialize a test image in a buffer. + * @test: KUnit test context object. + * @count: image size in bytes. + * + * Return: pointer to the newly allocated image. + */ +static char *init_test_buffer(struct kunit *test, size_t count) +{ + char *buf; + + KUNIT_ASSERT_GE(test, count, HEADER_SIZE); + + buf =3D kunit_kzalloc(test, count, GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf); + + memset(buf, HEADER_FILL, HEADER_SIZE); + memset(buf + HEADER_SIZE, IMAGE_FILL, count - HEADER_SIZE); + + return buf; +} + +/* + * Check the image header. Do not return an error code if the image check = fails + * since, in this case, it is a failure of the FPGA manager itself, not th= is + * op that tests it. + */ +static int op_parse_header(struct fpga_manager *mgr, struct fpga_image_inf= o *info, + const char *buf, size_t count) +{ + struct mgr_stats *stats =3D mgr->priv; + size_t i; + + stats->op_parse_header_state =3D mgr->state; + stats->op_parse_header_seq =3D stats->seq_num++; + + /* Set header_size and data_size for later */ + info->header_size =3D HEADER_SIZE; + info->data_size =3D info->count - HEADER_SIZE; + + stats->header_match =3D true; + for (i =3D 0; i < info->header_size; i++) { + if (buf[i] !=3D HEADER_FILL) { + stats->header_match =3D false; + break; + } + } + + return 0; +} + +static int op_write_init(struct fpga_manager *mgr, struct fpga_image_info = *info, + const char *buf, size_t count) +{ + struct mgr_stats *stats =3D mgr->priv; + + stats->op_write_init_state =3D mgr->state; + stats->op_write_init_seq =3D stats->seq_num++; + + return 0; +} + +/* + * Check the image data. As with op_parse_header, do not return an error c= ode + * if the image check fails. + */ +static int op_write(struct fpga_manager *mgr, const char *buf, size_t coun= t) +{ + struct mgr_stats *stats =3D mgr->priv; + size_t i; + + stats->op_write_state =3D mgr->state; + stats->op_write_seq =3D stats->seq_num++; + + stats->image_match =3D true; + for (i =3D 0; i < count; i++) { + if (buf[i] !=3D IMAGE_FILL) { + stats->image_match =3D false; + break; + } + } + + return 0; +} + +/* + * Check the image data, but first skip the header since write_sg will get + * the whole image in sg_table. As with op_parse_header, do not return an + * error code if the image check fails. + */ +static int op_write_sg(struct fpga_manager *mgr, struct sg_table *sgt) +{ + struct mgr_stats *stats =3D mgr->priv; + struct sg_mapping_iter miter; + char *img; + size_t i; + + stats->op_write_sg_state =3D mgr->state; + stats->op_write_sg_seq =3D stats->seq_num++; + + stats->image_match =3D true; + sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG); + + if (!sg_miter_skip(&miter, HEADER_SIZE)) { + stats->image_match =3D false; + goto out; + } + + while (sg_miter_next(&miter)) { + img =3D miter.addr; + for (i =3D 0; i < miter.length; i++) { + if (img[i] !=3D IMAGE_FILL) { + stats->image_match =3D false; + goto out; + } + } + } +out: + sg_miter_stop(&miter); + return 0; +} + +static int op_write_complete(struct fpga_manager *mgr, struct fpga_image_i= nfo *info) +{ + struct mgr_stats *stats =3D mgr->priv; + + stats->op_write_complete_state =3D mgr->state; + stats->op_write_complete_seq =3D stats->seq_num++; + + return 0; +} + +/* + * Fake FPGA manager that implements all ops required to check the program= ming + * sequence using a single contiguous buffer and a scatter gather table. + */ +static const struct fpga_manager_ops fake_mgr_ops =3D { + .skip_header =3D true, + .parse_header =3D op_parse_header, + .write_init =3D op_write_init, + .write =3D op_write, + .write_sg =3D op_write_sg, + .write_complete =3D op_write_complete, +}; + +static void fpga_mgr_test_get(struct kunit *test) +{ + struct mgr_ctx *ctx =3D test->priv; + struct fpga_manager *mgr; + + mgr =3D fpga_mgr_get(&ctx->pdev->dev); + KUNIT_EXPECT_PTR_EQ(test, mgr, ctx->mgr); + + fpga_mgr_put(ctx->mgr); +} + +static void fpga_mgr_test_lock(struct kunit *test) +{ + struct mgr_ctx *ctx =3D test->priv; + int ret; + + ret =3D fpga_mgr_lock(ctx->mgr); + KUNIT_EXPECT_EQ(test, ret, 0); + + ret =3D fpga_mgr_lock(ctx->mgr); + KUNIT_EXPECT_EQ(test, ret, -EBUSY); + + fpga_mgr_unlock(ctx->mgr); +} + +/* Check the programming sequence using an image in a buffer */ +static void fpga_mgr_test_img_load_buf(struct kunit *test) +{ + struct mgr_ctx *ctx =3D test->priv; + char *img_buf; + int ret; + + img_buf =3D init_test_buffer(test, IMAGE_SIZE); + + ctx->img_info->count =3D IMAGE_SIZE; + ctx->img_info->buf =3D img_buf; + + ret =3D fpga_mgr_load(ctx->mgr, ctx->img_info); + KUNIT_EXPECT_EQ(test, ret, 0); + + KUNIT_EXPECT_TRUE(test, ctx->stats.header_match); + KUNIT_EXPECT_TRUE(test, ctx->stats.image_match); + + KUNIT_EXPECT_EQ(test, ctx->stats.op_parse_header_state, FPGA_MGR_STATE_PA= RSE_HEADER); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_state, FPGA_MGR_STATE_WRIT= E_INIT); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_state, FPGA_MGR_STATE_WRITE); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_state, FPGA_MGR_STATE_= WRITE_COMPLETE); + + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_seq, ctx->stats.op_parse_h= eader_seq + 1); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_seq, ctx->stats.op_parse_header= _seq + 2); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_seq, ctx->stats.op_par= se_header_seq + 3); +} + +/* Check the programming sequence using an image in a scatter gather table= */ +static void fpga_mgr_test_img_load_sgt(struct kunit *test) +{ + struct mgr_ctx *ctx =3D test->priv; + struct sg_table *sgt; + char *img_buf; + int ret; + + img_buf =3D init_test_buffer(test, IMAGE_SIZE); + + sgt =3D kunit_kzalloc(test, sizeof(*sgt), GFP_KERNEL); + ret =3D sg_alloc_table(sgt, 1, GFP_KERNEL); + KUNIT_ASSERT_EQ(test, ret, 0); + sg_init_one(sgt->sgl, img_buf, IMAGE_SIZE); + + ctx->img_info->sgt =3D sgt; + + ret =3D fpga_mgr_load(ctx->mgr, ctx->img_info); + KUNIT_EXPECT_EQ(test, ret, 0); + + KUNIT_EXPECT_TRUE(test, ctx->stats.header_match); + KUNIT_EXPECT_TRUE(test, ctx->stats.image_match); + + KUNIT_EXPECT_EQ(test, ctx->stats.op_parse_header_state, FPGA_MGR_STATE_PA= RSE_HEADER); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_state, FPGA_MGR_STATE_WRIT= E_INIT); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_sg_state, FPGA_MGR_STATE_WRITE); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_state, FPGA_MGR_STATE_= WRITE_COMPLETE); + + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_seq, ctx->stats.op_parse_h= eader_seq + 1); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_sg_seq, ctx->stats.op_parse_hea= der_seq + 2); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_seq, ctx->stats.op_par= se_header_seq + 3); + + sg_free_table(ctx->img_info->sgt); +} + +static int fpga_mgr_test_init(struct kunit *test) +{ + struct mgr_ctx *ctx; + + ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx); + + ctx->pdev =3D platform_device_register_simple("mgr_pdev", PLATFORM_DEVID_= AUTO, NULL, 0); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->pdev); + + ctx->mgr =3D devm_fpga_mgr_register(&ctx->pdev->dev, "Fake FPGA Manager",= &fake_mgr_ops, + &ctx->stats); + KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->mgr)); + + ctx->img_info =3D fpga_image_info_alloc(&ctx->pdev->dev); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->img_info); + + test->priv =3D ctx; + + return 0; +} + +static void fpga_mgr_test_exit(struct kunit *test) +{ + struct mgr_ctx *ctx =3D test->priv; + + fpga_image_info_free(ctx->img_info); + platform_device_unregister(ctx->pdev); +} + +static struct kunit_case fpga_mgr_test_cases[] =3D { + KUNIT_CASE(fpga_mgr_test_get), + KUNIT_CASE(fpga_mgr_test_lock), + KUNIT_CASE(fpga_mgr_test_img_load_buf), + KUNIT_CASE(fpga_mgr_test_img_load_sgt), + {} +}; + +static struct kunit_suite fpga_mgr_suite =3D { + .name =3D "fpga_mgr", + .init =3D fpga_mgr_test_init, + .exit =3D fpga_mgr_test_exit, + .test_cases =3D fpga_mgr_test_cases, +}; + +kunit_test_suite(fpga_mgr_suite); + +MODULE_LICENSE("GPL"); --=20 2.41.0 From nobody Fri Sep 5 09:22:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56E78EB64DA for ; Tue, 18 Jul 2023 13:07:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231297AbjGRNHT (ORCPT ); Tue, 18 Jul 2023 09:07:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232503AbjGRNG4 (ORCPT ); Tue, 18 Jul 2023 09:06:56 -0400 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75E461FEF for ; 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[2.34.27.228]) by smtp.gmail.com with ESMTPSA id h18-20020a05620a10b200b00765ab6d3e81sm550221qkk.122.2023.07.18.06.03.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jul 2023 06:03:28 -0700 (PDT) From: Marco Pagani To: Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix Cc: Marco Pagani , linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org Subject: [PATCH v10 2/4] fpga: add an initial KUnit suite for the FPGA Bridge Date: Tue, 18 Jul 2023 15:03:02 +0200 Message-ID: <20230718130304.87048-3-marpagan@redhat.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230718130304.87048-1-marpagan@redhat.com> References: <20230718130304.87048-1-marpagan@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The suite tests the basic behaviors of the FPGA Bridge including the functions that operate on a list of bridges. Signed-off-by: Marco Pagani Acked-by: Xu Yilun --- drivers/fpga/tests/fpga-bridge-test.c | 175 ++++++++++++++++++++++++++ 1 file changed, 175 insertions(+) create mode 100644 drivers/fpga/tests/fpga-bridge-test.c diff --git a/drivers/fpga/tests/fpga-bridge-test.c b/drivers/fpga/tests/fpg= a-bridge-test.c new file mode 100644 index 000000000000..1d258002cdd7 --- /dev/null +++ b/drivers/fpga/tests/fpga-bridge-test.c @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * KUnit test for the FPGA Bridge + * + * Copyright (C) 2023 Red Hat, Inc. + * + * Author: Marco Pagani + */ + +#include +#include +#include +#include +#include + +struct bridge_stats { + bool enable; +}; + +struct bridge_ctx { + struct fpga_bridge *bridge; + struct platform_device *pdev; + struct bridge_stats stats; +}; + +static int op_enable_set(struct fpga_bridge *bridge, bool enable) +{ + struct bridge_stats *stats =3D bridge->priv; + + stats->enable =3D enable; + + return 0; +} + +/* + * Fake FPGA bridge that implements only the enable_set op to track + * the state. + */ +static const struct fpga_bridge_ops fake_bridge_ops =3D { + .enable_set =3D op_enable_set, +}; + +/** + * register_test_bridge() - Register a fake FPGA bridge for testing. + * @test: KUnit test context object. + * + * Return: Context of the newly registered FPGA bridge. + */ +static struct bridge_ctx *register_test_bridge(struct kunit *test) +{ + struct bridge_ctx *ctx; + + ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx); + + ctx->pdev =3D platform_device_register_simple("bridge_pdev", PLATFORM_DEV= ID_AUTO, NULL, 0); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->pdev); + + ctx->bridge =3D fpga_bridge_register(&ctx->pdev->dev, "Fake FPGA bridge",= &fake_bridge_ops, + &ctx->stats); + KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->bridge)); + + return ctx; +} + +static void unregister_test_bridge(struct bridge_ctx *ctx) +{ + fpga_bridge_unregister(ctx->bridge); + platform_device_unregister(ctx->pdev); +} + +static void fpga_bridge_test_get(struct kunit *test) +{ + struct bridge_ctx *ctx =3D test->priv; + struct fpga_bridge *bridge; + + bridge =3D fpga_bridge_get(&ctx->pdev->dev, NULL); + KUNIT_EXPECT_PTR_EQ(test, bridge, ctx->bridge); + + bridge =3D fpga_bridge_get(&ctx->pdev->dev, NULL); + KUNIT_EXPECT_EQ(test, PTR_ERR(bridge), -EBUSY); + + fpga_bridge_put(ctx->bridge); +} + +static void fpga_bridge_test_toggle(struct kunit *test) +{ + struct bridge_ctx *ctx =3D test->priv; + int ret; + + ret =3D fpga_bridge_disable(ctx->bridge); + KUNIT_EXPECT_EQ(test, ret, 0); + KUNIT_EXPECT_FALSE(test, ctx->stats.enable); + + ret =3D fpga_bridge_enable(ctx->bridge); + KUNIT_EXPECT_EQ(test, ret, 0); + KUNIT_EXPECT_TRUE(test, ctx->stats.enable); +} + +/* Test the functions for getting and controlling a list of bridges */ +static void fpga_bridge_test_get_put_list(struct kunit *test) +{ + struct list_head bridge_list; + struct bridge_ctx *ctx_0, *ctx_1; + int ret; + + ctx_0 =3D test->priv; + ctx_1 =3D register_test_bridge(test); + + INIT_LIST_HEAD(&bridge_list); + + /* Get bridge 0 and add it to the list */ + ret =3D fpga_bridge_get_to_list(&ctx_0->pdev->dev, NULL, &bridge_list); + KUNIT_EXPECT_EQ(test, ret, 0); + + KUNIT_EXPECT_PTR_EQ(test, ctx_0->bridge, + list_first_entry_or_null(&bridge_list, struct fpga_bridge, node)); + + /* Get bridge 1 and add it to the list */ + ret =3D fpga_bridge_get_to_list(&ctx_1->pdev->dev, NULL, &bridge_list); + KUNIT_EXPECT_EQ(test, ret, 0); + + KUNIT_EXPECT_PTR_EQ(test, ctx_1->bridge, + list_first_entry_or_null(&bridge_list, struct fpga_bridge, node)); + + /* Disable an then enable both bridges from the list */ + ret =3D fpga_bridges_disable(&bridge_list); + KUNIT_EXPECT_EQ(test, ret, 0); + + KUNIT_EXPECT_FALSE(test, ctx_0->stats.enable); + KUNIT_EXPECT_FALSE(test, ctx_1->stats.enable); + + ret =3D fpga_bridges_enable(&bridge_list); + KUNIT_EXPECT_EQ(test, ret, 0); + + KUNIT_EXPECT_TRUE(test, ctx_0->stats.enable); + KUNIT_EXPECT_TRUE(test, ctx_1->stats.enable); + + /* Put and remove both bridges from the list */ + fpga_bridges_put(&bridge_list); + + KUNIT_EXPECT_TRUE(test, list_empty(&bridge_list)); + + unregister_test_bridge(ctx_1); +} + +static int fpga_bridge_test_init(struct kunit *test) +{ + test->priv =3D register_test_bridge(test); + + return 0; +} + +static void fpga_bridge_test_exit(struct kunit *test) +{ + unregister_test_bridge(test->priv); +} + +static struct kunit_case fpga_bridge_test_cases[] =3D { + KUNIT_CASE(fpga_bridge_test_get), + KUNIT_CASE(fpga_bridge_test_toggle), + KUNIT_CASE(fpga_bridge_test_get_put_list), + {} +}; + +static struct kunit_suite fpga_bridge_suite =3D { + .name =3D "fpga_bridge", + .init =3D fpga_bridge_test_init, + .exit =3D fpga_bridge_test_exit, + .test_cases =3D fpga_bridge_test_cases, +}; + +kunit_test_suite(fpga_bridge_suite); + +MODULE_LICENSE("GPL"); --=20 2.41.0 From nobody Fri Sep 5 09:22:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2990EB64DC for ; Tue, 18 Jul 2023 13:07:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232613AbjGRNHe (ORCPT ); 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[2.34.27.228]) by smtp.gmail.com with ESMTPSA id h18-20020a05620a10b200b00765ab6d3e81sm550221qkk.122.2023.07.18.06.03.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jul 2023 06:03:35 -0700 (PDT) From: Marco Pagani To: Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix Cc: Marco Pagani , linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org Subject: [PATCH v10 3/4] fpga: add an initial KUnit suite for the FPGA Region Date: Tue, 18 Jul 2023 15:03:03 +0200 Message-ID: <20230718130304.87048-4-marpagan@redhat.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230718130304.87048-1-marpagan@redhat.com> References: <20230718130304.87048-1-marpagan@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The suite tests the basic behaviors of the FPGA Region including the programming and the function for finding a specific region. Signed-off-by: Marco Pagani Acked-by: Xu Yilun --- drivers/fpga/tests/fpga-region-test.c | 211 ++++++++++++++++++++++++++ 1 file changed, 211 insertions(+) create mode 100644 drivers/fpga/tests/fpga-region-test.c diff --git a/drivers/fpga/tests/fpga-region-test.c b/drivers/fpga/tests/fpg= a-region-test.c new file mode 100644 index 000000000000..9f9d50ee7871 --- /dev/null +++ b/drivers/fpga/tests/fpga-region-test.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * KUnit test for the FPGA Region + * + * Copyright (C) 2023 Red Hat, Inc. + * + * Author: Marco Pagani + */ + +#include +#include +#include +#include +#include +#include +#include + +struct mgr_stats { + u32 write_count; +}; + +struct bridge_stats { + bool enable; + u32 cycles_count; +}; + +struct test_ctx { + struct fpga_manager *mgr; + struct platform_device *mgr_pdev; + struct fpga_bridge *bridge; + struct platform_device *bridge_pdev; + struct fpga_region *region; + struct platform_device *region_pdev; + struct bridge_stats bridge_stats; + struct mgr_stats mgr_stats; +}; + +static int op_write(struct fpga_manager *mgr, const char *buf, size_t coun= t) +{ + struct mgr_stats *stats =3D mgr->priv; + + stats->write_count++; + + return 0; +} + +/* + * Fake FPGA manager that implements only the write op to count the number + * of programming cycles. The internals of the programming sequence are + * tested in the Manager suite since they are outside the responsibility + * of the Region. + */ +static const struct fpga_manager_ops fake_mgr_ops =3D { + .write =3D op_write, +}; + +static int op_enable_set(struct fpga_bridge *bridge, bool enable) +{ + struct bridge_stats *stats =3D bridge->priv; + + if (!stats->enable && enable) + stats->cycles_count++; + + stats->enable =3D enable; + + return 0; +} + +/* + * Fake FPGA bridge that implements only enable_set op to count the number + * of activation cycles. + */ +static const struct fpga_bridge_ops fake_bridge_ops =3D { + .enable_set =3D op_enable_set, +}; + +static int fake_region_get_bridges(struct fpga_region *region) +{ + struct fpga_bridge *bridge =3D region->priv; + + return fpga_bridge_get_to_list(bridge->dev.parent, region->info, ®ion-= >bridge_list); +} + +static int fake_region_match(struct device *dev, const void *data) +{ + return dev->parent =3D=3D data; +} + +static void fpga_region_test_class_find(struct kunit *test) +{ + struct test_ctx *ctx =3D test->priv; + struct fpga_region *region; + + region =3D fpga_region_class_find(NULL, &ctx->region_pdev->dev, fake_regi= on_match); + KUNIT_EXPECT_PTR_EQ(test, region, ctx->region); +} + +/* + * FPGA Region programming test. The Region must call get_bridges() to get + * and control the bridges, and then the Manager for the actual programmin= g. + */ +static void fpga_region_test_program_fpga(struct kunit *test) +{ + struct test_ctx *ctx =3D test->priv; + struct fpga_image_info *img_info; + char img_buf[4]; + int ret; + + img_info =3D fpga_image_info_alloc(&ctx->mgr_pdev->dev); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, img_info); + + img_info->buf =3D img_buf; + img_info->count =3D sizeof(img_buf); + + ctx->region->info =3D img_info; + ret =3D fpga_region_program_fpga(ctx->region); + KUNIT_ASSERT_EQ(test, ret, 0); + + KUNIT_EXPECT_EQ(test, 1, ctx->mgr_stats.write_count); + KUNIT_EXPECT_EQ(test, 1, ctx->bridge_stats.cycles_count); + + fpga_bridges_put(&ctx->region->bridge_list); + + ret =3D fpga_region_program_fpga(ctx->region); + KUNIT_ASSERT_EQ(test, ret, 0); + + KUNIT_EXPECT_EQ(test, 2, ctx->mgr_stats.write_count); + KUNIT_EXPECT_EQ(test, 2, ctx->bridge_stats.cycles_count); + + fpga_bridges_put(&ctx->region->bridge_list); + + fpga_image_info_free(img_info); +} + +/* + * The configuration used in this test suite uses a single bridge to + * limit the code under test to a single unit. The functions used by the + * Region for getting and controlling bridges are tested (with a list of + * multiple bridges) in the Bridge suite. + */ +static int fpga_region_test_init(struct kunit *test) +{ + struct test_ctx *ctx; + struct fpga_region_info region_info =3D { 0 }; + + ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx); + + ctx->mgr_pdev =3D platform_device_register_simple("mgr_pdev", PLATFORM_DE= VID_AUTO, NULL, 0); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->mgr_pdev); + + ctx->mgr =3D devm_fpga_mgr_register(&ctx->mgr_pdev->dev, "Fake FPGA Manag= er", &fake_mgr_ops, + &ctx->mgr_stats); + KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->mgr)); + + ctx->bridge_pdev =3D platform_device_register_simple("bridge_pdev", PLATF= ORM_DEVID_AUTO, + NULL, 0); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->bridge_pdev); + + ctx->bridge =3D fpga_bridge_register(&ctx->bridge_pdev->dev, "Fake FPGA B= ridge", + &fake_bridge_ops, &ctx->bridge_stats); + KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->bridge)); + + ctx->bridge_stats.enable =3D true; + + ctx->region_pdev =3D platform_device_register_simple("region_pdev", PLATF= ORM_DEVID_AUTO, + NULL, 0); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->region_pdev); + + region_info.mgr =3D ctx->mgr; + region_info.priv =3D ctx->bridge; + region_info.get_bridges =3D fake_region_get_bridges; + + ctx->region =3D fpga_region_register_full(&ctx->region_pdev->dev, ®ion= _info); + KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->region)); + + test->priv =3D ctx; + + return 0; +} + +static void fpga_region_test_exit(struct kunit *test) +{ + struct test_ctx *ctx =3D test->priv; + + fpga_region_unregister(ctx->region); + platform_device_unregister(ctx->region_pdev); + + fpga_bridge_unregister(ctx->bridge); + platform_device_unregister(ctx->bridge_pdev); + + platform_device_unregister(ctx->mgr_pdev); +} + +static struct kunit_case fpga_region_test_cases[] =3D { + KUNIT_CASE(fpga_region_test_class_find), + KUNIT_CASE(fpga_region_test_program_fpga), + + {} +}; + +static struct kunit_suite fpga_region_suite =3D { + .name =3D "fpga_mgr", + .init =3D fpga_region_test_init, + .exit =3D fpga_region_test_exit, + .test_cases =3D fpga_region_test_cases, +}; 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[2.34.27.228]) by smtp.gmail.com with ESMTPSA id h18-20020a05620a10b200b00765ab6d3e81sm550221qkk.122.2023.07.18.06.03.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Jul 2023 06:03:41 -0700 (PDT) From: Marco Pagani To: Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix Cc: Marco Pagani , linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org Subject: [PATCH v10 4/4] fpga: add configuration for the FPGA KUnit test suites. Date: Tue, 18 Jul 2023 15:03:04 +0200 Message-ID: <20230718130304.87048-5-marpagan@redhat.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230718130304.87048-1-marpagan@redhat.com> References: <20230718130304.87048-1-marpagan@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add configuration for the KUnit test suites for the core components of the FPGA subsystem. Signed-off-by: Marco Pagani Acked-by: Xu Yilun --- drivers/fpga/Kconfig | 2 ++ drivers/fpga/Makefile | 3 +++ drivers/fpga/tests/.kunitconfig | 5 +++++ drivers/fpga/tests/Kconfig | 11 +++++++++++ drivers/fpga/tests/Makefile | 6 ++++++ 5 files changed, 27 insertions(+) create mode 100644 drivers/fpga/tests/.kunitconfig create mode 100644 drivers/fpga/tests/Kconfig create mode 100644 drivers/fpga/tests/Makefile diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 0a00763b9f28..2f689ac4ba3a 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -276,4 +276,6 @@ config FPGA_MGR_LATTICE_SYSCONFIG_SPI FPGA manager driver support for Lattice FPGAs programming over slave SPI sysCONFIG interface. =20 +source "drivers/fpga/tests/Kconfig" + endif # FPGA diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 72e554b4d2f7..352a2612623e 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -55,3 +55,6 @@ obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) +=3D dfl-n300= 0-nios.o =20 # Drivers for FPGAs which implement DFL obj-$(CONFIG_FPGA_DFL_PCI) +=3D dfl-pci.o + +# KUnit tests +obj-$(CONFIG_FPGA_KUNIT_TESTS) +=3D tests/ diff --git a/drivers/fpga/tests/.kunitconfig b/drivers/fpga/tests/.kunitcon= fig new file mode 100644 index 000000000000..a1c2a2974c39 --- /dev/null +++ b/drivers/fpga/tests/.kunitconfig @@ -0,0 +1,5 @@ +CONFIG_KUNIT=3Dy +CONFIG_FPGA=3Dy +CONFIG_FPGA_REGION=3Dy +CONFIG_FPGA_BRIDGE=3Dy +CONFIG_FPGA_KUNIT_TESTS=3Dy diff --git a/drivers/fpga/tests/Kconfig b/drivers/fpga/tests/Kconfig new file mode 100644 index 000000000000..e4a64815f16d --- /dev/null +++ b/drivers/fpga/tests/Kconfig @@ -0,0 +1,11 @@ +config FPGA_KUNIT_TESTS + tristate "KUnit test for the FPGA subsystem" if !KUNIT_ALL_TESTS + depends on FPGA && FPGA_REGION && FPGA_BRIDGE && KUNIT=3Dy + default KUNIT_ALL_TESTS + help + This builds unit tests for the FPGA subsystem + + For more information on KUnit and unit tests in general, + please refer to the KUnit documentation in Documentation/dev-too= ls/kunit/. + + If unsure, say N. diff --git a/drivers/fpga/tests/Makefile b/drivers/fpga/tests/Makefile new file mode 100644 index 000000000000..bb78215c645c --- /dev/null +++ b/drivers/fpga/tests/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for KUnit test suites for the FPGA subsystem +# + +obj-$(CONFIG_FPGA_KUNIT_TESTS) +=3D fpga-mgr-test.o fpga-bridge-test.o fpg= a-region-test.o --=20 2.41.0