From nobody Fri Sep 20 13:45:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38D0BEB64DD for ; Tue, 18 Jul 2023 11:22:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231531AbjGRLWB (ORCPT ); Tue, 18 Jul 2023 07:22:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231423AbjGRLV5 (ORCPT ); Tue, 18 Jul 2023 07:21:57 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8278EA; Tue, 18 Jul 2023 04:21:55 -0700 (PDT) X-UUID: 4b65ac3a255d11ee9cb5633481061a41-20230718 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=KxwDmj9X8waLD1ymOgknd/mNl6ap37mlZ9CeBhasP2U=; b=N0KaOGYrSnsPVfCCFO23t3yWv2UWDosfb+h3eJJ2fU9ohgS48jmE0mPrvZHY5FHUnLpVaVNmRuhLSHsznGxtBz54mgWjosrh40rxfBYlMqPwXWd4rUailFuWu+uLwU5Z+af13o/OuHdnyWMitAAEGyCYBBITuSZzfLBqZIyk9Io=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.28,REQID:ba7b3c6c-a916-4494-8834-da9cffe38cb1,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:176cd25,CLOUDID:2104d84c-06c1-468b-847d-5b62d44dbb9b,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 4b65ac3a255d11ee9cb5633481061a41-20230718 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1770147722; Tue, 18 Jul 2023 19:21:52 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 18 Jul 2023 19:21:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 18 Jul 2023 19:21:50 +0800 From: William-tw Lin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kevin Hilman CC: , , , , , William-tw Lin Subject: [PATCH 1/3] soc: mediatek: mtk-socinfo: Add driver for getting chip information Date: Tue, 18 Jul 2023 19:21:41 +0800 Message-ID: <20230718112143.14036-2-william-tw.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230718112143.14036-1-william-tw.lin@mediatek.com> References: <20230718112143.14036-1-william-tw.lin@mediatek.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add driver for socinfo retrieval. This patch includes the following: 1. mtk-socinfo driver for chip info retrieval 2. Related changes to Makefile and Kconfig Signed-off-by: William-tw Lin --- drivers/soc/mediatek/Kconfig | 18 +++ drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mtk-socinfo.c | 203 +++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-socinfo.h | 213 +++++++++++++++++++++++++++++ 4 files changed, 435 insertions(+) create mode 100644 drivers/soc/mediatek/mtk-socinfo.c create mode 100644 drivers/soc/mediatek/mtk-socinfo.h diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index a88cf04fc803..50bd9ec75ca5 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -91,4 +91,22 @@ config MTK_SVS chip process corner, temperatures and other factors. Then DVFS driver could apply SVS bank voltage to PMIC/Buck. =20 +config MTK_SOCINFO + tristate "MediaTek SOCINFO" + depends on MTK_EFUSE && NVMEM + help + Say y here to enable mtk socinfo information. + This enables a sysfs node which shows attributes of MTK soc info. + Information of soc info includes the manufacturer, the marketing + name, and the soc used. + +config MTK_SOCINFO_DEBUG + tristate "MediaTek SOCINFO debug" + depends on MTK_SOCINFO + help + Say y here to enables a debug node which shows MTK SOC information. + This enables a debug node that gives details on MTK soc info attributes. + Information included in this debug node includes the manufacturer, the = marketing + name, the soc used, as well as the segment of the soc. + endmenu diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index 8c0ddacbcde8..c900e5f13a35 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) +=3D mtk-pm-domains.o obj-$(CONFIG_MTK_MMSYS) +=3D mtk-mmsys.o obj-$(CONFIG_MTK_MMSYS) +=3D mtk-mutex.o obj-$(CONFIG_MTK_SVS) +=3D mtk-svs.o +obj-$(CONFIG_MTK_SOCINFO) +=3D mtk-socinfo.o diff --git a/drivers/soc/mediatek/mtk-socinfo.c b/drivers/soc/mediatek/mtk-= socinfo.c new file mode 100644 index 000000000000..8c8964eb4670 --- /dev/null +++ b/drivers/soc/mediatek/mtk-socinfo.c @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 MediaTek Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mtk-socinfo.h" + + +#if IS_ENABLED(CONFIG_MTK_SOCINFO_DEBUG) +static int mtk_socinfo_socinfo_debug_show(struct seq_file *m, void *p) +{ + struct mtk_socinfo *mtk_socinfop =3D (struct mtk_socinfo *)m->private; + + seq_printf(m, "SOC Manufacturer: %s\n", soc_manufacturer); + seq_printf(m, "SOC Name: %s\n", mtk_socinfop->name_data->soc_na= me); + seq_printf(m, "SOC segment Name: %s\n", mtk_socinfop->name_data->soc_se= gment_name); + seq_printf(m, "Marketing Name: %s\n", mtk_socinfop->name_data->market= ing_name); + + return 0; +} +DEBUG_FOPS_RO(socinfo); + +static int mtk_socinfo_create_debug_cmds(struct mtk_socinfo *mtk_socinfop) +{ + const char *d =3D "mtk-socinfo"; + + struct mtk_socinfo_dentry { + const char *name; + const struct file_operations *fops; + }; + + struct mtk_socinfo_dentry mtk_socinfo_entries[] =3D { + MTK_SOCINFO_DENTRY_DATA(socinfo), + }; + + mtk_socinfo_dir =3D debugfs_create_dir(d, NULL); + if (IS_ERR(mtk_socinfo_dir)) { + dev_err(mtk_socinfop->dev, "Cannot create %s\n", d); + return 0; + } + + file_entry =3D debugfs_create_file(mtk_socinfo_entries[0].name, 0664, + mtk_socinfo_dir, mtk_socinfop, + mtk_socinfo_entries[0].fops); + if (IS_ERR(file_entry)) { + dev_err(mtk_socinfop->dev, "Cannot create %s/%s\n", d, mtk_socinfo_entri= es[0].name); + return PTR_ERR(file_entry); + } + return 0; +} +#endif + +static int mtk_socinfo_create_socinfo_node(struct mtk_socinfo *mtk_socinfo= p) +{ + struct soc_device_attribute *attrs; + static char machine[30] =3D {0}; + + attrs =3D devm_kzalloc(mtk_socinfop->dev, sizeof(*attrs), GFP_KERNEL); + if (!attrs) { + return -ENOMEM; + } + + snprintf(machine, 30, "%s (%s)", mtk_socinfop->name_data->marketing_name, + mtk_socinfop->name_data->soc_name); + attrs->family =3D soc_manufacturer; + attrs->machine =3D machine; + + soc_dev =3D soc_device_register(attrs); + if (IS_ERR(soc_dev)) { + dev_err(mtk_socinfop->dev, "Cannot create soc node, soc_device_register = failed\n"); + return PTR_ERR(soc_dev); + } + + dev_info(mtk_socinfop->dev, "%s %s SoC detected.\n", MODULE_NAME, attrs->= machine); + return 0; +} + +static int mtk_socinfo_get_socinfo_data(struct mtk_socinfo *mtk_socinfop) +{ + struct efuse_data *soc_efuse_data_infop =3D mtk_socinfop->soc_data->efuse= _data; + struct name_data *soc_name_data_infop =3D mtk_socinfop->soc_data->name_da= ta; + unsigned int soc_efuse_data_count =3D mtk_socinfop->soc_data->efuse_data_= count; + unsigned int soc_segment_count =3D mtk_socinfop->soc_data->efuse_segment_= count; + unsigned int i =3D 0, j =3D 0; + struct efuse_data *temp_efuse_datap; + struct nvmem_cell *cell; + size_t efuse_bytes; + char *nvmem_cell_name =3D ""; + u32 *efuse_temp_bufp; + int match_segment_index =3D -1; + + for (i =3D 0; i < soc_segment_count; i++) { + bool match_segment =3D true; + + for (j =3D 0; j < soc_efuse_data_count; j++) { + temp_efuse_datap =3D soc_efuse_data_infop + (i * soc_efuse_data_count += j); + nvmem_cell_name =3D temp_efuse_datap->nvmem_cell_name; + cell =3D nvmem_cell_get(mtk_socinfop->dev, nvmem_cell_name); + if (IS_ERR_OR_NULL(cell)) { + dev_err(mtk_socinfop->dev, "%s cell not found\n", nvmem_cell_name); + goto out; + } + efuse_temp_bufp =3D (u32 *)nvmem_cell_read(cell, &efuse_bytes); + nvmem_cell_put(cell); + if (*efuse_temp_bufp !=3D temp_efuse_datap->efuse_data) { + match_segment =3D false; + break; + } + } + if (match_segment) { + match_segment_index =3D i; + mtk_socinfop->name_data =3D soc_name_data_infop + i; + } + } + +out: + kfree(efuse_temp_bufp); + return match_segment_index; +} + +static const struct of_device_id mtk_socinfo_id_table[] =3D { + { .compatible =3D "mediatek,mt8173-socinfo", .data =3D &socinfo_data_tabl= e[INDEX_MT8173]}, + { .compatible =3D "mediatek,mt8183-socinfo", .data =3D &socinfo_data_tabl= e[INDEX_MT8183]}, + { .compatible =3D "mediatek,mt8186-socinfo", .data =3D &socinfo_data_tabl= e[INDEX_MT8186]}, + { .compatible =3D "mediatek,mt8188-socinfo", .data =3D &socinfo_data_tabl= e[INDEX_MT8188]}, + { .compatible =3D "mediatek,mt8192-socinfo", .data =3D &socinfo_data_tabl= e[INDEX_MT8192]}, + { .compatible =3D "mediatek,mt8195-socinfo", .data =3D &socinfo_data_tabl= e[INDEX_MT8195]}, + { }, +}; +MODULE_DEVICE_TABLE(of, mtk_socinfo_id_table); + +static int mtk_socinfo_probe(struct platform_device *pdev) +{ + struct mtk_socinfo *mtk_socinfop; + int ret =3D 0; + + mtk_socinfop =3D devm_kzalloc(&pdev->dev, sizeof(*mtk_socinfop), GFP_KERN= EL); + if (!mtk_socinfop) + return -ENOMEM; + + mtk_socinfop->dev =3D &pdev->dev; + mtk_socinfop->soc_data =3D (struct socinfo_data *)of_device_get_match_dat= a(mtk_socinfop->dev); + if (!mtk_socinfop->soc_data) { + dev_err(mtk_socinfop->dev, "No mtk-socinfo platform data found\n"); + return -EPERM; + } + + ret =3D mtk_socinfo_get_socinfo_data(mtk_socinfop); + if (ret < 0) { + dev_err(mtk_socinfop->dev, "Failed to get socinfo data (ret =3D %d)\n", = ret); + return -EINVAL; + } + + ret =3D mtk_socinfo_create_socinfo_node(mtk_socinfop); + if (ret !=3D 0) { + dev_err(mtk_socinfop->dev, "Failed to create socinfo node (ret =3D %d)\n= ", ret); + return ret; + } + +#if IS_ENABLED(CONFIG_MTK_SOCINFO_DEBUG) + ret =3D mtk_socinfo_create_debug_cmds(mtk_socinfop); + if (ret !=3D 0) { + dev_err(mtk_socinfop->dev, "Failed to create socinfo debug node (ret =3D= %d)\n", ret); + return ret; + } +#endif + return 0; +} + +static int mtk_socinfo_remove(struct platform_device *pdev) +{ + if (soc_dev) + soc_device_unregister(soc_dev); +#if IS_ENABLED(CONFIG_MTK_SOCINFO_DEBUG) + debugfs_remove(file_entry); +#endif + return 0; +} + +static struct platform_driver mtk_socinfo =3D { + .probe =3D mtk_socinfo_probe, + .remove =3D mtk_socinfo_remove, + .driver =3D { + .name =3D "mtk_socinfo", + .owner =3D THIS_MODULE, + .of_match_table =3D mtk_socinfo_id_table, + }, +}; +module_platform_driver(mtk_socinfo); +MODULE_AUTHOR("William-TW LIN "); +MODULE_DESCRIPTION("Mediatek socinfo driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/soc/mediatek/mtk-socinfo.h b/drivers/soc/mediatek/mtk-= socinfo.h new file mode 100644 index 000000000000..8fd490311c8b --- /dev/null +++ b/drivers/soc/mediatek/mtk-socinfo.h @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2023 MediaTek Inc. + */ + +#ifndef __MTK_SOCINFO_H__ +#define __MTK_SOCINFO_H__ + +#define MODULE_NAME "[mtk-socinfo]" + +#define DEBUG_FOPS_RO(name) \ + static int mtk_socinfo_##name##_debug_open(struct inode *inode, \ + struct file *filp) \ + { \ + return single_open(filp, mtk_socinfo_##name##_debug_show, \ + inode->i_private); \ + } \ + static const struct file_operations mtk_socinfo_##name##_debug_fops =3D {= \ + .owner =3D THIS_MODULE, \ + .open =3D mtk_socinfo_##name##_debug_open, \ + .read =3D seq_read, \ + .llseek =3D seq_lseek, \ + .release =3D single_release, \ + } + +#define MTK_SOCINFO_DENTRY_DATA(name) {__stringify(name), &mtk_socinfo_##n= ame##_debug_fops} + +const char *soc_manufacturer =3D "MediaTek"; + +struct soc_device *soc_dev; +struct dentry *mtk_socinfo_dir, *file_entry; + +struct mtk_socinfo { + struct device *dev; + struct name_data *name_data; + struct socinfo_data *soc_data; +}; + +struct efuse_data { + char *nvmem_cell_name; + u32 efuse_data; +}; + +struct name_data { + char *soc_name; + char *soc_segment_name; + char *marketing_name; +}; + +struct socinfo_data { + char *soc_name; + struct efuse_data *efuse_data; + struct name_data *name_data; + unsigned int efuse_segment_count; + unsigned int efuse_data_count; +}; + +enum socinfo_data_index { + INDEX_MT8186 =3D 0, + INDEX_MT8188, + INDEX_MT8195, + INDEX_MT8192, + INDEX_MT8183, + INDEX_MT8173, + SOCINFO_DATA_LAST_INDEX +}; + +/* begin 8186 info */ +#define mtk_mt8186_EFUSE_DATA_COUNT 1 +static struct efuse_data mtk_mt8186_efuse_data_info[][mtk_mt8186_EFUSE_DAT= A_COUNT] =3D { + {{.nvmem_cell_name =3D "socinfo-data1", .efuse_data =3D 0x81861001}}, + {{.nvmem_cell_name =3D "socinfo-data1", .efuse_data =3D 0x81862001}}, +}; + +static struct name_data mtk_mt8186_name_data_info[] =3D { + {.soc_name =3D "MT8186", + .soc_segment_name =3D "MT8186GV/AZA", + .marketing_name =3D "Kompanio 520"}, + {.soc_name =3D "MT8186T", + .soc_segment_name =3D "MT8186TV/AZA", + .marketing_name =3D "Kompanio 528"}, +}; +/* end 8186 info */ + +/* begin 8188 info */ +#define mtk_mt8188_EFUSE_DATA_COUNT 2 +static struct efuse_data mtk_mt8188_efuse_data_info[][mtk_mt8188_EFUSE_DAT= A_COUNT] =3D { + {{.nvmem_cell_name =3D "socinfo-data1", .efuse_data =3D 0x81880000}, + {.nvmem_cell_name =3D "socinfo-data2", .efuse_data =3D 0x00000010}}, + {{.nvmem_cell_name =3D "socinfo-data1", .efuse_data =3D 0x81880000}, + {.nvmem_cell_name =3D "socinfo-data2", .efuse_data =3D 0x00000011}}, +}; + +static struct name_data mtk_mt8188_name_data_info[] =3D { + {.soc_name =3D "MT8188", + .soc_segment_name =3D "MT8188GV/AZA", + .marketing_name =3D "Kompanio 830"}, + {.soc_name =3D "MT8188", + .soc_segment_name =3D "MT8188GV/HZA", + .marketing_name =3D "Kompanio 830"}, +}; +/* end 8188 info */ + +/* begin 8195 info */ +#define mtk_mt8195_EFUSE_DATA_COUNT 1 +static struct efuse_data mtk_mt8195_efuse_data_info[][mtk_mt8195_EFUSE_DAT= A_COUNT] =3D { + {{.nvmem_cell_name =3D "socinfo-data1", .efuse_data =3D 0x81950300}}, + {{.nvmem_cell_name =3D "socinfo-data1", .efuse_data =3D 0x81950304}}, + {{.nvmem_cell_name =3D "socinfo-data1", .efuse_data =3D 0x81950400}}, + {{.nvmem_cell_name =3D "socinfo-data1", .efuse_data =3D 0x81950404}}, +}; + +static struct name_data mtk_mt8195_name_data_info[] =3D { + {.soc_name =3D "MT8195", + .soc_segment_name =3D "MT8195GV/EZA", + .marketing_name =3D "Kompanio 1200"}, + {.soc_name =3D "MT8195", + .soc_segment_name =3D "MT8195GV/EHZA", + .marketing_name =3D "Kompanio 1200"}, + {.soc_name =3D "MT8195T", + .soc_segment_name =3D "MT8195TV/EZA", + .marketing_name =3D "Kompanio 1380"}, + {.soc_name =3D "MT8195T", + .soc_segment_name =3D "MT8195TV/EHZA", + .marketing_name =3D "Kompanio 1380"}, +}; +/* end 8195 info */ + +/* begin 8192 info */ +#define mtk_mt8192_EFUSE_DATA_COUNT 2 +static struct efuse_data mtk_mt8192_efuse_data_info[][mtk_mt8192_EFUSE_DAT= A_COUNT] =3D { + {{.nvmem_cell_name =3D "socinfo-data1", .efuse_data =3D 0x00001100}, + {.nvmem_cell_name =3D "socinfo-data2", .efuse_data =3D 0x00040080}}, + {{.nvmem_cell_name =3D "socinfo-data1", .efuse_data =3D 0x00000100}, + {.nvmem_cell_name =3D "socinfo-data2", .efuse_data =3D 0x000400C0}}, +}; + +static struct name_data mtk_mt8192_name_data_info[] =3D { + {.soc_name =3D "MT8192", + .soc_segment_name =3D "MT8192V/AZA", + .marketing_name =3D "Kompanio 820"}, + {.soc_name =3D "MT8192T", + .soc_segment_name =3D "MT8192V/ATZA", + .marketing_name =3D "Kompanio 828"}, +}; +/* end 8192 info */ + +/* begin 8183 info */ +#define mtk_mt8183_EFUSE_DATA_COUNT 2 +static struct efuse_data mtk_mt8183_efuse_data_info[][mtk_mt8183_EFUSE_DAT= A_COUNT] =3D { + {{.nvmem_cell_name =3D "socinfo-data1", .efuse_data =3D 0x00010043}, + {.nvmem_cell_name =3D "socinfo-data2", .efuse_data =3D 0x00000840}}, +}; + +static struct name_data mtk_mt8183_name_data_info[] =3D { + {.soc_name =3D "MT8183", + .soc_segment_name =3D "MT8183V/AZA", + .marketing_name =3D "Kompanio 500"}, +}; +/* end 8183 info */ + +/* begin 8173 info */ +#define mtk_mt8173_EFUSE_DATA_COUNT 2 +static struct efuse_data mtk_mt8173_efuse_data_info[][mtk_mt8173_EFUSE_DAT= A_COUNT] =3D { + {{.nvmem_cell_name =3D "socinfo-data1", .efuse_data =3D 0x6CA20004}, + {.nvmem_cell_name =3D "socinfo-data2", .efuse_data =3D 0x10000000}}, +}; + +static struct name_data mtk_mt8173_name_data_info[] =3D { + {.soc_name =3D "MT8173", + .soc_segment_name =3D "MT8173V/AC", + .marketing_name =3D "MT8173"}, +}; +/* end 8173 info */ + +/* begin socinfo_data table */ +/* for get_soc_data lookup purposes */ +static struct socinfo_data socinfo_data_table[] =3D { + [INDEX_MT8186] =3D {.soc_name =3D "mt8186", + .efuse_data =3D &(mtk_mt8186_efuse_data_info[0][0]), + .name_data =3D mtk_mt8186_name_data_info, + .efuse_segment_count =3D ARRAY_SIZE(mtk_mt8186_name_data_info), + .efuse_data_count =3D mtk_mt8186_EFUSE_DATA_COUNT}, + [INDEX_MT8188] =3D {.soc_name =3D "mt8188", + .efuse_data =3D &(mtk_mt8188_efuse_data_info[0][0]), + .name_data =3D mtk_mt8188_name_data_info, + .efuse_segment_count =3D ARRAY_SIZE(mtk_mt8188_name_data_info), + .efuse_data_count =3D mtk_mt8188_EFUSE_DATA_COUNT}, + [INDEX_MT8195] =3D {.soc_name =3D "mt8195", + .efuse_data =3D &(mtk_mt8195_efuse_data_info[0][0]), + .name_data =3D mtk_mt8195_name_data_info, + .efuse_segment_count =3D ARRAY_SIZE(mtk_mt8195_name_data_info), + .efuse_data_count =3D mtk_mt8195_EFUSE_DATA_COUNT}, + [INDEX_MT8192] =3D {.soc_name =3D "mt8192", + .efuse_data =3D &(mtk_mt8192_efuse_data_info[0][0]), + .name_data =3D mtk_mt8192_name_data_info, + .efuse_segment_count =3D ARRAY_SIZE(mtk_mt8192_name_data_info), + .efuse_data_count =3D mtk_mt8192_EFUSE_DATA_COUNT}, + [INDEX_MT8183] =3D {.soc_name =3D "mt8183", + .efuse_data =3D &(mtk_mt8183_efuse_data_info[0][0]), + .name_data =3D mtk_mt8183_name_data_info, + .efuse_segment_count =3D ARRAY_SIZE(mtk_mt8183_name_data_info), + .efuse_data_count =3D mtk_mt8183_EFUSE_DATA_COUNT}, + [INDEX_MT8173] =3D {.soc_name =3D "mt8173", + .efuse_data =3D &(mtk_mt8173_efuse_data_info[0][0]), + .name_data =3D mtk_mt8173_name_data_info, + .efuse_segment_count =3D ARRAY_SIZE(mtk_mt8173_name_data_info), + .efuse_data_count =3D mtk_mt8173_EFUSE_DATA_COUNT}, +}; +/* end socinfo_data table */ + + +#endif /* __MTK_SOCINFO_H__ */ --=20 2.18.0 From nobody Fri Sep 20 13:45:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FD10EB64DA for ; Tue, 18 Jul 2023 11:22:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231656AbjGRLWD (ORCPT ); Tue, 18 Jul 2023 07:22:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231460AbjGRLV7 (ORCPT ); Tue, 18 Jul 2023 07:21:59 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B04BE8; Tue, 18 Jul 2023 04:21:58 -0700 (PDT) X-UUID: 4c2ae040255d11eeb20a276fd37b9834-20230718 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; 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Tue, 18 Jul 2023 19:21:53 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 18 Jul 2023 19:21:52 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 18 Jul 2023 19:21:52 +0800 From: William-tw Lin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kevin Hilman CC: , , , , , William-tw Lin Subject: [PATCH 2/3] dt-bindings: soc: mediatek: Add mtk-socinfo driver Date: Tue, 18 Jul 2023 19:21:42 +0800 Message-ID: <20230718112143.14036-3-william-tw.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230718112143.14036-1-william-tw.lin@mediatek.com> References: <20230718112143.14036-1-william-tw.lin@mediatek.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" dt-binding documentation for mtk-socinfo driver. mtk-socinfo driver provides SoC-related information. Such information includes manufacturer information, SoC name, SoC segment name, and SoC marketing name. Signed-off-by: William-tw Lin --- .../bindings/soc/mediatek/mtk-socinfo.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mtk-soci= nfo.yaml diff --git a/Documentation/devicetree/bindings/soc/mediatek/mtk-socinfo.yam= l b/Documentation/devicetree/bindings/soc/mediatek/mtk-socinfo.yaml new file mode 100644 index 000000000000..4420430a9bca --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/mtk-socinfo.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mediatek/mtk-socinfo.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SOC information + +maintainers: + - William Lin + - Matthias Brugger + - Kevin Hilman + +description: + The MTK socinfo driver can retrieve several + SoC related information based on settings in eFuse. + Such information include manufacturer information, SoC name, + SoC segment name, and SoC marketing name. + + +properties: + compatible: + enum: + - mediatek,mt8173-socinfo + - mediatek,mt8183-socinfo + - mediatek,mt8186-socinfo + - mediatek,mt8188-socinfo + - mediatek,mt8192-socinfo + - mediatek,mt8195-socinfo + + + nvmem-cells: + description: + Phandle to the eFuse data for SoC differentiation. + items: + - description: eFuse data that mtk-socinfo driver uses for SoC diffe= rentiation + + nvmem-cell-names: + minItems: 1 + items: + - const: socinfo-data1 + - const: socinfo-data2 + +required: + - compatible + - nvmem-cells + - nvmem-cell-names + +additionalProperties: false + +examples: + - | + mtk_socinfo: socinfo { + compatible =3D "mediatek,mt8186-socinfo"; + nvmem-cells =3D <&socinfo_data1>; + nvmem-cell-names =3D "socinfo-data1"; + }; + --=20 2.18.0 From nobody Fri Sep 20 13:45:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA9F1EB64DD for ; Tue, 18 Jul 2023 11:22:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231769AbjGRLWZ (ORCPT ); Tue, 18 Jul 2023 07:22:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231460AbjGRLWW (ORCPT ); Tue, 18 Jul 2023 07:22:22 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2E1B1732; Tue, 18 Jul 2023 04:22:10 -0700 (PDT) X-UUID: 51c7ed4a255d11eeb20a276fd37b9834-20230718 DKIM-Signature: v=1; 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Tue, 18 Jul 2023 19:22:02 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 18 Jul 2023 19:21:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 18 Jul 2023 19:21:54 +0800 From: William-tw Lin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kevin Hilman CC: , , , , , William-tw Lin Subject: [PATCH 3/3] arm64: dts: Add node for chip info driver Date: Tue, 18 Jul 2023 19:21:43 +0800 Message-ID: <20230718112143.14036-4-william-tw.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230718112143.14036-1-william-tw.lin@mediatek.com> References: <20230718112143.14036-1-william-tw.lin@mediatek.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add dts node for socinfo retrieval. This includes the following projects: MT8173 MT8183 MT8186 MT8192 MT8195 Signed-off-by: William-tw Lin --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/mediatek/mt8186.dtsi | 10 ++++++++++ arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 9 +++++++++ 5 files changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts= /mediatek/mt8173.dtsi index c47d7d900f28..115f907751c1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -590,11 +590,26 @@ reg =3D <0 0x10206000 0 0x1000>; #address-cells =3D <1>; #size-cells =3D <1>; + + socinfo_data1: socinfo-data1 { + reg =3D <0x040 0x4>; + }; + + socinfo_data2: socinfo-data2 { + reg =3D <0x044 0x4>; + }; + thermal_calibration: calib@528 { reg =3D <0x528 0xc>; }; }; =20 + mtk_socinfo: mtk-socinfo { + compatible =3D "mediatek,mt8173-socinfo"; + nvmem-cells =3D <&socinfo_data1 &socinfo_data2>; + nvmem-cell-names =3D "socinfo-data1", "socinfo-data2"; + }; + apmixedsys: clock-controller@10209000 { compatible =3D "mediatek,mt8173-apmixedsys"; reg =3D <0 0x10209000 0 0x1000>; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts= /mediatek/mt8183.dtsi index 5169779d01df..1035c6d7eb91 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1706,6 +1706,15 @@ reg =3D <0 0x11f10000 0 0x1000>; #address-cells =3D <1>; #size-cells =3D <1>; + + socinfo_data1: socinfo-data1 { + reg =3D <0x04C 0x4>; + }; + + socinfo_data2: socinfo-data2 { + reg =3D <0x060 0x4>; + }; + thermal_calibration: calib@180 { reg =3D <0x180 0xc>; }; @@ -1719,6 +1728,12 @@ }; }; =20 + mtk_socinfo: mtk-socinfo { + compatible =3D "mediatek,mt8183-socinfo"; + nvmem-cells =3D <&socinfo_data1 &socinfo_data2>; + nvmem-cell-names =3D "socinfo-data1", "socinfo-data2"; + }; + u3phy: t-phy@11f40000 { compatible =3D "mediatek,mt8183-tphy", "mediatek,generic-tphy-v2"; diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index f04ae70c470a..e048e4d994e9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1660,6 +1660,16 @@ reg =3D <0x59c 0x4>; bits =3D <0 3>; }; + + socinfo_data1: socinfo-data1 { + reg =3D <0x7a0 0x4>; + }; + }; + + mtk_socinfo: socinfo { + compatible =3D "mediatek,mt8186-socinfo"; + nvmem-cells =3D <&socinfo_data1>; + nvmem-cell-names =3D "socinfo-data1"; }; =20 mipi_tx0: dsi-phy@11cc0000 { diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 5e94cb4aeb44..80066faf2b2c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1122,6 +1122,14 @@ #address-cells =3D <1>; #size-cells =3D <1>; =20 + socinfo_data1: socinfo-data1 { + reg =3D <0x044 0x4>; + }; + + socinfo_data2: socinfo-data2 { + reg =3D <0x050 0x4>; + }; + lvts_e_data1: data1@1c0 { reg =3D <0x1c0 0x58>; }; @@ -1131,6 +1139,12 @@ }; }; =20 + mtk_socinfo: mtk-socinfo { + compatible =3D "mediatek,mt8192-socinfo"; + nvmem-cells =3D <&socinfo_data1 &socinfo_data2>; + nvmem-cell-names =3D "socinfo-data1", "socinfo-data2"; + }; + i2c3: i2c@11cb0000 { compatible =3D "mediatek,mt8192-i2c"; reg =3D <0 0x11cb0000 0 0x1000>, diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 48b72b3645e1..ec8f2c8888cb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1683,6 +1683,15 @@ lvts_efuse_data2: lvts2-calib@1d0 { reg =3D <0x1d0 0x38>; }; + socinfo_data1: socinfo-data1 { + reg =3D <0x7a0 0x4>; + }; + }; + + mtk_socinfo: socinfo { + compatible =3D "mediatek,mt8195-socinfo"; + nvmem-cells =3D <&socinfo_data1>; + nvmem-cell-names =3D "socinfo-data1"; }; =20 u3phy2: t-phy@11c40000 { --=20 2.18.0