From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39F2DEB64DC for ; Mon, 17 Jul 2023 23:14:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231283AbjGQXOt (ORCPT ); Mon, 17 Jul 2023 19:14:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230219AbjGQXOo (ORCPT ); Mon, 17 Jul 2023 19:14:44 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 504CF10B for ; Mon, 17 Jul 2023 16:14:38 -0700 (PDT) Message-ID: <20230717223223.133987570@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635675; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=M0jSiCsQ7CMtXtLpUe8NnWl6LgxPIdT2LQPqXY/B010=; b=ERBnEIn79Bu9QSKIoMn+fHdK4gIfX8KEiTmh8bJE5iNHtOcSS3NkSFTc3RZ9wQTc+ZVw9O SIUDyRXPWb/iERKMUtrU1NWucmjEASGwGp0XcRWJVpREbAm1ftrSAdFRyOkFrQ0MVgL99s Lcncxdpx2p16ogw8Kr/7+DET0U9sW7ILHBUgpKXhhsxKgAdx81lvKLX8oFMxxrw2SWqQAD V+u40tZiRwS0Av9AZppWlIrYOQCLLNit/kzeF5O7eq3d8+32O4IM8kwA6N8ra//WOBlPKx Yl8u536+11Z6SaynRB1HN4M5LwdMe721i+WMfbXN9bZH4wAFOA9b1cGx9EgKSw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635675; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=M0jSiCsQ7CMtXtLpUe8NnWl6LgxPIdT2LQPqXY/B010=; b=0FkHf1ads7F4traM8giao9RtwB8UYif28wOFycU0DCs5KlpAQXiirEv68DhTAkL9tSiOiP SYJTc5IDenMcAvBg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 01/58] x86/cpu: Make identify_boot_cpu() static References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:14:35 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It's not longer used outside the source file. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/processor.h | 1 - arch/x86/kernel/cpu/common.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -190,7 +190,6 @@ static inline unsigned long long l1tf_pf } =20 extern void early_cpu_init(void); -extern void identify_boot_cpu(void); extern void identify_secondary_cpu(struct cpuinfo_x86 *); extern void print_cpu_info(struct cpuinfo_x86 *); void print_cpu_msr(struct cpuinfo_x86 *); --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1937,7 +1937,7 @@ void enable_sep_cpu(void) } #endif =20 -void __init identify_boot_cpu(void) +static __init void identify_boot_cpu(void) { identify_cpu(&boot_cpu_data); if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT)) From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 746D2C0015E for ; Mon, 17 Jul 2023 23:14:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230339AbjGQXOw (ORCPT ); Mon, 17 Jul 2023 19:14:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231186AbjGQXOo (ORCPT ); Mon, 17 Jul 2023 19:14:44 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B887E12D for ; Mon, 17 Jul 2023 16:14:38 -0700 (PDT) Message-ID: <20230717223223.194942624@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635677; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=wpfpHOFENc3IPULGB99WSPXmdgySC90OqR7vmMwU8qU=; b=qAJH9ZInd6QS57kqU21jjx7PhuqHsepVuGll5ofOEwQWJL1/sFLOnjZ34EBGsJwJWbKvpY wv+zh4cBYwLIzYXEPvnhIHZg8F86wcIdAl2xh8iRVq8plyF22kHCi4ZU5rD9mh8u3+yc2b BcKn8m/oiYwct7zjwIhDevHX2StrtmZzarP6GQkFUqkwqnZTYA+OqDymMH05RTuF2sGRk6 aiqek6XxC65mA9bJ3Klc1FP49ItANn3puhn0SNDgV4UcNPTKDCzKQNOF0vdJGr65iPfrHN bjDQkqSbexkWzcb/BN7wQYYsrxxFtUXSHylPl74uFG92tSDMrZ6GD6rfXRnK5Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635677; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=wpfpHOFENc3IPULGB99WSPXmdgySC90OqR7vmMwU8qU=; b=ZwLQueWk3iuye6RCxPL7GI5eQfeQLFp/Cmp+9F4jdovHOSbJt2O3OGatSO5ru7KKSf09oo qoIwD8KcUbsW+VBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 02/58] x86/cpu: Remove unused physid_*() nonsense References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:14:36 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Tons of silly unused bitmap wrappers... Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/mpspec.h | 26 -------------------------- 1 file changed, 26 deletions(-) --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -87,13 +87,7 @@ struct physid_mask { typedef struct physid_mask physid_mask_t; =20 #define physid_set(physid, map) set_bit(physid, (map).mask) -#define physid_clear(physid, map) clear_bit(physid, (map).mask) #define physid_isset(physid, map) test_bit(physid, (map).mask) -#define physid_test_and_set(physid, map) \ - test_and_set_bit(physid, (map).mask) - -#define physids_and(dst, src1, src2) \ - bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC) =20 #define physids_or(dst, src1, src2) \ bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC) @@ -101,29 +95,9 @@ typedef struct physid_mask physid_mask_t #define physids_clear(map) \ bitmap_zero((map).mask, MAX_LOCAL_APIC) =20 -#define physids_complement(dst, src) \ - bitmap_complement((dst).mask, (src).mask, MAX_LOCAL_APIC) - #define physids_empty(map) \ bitmap_empty((map).mask, MAX_LOCAL_APIC) =20 -#define physids_equal(map1, map2) \ - bitmap_equal((map1).mask, (map2).mask, MAX_LOCAL_APIC) - -#define physids_weight(map) \ - bitmap_weight((map).mask, MAX_LOCAL_APIC) - -#define physids_shift_right(d, s, n) \ - bitmap_shift_right((d).mask, (s).mask, n, MAX_LOCAL_APIC) - -#define physids_shift_left(d, s, n) \ - bitmap_shift_left((d).mask, (s).mask, n, MAX_LOCAL_APIC) - -static inline unsigned long physids_coerce(physid_mask_t *map) -{ - return map->mask[0]; -} - static inline void physids_promote(unsigned long physids, physid_mask_t *m= ap) { physids_clear(*map); From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59E7BEB64DC for ; Mon, 17 Jul 2023 23:14:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231339AbjGQXO5 (ORCPT ); Mon, 17 Jul 2023 19:14:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231276AbjGQXOr (ORCPT ); Mon, 17 Jul 2023 19:14:47 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F9D8134 for ; Mon, 17 Jul 2023 16:14:41 -0700 (PDT) Message-ID: <20230717223223.254985852@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635679; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=kmGoR4mtRRMrd4AtT9GP/yyIU8+rEj6XhsXhXl097vA=; b=OYTaewL/r1krBi7/RMUewtLpZAjjdK8XBzCYSA3e5FoFsCHBjhcV/w1LBCVXCMJG6oHkzU nKqRcxARz3gVxzT6vDFby5/k2C5NJqbfr8X3v6Fq1hfde7WihAiL/sQIgrCxVrCBSrrkIh 7C3KILzRfvkaXWsOH1EzeaBltlzdTW2tgIrF1fMMzzclfXw17n3v8a2gCVENjdFDg/8h9I nPkkY44s4LLmNEDoiKgvSrra84aKFxIFUp37j8dFkxb+lRzgAr5exn/FdqKt3yxBVZSdHP 1nBxuqJQM1DqM/+BppMCSQpjoY9oRYIx3M2Fy3C+dswONZtvhbAbaFKp18/1aQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635679; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=kmGoR4mtRRMrd4AtT9GP/yyIU8+rEj6XhsXhXl097vA=; b=iXr/4XntnkHqmSiW/g8fdw+oCcu+dignGQiY50w41sNM4KD3aEUwLpm3pwHjaG0hkciWc1 qUyDCuAm/fm+YgAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 03/58] x86/apic: Rename disable_apic References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:14:38 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It reflects a state and not a command. Make it bool while at it. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 4 ++-- arch/x86/kernel/apic/apic.c | 22 +++++++++++----------- arch/x86/kernel/apic/apic_noop.c | 6 +++--- arch/x86/kernel/apic/msi.c | 2 +- arch/x86/kernel/apic/vector.c | 2 +- arch/x86/kernel/setup.c | 2 +- arch/x86/pci/xen.c | 2 +- 7 files changed, 20 insertions(+), 20 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -52,7 +52,7 @@ static inline void generic_apic_probe(vo extern int apic_verbosity; extern int local_apic_timer_c2_ok; =20 -extern int disable_apic; +extern bool apic_is_disabled; extern unsigned int lapic_timer_period; =20 extern int cpuid_to_apicid[]; @@ -90,7 +90,7 @@ static inline void default_inquire_remot */ static inline bool apic_from_smp_config(void) { - return smp_found_config && !disable_apic; + return smp_found_config && !apic_is_disabled; } =20 /* --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -180,7 +180,7 @@ static __init int setup_apicpmtimer(char #endif =20 unsigned long mp_lapic_addr __ro_after_init; -int disable_apic __ro_after_init; +bool apic_is_disabled __ro_after_init; /* Disable local APIC timer from the kernel commandline or via dmi quirk */ static int disable_apic_timer __initdata; /* Local APIC timer works in C2 */ @@ -810,7 +810,7 @@ bool __init apic_needs_pit(void) return true; =20 /* Is there an APIC at all or is it disabled? */ - if (!boot_cpu_has(X86_FEATURE_APIC) || disable_apic) + if (!boot_cpu_has(X86_FEATURE_APIC) || apic_is_disabled) return true; =20 /* @@ -1299,7 +1299,7 @@ enum apic_intr_mode_id apic_intr_mode __ static int __init __apic_intr_mode_select(void) { /* Check kernel option */ - if (disable_apic) { + if (apic_is_disabled) { pr_info("APIC disabled via kernel command line\n"); return APIC_PIC; } @@ -1308,7 +1308,7 @@ static int __init __apic_intr_mode_selec #ifdef CONFIG_X86_64 /* On 64-bit, the APIC must be integrated, Check local APIC only */ if (!boot_cpu_has(X86_FEATURE_APIC)) { - disable_apic =3D 1; + apic_is_disabled =3D true; pr_info("APIC disabled by BIOS\n"); return APIC_PIC; } @@ -1317,14 +1317,14 @@ static int __init __apic_intr_mode_selec =20 /* Neither 82489DX nor integrated APIC ? */ if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { - disable_apic =3D 1; + apic_is_disabled =3D true; return APIC_PIC; } =20 /* If the BIOS pretends there is an integrated APIC ? */ if (!boot_cpu_has(X86_FEATURE_APIC) && APIC_INTEGRATED(boot_cpu_apic_version)) { - disable_apic =3D 1; + apic_is_disabled =3D true; pr_err(FW_BUG "Local APIC %d not detected, force emulation\n", boot_cpu_physical_apicid); return APIC_PIC; @@ -1567,7 +1567,7 @@ static void setup_local_APIC(void) int cpu =3D smp_processor_id(); unsigned int value; =20 - if (disable_apic) { + if (apic_is_disabled) { disable_ioapic_support(); return; } @@ -1943,7 +1943,7 @@ void __init check_x2apic(void) pr_err("Kernel does not support x2APIC, please recompile with CONFIG_X86_= X2APIC.\n"); pr_err("Disabling APIC, expect reduced performance and functionality.\n"); =20 - disable_apic =3D 1; + apic_is_disabled =3D true; setup_clear_cpu_cap(X86_FEATURE_APIC); } =20 @@ -2037,7 +2037,7 @@ int __init apic_force_enable(unsigned lo { u32 h, l; =20 - if (disable_apic) + if (apic_is_disabled) return -1; =20 /* @@ -2064,7 +2064,7 @@ int __init apic_force_enable(unsigned lo static int __init detect_init_APIC(void) { /* Disabled by kernel option? */ - if (disable_apic) + if (apic_is_disabled) return -1; =20 switch (boot_cpu_data.x86_vendor) { @@ -2919,7 +2919,7 @@ int apic_is_clustered_box(void) */ static int __init setup_disableapic(char *arg) { - disable_apic =3D 1; + apic_is_disabled =3D true; setup_clear_cpu_cap(X86_FEATURE_APIC); return 0; } --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -71,13 +71,13 @@ static int noop_apic_id_registered(void) =20 static u32 noop_apic_read(u32 reg) { - WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_APIC) && !disable_apic); + WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_APIC) && !apic_is_disabled); return 0; } =20 -static void noop_apic_write(u32 reg, u32 v) +static void noop_apic_write(u32 reg, u32 val) { - WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_APIC) && !disable_apic); + WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_APIC) && !apic_is_disabled); } =20 #ifdef CONFIG_X86_32 --- a/arch/x86/kernel/apic/msi.c +++ b/arch/x86/kernel/apic/msi.c @@ -269,7 +269,7 @@ static const struct msi_parent_ops x86_v =20 struct irq_domain * __init native_create_pci_msi_domain(void) { - if (disable_apic) + if (apic_is_disabled) return NULL; =20 x86_vector_domain->flags |=3D IRQ_DOMAIN_FLAG_MSI_PARENT; --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -536,7 +536,7 @@ static int x86_vector_alloc_irqs(struct struct irq_data *irqd; int i, err, node; =20 - if (disable_apic) + if (apic_is_disabled) return -ENXIO; =20 /* --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1020,7 +1020,7 @@ void __init setup_arch(char **cmdline_p) =20 if (acpi_mps_check()) { #ifdef CONFIG_X86_LOCAL_APIC - disable_apic =3D 1; + apic_is_disabled =3D true; #endif setup_clear_cpu_cap(X86_FEATURE_APIC); } --- a/arch/x86/pci/xen.c +++ b/arch/x86/pci/xen.c @@ -517,7 +517,7 @@ int __init pci_xen_init(void) #ifdef CONFIG_PCI_MSI static void __init xen_hvm_msi_init(void) { - if (!disable_apic) { + if (!apic_is_disabled) { /* * If hardware supports (x2)APIC virtualization (as indicated * by hypervisor's leaf 4) then we don't need to use pirqs/ From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66D50C001DC for ; Mon, 17 Jul 2023 23:14:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231300AbjGQXOy (ORCPT ); Mon, 17 Jul 2023 19:14:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231270AbjGQXOr (ORCPT ); Mon, 17 Jul 2023 19:14:47 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C81DEE for ; Mon, 17 Jul 2023 16:14:42 -0700 (PDT) Message-ID: <20230717223223.317323519@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635680; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=F/lkmcLew6wqhkY5nJAZg4imK+gggfMNV+OuyUmPL8o=; b=uiFj6CC6v/py1Hit7tvREfXSrDdl8w9xO+wN+Mr35tSIF1WJcillzcqndfYZoFIS0Cq70f KknJhHr/Gg0MnpqRg7Y+BKELgG0auUUjoI5EWKq6gya8zPlSk7ItJIJlOjwUa/gJseRkUl DFR/Cv6jmYuOGVLd3G8PtS+XoI6wd2XMs5E5Zo++suwaI9psUn/Mw3CJfKX2lvfEyVzGGy OAyuzEXqzu/q8ir/hX/zn2Oako1xwQfnIOpFYBQAws1nhDCou1bOAEpznPWAcnvz7/77a3 GmAsk+/TkC42G7PC4UYZN4FUnY7Y1x1HQC9maw47xRi2e9FmnUk5SLRhhrxdoQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635680; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=F/lkmcLew6wqhkY5nJAZg4imK+gggfMNV+OuyUmPL8o=; b=q2ghj+d5WmJExyAmN1P51i1+vZOwEurdMplxcG6ahp9nlsJkce/+Jg1dyUz0JTjqhDCpi4 HFhQmyOcsOXn+8Aw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 04/58] x86/apic/ioapic: Rename skip_ioapic_setup References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:14:40 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Another variable name which is confusing at best. Convert to bool. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/io_apic.h | 7 ++++--- arch/x86/kernel/acpi/boot.c | 2 +- arch/x86/kernel/apic/apic.c | 12 ++++++------ arch/x86/kernel/apic/io_apic.c | 12 ++++++------ arch/x86/xen/smp_pv.c | 2 +- 5 files changed, 18 insertions(+), 17 deletions(-) --- a/arch/x86/include/asm/io_apic.h +++ b/arch/x86/include/asm/io_apic.h @@ -109,8 +109,8 @@ extern int mp_irq_entries; /* MP IRQ source entries */ extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; =20 -/* 1 if "noapic" boot option passed */ -extern int skip_ioapic_setup; +/* True if "noapic" boot option passed */ +extern bool ioapic_is_disabled; =20 /* 1 if "noapic" boot option passed */ extern int noioapicquirk; @@ -129,7 +129,7 @@ extern unsigned long io_apic_irqs; * assignment of PCI IRQ's. */ #define io_apic_assign_pci_irqs \ - (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs) + (mp_irq_entries && !ioapic_is_disabled && io_apic_irqs) =20 struct irq_cfg; extern void ioapic_insert_resources(void); @@ -179,6 +179,7 @@ extern void print_IO_APICs(void); #define IO_APIC_IRQ(x) 0 #define io_apic_assign_pci_irqs 0 #define setup_ioapic_ids_from_mpc x86_init_noop +#define nr_ioapics (0) static inline void ioapic_insert_resources(void) { } static inline int arch_early_ioapic_init(void) { return 0; } static inline void print_IO_APICs(void) {} --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -1275,7 +1275,7 @@ static int __init acpi_parse_madt_ioapic /* * if "noapic" boot option, don't look for IO-APICs */ - if (skip_ioapic_setup) { + if (ioapic_is_disabled) { pr_info("Skipping IOAPIC probe due to 'noapic' option.\n"); return -ENODEV; } --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1691,7 +1691,7 @@ static void setup_local_APIC(void) * TODO: set up through-local-APIC from through-I/O-APIC? --macro */ value =3D apic_read(APIC_LVT0) & APIC_LVT_MASKED; - if (!cpu && (pic_mode || !value || skip_ioapic_setup)) { + if (!cpu && (pic_mode || !value || ioapic_is_disabled)) { value =3D APIC_DM_EXTINT; apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); } else { @@ -1956,7 +1956,7 @@ void __init enable_IR_x2apic(void) unsigned long flags; int ret, ir_stat; =20 - if (skip_ioapic_setup) { + if (ioapic_is_disabled) { pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n= "); return; } @@ -2956,11 +2956,11 @@ early_param("nolapic_timer", parse_nolap static int __init apic_set_verbosity(char *arg) { if (!arg) { -#ifdef CONFIG_X86_64 - skip_ioapic_setup =3D 0; + if (IS_ENABLED(CONFIG_X86_32)) + return -EINVAL; + + ioapic_is_disabled =3D false; return 0; -#endif - return -EINVAL; } =20 if (strcmp("debug", arg) =3D=3D 0) --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -178,7 +178,7 @@ int mp_bus_id_to_type[MAX_MP_BUSSES]; =20 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); =20 -int skip_ioapic_setup; +bool ioapic_is_disabled __ro_after_init; =20 /** * disable_ioapic_support() - disables ioapic support at runtime @@ -189,7 +189,7 @@ void disable_ioapic_support(void) noioapicquirk =3D 1; noioapicreroute =3D -1; #endif - skip_ioapic_setup =3D 1; + ioapic_is_disabled =3D true; } =20 static int __init parse_noapic(char *str) @@ -831,7 +831,7 @@ static int __acpi_get_override_irq(u32 g { int ioapic, pin, idx; =20 - if (skip_ioapic_setup) + if (ioapic_is_disabled) return -1; =20 ioapic =3D mp_find_ioapic(gsi); @@ -1366,7 +1366,7 @@ void __init enable_IO_APIC(void) int i8259_apic, i8259_pin; int apic, pin; =20 - if (skip_ioapic_setup) + if (ioapic_is_disabled) nr_ioapics =3D 0; =20 if (!nr_legacy_irqs() || !nr_ioapics) @@ -2399,7 +2399,7 @@ void __init setup_IO_APIC(void) { int ioapic; =20 - if (skip_ioapic_setup || !nr_ioapics) + if (ioapic_is_disabled || !nr_ioapics) return; =20 io_apic_irqs =3D nr_legacy_irqs() ? ~PIC_IRQS : ~0UL; @@ -2715,7 +2715,7 @@ void __init io_apic_init_mappings(void) "address found in MPTABLE, " "disabling IO/APIC support!\n"); smp_found_config =3D 0; - skip_ioapic_setup =3D 1; + ioapic_is_disabled =3D true; goto fake_ioapic_page; } #endif --- a/arch/x86/xen/smp_pv.c +++ b/arch/x86/xen/smp_pv.c @@ -209,7 +209,7 @@ static void __init xen_pv_smp_prepare_cp { unsigned cpu; =20 - if (skip_ioapic_setup) { + if (ioapic_is_disabled) { char *m =3D (max_cpus =3D=3D 0) ? "The nosmp parameter is incompatible with Xen; " \ "use Xen dom0_max_vcpus=3D1 parameter" : From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23526EB64DC for ; Mon, 17 Jul 2023 23:15:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231358AbjGQXO7 (ORCPT ); Mon, 17 Jul 2023 19:14:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231288AbjGQXOt (ORCPT ); Mon, 17 Jul 2023 19:14:49 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F070D103 for ; Mon, 17 Jul 2023 16:14:43 -0700 (PDT) Message-ID: <20230717223223.378340278@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635682; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=sgp4Cpxc278kVycdX9SIuNrsT7R7GKw0D1ebmk2Yzdc=; b=0q4LFQnJjpYRlnTDc8bZdTei1OzL5wuMK4xXXo1j3y7tjv7rh1PJipNPrk50e/vgGo2431 3tqtsT/EHzNnuIMOHa/8TEqxXMCiwGxNSoAGaVs4GDOmOFvEuihtXhgu+DjnwuhePZTFWU 0CzHimOzSBgJA5Q4wJU2WxpKEu0vRBTcGxuf1AGBgyXNfnvOLwc6L9y8jy2XS1ZyvRIGpf feA1F/N1VH4NG3n9cygptFjkz0wM7tj/W+PscLcAHXgXz5hM/3adFm3KKfBwD+ckLOmGrb fvzWECWgppZK/OhhRycITP0+G7ekmutGZ7l8ZrJ07x8sWmqaSj+qmhc5YfVCGg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635682; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=sgp4Cpxc278kVycdX9SIuNrsT7R7GKw0D1ebmk2Yzdc=; b=I2LneLJvvSILrQQSkCNlZLnjLon4cEtxb5pZSW/6MvTU7z2qiRk0/0FHavygX9Y6fBbf4g xR4yntUdN4xtIcBg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 05/58] x86/apic: Remove pointless x86_bios_cpu_apicid References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:14:41 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It's a useless copy of x86_cpu_to_apicid. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 2 -- arch/x86/include/asm/smp.h | 1 - arch/x86/kernel/apic/apic.c | 5 +---- arch/x86/kernel/apic/apic_common.c | 2 +- arch/x86/kernel/apic/bigsmp_32.c | 2 +- arch/x86/kernel/apic/probe_64.c | 4 +--- arch/x86/kernel/setup_percpu.c | 3 --- 7 files changed, 4 insertions(+), 15 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -477,8 +477,6 @@ extern void generic_bigsmp_probe(void); =20 #define APIC_DFR_VALUE (APIC_DFR_FLAT) =20 -DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); - extern struct apic apic_noop; =20 static inline unsigned int read_apic_id(void) --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -22,7 +22,6 @@ DECLARE_PER_CPU_READ_MOSTLY(u16, cpu_l2c =20 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid); DECLARE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid); -DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) DECLARE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid); #endif --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -108,10 +108,8 @@ unsigned long apic_mmio_base __ro_after_ * Map cpu index to physical APIC ID */ DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); -DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); -EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); =20 #ifdef CONFIG_X86_32 @@ -2511,7 +2509,7 @@ int generic_processor_info(int apicid, i =20 if (apicid =3D=3D boot_cpu_physical_apicid) { /* - * x86_bios_cpu_apicid is required to have processors listed + * x86_cpu_to_apicid is required to have processors listed * in same order as logical cpu numbers. Hence the first * entry is BSP, and so on. * boot_cpu_init() already hold bit 0 in cpu_present_mask @@ -2548,7 +2546,6 @@ int generic_processor_info(int apicid, i =20 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) early_per_cpu(x86_cpu_to_apicid, cpu) =3D apicid; - early_per_cpu(x86_bios_cpu_apicid, cpu) =3D apicid; #endif #ifdef CONFIG_X86_32 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =3D --- a/arch/x86/kernel/apic/apic_common.c +++ b/arch/x86/kernel/apic/apic_common.c @@ -29,7 +29,7 @@ void default_ioapic_phys_id_map(physid_m int default_cpu_present_to_apicid(int mps_cpu) { if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) - return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); + return (int)per_cpu(x86_cpu_to_apicid, mps_cpu); else return BAD_APICID; } --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -52,7 +52,7 @@ static void bigsmp_setup_apic_routing(vo static int bigsmp_cpu_present_to_apicid(int mps_cpu) { if (mps_cpu < nr_cpu_ids) - return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu); + return (int) per_cpu(x86_cpu_to_apicid, mps_cpu); =20 return BAD_APICID; } --- a/arch/x86/kernel/apic/probe_64.c +++ b/arch/x86/kernel/apic/probe_64.c @@ -13,9 +13,7 @@ =20 #include "local.h" =20 -/* - * Check the APIC IDs in bios_cpu_apicid and choose the APIC mode. - */ +/* Select the appropriate APIC driver */ void __init default_setup_apic_routing(void) { struct apic **drv; --- a/arch/x86/kernel/setup_percpu.c +++ b/arch/x86/kernel/setup_percpu.c @@ -181,8 +181,6 @@ void __init setup_per_cpu_areas(void) #ifdef CONFIG_X86_LOCAL_APIC per_cpu(x86_cpu_to_apicid, cpu) =3D early_per_cpu_map(x86_cpu_to_apicid, cpu); - per_cpu(x86_bios_cpu_apicid, cpu) =3D - early_per_cpu_map(x86_bios_cpu_apicid, cpu); per_cpu(x86_cpu_to_acpiid, cpu) =3D early_per_cpu_map(x86_cpu_to_acpiid, cpu); #endif @@ -214,7 +212,6 @@ void __init setup_per_cpu_areas(void) /* indicate the early static arrays will soon be gone */ #ifdef CONFIG_X86_LOCAL_APIC early_per_cpu_ptr(x86_cpu_to_apicid) =3D NULL; - early_per_cpu_ptr(x86_bios_cpu_apicid) =3D NULL; early_per_cpu_ptr(x86_cpu_to_acpiid) =3D NULL; #endif #ifdef CONFIG_X86_32 From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0303FEB64DC for ; Mon, 17 Jul 2023 23:15:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229764AbjGQXPF (ORCPT ); Mon, 17 Jul 2023 19:15:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231289AbjGQXOu (ORCPT ); Mon, 17 Jul 2023 19:14:50 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4109D12D for ; Mon, 17 Jul 2023 16:14:46 -0700 (PDT) Message-ID: <20230717223223.438098301@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635683; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=H6xuaSb8Kv7Un+nSM3Vt2lhh8dacGbRBYIeoXvHjk4U=; b=ZJdVRLZPN67L2dDZ8WvxnfDEt6uQADsS5bnFlPHvH3ZRokAIdVrgaEVoGxFE5UMbpwyDpv nF4bEllwtYfNdLtVwXJ6jaBIatetjaRvX0m4A7FoTO/ZECJiJRRvxpwgxmGj9MMqZa4cYA N8tyvOa5T46kp31qUnrrsWwKICmDRC/lUQ5iXXNiIS1alfimY4XPDxpGeqyqG00EQUVMay yoQkOaCtTaaB9W8lw1zqtjQ+3L4fXyHeNOEZxlfNkxDdRlzV6OSf+VEkaITAn288LuxqTm TdMk2I16aIMyq1F78nBA7FpBp4ZEMPl45zL1Kcye9hJGHU1LmyqM6EbBdM8+Qg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635683; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=H6xuaSb8Kv7Un+nSM3Vt2lhh8dacGbRBYIeoXvHjk4U=; b=fz3+bO0FtQwi+qTH7NfLuuj8FqYv8Q2KtVMXfd2KDhSIJ3inQcicCkuFCsIh1GYw3WqUB5 STHbbuMJxXOwMeCQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 06/58] x86/apic: Get rid of hard_smp_processor_id() References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:14:43 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" No point in having a wrapper around read_apic_id(). Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 6 +++++- arch/x86/include/asm/smp.h | 7 ------- arch/x86/kernel/apic/apic.c | 5 ----- arch/x86/kernel/apic/io_apic.c | 2 +- arch/x86/kernel/apic/ipi.c | 2 +- arch/x86/kernel/apic/vector.c | 2 +- arch/x86/kernel/cpu/amd.c | 2 +- arch/x86/kernel/cpu/hygon.c | 3 ++- arch/x86/kernel/smpboot.c | 10 +++++----- arch/x86/kernel/vsmp_64.c | 2 +- 10 files changed, 17 insertions(+), 24 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -503,7 +503,11 @@ extern void default_ioapic_phys_id_map(p extern int default_cpu_present_to_apicid(int mps_cpu); extern int default_check_phys_apicid_present(int phys_apicid); =20 -#endif /* CONFIG_X86_LOCAL_APIC */ +#else /* CONFIG_X86_LOCAL_APIC */ + +static inline unsigned int read_apic_id(void) { return 0; } + +#endif /* !CONFIG_X86_LOCAL_APIC */ =20 #ifdef CONFIG_SMP void apic_smt_update(void); --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -185,13 +185,6 @@ static inline struct cpumask *cpu_llc_sh =20 extern unsigned disabled_cpus; =20 -#ifdef CONFIG_X86_LOCAL_APIC -extern int hard_smp_processor_id(void); - -#else /* CONFIG_X86_LOCAL_APIC */ -#define hard_smp_processor_id() 0 -#endif /* CONFIG_X86_LOCAL_APIC */ - #ifdef CONFIG_DEBUG_NMI_SELFTEST extern void nmi_selftest(void); #else --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2562,11 +2562,6 @@ int generic_processor_info(int apicid, i return cpu; } =20 -int hard_smp_processor_id(void) -{ - return read_apic_id(); -} - void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, bool dmar) { --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -2095,7 +2095,7 @@ static inline void __init unlock_ExtINT_ entry0 =3D ioapic_read_entry(apic, pin); clear_IO_APIC_pin(apic, pin); =20 - apic_id =3D hard_smp_processor_id(); + apic_id =3D read_apic_id(); memset(&entry1, 0, sizeof(entry1)); =20 entry1.dest_mode_logical =3D true; --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -320,7 +320,7 @@ int safe_smp_processor_id(void) if (!boot_cpu_has(X86_FEATURE_APIC)) return 0; =20 - apicid =3D hard_smp_processor_id(); + apicid =3D read_apic_id(); if (apicid =3D=3D BAD_APICID) return 0; =20 --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -1150,7 +1150,7 @@ static void __init print_local_APIC(void u64 icr; =20 pr_debug("printing local APIC contents on CPU#%d/%d:\n", - smp_processor_id(), hard_smp_processor_id()); + smp_processor_id(), read_apic_id()); v =3D apic_read(APIC_ID); pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); v =3D apic_read(APIC_LVR); --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -934,7 +934,7 @@ static void init_amd(struct cpuinfo_x86 set_cpu_cap(c, X86_FEATURE_FSRS); =20 /* get apicid instead of initial apic id from cpuid */ - c->apicid =3D hard_smp_processor_id(); + c->apicid =3D read_apic_id(); =20 /* K6s reports MCEs but don't actually have all the MSRs */ if (c->x86 < 6) --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -8,6 +8,7 @@ */ #include =20 +#include #include #include #include @@ -300,7 +301,7 @@ static void init_hygon(struct cpuinfo_x8 set_cpu_cap(c, X86_FEATURE_REP_GOOD); =20 /* get apicid instead of initial apic id from cpuid */ - c->apicid =3D hard_smp_processor_id(); + c->apicid =3D read_apic_id(); =20 /* * XXX someone from Hygon needs to confirm this DTRT --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1220,11 +1220,11 @@ static void __init smp_sanity_check(void } #endif =20 - if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { + if (!physid_isset(read_apic_id(), phys_cpu_present_map)) { pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", - hard_smp_processor_id()); + read_apic_id()); =20 - physid_set(hard_smp_processor_id(), phys_cpu_present_map); + physid_set(read_apic_id(), phys_cpu_present_map); } =20 /* @@ -1234,7 +1234,7 @@ static void __init smp_sanity_check(void if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", boot_cpu_physical_apicid); - physid_set(hard_smp_processor_id(), phys_cpu_present_map); + physid_set(read_apic_id(), phys_cpu_present_map); } preempt_enable(); } @@ -1431,7 +1431,7 @@ early_param("possible_cpus", _setup_poss if (!num_processors) { if (boot_cpu_has(X86_FEATURE_APIC)) { int apicid =3D boot_cpu_physical_apicid; - int cpu =3D hard_smp_processor_id(); + int cpu =3D read_apic_id(); =20 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); =20 --- a/arch/x86/kernel/vsmp_64.c +++ b/arch/x86/kernel/vsmp_64.c @@ -129,7 +129,7 @@ static void __init vsmp_cap_cpus(void) =20 static int apicid_phys_pkg_id(int initial_apic_id, int index_msb) { - return hard_smp_processor_id() >> index_msb; + return read_apic_id() >> index_msb; } =20 static void vsmp_apic_post_init(void) From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6405FC001DC for ; Mon, 17 Jul 2023 23:15:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231320AbjGQXPD (ORCPT ); Mon, 17 Jul 2023 19:15:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231265AbjGQXOu (ORCPT ); Mon, 17 Jul 2023 19:14:50 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8F1213D for ; Mon, 17 Jul 2023 16:14:46 -0700 (PDT) Message-ID: <20230717223223.499996154@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635685; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=809REvyTd02dVym8hZUdnfHZr/NK3BOiIohksfQj1oM=; b=OSPy2UhFd09/ntzkIYSXS6s/mbRnTChHppEUB/1L2PXKotrU23qCWkP8rxGdbPNv02bis+ a3VCnrvCQZPqGUmclFr74+BQHp9hdtpLRFY7zP36qb4OjntldkSH8WFQ5b0ADcfT+ig4LF eodtB48BkmezgzqNwbtnP17fFMJR448pc8MEA0r6+T+7ly8pKiDaFwuF8n3F0cnIAz0Mc0 xyu+Ma0s7h2rS+J5rRTiPPbqBZw2H9d61TYrZwzO1nnnvxnr4WPVs8iiOItqVIaMHA79th f1kiVjK9qaWpdmb3IH0SVvyhkWHNKuJAaaL6FDyF6uUP9hTmct+e4Xg6WjONyQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635685; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=809REvyTd02dVym8hZUdnfHZr/NK3BOiIohksfQj1oM=; b=ADoR2blho6PKngC8a52eEUoeHgo7A+4lZEFer0P0ADyyZzbXHXrPAP/lkqekL+1+GQLbtY lfMOU4x36OYNRbDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 07/58] x86/apic: Remove unused max_physical_apicid References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:14:44 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/apic.c | 8 -------- 1 file changed, 8 deletions(-) --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -74,11 +74,6 @@ EXPORT_SYMBOL_GPL(boot_cpu_physical_apic u8 boot_cpu_apic_version __ro_after_init; =20 /* - * The highest APIC ID seen during enumeration. - */ -static unsigned int max_physical_apicid; - -/* * Bitmask of physically existing CPUs: */ physid_mask_t phys_cpu_present_map; @@ -2541,9 +2536,6 @@ int generic_processor_info(int apicid, i boot_cpu_apic_version, cpu, version); } =20 - if (apicid > max_physical_apicid) - max_physical_apicid =3D apicid; - #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) early_per_cpu(x86_cpu_to_apicid, cpu) =3D apicid; #endif From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12A4BEB64DC for ; Mon, 17 Jul 2023 23:15:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231401AbjGQXPK (ORCPT ); Mon, 17 Jul 2023 19:15:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231276AbjGQXO5 (ORCPT ); Mon, 17 Jul 2023 19:14:57 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 374771B1 for ; Mon, 17 Jul 2023 16:14:49 -0700 (PDT) Message-ID: <20230717223223.560174779@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635687; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=4e7J9tdOEFPNygIrLyHrVQ7kBA5TGJ7oCmaEMf40odE=; b=roXABOm6JzrHGMN1SS6GsUcPfnP+P2vXUTi9U1fWSZrNOmhixrvlLyT2mBh3kx9QbBlTPo jZW21CSS5Al1ujrgpEswN7MKRQ6r9SOcELaz+qZm/hwi1LEH/xYssoTfwB1CrxDVX4dTNB c8b5EmRTiWGD4coqUPh9ISRzXL7dkHuK/ZEgl5IBCAcHX3pVKpk8GD5bEnBChE9gPFBPkA mG8gtU0dBekBxTG46EuWl+eCok3KUTug1vPIhb8IJSpEvrWgpwMlvMTbIZEpqqVi6id3pD ywQHdVdM1pDnYC2H4ntvJP2LDTQE4Lu68zghWgvho3hKeYpRikVAXbQwHr8diA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635687; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=4e7J9tdOEFPNygIrLyHrVQ7kBA5TGJ7oCmaEMf40odE=; b=cYBl40JbWXYzWsB7zA7tcgBD1FPoNWdUP9nok6MbS6FbUbn/ABbMN3gqAvRZ+BHSohh+RR m9buVCYMnuchb5BQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 08/58] x86/apic: Nuke unused apic::inquire_remote_apic() References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:14:46 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Put it to the other historical leftovers. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 16 -------------- arch/x86/kernel/apic/apic_flat_64.c | 4 --- arch/x86/kernel/apic/apic_noop.c | 2 - arch/x86/kernel/apic/apic_numachip.c | 2 - arch/x86/kernel/apic/bigsmp_32.c | 2 - arch/x86/kernel/apic/probe_32.c | 2 - arch/x86/kernel/apic/x2apic_cluster.c | 2 - arch/x86/kernel/apic/x2apic_phys.c | 2 - arch/x86/kernel/apic/x2apic_uv_x.c | 1=20 arch/x86/kernel/smpboot.c | 38 -----------------------------= ----- arch/x86/xen/apic.c | 7 ------ 11 files changed, 78 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -66,20 +66,6 @@ enum apic_intr_mode_id { APIC_SYMMETRIC_IO_NO_ROUTING }; =20 -#ifdef CONFIG_SMP -extern void __inquire_remote_apic(int apicid); -#else /* CONFIG_SMP */ -static inline void __inquire_remote_apic(int apicid) -{ -} -#endif /* CONFIG_SMP */ - -static inline void default_inquire_remote_apic(int apicid) -{ - if (apic_verbosity >=3D APIC_DEBUG) - __inquire_remote_apic(apicid); -} - /* * With 82489DX we can't rely on apic feature bit * retrieved via cpuid but still have to deal with @@ -330,8 +316,6 @@ struct apic { /* wakeup secondary CPU using 64-bit wakeup point */ int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip); =20 - void (*inquire_remote_apic)(int apicid); - #ifdef CONFIG_X86_32 /* * Called very early during boot from get_smp_config(). It should --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -139,8 +139,6 @@ static struct apic apic_flat __ro_after_ .send_IPI_all =3D default_send_IPI_all, .send_IPI_self =3D default_send_IPI_self, =20 - .inquire_remote_apic =3D default_inquire_remote_apic, - .read =3D native_apic_mem_read, .write =3D native_apic_mem_write, .eoi_write =3D native_apic_mem_write, @@ -230,8 +228,6 @@ static struct apic apic_physflat __ro_af .send_IPI_all =3D default_send_IPI_all, .send_IPI_self =3D default_send_IPI_self, =20 - .inquire_remote_apic =3D default_inquire_remote_apic, - .read =3D native_apic_mem_read, .write =3D native_apic_mem_write, .eoi_write =3D native_apic_mem_write, --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -125,8 +125,6 @@ struct apic apic_noop __ro_after_init =3D =20 .wakeup_secondary_cpu =3D noop_wakeup_secondary_cpu, =20 - .inquire_remote_apic =3D NULL, - .read =3D noop_apic_read, .write =3D noop_apic_write, .eoi_write =3D noop_apic_write, --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -273,7 +273,6 @@ static const struct apic apic_numachip1 .send_IPI_self =3D numachip_send_IPI_self, =20 .wakeup_secondary_cpu =3D numachip_wakeup_secondary, - .inquire_remote_apic =3D NULL, /* REMRD not supported */ =20 .read =3D native_apic_mem_read, .write =3D native_apic_mem_write, @@ -320,7 +319,6 @@ static const struct apic apic_numachip2 .send_IPI_self =3D numachip_send_IPI_self, =20 .wakeup_secondary_cpu =3D numachip_wakeup_secondary, - .inquire_remote_apic =3D NULL, /* REMRD not supported */ =20 .read =3D native_apic_mem_read, .write =3D native_apic_mem_write, --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -153,8 +153,6 @@ static struct apic apic_bigsmp __ro_afte .send_IPI_all =3D bigsmp_send_IPI_all, .send_IPI_self =3D default_send_IPI_self, =20 - .inquire_remote_apic =3D default_inquire_remote_apic, - .read =3D native_apic_mem_read, .write =3D native_apic_mem_write, .eoi_write =3D native_apic_mem_write, --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -95,8 +95,6 @@ static struct apic apic_default __ro_aft .send_IPI_all =3D default_send_IPI_all, .send_IPI_self =3D default_send_IPI_self, =20 - .inquire_remote_apic =3D default_inquire_remote_apic, - .read =3D native_apic_mem_read, .write =3D native_apic_mem_write, .eoi_write =3D native_apic_mem_write, --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -265,8 +265,6 @@ static struct apic apic_x2apic_cluster _ .send_IPI_all =3D x2apic_send_IPI_all, .send_IPI_self =3D x2apic_send_IPI_self, =20 - .inquire_remote_apic =3D NULL, - .read =3D native_apic_msr_read, .write =3D native_apic_msr_write, .eoi_write =3D native_apic_msr_eoi_write, --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -189,8 +189,6 @@ static struct apic apic_x2apic_phys __ro .send_IPI_all =3D x2apic_send_IPI_all, .send_IPI_self =3D x2apic_send_IPI_self, =20 - .inquire_remote_apic =3D NULL, - .read =3D native_apic_msr_read, .write =3D native_apic_msr_write, .eoi_write =3D native_apic_msr_eoi_write, --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -862,7 +862,6 @@ static struct apic apic_x2apic_uv_x __ro .send_IPI_self =3D uv_send_IPI_self, =20 .wakeup_secondary_cpu =3D uv_wakeup_secondary, - .inquire_remote_apic =3D NULL, =20 .read =3D native_apic_msr_read, .write =3D native_apic_msr_write, --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -774,44 +774,6 @@ static void impress_friends(void) pr_debug("Before bogocount - setting activated=3D1\n"); } =20 -void __inquire_remote_apic(int apicid) -{ - unsigned i, regs[] =3D { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; - const char * const names[] =3D { "ID", "VERSION", "SPIV" }; - int timeout; - u32 status; - - pr_info("Inquiring remote APIC 0x%x...\n", apicid); - - for (i =3D 0; i < ARRAY_SIZE(regs); i++) { - pr_info("... APIC 0x%x %s: ", apicid, names[i]); - - /* - * Wait for idle. - */ - status =3D safe_apic_wait_icr_idle(); - if (status) - pr_cont("a previous APIC delivery may have failed\n"); - - apic_icr_write(APIC_DM_REMRD | regs[i], apicid); - - timeout =3D 0; - do { - udelay(100); - status =3D apic_read(APIC_ICR) & APIC_ICR_RR_MASK; - } while (status =3D=3D APIC_ICR_RR_INPROG && timeout++ < 1000); - - switch (status) { - case APIC_ICR_RR_VALID: - status =3D apic_read(APIC_RRR); - pr_cont("%08x\n", status); - break; - default: - pr_cont("failed\n"); - } - } -} - /* * The Multiprocessor Specification 1.4 (1997) example code suggests * that there should be a 10ms delay between the BSP asserting INIT --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -129,10 +129,6 @@ static void xen_noop(void) { } =20 -static void xen_silent_inquire(int apicid) -{ -} - static int xen_cpu_present_to_apicid(int cpu) { if (cpu_present(cpu)) @@ -173,9 +169,6 @@ static struct apic xen_pv_apic =3D { .send_IPI_all =3D xen_send_IPI_all, .send_IPI_self =3D xen_send_IPI_self, #endif - /* .wait_for_init_deassert- used by AP bootup - smp_callin which we don'= t use */ - .inquire_remote_apic =3D xen_silent_inquire, - .read =3D xen_apic_read, .write =3D xen_apic_write, .eoi_write =3D xen_apic_write, From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0810AC0015E for ; Mon, 17 Jul 2023 23:15:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229736AbjGQXPN (ORCPT ); Mon, 17 Jul 2023 19:15:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35138 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231345AbjGQXO6 (ORCPT ); Mon, 17 Jul 2023 19:14:58 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DF88EE for ; Mon, 17 Jul 2023 16:14:50 -0700 (PDT) Message-ID: <20230717223223.619742209@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635688; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=H5i4GGKgRO3TiiYH+SmmQBdthZUJ+Bs0TnVK3jLC+DU=; b=0eEZsi8l3pELHg1uw7TgE6WQyXiehyoMohC4RaoBFxKY6CU6j4nuf87eB8xfx55yfJKbkJ cxJHtVLCqxqEQmGdhHUnZTO1Uk68d5btdmFF8GiQDvfoIv/1IxTOd7kllbMBHPc073HUyD N1CPQIDbYwq0EspllFFI25M0uWPUVggoolU6+6kk/xbqHW8sZFgjr4u4mWoQZKlNyTcv4Z vl2nkNes58MpKh2Y6iwXpscx5unsbgXgnZXuOb/jnRDf6JuHH4cqO6ZSNIvh3I9N1asaMu NRPkhwozIg6tCqrhIEikbzoaaCpOju0Ulu6J6LmY4K9yuZC1eb/xo0rsi5VXLQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635688; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=H5i4GGKgRO3TiiYH+SmmQBdthZUJ+Bs0TnVK3jLC+DU=; b=uQDan8++eDr5/q31MdW+XBJjSY5q8cCK5Jhe7aKeuc1TcVbN84ScwI+nxx+mRq5y6eu+r0 yY5mhplJ7RbBclBQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 09/58] x86/apic: Get rid of boot_cpu_physical_apicid madness References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:14:48 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" boot_cpu_physical_apicid is written in random places and in the last consequence filled with the APIC ID read from the local APIC. That causes it to have inconsistent state when the MPTABLE is broken. As a consequence tons of moronic checks are sprinkled all over the place. Consolidate the code and read it exactly once when either X2APIC mode is detected early or when the APIC mapping is established. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 2=20 arch/x86/kernel/apic/apic.c | 102 +++++++++++++--------------------------= ----- arch/x86/kernel/mpparse.c | 4 - 3 files changed, 34 insertions(+), 74 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -247,7 +247,7 @@ static inline int x2apic_enabled(void) #else /* !CONFIG_X86_X2APIC */ static inline void x2apic_setup(void) { } static inline int x2apic_enabled(void) { return 0; } - +static inline u32 native_apic_msr_read(u32 reg) { BUG(); } #define x2apic_mode (0) #define x2apic_supported() (0) #endif /* !CONFIG_X86_X2APIC */ --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1318,8 +1318,7 @@ static int __init __apic_intr_mode_selec if (!boot_cpu_has(X86_FEATURE_APIC) && APIC_INTEGRATED(boot_cpu_apic_version)) { apic_is_disabled =3D true; - pr_err(FW_BUG "Local APIC %d not detected, force emulation\n", - boot_cpu_physical_apicid); + pr_err(FW_BUG "Local APIC not detected, force emulation\n"); return APIC_PIC; } #endif @@ -1340,12 +1339,6 @@ static int __init __apic_intr_mode_selec pr_info("APIC: SMP mode deactivated\n"); return APIC_SYMMETRIC_IO_NO_ROUTING; } - - if (read_apic_id() !=3D boot_cpu_physical_apicid) { - panic("Boot APIC ID in local APIC unexpected (%d vs %d)", - read_apic_id(), boot_cpu_physical_apicid); - /* Or can we switch back to PIC here? */ - } #endif =20 return APIC_SYMMETRIC_IO; @@ -1741,6 +1734,23 @@ void apic_ap_setup(void) end_local_APIC_setup(); } =20 +static __init void apic_read_boot_cpu_id(bool x2apic) +{ + /* + * This can be invoked from check_x2apic() before the APIC has been + * selected. But that code knows for sure that the BIOS enabled + * X2APIC. + */ + if (x2apic) { + boot_cpu_physical_apicid =3D native_apic_msr_read(APIC_ID); + boot_cpu_apic_version =3D GET_APIC_VERSION(native_apic_msr_read(APIC_LVR= )); + } else { + boot_cpu_physical_apicid =3D read_apic_id(); + boot_cpu_apic_version =3D GET_APIC_VERSION(apic_read(APIC_LVR)); + } +} + + #ifdef CONFIG_X86_X2APIC int x2apic_mode; EXPORT_SYMBOL_GPL(x2apic_mode); @@ -1921,6 +1931,7 @@ void __init check_x2apic(void) x2apic_state =3D X2APIC_ON_LOCKED; else x2apic_state =3D X2APIC_ON; + apic_read_boot_cpu_id(true); } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { x2apic_state =3D X2APIC_DISABLED; } @@ -2109,15 +2120,11 @@ static int __init detect_init_APIC(void) */ void __init init_apic_mappings(void) { - unsigned int new_apicid; - if (apic_validate_deadline_timer()) pr_info("TSC deadline timer available\n"); =20 - if (x2apic_mode) { - boot_cpu_physical_apicid =3D read_apic_id(); + if (x2apic_mode) return; - } =20 /* If no local APIC can be found return early */ if (!smp_found_config && detect_init_APIC()) { @@ -2134,39 +2141,19 @@ void __init init_apic_mappings(void) if (!acpi_lapic && !smp_found_config) register_lapic_address(apic_phys); } - - /* - * Fetch the APIC ID of the BSP in case we have a - * default configuration (or the MP table is broken). - */ - new_apicid =3D read_apic_id(); - if (boot_cpu_physical_apicid !=3D new_apicid) { - boot_cpu_physical_apicid =3D new_apicid; - /* - * yeah -- we lie about apic_version - * in case if apic was disabled via boot option - * but it's not a problem for SMP compiled kernel - * since apic_intr_mode_select is prepared for such - * a case and disable smp mode - */ - boot_cpu_apic_version =3D GET_APIC_VERSION(apic_read(APIC_LVR)); - } } =20 void __init register_lapic_address(unsigned long address) { mp_lapic_addr =3D address; =20 - if (!x2apic_mode) { - set_fixmap_nocache(FIX_APIC_BASE, address); - apic_mmio_base =3D APIC_BASE; - apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", - APIC_BASE, address); - } - if (boot_cpu_physical_apicid =3D=3D -1U) { - boot_cpu_physical_apicid =3D read_apic_id(); - boot_cpu_apic_version =3D GET_APIC_VERSION(apic_read(APIC_LVR)); - } + if (x2apic_mode) + return; + + set_fixmap_nocache(FIX_APIC_BASE, address); + apic_mmio_base =3D APIC_BASE; + apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", APIC_BASE, ad= dress); + apic_read_boot_cpu_id(false); } =20 /* @@ -2446,31 +2433,15 @@ int generic_processor_info(int apicid, i phys_cpu_present_map); =20 /* - * boot_cpu_physical_apicid is designed to have the apicid - * returned by read_apic_id(), i.e, the apicid of the - * currently booting-up processor. However, on some platforms, - * it is temporarily modified by the apicid reported as BSP - * through MP table. Concretely: - * - * - arch/x86/kernel/mpparse.c: MP_processor_info() - * - arch/x86/mm/amdtopology.c: amd_numa_init() - * - * This function is executed with the modified - * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel - * parameter doesn't work to disable APs on kdump 2nd kernel. - * - * Since fixing handling of boot_cpu_physical_apicid requires - * another discussion and tests on each platform, we leave it - * for now and here we use read_apic_id() directly in this - * function, generic_processor_info(). + * boot_cpu_physical_apicid is guaranteed to contain the boot CPU + * APIC ID read from the local APIC when this function is invoked. */ - if (disabled_cpu_apicid !=3D BAD_APICID && - disabled_cpu_apicid !=3D read_apic_id() && + if (disabled_cpu_apicid !=3D boot_cpu_physical_apicid && disabled_cpu_apicid =3D=3D apicid) { int thiscpu =3D num_processors + disabled_cpus; =20 - pr_warn("APIC: Disabling requested cpu." - " Processor %d/0x%x ignored.\n", thiscpu, apicid); + pr_warn("APIC: Disabling requested cpu. Processor %d/0x%x ignored.\n", + thiscpu, apicid); =20 disabled_cpus++; return -ENODEV; @@ -2626,15 +2597,6 @@ static void __init apic_bsp_up_setup(voi { #ifdef CONFIG_X86_64 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); -#else - /* - * Hack: In case of kdump, after a crash, kernel might be booting - * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid - * might be zero if read from MP tables. Get it from LAPIC. - */ -# ifdef CONFIG_CRASH_DUMP - boot_cpu_physical_apicid =3D read_apic_id(); -# endif #endif physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map= ); } --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -58,10 +58,8 @@ static void __init MP_processor_info(str =20 apicid =3D m->apicid; =20 - if (m->cpuflag & CPU_BOOTPROCESSOR) { + if (m->cpuflag & CPU_BOOTPROCESSOR) bootup_cpu =3D " (Bootup-CPU)"; - boot_cpu_physical_apicid =3D m->apicid; - } =20 pr_info("Processor #%d%s\n", m->apicid, bootup_cpu); generic_processor_info(apicid, m->apicver); From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 382C9EB64DC for ; Mon, 17 Jul 2023 23:15:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231365AbjGQXPR (ORCPT ); Mon, 17 Jul 2023 19:15:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231316AbjGQXPC (ORCPT ); Mon, 17 Jul 2023 19:15:02 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20004E51 for ; Mon, 17 Jul 2023 16:14:51 -0700 (PDT) Message-ID: <20230717223223.679207826@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635690; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=+hrw46hsMBswWQNzqDZfoOo5VDQtds9fIHiVlhGFvxE=; b=1iTxgDBd2IbtrJHBH42NS0qXgndUHXqc+7hJZhMPlsQ1A5nnuWul3sMzl1eRLXfeL79pal 6M8fKqhPBbLvUGtpV6azGOGtAzJJrbxi3/x2wDCA7V1+RmHC84NRiWYKNXIHmwWZhW5ny3 YCN5lpG9uZAC0AveAZ1JK0yfseY4HNZFMCGOTUlTg8Ggn/anco5DaSbMbIqMMll3AVbWBe mzIBF21GQmLd55tm7d3RRgZZ4sXmkgKz44j9OpUBGcjdxBBuoKp7X/Sh6zmwAHZuCnIF/t sC3HmdEAFAdUrBq7X9t+1n9PNKlpW5p2orCq35A8ulMSINTDxYzaI6vGi1rfeg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635690; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=+hrw46hsMBswWQNzqDZfoOo5VDQtds9fIHiVlhGFvxE=; b=iAwgexARZuIjyMMP7UxCAZX4JGqXaF5PrTmuzRWnXmv0RdbAK+3jOqKoz3aUpSMx1/Ml/O n+7JxTHMmJ8CMNCw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 10/58] x86/apic: Register boot CPU APIC early References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:14:49 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Register the boot CPU APIC right when the boot CPUs APIC is read from the hardware. No point is doing this on random places and having wild heuristics to save the boot CPU APIC ID slot and CPU number 0 reserved. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/apic.c | 120 ++++++++++++++++++---------------------= ----- 1 file changed, 50 insertions(+), 70 deletions(-) --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1734,6 +1734,8 @@ void apic_ap_setup(void) end_local_APIC_setup(); } =20 +static __init void cpu_set_boot_apic(void); + static __init void apic_read_boot_cpu_id(bool x2apic) { /* @@ -1748,9 +1750,9 @@ static __init void apic_read_boot_cpu_id boot_cpu_physical_apicid =3D read_apic_id(); boot_cpu_apic_version =3D GET_APIC_VERSION(apic_read(APIC_LVR)); } + cpu_set_boot_apic(); } =20 - #ifdef CONFIG_X86_X2APIC int x2apic_mode; EXPORT_SYMBOL_GPL(x2apic_mode); @@ -2426,76 +2428,8 @@ static int allocate_logical_cpuid(int ap return nr_logical_cpuids++; } =20 -int generic_processor_info(int apicid, int version) +static void cpu_update_apic(int cpu, int apicid, int version) { - int cpu, max =3D nr_cpu_ids; - bool boot_cpu_detected =3D physid_isset(boot_cpu_physical_apicid, - phys_cpu_present_map); - - /* - * boot_cpu_physical_apicid is guaranteed to contain the boot CPU - * APIC ID read from the local APIC when this function is invoked. - */ - if (disabled_cpu_apicid !=3D boot_cpu_physical_apicid && - disabled_cpu_apicid =3D=3D apicid) { - int thiscpu =3D num_processors + disabled_cpus; - - pr_warn("APIC: Disabling requested cpu. Processor %d/0x%x ignored.\n", - thiscpu, apicid); - - disabled_cpus++; - return -ENODEV; - } - - /* - * If boot cpu has not been detected yet, then only allow upto - * nr_cpu_ids - 1 processors and keep one slot free for boot cpu - */ - if (!boot_cpu_detected && num_processors >=3D nr_cpu_ids - 1 && - apicid !=3D boot_cpu_physical_apicid) { - int thiscpu =3D max + disabled_cpus - 1; - - pr_warn("APIC: NR_CPUS/possible_cpus limit of %i almost" - " reached. Keeping one slot for boot cpu." - " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); - - disabled_cpus++; - return -ENODEV; - } - - if (num_processors >=3D nr_cpu_ids) { - int thiscpu =3D max + disabled_cpus; - - pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. " - "Processor %d/0x%x ignored.\n", max, thiscpu, apicid); - - disabled_cpus++; - return -EINVAL; - } - - if (apicid =3D=3D boot_cpu_physical_apicid) { - /* - * x86_cpu_to_apicid is required to have processors listed - * in same order as logical cpu numbers. Hence the first - * entry is BSP, and so on. - * boot_cpu_init() already hold bit 0 in cpu_present_mask - * for BSP. - */ - cpu =3D 0; - - /* Logical cpuid 0 is reserved for BSP. */ - cpuid_to_apicid[0] =3D apicid; - } else { - cpu =3D allocate_logical_cpuid(apicid); - if (cpu < 0) { - disabled_cpus++; - return -EINVAL; - } - } - - /* - * Validate version - */ if (version =3D=3D 0x0) { pr_warn("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\= n", cpu, apicid); @@ -2521,10 +2455,56 @@ int generic_processor_info(int apicid, i =20 if (system_state !=3D SYSTEM_BOOTING) cpu_mark_primary_thread(cpu, apicid); +} + +static __init void cpu_set_boot_apic(void) +{ + cpuid_to_apicid[0] =3D boot_cpu_physical_apicid; + cpu_update_apic(0, boot_cpu_physical_apicid, boot_cpu_apic_version); +} + +int generic_processor_info(int apicid, int version) +{ + int cpu, max =3D nr_cpu_ids; + + /* The boot CPU must be set before MADT/MPTABLE parsing happens */ + if (cpuid_to_apicid[0] =3D=3D BAD_APICID) + panic("Boot CPU APIC not registered yet\n"); + + if (apicid =3D=3D boot_cpu_physical_apicid) + return 0; + + if (disabled_cpu_apicid =3D=3D apicid) { + int thiscpu =3D num_processors + disabled_cpus; + + pr_warn("APIC: Disabling requested cpu. Processor %d/0x%x ignored.\n", + thiscpu, apicid); =20 + disabled_cpus++; + return -ENODEV; + } + + if (num_processors >=3D nr_cpu_ids) { + int thiscpu =3D max + disabled_cpus; + + pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. " + "Processor %d/0x%x ignored.\n", max, thiscpu, apicid); + + disabled_cpus++; + return -EINVAL; + } + + cpu =3D allocate_logical_cpuid(apicid); + if (cpu < 0) { + disabled_cpus++; + return -EINVAL; + } + + cpu_update_apic(cpu, apicid, version); return cpu; } =20 + void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, bool dmar) { From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EFF2EB64DC for ; Mon, 17 Jul 2023 23:15:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230201AbjGQXPY (ORCPT ); Mon, 17 Jul 2023 19:15:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35008 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231342AbjGQXPI (ORCPT ); Mon, 17 Jul 2023 19:15:08 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 855AA1705 for ; Mon, 17 Jul 2023 16:14:54 -0700 (PDT) Message-ID: <20230717223223.737031480@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635691; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=OZddm0qMa+fCQ/gmjuY/HZsd/K8NL9drgmrzgYZMbN0=; b=DTHVIP8iXYhNrFjvw9p/C2zr4c7ot1d9tCd6POZvTETzn0MTNiS5u7DZwMdZoIoYAOmw1O 9NMHAnqpb4W/lZlutMAxq/SbEPbQU2I+TqWaAExtQngcEsNZuw1XYcswpck1epK5BwrM7P oias9id99krUtB0tUxmV6y+NjT6C/ejpLsTz2cPmwQTww96bilAv/rghpHIV5fhjWB4IhX gVOPKswnR5rOn0qMfkGw9O+i4JPLPgOHwCesez9uaBQ47nb/iljsviKJmpWEQc0Bpx/wN/ RwEqmRk1fU4c52/0sd/puvM7J1x6Gz2nxgWIKfJc6c+iYgC33WLaT0PHZk89qg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635691; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=OZddm0qMa+fCQ/gmjuY/HZsd/K8NL9drgmrzgYZMbN0=; b=uOTNnL5z3cSHcYx8OH+2g7Ajf3JECnWtkbAWERtDmsPHq3HawaQth2gZnAjWUJHugdxbTC dfPJ4MR2zHOIyvBQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 11/58] x86/apic: Remove the pointless APIC version check References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:14:51 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This historical leftover is really uninteresting today. Whatever MPTABLE or MADT delivers we only trust the hardware anyway. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/mpspec.h | 2 +- arch/x86/kernel/acpi/boot.c | 6 +----- arch/x86/kernel/apic/apic.c | 19 ++++--------------- arch/x86/kernel/devicetree.c | 5 ++--- arch/x86/kernel/jailhouse.c | 6 ++---- arch/x86/kernel/mpparse.c | 2 +- arch/x86/kernel/smpboot.c | 4 ++-- 7 files changed, 13 insertions(+), 31 deletions(-) --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -76,7 +76,7 @@ static inline void e820__memblock_alloc_ #define default_get_smp_config x86_init_uint_noop #endif =20 -int generic_processor_info(int apicid, int version); +int generic_processor_info(int apicid); =20 #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_LOCAL_APIC) =20 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -169,7 +169,6 @@ static int __init acpi_parse_madt(struct */ static int acpi_register_lapic(int id, u32 acpiid, u8 enabled) { - unsigned int ver =3D 0; int cpu; =20 if (id >=3D MAX_LOCAL_APIC) { @@ -182,10 +181,7 @@ static int acpi_register_lapic(int id, u return -EINVAL; } =20 - if (boot_cpu_physical_apicid !=3D -1U) - ver =3D boot_cpu_apic_version; - - cpu =3D generic_processor_info(id, ver); + cpu =3D generic_processor_info(id); if (cpu >=3D 0) early_per_cpu(x86_cpu_to_acpiid, cpu) =3D acpiid; =20 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2428,19 +2428,8 @@ static int allocate_logical_cpuid(int ap return nr_logical_cpuids++; } =20 -static void cpu_update_apic(int cpu, int apicid, int version) +static void cpu_update_apic(int cpu, int apicid) { - if (version =3D=3D 0x0) { - pr_warn("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\= n", - cpu, apicid); - version =3D 0x10; - } - - if (version !=3D boot_cpu_apic_version) { - pr_warn("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version = %x\n", - boot_cpu_apic_version, cpu, version); - } - #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) early_per_cpu(x86_cpu_to_apicid, cpu) =3D apicid; #endif @@ -2460,10 +2449,10 @@ static void cpu_update_apic(int cpu, int static __init void cpu_set_boot_apic(void) { cpuid_to_apicid[0] =3D boot_cpu_physical_apicid; - cpu_update_apic(0, boot_cpu_physical_apicid, boot_cpu_apic_version); + cpu_update_apic(0, boot_cpu_physical_apicid); } =20 -int generic_processor_info(int apicid, int version) +int generic_processor_info(int apicid) { int cpu, max =3D nr_cpu_ids; =20 @@ -2500,7 +2489,7 @@ int generic_processor_info(int apicid, i return -EINVAL; } =20 - cpu_update_apic(cpu, apicid, version); + cpu_update_apic(cpu, apicid); return cpu; } =20 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -128,16 +128,15 @@ static void __init dtb_setup_hpet(void) static void __init dtb_cpu_setup(void) { struct device_node *dn; - u32 apic_id, version; + u32 apic_id; =20 - version =3D GET_APIC_VERSION(apic_read(APIC_LVR)); for_each_of_cpu_node(dn) { apic_id =3D of_get_cpu_hwid(dn, 0); if (apic_id =3D=3D ~0U) { pr_warn("%pOF: missing local APIC ID\n", dn); continue; } - generic_processor_info(apic_id, version); + generic_processor_info(apic_id); } } =20 --- a/arch/x86/kernel/jailhouse.c +++ b/arch/x86/kernel/jailhouse.c @@ -101,10 +101,8 @@ static void __init jailhouse_get_smp_con =20 register_lapic_address(0xfee00000); =20 - for (cpu =3D 0; cpu < setup_data.v1.num_cpus; cpu++) { - generic_processor_info(setup_data.v1.cpu_ids[cpu], - boot_cpu_apic_version); - } + for (cpu =3D 0; cpu < setup_data.v1.num_cpus; cpu++) + generic_processor_info(setup_data.v1.cpu_ids[cpu]); =20 smp_found_config =3D 1; =20 --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -62,7 +62,7 @@ static void __init MP_processor_info(str bootup_cpu =3D " (Bootup-CPU)"; =20 pr_info("Processor #%d%s\n", m->apicid, bootup_cpu); - generic_processor_info(apicid, m->apicver); + generic_processor_info(apicid); } =20 #ifdef CONFIG_X86_IO_APIC --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1389,7 +1389,7 @@ early_param("possible_cpus", _setup_poss { int i, possible; =20 - /* No boot processor was found in mptable or ACPI MADT */ + /* No processor was found in mptable or ACPI MADT */ if (!num_processors) { if (boot_cpu_has(X86_FEATURE_APIC)) { int apicid =3D boot_cpu_physical_apicid; @@ -1400,7 +1400,7 @@ early_param("possible_cpus", _setup_poss /* Make sure boot cpu is enumerated */ if (apic->cpu_present_to_apicid(0) =3D=3D BAD_APICID && apic->apic_id_valid(apicid)) - generic_processor_info(apicid, boot_cpu_apic_version); + generic_processor_info(apicid); } =20 if (!num_processors) From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1C72C0015E for ; Mon, 17 Jul 2023 23:15:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231370AbjGQXP0 (ORCPT ); Mon, 17 Jul 2023 19:15:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231311AbjGQXPM (ORCPT ); Mon, 17 Jul 2023 19:15:12 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D24A170F for ; Mon, 17 Jul 2023 16:14:55 -0700 (PDT) Message-ID: <20230717223223.795705685@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635693; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=oO9hcqnpNwvqYXrZ+6Z6cARd5ofqbuQWYypUIdXUUcI=; b=p7b6/Bis4eXvJ7P7OK19N8ZEt+C+dp7pjK1yD7IFcMFEtxgTJl/IOBgPbh/NH6/bVPfEtC Czqqoyll9VnvOxtEJyIjAvCu4MvMRESmDb0VPpLkAh0kOdiMOzcyseAr5qz64QkYxsuW6E Df1ytueO2TeawBnB7AQ4SjbREIiyOtCkPaJORc7Lzi6T3dcXVJTtZV0oDnovkz1SOoNb4S iFSvOFBCbL0BCHi2YBAeI7UCunfSMds2s06ogGyPWe3Dgiyf5hm35WtNp4HeqwIDD5sUtk 5qg7YT2NCTcZSIeekDKkhG0NriDLzT0xxBrLR0FbUF22dUH4d4y2B/Gg5pcy5w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635693; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=oO9hcqnpNwvqYXrZ+6Z6cARd5ofqbuQWYypUIdXUUcI=; b=wZpkUn2cRMrRvmnxKnBieim+IVSwk2CPB0K19234yqR5v4qeFA6mJIP/kDNHpMJXAyyovl 53nr1vAHeDKHfzAw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 12/58] x86/of: Fix the APIC address registration References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:14:52 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The device tree APIC parser tries to force enable the local APIC when it is not set in CPUID. apic_force_enable() registers the boot CPU apic on success. If that succeeds then dtb_lapic_setup() registers the local APIC again eventually with a different address. Rewrite the code so that it only registers it once. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/devicetree.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -157,19 +157,15 @@ static void __init dtb_lapic_setup(void) =20 /* Did the boot loader setup the local APIC ? */ if (!boot_cpu_has(X86_FEATURE_APIC)) { + /* Try force enabling, which registers the APIC address */ if (apic_force_enable(lapic_addr)) return; - } - smp_found_config =3D 1; - if (of_property_read_bool(dn, "intel,virtual-wire-mode")) { - pr_info("Virtual Wire compatibility mode.\n"); - pic_mode =3D 0; } else { - pr_info("IMCR and PIC compatibility mode.\n"); - pic_mode =3D 1; + register_lapic_address(lapic_addr); } - - register_lapic_address(lapic_addr); + smp_found_config =3D 1; + pic_mode =3D !of_property_read_bool(dn, "intel,virtual-wire-mode"); + pr_info("%s compatibility mode.\n", pic_mode ? "IMCR and PIC" : "Virtual = Wire"); } =20 #endif /* CONFIG_X86_LOCAL_APIC */ From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F32A7EB64DC for ; Mon, 17 Jul 2023 23:15:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231408AbjGQXP2 (ORCPT ); Mon, 17 Jul 2023 19:15:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231315AbjGQXPQ (ORCPT ); Mon, 17 Jul 2023 19:15:16 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE08B1726 for ; Mon, 17 Jul 2023 16:14:56 -0700 (PDT) Message-ID: <20230717223223.853631722@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635694; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=pZQ9lH7uKukYhk1nKowW452zbwwO1eTDkvObOGS1SuA=; b=bBgGdLV6z4Gucf5BLCilurt+G4NPVjt7yUAMe2NpLbuO4kYTMDXwYp69w8fNDwrIFZr06F c4whOHyL0bv8WGB6q2q/uZZlgrnaqJpQ9aNE2wknLupIPzrMDRUzxJFXB3yOaZTRN7ZZLJ W+1OhHbiVl12bb+JlTy+jZ8KgF5x1FzeKWauWZtc2Lw61kosGiptRF4EmxpZvTlJoNS9pB QavdBqbURkoHl+306co554Co5kPodOX/hxwSjrNNTgD6CiM971XVekYXmEg00+86C+YUuD EhT7nlvziwwzcr40h3abV/ouf8SydJ7VHo1pdIdwiqIBZCFFy7anVD8+Gx2fQw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635694; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=pZQ9lH7uKukYhk1nKowW452zbwwO1eTDkvObOGS1SuA=; b=Md1YPbX2At1yWdGCd3T6EY7E8h4c5v+OzzmVQtmvSUspYaw0xYaLUdCVLjW8oA+aumR6n4 0I1fBIQXE9KNmuCA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 13/58] x86/apic: Make some APIC init functions bool References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:14:54 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Quite some APIC init functions are pure boolean, but use the success =3D 0, fail < 0 model. That's confusing as hell when reading through the code. Convert them to boolean. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 6 +++--- arch/x86/kernel/apic/apic.c | 36 ++++++++++++++++++------------------ arch/x86/kernel/devicetree.c | 2 +- 3 files changed, 22 insertions(+), 22 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -135,12 +135,12 @@ extern void setup_secondary_APIC_clock(v extern void lapic_update_tsc_freq(void); =20 #ifdef CONFIG_X86_64 -static inline int apic_force_enable(unsigned long addr) +static inline bool apic_force_enable(unsigned long addr) { - return -1; + return false; } #else -extern int apic_force_enable(unsigned long addr); +extern bool apic_force_enable(unsigned long addr); #endif =20 extern void apic_ap_setup(void); --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2000,19 +2000,19 @@ void __init enable_IR_x2apic(void) * On AMD64 we trust the BIOS - if it says no APIC it is likely * not correctly set up (usually the APIC timer won't work etc.) */ -static int __init detect_init_APIC(void) +static bool __init detect_init_APIC(void) { if (!boot_cpu_has(X86_FEATURE_APIC)) { pr_info("No local APIC present\n"); - return -1; + return false; } =20 mp_lapic_addr =3D APIC_DEFAULT_PHYS_BASE; - return 0; + return true; } #else =20 -static int __init apic_verify(void) +static bool __init apic_verify(void) { u32 features, h, l; =20 @@ -2023,7 +2023,7 @@ static int __init apic_verify(void) features =3D cpuid_edx(1); if (!(features & (1 << X86_FEATURE_APIC))) { pr_warn("Could not enable APIC!\n"); - return -1; + return false; } set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); mp_lapic_addr =3D APIC_DEFAULT_PHYS_BASE; @@ -2036,15 +2036,15 @@ static int __init apic_verify(void) } =20 pr_info("Found and enabled local APIC!\n"); - return 0; + return true; } =20 -int __init apic_force_enable(unsigned long addr) +bool __init apic_force_enable(unsigned long addr) { u32 h, l; =20 if (apic_is_disabled) - return -1; + return false; =20 /* * Some BIOSes disable the local APIC in the APIC_BASE @@ -2067,11 +2067,11 @@ int __init apic_force_enable(unsigned lo /* * Detect and initialize APIC */ -static int __init detect_init_APIC(void) +static bool __init detect_init_APIC(void) { /* Disabled by kernel option? */ if (apic_is_disabled) - return -1; + return false; =20 switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: @@ -2098,22 +2098,22 @@ static int __init detect_init_APIC(void) if (!force_enable_local_apic) { pr_info("Local APIC disabled by BIOS -- " "you can enable it with \"lapic\"\n"); - return -1; + return false; } - if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) - return -1; + if (!apic_force_enable(APIC_DEFAULT_PHYS_BASE)) + return false; } else { - if (apic_verify()) - return -1; + if (!apic_verify()) + return false; } =20 apic_pm_activate(); =20 - return 0; + return true; =20 no_apic: pr_info("No local APIC present or hardware disabled\n"); - return -1; + return false; } #endif =20 @@ -2129,7 +2129,7 @@ void __init init_apic_mappings(void) return; =20 /* If no local APIC can be found return early */ - if (!smp_found_config && detect_init_APIC()) { + if (!smp_found_config && !detect_init_APIC()) { /* lets NOP'ify apic operations */ pr_info("APIC: disable apic facility\n"); apic_disable(); --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -158,7 +158,7 @@ static void __init dtb_lapic_setup(void) /* Did the boot loader setup the local APIC ? */ if (!boot_cpu_has(X86_FEATURE_APIC)) { /* Try force enabling, which registers the APIC address */ - if (apic_force_enable(lapic_addr)) + if (!apic_force_enable(lapic_addr)) return; } else { register_lapic_address(lapic_addr); From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45DD7EB64DC for ; Mon, 17 Jul 2023 23:15:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230469AbjGQXPl (ORCPT ); Mon, 17 Jul 2023 19:15:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231316AbjGQXP1 (ORCPT ); Mon, 17 Jul 2023 19:15:27 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6585B173B for ; Mon, 17 Jul 2023 16:14:58 -0700 (PDT) Message-ID: <20230717223223.913161388@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635696; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=6lsXOSCdebUCwT7n6zhHvn8DJi5YZlZjkDwKMSiOzL0=; b=MXEXcw0tO5uqiDRsXTnO1WBHMsD/0ClTumSqTLX7DyN70nfu5/fdzzOhrzzHZveO4r1D6b 6oFfLSbK9kF08uQuLICNty1yodyumD3rKz9EfI1n6JlwYTnhRbYjPmjljqGX88Fpw6La/A IfOhKQHwTm4IMWL9cXEE2SV8Oud65buCZfMODG/e15uAOUkuas3ZVUryW2B8WNTWnC2Stl l21SnNLcNOUFeL3EoBv9UMs5smQlqxLC6U0Vt8nUWuPCE7I6TslCptB5rm3FY2B8Lu5SSw IJdpheAGkEm4JBZDXY9EzzzUCRWQSdGzg476eSlIl9BHbbmZCowo7t8utmrO+A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635696; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=6lsXOSCdebUCwT7n6zhHvn8DJi5YZlZjkDwKMSiOzL0=; b=7Y5AMRjCRyDwmGRaUhRVIFOHgb79/2tewqVXhnRTQVeAcdD8zj38cRXDrd1JXiGD518QaE KdXPf7Sd90IYV3CQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 14/58] x86/apic: Split register_apic_address() References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:14:55 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Split the fixmap setup out of register_lapic_address() and reuse it when the X2APIC is disabled during setup. This avoids that the APIC ID is registered twice. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/apic.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1852,6 +1852,8 @@ void x2apic_setup(void) __x2apic_enable(); } =20 +static __init void apic_set_fixmap(void); + static __init void x2apic_disable(void) { u32 x2apic_id, state =3D x2apic_state; @@ -1872,7 +1874,7 @@ static __init void x2apic_disable(void) } =20 __x2apic_disable(); - register_lapic_address(mp_lapic_addr); + apic_set_fixmap(); } =20 static __init void x2apic_enable(void) @@ -2145,17 +2147,21 @@ void __init init_apic_mappings(void) } } =20 +static __init void apic_set_fixmap(void) +{ + set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); + apic_mmio_base =3D APIC_BASE; + apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", + apic_mmio_base, mp_lapic_addr); + apic_read_boot_cpu_id(false); +} + void __init register_lapic_address(unsigned long address) { mp_lapic_addr =3D address; =20 - if (x2apic_mode) - return; - - set_fixmap_nocache(FIX_APIC_BASE, address); - apic_mmio_base =3D APIC_BASE; - apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", APIC_BASE, ad= dress); - apic_read_boot_cpu_id(false); + if (!x2apic_mode) + apic_set_fixmap(); } =20 /* From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF57EEB64DC for ; Mon, 17 Jul 2023 23:15:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231316AbjGQXPq (ORCPT ); Mon, 17 Jul 2023 19:15:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35168 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229470AbjGQXPj (ORCPT ); Mon, 17 Jul 2023 19:15:39 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5072B198B for ; Mon, 17 Jul 2023 16:15:00 -0700 (PDT) Message-ID: <20230717223223.971994770@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635697; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=8u5DJ4HOBNg4NQW33fRGAZF4EOI10KBFaQA+4tROpKs=; b=QLI6o7zZfUJ6uEVO0T/AOaNQcFm6gfKddASqWmV7W5RXFSwy+nUSFe+jExElnmyMygYN6h O+A5BETXOY1qqqEmS9oY4XobPnGU8HRsrbtcHv5Dn94m867kCJI7J+ttmS9qV65vU6Vssm FsumQO6gxgYEnklbeiHdvqw0/jtVCo/zvPRZ9UXkKY2VfzJlu/StHZP59Sn0pHK3a8g24R BjRFse4HgOgghai1BtadP3xVsgPMXnCBCavZHPnwdRl+ZHOfRdGz/Ev2KB4az9ANz9MAnQ FKYADvdw62f6MK9bCryiUKZcK/pPQbhyeq/Ju/O8+m534u8J+HoKFD3u44SOuQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635697; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=8u5DJ4HOBNg4NQW33fRGAZF4EOI10KBFaQA+4tROpKs=; b=6oIKa1QrGezq5SuZ1jAJQe+seQVOmDV0SoWdTq18WSUjH1qD+gBOI2S4ha/qprGXeVBtCz C8rL0lbTGf5dxABA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 15/58] x86/apic: Sanitize APIC address setup References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:14:57 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert places which just write mp_lapic_addr and let them register the local APIC address directly instead of relying on magic other code to do so. Add a WARN_ON() into register_lapic_address() which is raised when register_lapic_address() is invoked more than once during boot. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/apic.c | 25 ++++++++----------------- 1 file changed, 8 insertions(+), 17 deletions(-) --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2009,12 +2009,12 @@ static bool __init detect_init_APIC(void return false; } =20 - mp_lapic_addr =3D APIC_DEFAULT_PHYS_BASE; + register_lapic_address(APIC_DEFAULT_PHYS_BASE); return true; } #else =20 -static bool __init apic_verify(void) +static bool __init apic_verify(unsigned long addr) { u32 features, h, l; =20 @@ -2028,15 +2028,15 @@ static bool __init apic_verify(void) return false; } set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); - mp_lapic_addr =3D APIC_DEFAULT_PHYS_BASE; =20 /* The BIOS may have set up the APIC at some other address */ if (boot_cpu_data.x86 >=3D 6) { rdmsr(MSR_IA32_APICBASE, l, h); if (l & MSR_IA32_APICBASE_ENABLE) - mp_lapic_addr =3D l & MSR_IA32_APICBASE_BASE; + addr =3D l & MSR_IA32_APICBASE_BASE; } =20 + register_lapic_address(addr); pr_info("Found and enabled local APIC!\n"); return true; } @@ -2063,7 +2063,7 @@ bool __init apic_force_enable(unsigned l enabled_via_apicbase =3D 1; } } - return apic_verify(); + return apic_verify(addr); } =20 /* @@ -2105,7 +2105,7 @@ static bool __init detect_init_APIC(void if (!apic_force_enable(APIC_DEFAULT_PHYS_BASE)) return false; } else { - if (!apic_verify()) + if (!apic_verify(APIC_DEFAULT_PHYS_BASE)) return false; } =20 @@ -2130,20 +2130,9 @@ void __init init_apic_mappings(void) if (x2apic_mode) return; =20 - /* If no local APIC can be found return early */ if (!smp_found_config && !detect_init_APIC()) { - /* lets NOP'ify apic operations */ pr_info("APIC: disable apic facility\n"); apic_disable(); - } else { - apic_phys =3D mp_lapic_addr; - - /* - * If the system has ACPI MADT tables or MP info, the LAPIC - * address is already registered. - */ - if (!acpi_lapic && !smp_found_config) - register_lapic_address(apic_phys); } } =20 @@ -2158,6 +2147,8 @@ static __init void apic_set_fixmap(void) =20 void __init register_lapic_address(unsigned long address) { + /* This should only happen once */ + WARN_ON_ONCE(mp_lapic_addr); mp_lapic_addr =3D address; =20 if (!x2apic_mode) From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A64CC001DC for ; Mon, 17 Jul 2023 23:15:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231397AbjGQXPt (ORCPT ); Mon, 17 Jul 2023 19:15:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229724AbjGQXPk (ORCPT ); Mon, 17 Jul 2023 19:15:40 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2301A1BCF for ; Mon, 17 Jul 2023 16:15:01 -0700 (PDT) Message-ID: <20230717223224.030628920@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635699; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=rxQN3La4uHdTmHXWvnEPxqt3sCLh4RNMZmN6BFMgny4=; b=NcyMzc1SpuMYk05jsCRG2BlucobaDGGxjcwIrVbflUWp+DfMWiCjUrOP+3T+SHBItpDnJz JQr/UwH+IrAWFgJHt+49ROFOgVq7XMwdrqWa3LoPyQNrsokPM2L/hm6rOLOxye6alIHXNu d+in5MQswN9Xf2J5maeJBeEjIlAiNDVaybk/8iFq9y+Pl7tX9B26CTM/jkG2tCTAzAxfex 1gAqexir7pwpa8+ntX2jez7qrxyTZQjDNTsyGVvwhm3gQvaaOYMA5Q7jUuQ249K0aqwulA VuQ0imijJyYSAG6hb74CJdYn7kMHxSPWQEFrohzQ+t675BzWo6RSomjFTM4RHg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635699; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=rxQN3La4uHdTmHXWvnEPxqt3sCLh4RNMZmN6BFMgny4=; b=B6sKhRrWrOBnzZ3M5Uk7oINAy9QWuQJLDHj4bnToS+GnxoWP+NoHkWASgNtcqo603IhS08 YD51KKO/6iFbZLCw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 16/58] x86/apic: Sanitize num_processors handling References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:14:59 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" num_processors is 0 by default and only gets incremented when local APICs are registered. Make init_apic_mappings(), which tries to enable the local APIC in the case that no SMP configuration was found set num_processors to 1. This allows to remove yet another check for the local APIC and yet another place which registers the boot CPUs local APIC ID. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/apic.c | 9 ++++++--- arch/x86/kernel/smpboot.c | 18 ------------------ 2 files changed, 6 insertions(+), 21 deletions(-) --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2130,9 +2130,12 @@ void __init init_apic_mappings(void) if (x2apic_mode) return; =20 - if (!smp_found_config && !detect_init_APIC()) { - pr_info("APIC: disable apic facility\n"); - apic_disable(); + if (!smp_found_config) { + if (!detect_init_APIC()) { + pr_info("APIC: disable apic facility\n"); + apic_disable(); + } + num_processors =3D 1; } } =20 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1389,24 +1389,6 @@ early_param("possible_cpus", _setup_poss { int i, possible; =20 - /* No processor was found in mptable or ACPI MADT */ - if (!num_processors) { - if (boot_cpu_has(X86_FEATURE_APIC)) { - int apicid =3D boot_cpu_physical_apicid; - int cpu =3D read_apic_id(); - - pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); - - /* Make sure boot cpu is enumerated */ - if (apic->cpu_present_to_apicid(0) =3D=3D BAD_APICID && - apic->apic_id_valid(apicid)) - generic_processor_info(apicid); - } - - if (!num_processors) - num_processors =3D 1; - } - i =3D setup_max_cpus ?: 1; if (setup_possible_cpus =3D=3D -1) { possible =3D num_processors; From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADD4AEB64DC for ; Mon, 17 Jul 2023 23:16:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231416AbjGQXQA (ORCPT ); Mon, 17 Jul 2023 19:16:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229637AbjGQXP6 (ORCPT ); Mon, 17 Jul 2023 19:15:58 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC62A1BE9 for ; Mon, 17 Jul 2023 16:15:06 -0700 (PDT) Message-ID: <20230717223224.087678447@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635701; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=XkrXDbsHY2D9ad8FanhOEsbWH/XRHFiUnXbnPluBQA4=; b=qHr9oU0r8qd75flp4JICvC2WzEGZhBOzfBTH3weDwjKcfD6yYyGalQdW4miVeRgWj0l2e/ tIDwfzYN6GoMqSDz2C9DJDCM2DFUEtyol2WRxlDye+RWteoV9blj8j1+KozQJQlZvu9Qo8 XuFhXBO9qA6pYyfvhWleXKXTiw7IjJko1rC/K63sU+BkFiX2YhaO/4iEWZqfizTTIFMPeB ifAgFG8CjrNLaQ2LP0KVQR8U/PW+1xWjo8JhDNmjTccvNR3jtSAfRzQvk1HGSb7wBS+NAf NswX7cpXaJtqH6x9MQpUsffedDA9nI9KrDeKCFwpMdRD0Xu4zfd7Fl7ZISn68g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635701; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=XkrXDbsHY2D9ad8FanhOEsbWH/XRHFiUnXbnPluBQA4=; b=Y2epMBLyA0KIYVFu+nXXQ8o2u/0MgriTKxN4OMyc74CJxKXayyzEDBjmXwEq0julz01liv r0SLracH4XiXNzBg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 17/58] x86/apic: Nuke another processor check References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:00 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The boot CPUs local APIC is now always registered, so there is no point to have another unreadable validatation for it. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/smpboot.c | 17 ----------------- 1 file changed, 17 deletions(-) --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1181,23 +1181,6 @@ static void __init smp_sanity_check(void set_nr_cpu_ids(8); } #endif - - if (!physid_isset(read_apic_id(), phys_cpu_present_map)) { - pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", - read_apic_id()); - - physid_set(read_apic_id(), phys_cpu_present_map); - } - - /* - * Should not be necessary because the MP table should list the boot - * CPU too, but we do it for the sake of robustness anyway. - */ - if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { - pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", - boot_cpu_physical_apicid); - physid_set(read_apic_id(), phys_cpu_present_map); - } preempt_enable(); } From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC76CEB64DC for ; Mon, 17 Jul 2023 23:16:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230236AbjGQXQQ (ORCPT ); Mon, 17 Jul 2023 19:16:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229823AbjGQXQO (ORCPT ); Mon, 17 Jul 2023 19:16:14 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E2C110F9 for ; Mon, 17 Jul 2023 16:15:23 -0700 (PDT) Message-ID: <20230717223224.147988474@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635702; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=JNhxutEtXryZ8mfn8zBsCWNzhhaSX4crArjVTieUfW4=; b=tPVYPQ5RwA3FpuRSmL8I88TiobqjXSpUowNZ/tKDY0KoCSGmLqD3NtophJLqqvygbzti5i 3tkJ0Vbjm01eJtK4Of+ClRDKtE0zk71QK9xPc3N+V9AZbAUQAFfmDt7GHCFy2ecdbp48iJ izC9uSSC0b3GmylnUYjcmiOlZNLATAkrtGMXcqUjVD6XuOt2MtVkq7agmh/lVY7VbbZEYw y7GNgLIIMcWbx9TJB0HQArMj+OCK/NJj7IfmaZoWWIHicxOIYSJ0Xw3a6y7Ps91HH4foMA keEjeo0SRiEOgKfs+cJi+m8vpYMFJKNp3w4SUEdBrQG/5eS8RTuXsxyGzPtz0w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635702; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=JNhxutEtXryZ8mfn8zBsCWNzhhaSX4crArjVTieUfW4=; b=chAts+bFtOccc+XLYzmttX7xrePhNREvW4V+SHtWSutziUOSPsG7D2igHx7bALrXPXHFVw T0ydmwyvwVQhCUBQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 18/58] x86/apic: Remove check_phys_apicid_present() References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:02 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The only silly usage site is gone. Remove the gunk which was even outright wrong in the bigsmp_32 case which returned true unconditionally. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 2 -- arch/x86/kernel/apic/apic_common.c | 5 ----- arch/x86/kernel/apic/apic_flat_64.c | 2 -- arch/x86/kernel/apic/apic_noop.c | 2 -- arch/x86/kernel/apic/apic_numachip.c | 2 -- arch/x86/kernel/apic/bigsmp_32.c | 6 ------ arch/x86/kernel/apic/probe_32.c | 1 - arch/x86/kernel/apic/x2apic_cluster.c | 1 - arch/x86/kernel/apic/x2apic_phys.c | 1 - arch/x86/kernel/apic/x2apic_uv_x.c | 1 - arch/x86/xen/apic.c | 1 - 11 files changed, 24 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -305,7 +305,6 @@ struct apic { void (*setup_apic_routing)(void); int (*cpu_present_to_apicid)(int mps_cpu); void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); - int (*check_phys_apicid_present)(int phys_apicid); int (*phys_pkg_id)(int cpuid_apic, int index_msb); =20 u32 (*get_apic_id)(unsigned long x); @@ -485,7 +484,6 @@ extern u32 apic_flat_calc_apicid(unsigne extern bool default_check_apicid_used(physid_mask_t *map, int apicid); extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mas= k_t *retmap); extern int default_cpu_present_to_apicid(int mps_cpu); -extern int default_check_phys_apicid_present(int phys_apicid); =20 #else /* CONFIG_X86_LOCAL_APIC */ =20 --- a/arch/x86/kernel/apic/apic_common.c +++ b/arch/x86/kernel/apic/apic_common.c @@ -35,11 +35,6 @@ int default_cpu_present_to_apicid(int mp } EXPORT_SYMBOL_GPL(default_cpu_present_to_apicid); =20 -int default_check_phys_apicid_present(int phys_apicid) -{ - return physid_isset(phys_apicid, phys_cpu_present_map); -} - int default_apic_id_valid(u32 apicid) { return (apicid < 255); --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -124,7 +124,6 @@ static struct apic apic_flat __ro_after_ .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .apicid_to_cpu_present =3D NULL, - .check_phys_apicid_present =3D default_check_phys_apicid_present, .phys_pkg_id =3D flat_phys_pkg_id, =20 .get_apic_id =3D flat_get_apic_id, @@ -213,7 +212,6 @@ static struct apic apic_physflat __ro_af .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .apicid_to_cpu_present =3D NULL, - .check_phys_apicid_present =3D default_check_phys_apicid_present, .phys_pkg_id =3D flat_phys_pkg_id, =20 .get_apic_id =3D flat_get_apic_id, --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -107,8 +107,6 @@ struct apic apic_noop __ro_after_init =3D .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .apicid_to_cpu_present =3D physid_set_mask_of_physid, =20 - .check_phys_apicid_present =3D default_check_phys_apicid_present, - .phys_pkg_id =3D noop_phys_pkg_id, =20 .get_apic_id =3D noop_get_apic_id, --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -257,7 +257,6 @@ static const struct apic apic_numachip1 .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .apicid_to_cpu_present =3D NULL, - .check_phys_apicid_present =3D default_check_phys_apicid_present, .phys_pkg_id =3D numachip_phys_pkg_id, =20 .get_apic_id =3D numachip1_get_apic_id, @@ -303,7 +302,6 @@ static const struct apic apic_numachip2 .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .apicid_to_cpu_present =3D NULL, - .check_phys_apicid_present =3D default_check_phys_apicid_present, .phys_pkg_id =3D numachip_phys_pkg_id, =20 .get_apic_id =3D numachip2_get_apic_id, --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -63,11 +63,6 @@ static void bigsmp_ioapic_phys_id_map(ph physids_promote(0xFFL, retmap); } =20 -static int bigsmp_check_phys_apicid_present(int phys_apicid) -{ - return 1; -} - static int bigsmp_phys_pkg_id(int cpuid_apic, int index_msb) { return cpuid_apic >> index_msb; @@ -138,7 +133,6 @@ static struct apic apic_bigsmp __ro_afte .setup_apic_routing =3D bigsmp_setup_apic_routing, .cpu_present_to_apicid =3D bigsmp_cpu_present_to_apicid, .apicid_to_cpu_present =3D physid_set_mask_of_physid, - .check_phys_apicid_present =3D bigsmp_check_phys_apicid_present, .phys_pkg_id =3D bigsmp_phys_pkg_id, =20 .get_apic_id =3D bigsmp_get_apic_id, --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -80,7 +80,6 @@ static struct apic apic_default __ro_aft .setup_apic_routing =3D setup_apic_flat_routing, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .apicid_to_cpu_present =3D physid_set_mask_of_physid, - .check_phys_apicid_present =3D default_check_phys_apicid_present, .phys_pkg_id =3D default_phys_pkg_id, =20 .get_apic_id =3D default_get_apic_id, --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -250,7 +250,6 @@ static struct apic apic_x2apic_cluster _ .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .apicid_to_cpu_present =3D NULL, - .check_phys_apicid_present =3D default_check_phys_apicid_present, .phys_pkg_id =3D x2apic_phys_pkg_id, =20 .get_apic_id =3D x2apic_get_apic_id, --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -174,7 +174,6 @@ static struct apic apic_x2apic_phys __ro .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .apicid_to_cpu_present =3D NULL, - .check_phys_apicid_present =3D default_check_phys_apicid_present, .phys_pkg_id =3D x2apic_phys_pkg_id, =20 .get_apic_id =3D x2apic_get_apic_id, --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -846,7 +846,6 @@ static struct apic apic_x2apic_uv_x __ro .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .apicid_to_cpu_present =3D NULL, - .check_phys_apicid_present =3D default_check_phys_apicid_present, .phys_pkg_id =3D uv_phys_pkg_id, =20 .get_apic_id =3D x2apic_get_apic_id, --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -154,7 +154,6 @@ static struct apic xen_pv_apic =3D { .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D xen_cpu_present_to_apicid, .apicid_to_cpu_present =3D physid_set_mask_of_physid, /* Used on 32-bit = */ - .check_phys_apicid_present =3D default_check_phys_apicid_present, /* smp_= sanity_check needs it */ .phys_pkg_id =3D xen_phys_pkg_id, /* detect_ht */ =20 .get_apic_id =3D xen_get_apic_id, From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BA02C001DC for ; Mon, 17 Jul 2023 23:16:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230299AbjGQXQS (ORCPT ); Mon, 17 Jul 2023 19:16:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231403AbjGQXQP (ORCPT ); Mon, 17 Jul 2023 19:16:15 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F872170A for ; Mon, 17 Jul 2023 16:15:28 -0700 (PDT) Message-ID: <20230717223224.207131427@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635704; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=aIQdyjgeuqgS020loHjY5emNS2jBJ0TkBAxP1UcK54o=; b=pVf2lpDpYh4f4Usviw2kiFQu2Jrlvpla6YoI0IZG/Je+7EeA9q4wQXJO7zgw2cGOIhTr7D G4/L0eSr2IO68nZPcnUThmeg6prXf8by+wFL0/cALVQ4VwnxzppGdKnEzxwQ7mgvGtmj8N SoxA4LHNYRvpK8PxwvSezE5MkEjpahZhFSpPzqZV1eV95sdImEjwNkB6x8lxPw1RXe2iwS jTQNbfeR2A+ZrpwUfUL/Ts+u+1tsNYfls1dsVbMiJCbiFpdwiLLEQ1BlT2LXP+Df9+7rXu Rgj927xY2AUtkww2RNplnOw9rY5Zp7dN0wN1xilJibUpyDO9RjAYDf3MwNAlYw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635704; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=aIQdyjgeuqgS020loHjY5emNS2jBJ0TkBAxP1UcK54o=; b=09NZQgSJHMQd45+whsEMRbCci79Ic6kHVNQJPgI/5G8hxpJby9SlVUEoYFWvRr+g/wYcg4 FMJ2PnKAbU/wNAAA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 19/58] x86/apic: Get rid of apic_phys References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:03 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" No need for an extra variable to find out whether the APIC has been mapped or is accessible (X2APIC mode). Provide an inline for this and check apic_mmio_base which is only set when the local APIC has been mapped. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/apic.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -99,6 +99,11 @@ static bool virt_ext_dest_id __ro_after_ /* For parallel bootup. */ unsigned long apic_mmio_base __ro_after_init; =20 +static inline bool apic_accessible(void) +{ + return x2apic_mode || apic_mmio_base; +} + /* * Map cpu index to physical APIC ID */ @@ -199,8 +204,6 @@ unsigned int lapic_timer_period =3D 0; =20 static void apic_pm_activate(void); =20 -static unsigned long apic_phys __ro_after_init; - /* * Get the LAPIC version */ @@ -1127,8 +1130,7 @@ void clear_local_APIC(void) int maxlvt; u32 v; =20 - /* APIC hasn't been mapped yet */ - if (!x2apic_mode && !apic_phys) + if (!apic_accessible()) return; =20 maxlvt =3D lapic_get_maxlvt(); @@ -1218,8 +1220,7 @@ void apic_soft_disable(void) */ void disable_local_APIC(void) { - /* APIC hasn't been mapped yet */ - if (!x2apic_mode && !apic_phys) + if (!apic_accessible()) return; =20 apic_soft_disable(); @@ -1921,7 +1922,6 @@ static __init void try_to_enable_x2apic( * be addressed must not be brought online. */ x2apic_set_max_apicid(apic_limit); - x2apic_phys =3D 1; } x2apic_enable(); } @@ -2895,11 +2895,11 @@ early_param("apic", apic_set_verbosity); =20 static int __init lapic_insert_resource(void) { - if (!apic_phys) + if (!apic_mmio_base) return -1; =20 /* Put local APIC into the resource map. */ - lapic_resource.start =3D apic_phys; + lapic_resource.start =3D apic_mmio_base; lapic_resource.end =3D lapic_resource.start + PAGE_SIZE - 1; insert_resource(&iomem_resource, &lapic_resource); From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0944EEB64DC for ; Mon, 17 Jul 2023 23:16:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231405AbjGQXQU (ORCPT ); Mon, 17 Jul 2023 19:16:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231420AbjGQXQQ (ORCPT ); Mon, 17 Jul 2023 19:16:16 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A58D170B for ; Mon, 17 Jul 2023 16:15:28 -0700 (PDT) Message-ID: <20230717223224.268566460@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635706; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=LOe1UoiHO0aHtIvZLfVAh+MlqMt/c3MCV5lR+OfD/ak=; b=DP+ucTBLyxyq0EBs0k+ln0LD9AxMX1VyQ/hhPgpJMOnhr+QtIZw+EfjFAkP+DXSk5iRbIP 0hpeyOn/xyVxTcczHjbCaXTSZd3CT6xDA3OsEercG21qP3isLsEw0n+bIwMpHa6NNhhoe5 zrC41CD2xPyi+3RrnrbuNlGPvTV40Nn1raqZO1iSepAcIBByu5ORIjAMShN5rEAyGShwLf enlkPe1F1b9r55isJkG7JlterUd8SLiuaNT9euIcalvrwhgU92/qoT97JeAqPs8RQv9cig hp4OYrX7Hp/HV+dW3wvzL+PBGBl4smrM0dCgWrNyP+hJ88ZUG5STDyJxWhliVQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635706; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=LOe1UoiHO0aHtIvZLfVAh+MlqMt/c3MCV5lR+OfD/ak=; b=RQbAdPYOX2KtL5Tcp4ULrped4lliiLCRgEZOw57CX7AxHODoEhlxpJG9oeqPb4wknIR7+4 5BvEYYF3dlenBYCQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 20/58] x86/apic/32: Sanitize logical APIC ID handling References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:05 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" apic::x86_32_early_logical_apicid() is yet another historical joke. It is used to preset the x86_cpu_to_logical_apicid per CPU variable during APIC enumeration with: - 1 shifted left by the CPU number - the physical APIC ID in case of bigsmp The latter is hillarious because bigsmp uses physical destination mode which never can use the logical APIC ID. It gets even worse. As bigsmp can be enforced late in the boot process the probe function overwrites the per CPU variable which is never used for this APIC type once again. Remove that gunk and store 1 << cpunr unconditionally if and only if the CPU number is less than 8, because the default logical destination mode only allows up to 8 CPUs. This is just an intermediate step before removing the per CPU insanity completely. Stay tuned. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 13 ------------- arch/x86/kernel/apic/apic.c | 4 ++-- arch/x86/kernel/apic/apic_noop.c | 11 ----------- arch/x86/kernel/apic/bigsmp_32.c | 18 ------------------ arch/x86/kernel/apic/probe_32.c | 7 ------- 5 files changed, 2 insertions(+), 51 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -315,19 +315,6 @@ struct apic { /* wakeup secondary CPU using 64-bit wakeup point */ int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip); =20 -#ifdef CONFIG_X86_32 - /* - * Called very early during boot from get_smp_config(). It should - * return the logical apicid. x86_[bios]_cpu_to_apicid is - * initialized before this function is called. - * - * If logical apicid can't be determined that early, the function - * may return BAD_APICID. Logical apicid will be configured after - * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity - * won't be applied properly during early boot in this case. - */ - int (*x86_32_early_logical_apicid)(int cpu); -#endif char *name; }; =20 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2434,8 +2434,8 @@ static void cpu_update_apic(int cpu, int early_per_cpu(x86_cpu_to_apicid, cpu) =3D apicid; #endif #ifdef CONFIG_X86_32 - early_per_cpu(x86_cpu_to_logical_apicid, cpu) =3D - apic->x86_32_early_logical_apicid(cpu); + if (cpu < 8) + early_per_cpu(x86_cpu_to_logical_apicid, cpu) =3D 1U << cpu; #endif set_cpu_possible(cpu, true); physid_set(apicid, phys_cpu_present_map); --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -80,13 +80,6 @@ static void noop_apic_write(u32 reg, u32 WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_APIC) && !apic_is_disabled); } =20 -#ifdef CONFIG_X86_32 -static int noop_x86_32_early_logical_apicid(int cpu) -{ - return BAD_APICID; -} -#endif - struct apic apic_noop __ro_after_init =3D { .name =3D "noop", .probe =3D noop_probe, @@ -130,8 +123,4 @@ struct apic apic_noop __ro_after_init =3D .icr_write =3D noop_apic_icr_write, .wait_icr_idle =3D noop_apic_wait_icr_idle, .safe_wait_icr_idle =3D noop_safe_apic_wait_icr_idle, - -#ifdef CONFIG_X86_32 - .x86_32_early_logical_apicid =3D noop_x86_32_early_logical_apicid, -#endif }; --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -28,12 +28,6 @@ static bool bigsmp_check_apicid_used(phy return false; } =20 -static int bigsmp_early_logical_apicid(int cpu) -{ - /* on bigsmp, logical apicid is the same as physical */ - return early_per_cpu(x86_cpu_to_apicid, cpu); -} - /* * bigsmp enables physical destination mode * and doesn't use LDR and DFR @@ -154,27 +148,15 @@ static struct apic apic_bigsmp __ro_afte .icr_write =3D native_apic_icr_write, .wait_icr_idle =3D native_apic_wait_icr_idle, .safe_wait_icr_idle =3D native_safe_apic_wait_icr_idle, - - .x86_32_early_logical_apicid =3D bigsmp_early_logical_apicid, }; =20 void __init generic_bigsmp_probe(void) { - unsigned int cpu; - if (!probe_bigsmp()) return; =20 apic =3D &apic_bigsmp; =20 - for_each_possible_cpu(cpu) { - if (early_per_cpu(x86_cpu_to_logical_apicid, - cpu) =3D=3D BAD_APICID) - continue; - early_per_cpu(x86_cpu_to_logical_apicid, cpu) =3D - bigsmp_early_logical_apicid(cpu); - } - pr_info("Overriding APIC driver with %s\n", apic_bigsmp.name); } =20 --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -16,11 +16,6 @@ =20 #include "local.h" =20 -static int default_x86_32_early_logical_apicid(int cpu) -{ - return 1 << cpu; -} - static void setup_apic_flat_routing(void) { #ifdef CONFIG_X86_IO_APIC @@ -101,8 +96,6 @@ static struct apic apic_default __ro_aft .icr_write =3D native_apic_icr_write, .wait_icr_idle =3D native_apic_wait_icr_idle, .safe_wait_icr_idle =3D native_safe_apic_wait_icr_idle, - - .x86_32_early_logical_apicid =3D default_x86_32_early_logical_apicid, }; =20 apic_driver(apic_default); From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 971FFC001DC for ; Mon, 17 Jul 2023 23:16:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231440AbjGQXQe (ORCPT ); Mon, 17 Jul 2023 19:16:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231422AbjGQXQb (ORCPT ); Mon, 17 Jul 2023 19:16:31 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A999172E for ; Mon, 17 Jul 2023 16:15:45 -0700 (PDT) Message-ID: <20230717223224.328307760@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635707; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=RDUEJbQ4kWbt2l91v1HLuRRyZwh425n2zPuDH8hhE+w=; b=EQ3Rk00rf3sVU10BxtvPZV6/6BI2sAMv0ynyJSJy/ZQqfJYlDchem0giciNwE4fkR0LiIU h1IWUm6bDWXUkjLh1icTpmQ5rJJvKR7tAlFBevC2C0nqVCbLd2/plc2gTMEHgFsjAnvZ4T c9ZW65DamhpU+j+AZIWXIsxO0foCDrdsmYLzDPgcyh3W/D1ORWz57jXWCezRQDo10GA6M2 iia08BiH8QBiQpMKoydcAT9mJCPnmD0mTJ0aKDXdP/XfefJKD+iHmLx/oP56X5dOzdIDkv ASzgwR1C6ZYyKc+i/AoLJkOKFrQN8ZHNgMlxXc+T+iI9cw7811WPUOwSKdAHdg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635707; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=RDUEJbQ4kWbt2l91v1HLuRRyZwh425n2zPuDH8hhE+w=; b=M59EGHjAOsvIzjUf7LmE/wgADhnqezVIlDcvVLUqSDmSgmyL4ug52kJfOBduHpim92br9C RLEqt6oxqAP+h7DQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 21/58] x86/apic/32: Remove x86_cpu_to_logical_apicid References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:07 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This per CPU variable is just yet another form of voodoo programming. The boot ordering is: per_cpu(x86_cpu_to_logical_apicid, cpu) =3D 1U << cpu; ..... setup_apic() apic->init_apic_ldr() default_init_apic_ldr() apic_write(SET_APIC_LOGICAL_ID(1UL << smp_processor_id(), APIC_LDR= ); id =3D GET_APIC_LOGICAL_ID(apic_read(APIC_LDR); WARN_ON(id !=3D per_cpu(x86_cpu_to_logical_apicid, cpu)); per_cpu(x86_cpu_to_logical_apicid, cpu) =3D id; So first write the default into LDR and then validate it against the same d= efault which was set up during early boot APIC enumeration. Brilliant, isn't it? The comment above the per CPU variable declaration describes it well: 'Let's keep it ugly for now.' Remove the useless gunk and use '1U << cpu' consistently all over the place. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/smp.h | 3 --- arch/x86/kernel/apic/apic.c | 31 ------------------------------- arch/x86/kernel/apic/ipi.c | 36 +++++++++--------------------------- arch/x86/kernel/setup_percpu.c | 7 ------- 4 files changed, 9 insertions(+), 68 deletions(-) --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -22,9 +22,6 @@ DECLARE_PER_CPU_READ_MOSTLY(u16, cpu_l2c =20 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid); DECLARE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid); -#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) -DECLARE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid); -#endif =20 struct task_struct; =20 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -113,15 +113,6 @@ EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_a EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); =20 #ifdef CONFIG_X86_32 - -/* - * On x86_32, the mapping between cpu and logical apicid may vary - * depending on apic in use. The following early percpu variable is - * used for the mapping. This is where the behaviors of x86_64 and 32 - * actually diverge. Let's keep it ugly for now. - */ -DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICI= D); - /* Local APIC was disabled by the BIOS and enabled by the kernel */ static int enabled_via_apicbase __ro_after_init; =20 @@ -1589,24 +1580,6 @@ static void setup_local_APIC(void) */ apic->init_apic_ldr(); =20 -#ifdef CONFIG_X86_32 - if (apic->dest_mode_logical) { - int logical_apicid, ldr_apicid; - - /* - * APIC LDR is initialized. If logical_apicid mapping was - * initialized during get_smp_config(), make sure it matches - * the actual value. - */ - logical_apicid =3D early_per_cpu(x86_cpu_to_logical_apicid, cpu); - ldr_apicid =3D GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); - if (logical_apicid !=3D BAD_APICID) - WARN_ON(logical_apicid !=3D ldr_apicid); - /* Always use the value from LDR. */ - early_per_cpu(x86_cpu_to_logical_apicid, cpu) =3D ldr_apicid; - } -#endif - /* * Set Task Priority to 'accept all except vectors 0-31'. An APIC * vector in the 16-31 range could be delivered if TPR =3D=3D 0, but we @@ -2433,10 +2406,6 @@ static void cpu_update_apic(int cpu, int #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) early_per_cpu(x86_cpu_to_apicid, cpu) =3D apicid; #endif -#ifdef CONFIG_X86_32 - if (cpu < 8) - early_per_cpu(x86_cpu_to_logical_apicid, cpu) =3D 1U << cpu; -#endif set_cpu_possible(cpu, true); physid_set(apicid, phys_cpu_present_map); set_cpu_present(cpu, true); --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -243,50 +243,32 @@ void default_send_IPI_self(int vector) } =20 #ifdef CONFIG_X86_32 - -void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, - int vector) +void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, in= t vector) { unsigned long flags; - unsigned int query_cpu; - - /* - * Hack. The clustered APIC addressing mode doesn't allow us to send - * to an arbitrary mask, so I do a unicasts to each CPU instead. This - * should be modified to do 1 message per cluster ID - mbligh - */ + unsigned int cpu; =20 local_irq_save(flags); - for_each_cpu(query_cpu, mask) - __default_send_IPI_dest_field( - early_per_cpu(x86_cpu_to_logical_apicid, query_cpu), - vector, APIC_DEST_LOGICAL); + for_each_cpu(cpu, mask) + __default_send_IPI_dest_field(1U << cpu, vector, APIC_DEST_LOGICAL); local_irq_restore(flags); } =20 void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask, int vector) { + unsigned int cpu, this_cpu =3D smp_processor_id(); unsigned long flags; - unsigned int query_cpu; - unsigned int this_cpu =3D smp_processor_id(); - - /* See Hack comment above */ =20 local_irq_save(flags); - for_each_cpu(query_cpu, mask) { - if (query_cpu =3D=3D this_cpu) + for_each_cpu(cpu, mask) { + if (cpu =3D=3D this_cpu) continue; - __default_send_IPI_dest_field( - early_per_cpu(x86_cpu_to_logical_apicid, query_cpu), - vector, APIC_DEST_LOGICAL); - } + __default_send_IPI_dest_field(1U << cpu, vector, APIC_DEST_LOGICAL); + } local_irq_restore(flags); } =20 -/* - * This is only used on smaller machines. - */ void default_send_IPI_mask_logical(const struct cpumask *cpumask, int vect= or) { unsigned long mask =3D cpumask_bits(cpumask)[0]; --- a/arch/x86/kernel/setup_percpu.c +++ b/arch/x86/kernel/setup_percpu.c @@ -184,10 +184,6 @@ void __init setup_per_cpu_areas(void) per_cpu(x86_cpu_to_acpiid, cpu) =3D early_per_cpu_map(x86_cpu_to_acpiid, cpu); #endif -#ifdef CONFIG_X86_32 - per_cpu(x86_cpu_to_logical_apicid, cpu) =3D - early_per_cpu_map(x86_cpu_to_logical_apicid, cpu); -#endif #ifdef CONFIG_NUMA per_cpu(x86_cpu_to_node_map, cpu) =3D early_per_cpu_map(x86_cpu_to_node_map, cpu); @@ -214,9 +210,6 @@ void __init setup_per_cpu_areas(void) early_per_cpu_ptr(x86_cpu_to_apicid) =3D NULL; early_per_cpu_ptr(x86_cpu_to_acpiid) =3D NULL; #endif -#ifdef CONFIG_X86_32 - early_per_cpu_ptr(x86_cpu_to_logical_apicid) =3D NULL; -#endif #ifdef CONFIG_NUMA early_per_cpu_ptr(x86_cpu_to_node_map) =3D NULL; #endif From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EE67EB64DC for ; Mon, 17 Jul 2023 23:16:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231433AbjGQXQb (ORCPT ); Mon, 17 Jul 2023 19:16:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36276 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231432AbjGQXQ3 (ORCPT ); Mon, 17 Jul 2023 19:16:29 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 002A4132 for ; Mon, 17 Jul 2023 16:15:42 -0700 (PDT) Message-ID: <20230717223224.387322230@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635709; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=oBy16z9oVs8uzIdM6vzKosS3I9qeD3Jk8eFl+Cs6+fk=; b=tmIcEk9XpjQcUhC77tzrt+q6FJfA7Knf1Ts0BMgMqrctHb+QoRjibisDoJ+IlNuvLYbdHv Y3t5PbjQ34QB12uGL4rRDgtbBlTsBEQM1vUxhslhlp+EL0AXi6WVOspkW3vWriRoDHWIcF 21rlQp09gIBPBDTSx5doUgfDue9Dj3Lope9QbyjBGRcC+4Cm52sVTdR9caVuRM9ub1XIyf VeDbUgz7AcsvfhZUDIy3CS8yderQtxaVl1K0cR6ELUAAA0RG9Mv6X6IA57H6O05F5gE60d 8U9Y6un/5bfDVB6EWESnD706BJrJHTDUmKTYhdgwzI0qnB0Fppl2yyODXwiD+g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635709; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=oBy16z9oVs8uzIdM6vzKosS3I9qeD3Jk8eFl+Cs6+fk=; b=OMBprqP0VGos8jmJkNRVP95C0AxZwsyctJ+1dU9Xsy94RSKAwUReBcNWlf5zFtOlMcIbqH rmyWLpGg2NiFaDAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 22/58] x86/apic/ipi: Code cleanup References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:08 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove completely useless and mindlessly copied comments and tidy up the code which causes eye bleed when looking at it. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/ipi.c | 23 +++++++---------------- 1 file changed, 7 insertions(+), 16 deletions(-) --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -184,18 +184,13 @@ void default_send_IPI_single_phys(int cp =20 void default_send_IPI_mask_sequence_phys(const struct cpumask *mask, int v= ector) { - unsigned long query_cpu; unsigned long flags; + unsigned long cpu; =20 - /* - * Hack. The clustered APIC addressing mode doesn't allow us to send - * to an arbitrary mask, so I do a unicast to each CPU instead. - * - mbligh - */ local_irq_save(flags); - for_each_cpu(query_cpu, mask) { + for_each_cpu(cpu, mask) { __default_send_IPI_dest_field(per_cpu(x86_cpu_to_apicid, - query_cpu), vector, APIC_DEST_PHYSICAL); + cpu), vector, APIC_DEST_PHYSICAL); } local_irq_restore(flags); } @@ -203,18 +198,15 @@ void default_send_IPI_mask_sequence_phys void default_send_IPI_mask_allbutself_phys(const struct cpumask *mask, int vector) { - unsigned int this_cpu =3D smp_processor_id(); - unsigned int query_cpu; + unsigned int cpu, this_cpu =3D smp_processor_id(); unsigned long flags; =20 - /* See Hack comment above */ - local_irq_save(flags); - for_each_cpu(query_cpu, mask) { - if (query_cpu =3D=3D this_cpu) + for_each_cpu(cpu, mask) { + if (cpu =3D=3D this_cpu) continue; __default_send_IPI_dest_field(per_cpu(x86_cpu_to_apicid, - query_cpu), vector, APIC_DEST_PHYSICAL); + cpu), vector, APIC_DEST_PHYSICAL); } local_irq_restore(flags); } @@ -283,7 +275,6 @@ void default_send_IPI_mask_logical(const local_irq_restore(flags); } =20 -/* must come after the send_IPI functions above for inlining */ static int convert_apicid_to_cpu(int apic_id) { int i; From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F5BDEB64DC for ; Mon, 17 Jul 2023 23:16:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231454AbjGQXQl (ORCPT ); Mon, 17 Jul 2023 19:16:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231444AbjGQXQe (ORCPT ); Mon, 17 Jul 2023 19:16:34 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7DBE1737 for ; Mon, 17 Jul 2023 16:15:46 -0700 (PDT) Message-ID: <20230717223224.444954484@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635710; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=cjdrCvZHnH3sO0Olcvdwl8Hi5blCr2ZcSnmxA24BUR4=; b=y+8T2oDvcEKeyeCklnaCk/WqabLO+VADf6/86pJOumvRNn807m/oM/f4/ZaF5eqKLpUJMe WyyZIKdKMOnXFZNL85mdijnrsPok8rCWBoj9m6n7YP9eOec6BJKerMR02JPrpKCRR/SgkY LbcIieBr6+SgFB4gdawQZfkdS50w1fmwXJeSWkXHPVewa1s7kHPQ1X7++8wM3nWpPW+NM6 OmjEhNgCSCHKySE0xdxT3/CixuiiJVA+YYByUOX79ZvuNHnvmLaKE0elftUvvTdKaXXqVD q4HbBJSqcwbs9y+B1XUrZAHXcZmTZa8zUsfTe6b7+Z1lIaWCSNLjhKvSKWJFCw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635710; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=cjdrCvZHnH3sO0Olcvdwl8Hi5blCr2ZcSnmxA24BUR4=; b=dMchqiD6AEKV99oENrDA29LWzQtH/vD5fWx6eCd9Xl/jF7vVCTzTSpOQGbuMgA35gtqdJP gX912dygNeZJVnCQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 23/58] x86/apic: Mop up early_per_cpu() abuse References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:10 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" UV X2APIC uses the per CPU variable from: native_smp_prepare_cpus() uv_system_init() uv_system_init_hub() which is long after the per CPU areas have been set up. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/x2apic_uv_x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -1843,7 +1843,7 @@ static void __init uv_system_init_hub(vo =20 /* Initialize per CPU info: */ for_each_possible_cpu(cpu) { - int apicid =3D early_per_cpu(x86_cpu_to_apicid, cpu); + int apicid =3D per_cpu(x86_cpu_to_apicid, cpu); unsigned short bid; unsigned short pnode; From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1727C001DC for ; Mon, 17 Jul 2023 23:16:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231453AbjGQXQo (ORCPT ); Mon, 17 Jul 2023 19:16:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231459AbjGQXQk (ORCPT ); Mon, 17 Jul 2023 19:16:40 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E67619B3 for ; Mon, 17 Jul 2023 16:15:51 -0700 (PDT) Message-ID: <20230717223224.504601096@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635712; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=KOrCgxfZUWOEP5kQU9kDQX721qeaGgb7AagTW/GicUQ=; b=oiRhFEFFvGuOGsKWDiQ8THEq6of5+8aMxDRz8+YOj50I8rOP8AY970wOn35phqd76f38XD 8zFZw3BC4E+ZRTJpTr258Pf6glz18bevFmz9K6hBj8mpl+QBFT1gSk4iufxaN9carsBtW5 Y9hPPM2z54hgpT/d95k7+tP8iAenhd3Zu24DrOkb4wMhbk71PFHTUeaAQHx9cMzZ1ScpzO +vonEO4uHaQTiCsl6RtjECwQNpDVscxUFX9mv5tM7A1TvJmY9NGwsttjuzZyNEnnMhNsdZ +cZpTde91cpythj/IUHK3pJ0alWpYsPvUwPplg6p/kTdR+rYnQmi2MFL3FPH8w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635712; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=KOrCgxfZUWOEP5kQU9kDQX721qeaGgb7AagTW/GicUQ=; b=Nc/fnigbZfoKzY8HMkUzD6HHp5XpCEeUqCsfekUtoDmN4YGLGQMvvszhGWqLGWAXsaq1Ai 5HwnoT74tFmHmJAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 24/58] x86/apic/32: Remove pointless default_acpi_madt_oem_check() References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:11 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On 32bit there is no APIC implementing the acpi_madt_oem_check() except XEN PV, but that does not matter at all. generic_apic_probe() runs before ACPI tables are parsed. This selects the XEN APIC if there is no command line override because the XEN APIC driver is the first to be probed. If there is a command line override then the XEN PV driver won't be selected in the MADT OEM check either. As there is no other MADT check implemented for 32bit APICs, this whole excercise is a NOOP and can be removed. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 4 +++- arch/x86/kernel/apic/bigsmp_32.c | 1 - arch/x86/kernel/apic/probe_32.c | 22 ---------------------- 3 files changed, 3 insertions(+), 24 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -459,10 +459,12 @@ static inline unsigned int read_apic_id( #ifdef CONFIG_X86_64 typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip); extern void acpi_wake_cpu_handler_update(wakeup_cpu_handler handler); +extern int default_acpi_madt_oem_check(char *, char *); +#else +static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0= ; } #endif =20 extern int default_apic_id_valid(u32 apicid); -extern int default_acpi_madt_oem_check(char *, char *); extern void default_setup_apic_routing(void); =20 extern u32 apic_default_calc_apicid(unsigned int cpu); --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -112,7 +112,6 @@ static struct apic apic_bigsmp __ro_afte =20 .name =3D "bigsmp", .probe =3D probe_bigsmp, - .acpi_madt_oem_check =3D NULL, .apic_id_valid =3D default_apic_id_valid, .apic_id_registered =3D bigsmp_apic_id_registered, =20 --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -60,7 +60,6 @@ static struct apic apic_default __ro_aft =20 .name =3D "default", .probe =3D probe_default, - .acpi_madt_oem_check =3D NULL, .apic_id_valid =3D default_apic_id_valid, .apic_id_registered =3D default_apic_id_registered, =20 @@ -176,24 +175,3 @@ void __init generic_apic_probe(void) } printk(KERN_INFO "Using APIC driver %s\n", apic->name); } - -/* This function can switch the APIC even after the initial ->probe() */ -int __init default_acpi_madt_oem_check(char *oem_id, char *oem_table_id) -{ - struct apic **drv; - - for (drv =3D __apicdrivers; drv < __apicdrivers_end; drv++) { - if (!(*drv)->acpi_madt_oem_check) - continue; - if (!(*drv)->acpi_madt_oem_check(oem_id, oem_table_id)) - continue; - - if (!cmdline_apic) { - apic =3D *drv; - printk(KERN_INFO "Switched to APIC driver `%s'.\n", - apic->name); - } - return 1; - } - return 0; -} From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E749EB64DC for ; Mon, 17 Jul 2023 23:17:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231477AbjGQXR2 (ORCPT ); Mon, 17 Jul 2023 19:17:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230325AbjGQXRZ (ORCPT ); Mon, 17 Jul 2023 19:17:25 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E71691AC for ; Mon, 17 Jul 2023 16:16:43 -0700 (PDT) Message-ID: <20230717223224.564567063@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635713; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=rQwiDVrZdKXtkOeCkuU+BAsq9XS3fbn/pUNfphOa6Ug=; b=Pim/4LrukbAuWI2R7g6Iki1lM0VXNQWjRthfzaL22Na0tDjjPIfMO5sG/Y6coO6Hx3eb3l +umH32CdFdB1Ob8eT0EkEZ3Ze62SiYZ4R1u0D4UYMq4MadwqEqY0I0i/e+O1c4wVJNbrbb hEfFbVzsi9TwesIU9bhBMJqLZe9fIIE5b8zKJOn14+aOyjL0Upyl5ok+ay7vPSp6WLyPky Q22Uu/FVeLSFid2urWQDQB/I1OWGPUzMhJGSjUvSI/J/ZqsQEPlQWtrW+IQMLLIsAPLli3 7GGmJw1HB4Mc4gguWxqKhM1y3EV3Ra+Y7tZyMjbmAsFr4L6PW3P1yFYKaXUGtQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635713; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=rQwiDVrZdKXtkOeCkuU+BAsq9XS3fbn/pUNfphOa6Ug=; b=hzhBJlXwg7x0YxSpbK4V31U/2U+qJdnSGHMqjXU+hC3oXhHjNOl5cN7+sqnSEqcDyf5oMO Jf/joeeBgWmmaNAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 25/58] x86/apic/32: Decrapify the def_bigsmp mechanism References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:13 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If the system has more than 8 CPUs then XAPIC and the bigsmp APIC driver is required. This is ensured via: 1) Enumerating all possible CPUs up to NR_CPUS 2) Checking at boot CPU APIC setup time whether the system has more than 8 CPUs and has an XAPIC. If that's the case then it's attempted to install the bigsmp APIC driver and a magic variable 'def_to_bigsmp' is set to one. 3) If that magic variable is set and CONFIG_X86_BIGSMP=3Dn and the system has more than 8 CPUs smp_sanity_check() removes all CPUs >=3D #8 from the present and possible mask in the most convoluted way. This logic is completely broken for the case where the bigsmp driver is enabled, but not selected due to a command line option specifying the default APIC. In that case the system boots with default APIC in logical destination mode and fails to reduce the number of CPUs. That aside the above which is sprinkled over 3 different places is yet another piece of art. It would have been too obvious to check the requirements upfront and limit nr_cpu_ids _before_ enumerating tons of CPUs and then removing them again. Implement exactly this. Check the bigsmp requirement when the boot APIC is registered which happens _before_ ACPI/MPTABLE parsing and limit the number of CPUs to 8 if it can't be used. Switch it over when the boot CPU apic is set up if necessary. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/apic.c | 3 +++ arch/x86/kernel/apic/bigsmp_32.c | 22 ++++++++++------------ arch/x86/kernel/apic/local.h | 11 +++++++++++ arch/x86/kernel/apic/probe_32.c | 35 +++++++++++++++++------------------ arch/x86/kernel/smpboot.c | 37 ----------------------------------= --- 5 files changed, 41 insertions(+), 67 deletions(-) --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -63,6 +63,8 @@ #include #include =20 +#include "local.h" + unsigned int num_processors; =20 unsigned disabled_cpus; @@ -2418,6 +2420,7 @@ static __init void cpu_set_boot_apic(voi { cpuid_to_apicid[0] =3D boot_cpu_physical_apicid; cpu_update_apic(0, boot_cpu_physical_apicid); + x86_32_probe_bigsmp_early(); } =20 int generic_processor_info(int apicid) --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -100,12 +100,7 @@ static const struct dmi_system_id bigsmp =20 static int probe_bigsmp(void) { - if (def_to_bigsmp) - dmi_bigsmp =3D 1; - else - dmi_check_system(bigsmp_dmi_table); - - return dmi_bigsmp; + return dmi_check_system(bigsmp_dmi_table); } =20 static struct apic apic_bigsmp __ro_after_init =3D { @@ -149,14 +144,17 @@ static struct apic apic_bigsmp __ro_afte .safe_wait_icr_idle =3D native_safe_apic_wait_icr_idle, }; =20 -void __init generic_bigsmp_probe(void) +bool __init apic_bigsmp_possible(bool cmdline_override) { - if (!probe_bigsmp()) - return; - - apic =3D &apic_bigsmp; + return apic =3D=3D &apic_bigsmp || !cmdline_override; +} =20 - pr_info("Overriding APIC driver with %s\n", apic_bigsmp.name); +void __init apic_bigsmp_force(void) +{ + if (apic !=3D &apic_bigsmp) { + apic =3D &apic_bigsmp; + pr_info("Overriding APIC driver with bigsmp\n"); + } } =20 apic_driver(apic_bigsmp); --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -66,4 +66,15 @@ void default_send_IPI_self(int vector); void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, in= t vector); void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask, = int vector); void default_send_IPI_mask_logical(const struct cpumask *mask, int vector); +void x86_32_probe_bigsmp_early(void); +#else +static inline void x86_32_probe_bigsmp_early(void) { } +#endif + +#ifdef CONFIG_X86_BIGSMP +bool apic_bigsmp_possible(bool cmdline_selected); +void apic_bigsmp_force(void); +#else +static inline bool apic_bigsmp_possible(bool cmdline_selected) { return fa= lse; }; +static inline void apic_bigsmp_force(void) { } #endif --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -10,6 +10,8 @@ #include #include =20 +#include + #include #include #include @@ -123,36 +125,33 @@ static int __init parse_apic(char *arg) } early_param("apic", parse_apic); =20 -void __init default_setup_apic_routing(void) +void __init x86_32_probe_bigsmp_early(void) { - int version =3D boot_cpu_apic_version; + if (nr_cpu_ids <=3D 8 || xen_pv_domain()) + return; =20 - if (num_possible_cpus() > 8) { + if (IS_ENABLED(CONFIG_X86_BIGSMP)) { switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_INTEL: - if (!APIC_XAPIC(version)) { - def_to_bigsmp =3D 0; + if (!APIC_XAPIC(boot_cpu_apic_version)) break; - } /* P4 and above */ fallthrough; case X86_VENDOR_HYGON: case X86_VENDOR_AMD: - def_to_bigsmp =3D 1; + if (apic_bigsmp_possible(cmdline_apic)) + return; + break; } } + pr_info("Limiting to 8 possible CPUs\n"); + set_nr_cpu_ids(8); +} =20 -#ifdef CONFIG_X86_BIGSMP - /* - * This is used to switch to bigsmp mode when - * - There is no apic=3D option specified by the user - * - generic_apic_probe() has chosen apic_default as the sub_arch - * - we find more than 8 CPUs in acpi LAPIC listing with xAPIC support - */ - - if (!cmdline_apic && apic =3D=3D &apic_default) - generic_bigsmp_probe(); -#endif +void __init default_setup_apic_routing(void) +{ + if (nr_cpu_ids >=3D 8 && !xen_pv_domain()) + apic_bigsmp_force(); =20 if (apic->setup_apic_routing) apic->setup_apic_routing(); --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1149,41 +1149,6 @@ static __init void disable_smp(void) cpumask_set_cpu(0, topology_die_cpumask(0)); } =20 -/* - * Various sanity checks. - */ -static void __init smp_sanity_check(void) -{ - preempt_disable(); - -#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) - if (def_to_bigsmp && nr_cpu_ids > 8) { - unsigned int cpu; - unsigned nr; - - pr_warn("More than 8 CPUs detected - skipping them\n" - "Use CONFIG_X86_BIGSMP\n"); - - nr =3D 0; - for_each_present_cpu(cpu) { - if (nr >=3D 8) - set_cpu_present(cpu, false); - nr++; - } - - nr =3D 0; - for_each_possible_cpu(cpu) { - if (nr >=3D 8) - set_cpu_possible(cpu, false); - nr++; - } - - set_nr_cpu_ids(8); - } -#endif - preempt_enable(); -} - static void __init smp_cpu_index_default(void) { int i; @@ -1243,8 +1208,6 @@ void __init native_smp_prepare_cpus(unsi { smp_prepare_cpus_common(); =20 - smp_sanity_check(); - switch (apic_intr_mode) { case APIC_PIC: case APIC_VIRTUAL_WIRE_NO_CONFIG: From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82D61EB64DC for ; Mon, 17 Jul 2023 23:27:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231641AbjGQX1d (ORCPT ); Mon, 17 Jul 2023 19:27:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229688AbjGQX1a (ORCPT ); Mon, 17 Jul 2023 19:27:30 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5643186 for ; Mon, 17 Jul 2023 16:26:44 -0700 (PDT) Message-ID: <20230717223224.623297513@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635715; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=EVZ3Nalwxs4PGlJG4O/zCaoIlP8Kdk3XpwGeUBcVZSg=; b=0pf9RWB1fwKjGpEZA2bDmksipqXKofRhPUeloFtOb3VR7ML7OYdXyDCeKOdNSKBwOC43r4 Vwu+tTGK1yHwm0Mf61yxA7ejaUNV5eIJptgXC7sQx7N/Vw5YJYxssU94+dEccyMqX4e2Qm ztXccliUFlnCFAU+7Z8QFRMfrxUpqVvL24eFMXNoeVHYxRB7qgAPT0BU2v25/HIp0w369N XQs1N4losx/R/25jl8bWHGtcz2PR4NOnx532FpAE4Ib6YqNjqfFbtz2BdTPI9jYt2hvXQ8 gHf0DeWBbnPDqrtBzzhJ4iz017o91rICWKuOfLC50GPUxoczfKErrhcXaNC6qQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635715; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=EVZ3Nalwxs4PGlJG4O/zCaoIlP8Kdk3XpwGeUBcVZSg=; b=cwwdVUeQvFPDl21od6SdWk2ZI0dFdarJO/au6C/T1qOTHKScqvO0XGiK/RN9uGLw0vRh4t cec6hDjXpELcFGAA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 26/58] x86/apic/32: Remove bigsmp_cpu_present_to_apicid() References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:14 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It's a copy of default_cpu_present_to_apicid() with the omission of the actual check whether the CPU is present. This APIC callback should die completely, but the XEN APIC implementation does something different which needs to be addressed first. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/bigsmp_32.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -43,14 +43,6 @@ static void bigsmp_setup_apic_routing(vo nr_ioapics); } =20 -static int bigsmp_cpu_present_to_apicid(int mps_cpu) -{ - if (mps_cpu < nr_cpu_ids) - return (int) per_cpu(x86_cpu_to_apicid, mps_cpu); - - return BAD_APICID; -} - static void bigsmp_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask= _t *retmap) { /* For clustered we don't have a good way to do this yet - hack */ @@ -119,7 +111,7 @@ static struct apic apic_bigsmp __ro_afte .init_apic_ldr =3D bigsmp_init_apic_ldr, .ioapic_phys_id_map =3D bigsmp_ioapic_phys_id_map, .setup_apic_routing =3D bigsmp_setup_apic_routing, - .cpu_present_to_apicid =3D bigsmp_cpu_present_to_apicid, + .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .apicid_to_cpu_present =3D physid_set_mask_of_physid, .phys_pkg_id =3D bigsmp_phys_pkg_id, From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC19BC0015E for ; Mon, 17 Jul 2023 23:16:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231465AbjGQXQv (ORCPT ); Mon, 17 Jul 2023 19:16:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231455AbjGQXQq (ORCPT ); Mon, 17 Jul 2023 19:16:46 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D303D8E for ; Mon, 17 Jul 2023 16:16:00 -0700 (PDT) Message-ID: <20230717223224.682027281@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635716; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=2GgBvlBwBjHxdRJmr9WUDSqYy6anA/COSWCNzKyoDG8=; b=2/Vn8u2+5/SRnXwpXbVScxhgRhTVpcYBF1bp0Qm/eorg2zZ10PWEtPP7zC1kuoeejFt4ck uHW0cDhYA4ZtpVzipDMw9xmyzIbhck5hWat7PhMZM1CMJXcex/4NkY9R/i8xmzLRdLIZlJ wJIk4Yw6zruuwmQxGOZXV2g0EsXQuZgab6O8CHg30q4ycyxMZopKsi9kejHqFHq9j98xjz /WPUnck8R3NVqQCVA70OlPpYwjzVhXXo7r+vPqb+orP4GlUq2RvEPTX7tBG98vwDMaZuKQ FDeUMaGnmqCWtwAnoZcVKKGYzShPHF+Xr71OQ0E2R3i9OH2ffqQPsClypsVbIw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635716; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=2GgBvlBwBjHxdRJmr9WUDSqYy6anA/COSWCNzKyoDG8=; b=+45cMtNHe2gF+qi3ndt0ELLn3sJ2cayrCo/T3BcL/O6wM4XHQFN8OmK1fLJBTkOsNBlECf Tc+s0g0pYK1zSgCQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 27/58] x86/apic: Nuke empty init_apic_ldr() callbacks References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:16 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" apic::init_apic_ldr() is only invoked when the APIC is initialized. So there is really no point in having: - Default empty callbacks all over the place - Two implementations of the actual LDR init function where one is just unreadable gunk but does exactly the same as the other. Make the apic::init_apic_ldr() invocation conditional, remove the empty callbacks and consolidate the two implementation into one. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 2 -- arch/x86/kernel/apic/apic.c | 7 +++++-- arch/x86/kernel/apic/apic_common.c | 16 ++++++++++++++++ arch/x86/kernel/apic/apic_flat_64.c | 32 +-----------------------------= -- arch/x86/kernel/apic/apic_noop.c | 2 -- arch/x86/kernel/apic/apic_numachip.c | 2 -- arch/x86/kernel/apic/bigsmp_32.c | 9 --------- arch/x86/kernel/apic/local.h | 5 ++--- arch/x86/kernel/apic/probe_32.c | 15 --------------- arch/x86/kernel/apic/x2apic_phys.c | 5 ----- arch/x86/kernel/apic/x2apic_uv_x.c | 5 ----- arch/x86/xen/apic.c | 1 - 12 files changed, 24 insertions(+), 77 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -445,8 +445,6 @@ extern void generic_bigsmp_probe(void); =20 #include =20 -#define APIC_DFR_VALUE (APIC_DFR_FLAT) - extern struct apic apic_noop; =20 static inline unsigned int read_apic_id(void) --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1578,9 +1578,12 @@ static void setup_local_APIC(void) /* * Intel recommends to set DFR, LDR and TPR before enabling * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel - * document number 292116). So here it goes... + * document number 292116). + * + * Except for APICs which operate in physical destination mode. */ - apic->init_apic_ldr(); + if (apic->init_apic_ldr) + apic->init_apic_ldr(); =20 /* * Set Task Priority to 'accept all except vectors 0-31'. An APIC --- a/arch/x86/kernel/apic/apic_common.c +++ b/arch/x86/kernel/apic/apic_common.c @@ -6,6 +6,8 @@ #include #include =20 +#include "local.h" + u32 apic_default_calc_apicid(unsigned int cpu) { return per_cpu(x86_cpu_to_apicid, cpu); @@ -39,3 +41,17 @@ int default_apic_id_valid(u32 apicid) { return (apicid < 255); } + +/* + * Set up the logical destination ID when the APIC operates in logical + * destination mode. + */ +void default_init_apic_ldr(void) +{ + unsigned long val; + + apic_write(APIC_DFR, APIC_DFR_FLAT); + val =3D apic_read(APIC_LDR) & ~APIC_LDR_MASK; + val |=3D SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); + apic_write(APIC_LDR, val); +} --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -28,26 +28,6 @@ static int flat_acpi_madt_oem_check(char return 1; } =20 -/* - * Set up the logical destination ID. - * - * Intel recommends to set DFR, LDR and TPR before enabling - * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel - * document number 292116). So here it goes... - */ -void flat_init_apic_ldr(void) -{ - unsigned long val; - unsigned long num, id; - - num =3D smp_processor_id(); - id =3D 1UL << num; - apic_write(APIC_DFR, APIC_DFR_FLAT); - val =3D apic_read(APIC_LDR) & ~APIC_LDR_MASK; - val |=3D SET_APIC_LOGICAL_ID(id); - apic_write(APIC_LDR, val); -} - static void _flat_send_IPI_mask(unsigned long mask, int vector) { unsigned long flags; @@ -119,7 +99,7 @@ static struct apic apic_flat __ro_after_ .disable_esr =3D 0, =20 .check_apicid_used =3D NULL, - .init_apic_ldr =3D flat_init_apic_ldr, + .init_apic_ldr =3D default_init_apic_ldr, .ioapic_phys_id_map =3D NULL, .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, @@ -175,15 +155,6 @@ static int physflat_acpi_madt_oem_check( return 0; } =20 -static void physflat_init_apic_ldr(void) -{ - /* - * LDR and DFR are not involved in physflat mode, rather: - * "In physical destination mode, the destination processor is - * specified by its local APIC ID [...]." (Intel SDM, 10.6.2.1) - */ -} - static int physflat_probe(void) { if (apic =3D=3D &apic_physflat || num_possible_cpus() > 8 || @@ -207,7 +178,6 @@ static struct apic apic_physflat __ro_af .disable_esr =3D 0, =20 .check_apicid_used =3D NULL, - .init_apic_ldr =3D physflat_init_apic_ldr, .ioapic_phys_id_map =3D NULL, .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -14,7 +14,6 @@ =20 #include =20 -static void noop_init_apic_ldr(void) { } static void noop_send_IPI(int cpu, int vector) { } static void noop_send_IPI_mask(const struct cpumask *cpumask, int vector) = { } static void noop_send_IPI_mask_allbutself(const struct cpumask *cpumask, i= nt vector) { } @@ -94,7 +93,6 @@ struct apic apic_noop __ro_after_init =3D .disable_esr =3D 0, =20 .check_apicid_used =3D default_check_apicid_used, - .init_apic_ldr =3D noop_init_apic_ldr, .ioapic_phys_id_map =3D default_ioapic_phys_id_map, .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -252,7 +252,6 @@ static const struct apic apic_numachip1 .disable_esr =3D 0, =20 .check_apicid_used =3D NULL, - .init_apic_ldr =3D flat_init_apic_ldr, .ioapic_phys_id_map =3D NULL, .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, @@ -297,7 +296,6 @@ static const struct apic apic_numachip2 .disable_esr =3D 0, =20 .check_apicid_used =3D NULL, - .init_apic_ldr =3D flat_init_apic_ldr, .ioapic_phys_id_map =3D NULL, .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -28,14 +28,6 @@ static bool bigsmp_check_apicid_used(phy return false; } =20 -/* - * bigsmp enables physical destination mode - * and doesn't use LDR and DFR - */ -static void bigsmp_init_apic_ldr(void) -{ -} - static void bigsmp_setup_apic_routing(void) { printk(KERN_INFO @@ -108,7 +100,6 @@ static struct apic apic_bigsmp __ro_afte .disable_esr =3D 1, =20 .check_apicid_used =3D bigsmp_check_apicid_used, - .init_apic_ldr =3D bigsmp_init_apic_ldr, .ioapic_phys_id_map =3D bigsmp_ioapic_phys_id_map, .setup_apic_routing =3D bigsmp_setup_apic_routing, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -13,9 +13,6 @@ #include #include =20 -/* APIC flat 64 */ -void flat_init_apic_ldr(void); - /* X2APIC */ int x2apic_apic_id_valid(u32 apicid); int x2apic_apic_id_registered(void); @@ -46,6 +43,8 @@ static inline unsigned int __prepare_ICR return icr; } =20 +void default_init_apic_ldr(void); + void __default_send_IPI_shortcut(unsigned int shortcut, int vector); =20 /* --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -32,21 +32,6 @@ static int default_apic_id_registered(vo return physid_isset(read_apic_id(), phys_cpu_present_map); } =20 -/* - * Set up the logical destination ID. Intel recommends to set DFR, LDR and - * TPR before enabling an APIC. See e.g. "AP-388 82489DX User's Manual" - * (Intel document number 292116). - */ -static void default_init_apic_ldr(void) -{ - unsigned long val; - - apic_write(APIC_DFR, APIC_DFR_VALUE); - val =3D apic_read(APIC_LDR) & ~APIC_LDR_MASK; - val |=3D SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); - apic_write(APIC_LDR, val); -} - static int default_phys_pkg_id(int cpuid_apic, int index_msb) { return cpuid_apic >> index_msb; --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -91,10 +91,6 @@ static void x2apic_send_IPI_all(int vect __x2apic_send_IPI_shorthand(vector, APIC_DEST_ALLINC); } =20 -static void init_x2apic_ldr(void) -{ -} - static int x2apic_phys_probe(void) { if (!x2apic_mode) @@ -169,7 +165,6 @@ static struct apic apic_x2apic_phys __ro .disable_esr =3D 0, =20 .check_apicid_used =3D NULL, - .init_apic_ldr =3D init_x2apic_ldr, .ioapic_phys_id_map =3D NULL, .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -788,10 +788,6 @@ static int uv_apic_id_registered(void) return 1; } =20 -static void uv_init_apic_ldr(void) -{ -} - static u32 apic_uv_calc_apicid(unsigned int cpu) { return apic_default_calc_apicid(cpu); @@ -841,7 +837,6 @@ static struct apic apic_x2apic_uv_x __ro .disable_esr =3D 0, =20 .check_apicid_used =3D NULL, - .init_apic_ldr =3D uv_init_apic_ldr, .ioapic_phys_id_map =3D NULL, .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -149,7 +149,6 @@ static struct apic xen_pv_apic =3D { .disable_esr =3D 0, =20 .check_apicid_used =3D default_check_apicid_used, /* Used on 32-bit */ - .init_apic_ldr =3D xen_noop, /* setup_local_APIC calls it */ .ioapic_phys_id_map =3D default_ioapic_phys_id_map, /* Used on 32-bit */ .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D xen_cpu_present_to_apicid, From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1768C0015E for ; Mon, 17 Jul 2023 23:23:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231562AbjGQXXa (ORCPT ); Mon, 17 Jul 2023 19:23:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231656AbjGQXXF (ORCPT ); Mon, 17 Jul 2023 19:23:05 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBD1B1BE for ; Mon, 17 Jul 2023 16:22:27 -0700 (PDT) Message-ID: <20230717223224.743460570@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635718; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=06ExdfZEOQwXniOfctX3V6uycMvnEsSlc1/tN9llaWA=; b=Y5TIsgm3UB4GQd4xPU3Jxtpjd+P64bIN4L0cCuI5aJFNUojUyHpraiU8nzdHWhGjxrk/fA dqYip7WtPPV+lz7RLKaOEkv1AmKvQSiTF4x2YVPzo3NHtOgXfmPA6LtY7vJuBr0H49HSqn d0PsZNGJ3OPbl08OauxkypDlGgJNWeg5JzN3NiYW3jJVSkYEcTv/ExQ7kGm3WC2mkaFlYY p+tS+wnw/cObQ7A2eMAt4YN8YUDi4DNryJK+cukhHck49ND6U4ZCKKd3eItKwZXCIcdIf9 kYc+ll9vu9vupoWFA0b19VCfAKgTVzthUmo5daBiKABbSD+2dg8z7XEob/GEQQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635718; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=06ExdfZEOQwXniOfctX3V6uycMvnEsSlc1/tN9llaWA=; b=yAf99dYfM9/hctShZts9tsNqrTREmcL4MAvMxrxTJxfe1cwm4n/izQxAEGGiXl2Red32a6 vLH1fUZBasT7FeCA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 28/58] x86/apic: Nuke apic::apicid_to_cpu_present() References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:17 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This is only used on 32bit and is a wrapper around physid_set_mask_of_physid() in all 32bit APIC drivers. Remove the callback and use physid_set_mask_of_physid() in the code directly, Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 1 - arch/x86/kernel/apic/apic_flat_64.c | 2 -- arch/x86/kernel/apic/apic_noop.c | 1 - arch/x86/kernel/apic/apic_numachip.c | 2 -- arch/x86/kernel/apic/bigsmp_32.c | 1 - arch/x86/kernel/apic/io_apic.c | 11 +++++------ arch/x86/kernel/apic/probe_32.c | 1 - arch/x86/kernel/apic/x2apic_cluster.c | 1 - arch/x86/kernel/apic/x2apic_phys.c | 1 - arch/x86/kernel/apic/x2apic_uv_x.c | 1 - arch/x86/xen/apic.c | 1 - 11 files changed, 5 insertions(+), 18 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -304,7 +304,6 @@ struct apic { void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap= ); void (*setup_apic_routing)(void); int (*cpu_present_to_apicid)(int mps_cpu); - void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); int (*phys_pkg_id)(int cpuid_apic, int index_msb); =20 u32 (*get_apic_id)(unsigned long x); --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -103,7 +103,6 @@ static struct apic apic_flat __ro_after_ .ioapic_phys_id_map =3D NULL, .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - .apicid_to_cpu_present =3D NULL, .phys_pkg_id =3D flat_phys_pkg_id, =20 .get_apic_id =3D flat_get_apic_id, @@ -181,7 +180,6 @@ static struct apic apic_physflat __ro_af .ioapic_phys_id_map =3D NULL, .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - .apicid_to_cpu_present =3D NULL, .phys_pkg_id =3D flat_phys_pkg_id, =20 .get_apic_id =3D flat_get_apic_id, --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -96,7 +96,6 @@ struct apic apic_noop __ro_after_init =3D .ioapic_phys_id_map =3D default_ioapic_phys_id_map, .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - .apicid_to_cpu_present =3D physid_set_mask_of_physid, =20 .phys_pkg_id =3D noop_phys_pkg_id, =20 --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -255,7 +255,6 @@ static const struct apic apic_numachip1 .ioapic_phys_id_map =3D NULL, .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - .apicid_to_cpu_present =3D NULL, .phys_pkg_id =3D numachip_phys_pkg_id, =20 .get_apic_id =3D numachip1_get_apic_id, @@ -299,7 +298,6 @@ static const struct apic apic_numachip2 .ioapic_phys_id_map =3D NULL, .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - .apicid_to_cpu_present =3D NULL, .phys_pkg_id =3D numachip_phys_pkg_id, =20 .get_apic_id =3D numachip2_get_apic_id, --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -103,7 +103,6 @@ static struct apic apic_bigsmp __ro_afte .ioapic_phys_id_map =3D bigsmp_ioapic_phys_id_map, .setup_apic_routing =3D bigsmp_setup_apic_routing, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - .apicid_to_cpu_present =3D physid_set_mask_of_physid, .phys_pkg_id =3D bigsmp_phys_pkg_id, =20 .get_apic_id =3D bigsmp_get_apic_id, --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1512,11 +1512,10 @@ void __init setup_ioapic_ids_from_mpc_no ioapics[ioapic_idx].mp_config.apicid =3D i; } else { physid_mask_t tmp; - apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx), - &tmp); - apic_printk(APIC_VERBOSE, "Setting %d in the " - "phys_id_present_map\n", - mpc_ioapic_id(ioapic_idx)); + + physid_set_mask_of_physid(mpc_ioapic_id(ioapic_idx), &tmp); + apic_printk(APIC_VERBOSE, "Setting %d in the phys_id_present_map\n", + mpc_ioapic_id(ioapic_idx)); physids_or(phys_id_present_map, phys_id_present_map, tmp); } =20 @@ -2546,7 +2545,7 @@ static int io_apic_get_unique_id(int ioa apic_id =3D i; } =20 - apic->apicid_to_cpu_present(apic_id, &tmp); + physid_set_mask_of_physid(apic_id, &tmp); physids_or(apic_id_map, apic_id_map, tmp); =20 if (reg_00.bits.ID !=3D apic_id) { --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -60,7 +60,6 @@ static struct apic apic_default __ro_aft .ioapic_phys_id_map =3D default_ioapic_phys_id_map, .setup_apic_routing =3D setup_apic_flat_routing, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - .apicid_to_cpu_present =3D physid_set_mask_of_physid, .phys_pkg_id =3D default_phys_pkg_id, =20 .get_apic_id =3D default_get_apic_id, --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -249,7 +249,6 @@ static struct apic apic_x2apic_cluster _ .ioapic_phys_id_map =3D NULL, .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - .apicid_to_cpu_present =3D NULL, .phys_pkg_id =3D x2apic_phys_pkg_id, =20 .get_apic_id =3D x2apic_get_apic_id, --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -168,7 +168,6 @@ static struct apic apic_x2apic_phys __ro .ioapic_phys_id_map =3D NULL, .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - .apicid_to_cpu_present =3D NULL, .phys_pkg_id =3D x2apic_phys_pkg_id, =20 .get_apic_id =3D x2apic_get_apic_id, --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -840,7 +840,6 @@ static struct apic apic_x2apic_uv_x __ro .ioapic_phys_id_map =3D NULL, .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, - .apicid_to_cpu_present =3D NULL, .phys_pkg_id =3D uv_phys_pkg_id, =20 .get_apic_id =3D x2apic_get_apic_id, --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -152,7 +152,6 @@ static struct apic xen_pv_apic =3D { .ioapic_phys_id_map =3D default_ioapic_phys_id_map, /* Used on 32-bit */ .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D xen_cpu_present_to_apicid, - .apicid_to_cpu_present =3D physid_set_mask_of_physid, /* Used on 32-bit = */ .phys_pkg_id =3D xen_phys_pkg_id, /* detect_ht */ =20 .get_apic_id =3D xen_get_apic_id, From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98C32EB64DC for ; Mon, 17 Jul 2023 23:18:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231585AbjGQXSU (ORCPT ); Mon, 17 Jul 2023 19:18:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231508AbjGQXSR (ORCPT ); Mon, 17 Jul 2023 19:18:17 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3774F172E for ; Mon, 17 Jul 2023 16:17:27 -0700 (PDT) Message-ID: <20230717223224.801556578@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635720; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=1fi5EfwywiW+JxLoqkaaJxdnnrJM3lL64yD5t1OC3bQ=; b=BADiRAFTkC6r+a6gyybktPa+HfMXroxjn94l+bXbqaw3hq9umOUNeI+hfDtflvabJCgkd5 QafHXvflNvNJy/0aP7T1om1tokKWKy0kWeS+wIa6a4G5IGSmufLN9xvcqtTEjwOi5+MXx3 8GezOJsDcGML0gR+CwAMJGMfWTiy3rS/rOqo0rJkKJerU87KohFbetomtjwF9muWhZpVNZ RESKOnkG/WXU0hxG3iczaPFjdgcOdTFWoH2KDBpEX4wf1GuCXUvbJphNnlnb2y2YfXeuTK uvQ6KOXl/URhjav4FU825U9eo8rowRqpyoA8+YJI3k64zJF5s4YiDqPk1NdtLQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635720; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=1fi5EfwywiW+JxLoqkaaJxdnnrJM3lL64yD5t1OC3bQ=; b=gEMTuYy1EBhlm7p9f9Q1LKgSaDPFxw28WPcOb9fBTWlqY6cWG1255arVxNdYPX4Kr9ZFwy ZCcvTKnNXjsBQoCw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 29/58] x86/ioapic/32: Decrapify phys_id_present_map operation References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:19 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The operation to set the IOAPIC ID in phys_id_present_map is as convoluted as it can be. 1) Allocate a bitmap of 32byte size on the stack 2) Zero the bitmap and set the IOAPIC ID bit 3) Or the temporary bitmap over phys_id_present_map The same functionality can be achieved by setting the IOAPIC ID bit directly in the phys_id_present_map. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/io_apic.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1511,12 +1511,9 @@ void __init setup_ioapic_ids_from_mpc_no physid_set(i, phys_id_present_map); ioapics[ioapic_idx].mp_config.apicid =3D i; } else { - physid_mask_t tmp; - - physid_set_mask_of_physid(mpc_ioapic_id(ioapic_idx), &tmp); apic_printk(APIC_VERBOSE, "Setting %d in the phys_id_present_map\n", mpc_ioapic_id(ioapic_idx)); - physids_or(phys_id_present_map, phys_id_present_map, tmp); + physid_set(mpc_ioapic_id(ioapic_idx), phys_id_present_map); } =20 /* From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B5FEC0015E for ; Mon, 17 Jul 2023 23:17:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231474AbjGQXRC (ORCPT ); Mon, 17 Jul 2023 19:17:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229939AbjGQXRA (ORCPT ); Mon, 17 Jul 2023 19:17:00 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73EDE170C for ; Mon, 17 Jul 2023 16:16:18 -0700 (PDT) Message-ID: <20230717223224.862165651@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635721; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=iXqYtXrlduXImtg8HbwwswgIFt4N10phn1SThuuoL6E=; b=0dN0OrCKNxWlr5OUQVlboRcw+6j9f+o+Z+6J+4QtQ3GKT2Cgj0hsFEfQrxu+xACuAcS61S jrW2X46+nGZAH1ez5UXmb3euZvH09YDs0h86ztj5vWsD+PglInLBG1bUn7UVP0xq17fjUs Ppd2Qr6TZg4jMEIB57MOqiQW6Uk8yKl7eH5movcXVeGxa8G/s5HjeU/NAncBTQCpSqcsay wMm9dnBJNheAOXFoRWfXQoPJ0cR2M5R94OHwTqm5yE+f2OETSt6EprXQyDhM7AWbxSD253 e1hH4ajwe8DVFBURr+tT2Qt3BWVDfLZ6MmhPlgXhI07OeKtlBmi+GywO4FC4dw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635721; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=iXqYtXrlduXImtg8HbwwswgIFt4N10phn1SThuuoL6E=; b=KTUaoc8lM7LP9M80N+0b8tgyPboz6lk8Eo7zzKzV6CRIrHbLn3ug4RN3UiRrj39yEbUU4U 38HzOpfLbVM0ZzAw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 30/58] x86/apic: Mop up *setup_apic_routing() References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:21 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" default_setup_apic_routing() is a complete misnomer. On 64bit it does the actual APIC probing and on 32bit it is used to force select the bigsmp APIC and to emit a redundant message in the apic::setup_apic_routing() callback. Rename the 64bit and 32bit function so they reflect what they are doing and remove the useless APIC callback. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 10 ++++------ arch/x86/kernel/apic/apic.c | 4 +++- arch/x86/kernel/apic/apic_flat_64.c | 2 -- arch/x86/kernel/apic/apic_noop.c | 1 - arch/x86/kernel/apic/apic_numachip.c | 2 -- arch/x86/kernel/apic/bigsmp_32.c | 8 -------- arch/x86/kernel/apic/local.h | 2 ++ arch/x86/kernel/apic/probe_32.c | 17 ++--------------- arch/x86/kernel/apic/probe_64.c | 2 +- arch/x86/kernel/apic/x2apic_cluster.c | 1 - arch/x86/kernel/apic/x2apic_phys.c | 1 - arch/x86/kernel/apic/x2apic_uv_x.c | 1 - arch/x86/kernel/setup.c | 2 +- arch/x86/xen/apic.c | 1 - 14 files changed, 13 insertions(+), 41 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -40,11 +40,9 @@ =20 =20 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) -extern void generic_apic_probe(void); +extern void x86_32_probe_apic(void); #else -static inline void generic_apic_probe(void) -{ -} +static inline void x86_32_probe_apic(void) { } #endif =20 #ifdef CONFIG_X86_LOCAL_APIC @@ -302,7 +300,6 @@ struct apic { bool (*check_apicid_used)(physid_mask_t *map, int apicid); void (*init_apic_ldr)(void); void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap= ); - void (*setup_apic_routing)(void); int (*cpu_present_to_apicid)(int mps_cpu); int (*phys_pkg_id)(int cpuid_apic, int index_msb); =20 @@ -457,12 +454,13 @@ static inline unsigned int read_apic_id( typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip); extern void acpi_wake_cpu_handler_update(wakeup_cpu_handler handler); extern int default_acpi_madt_oem_check(char *, char *); +extern void x86_64_probe_apic(void); #else static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0= ; } +static inline void x86_64_probe_apic(void) { } #endif =20 extern int default_apic_id_valid(u32 apicid); -extern void default_setup_apic_routing(void); =20 extern u32 apic_default_calc_apicid(unsigned int cpu); extern u32 apic_flat_calc_apicid(unsigned int cpu); --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1419,7 +1419,9 @@ void __init apic_intr_mode_init(void) break; } =20 - default_setup_apic_routing(); + x86_64_probe_apic(); + + x86_32_install_bigsmp(); =20 if (x86_platform.apic_post_init) x86_platform.apic_post_init(); --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -101,7 +101,6 @@ static struct apic apic_flat __ro_after_ .check_apicid_used =3D NULL, .init_apic_ldr =3D default_init_apic_ldr, .ioapic_phys_id_map =3D NULL, - .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D flat_phys_pkg_id, =20 @@ -178,7 +177,6 @@ static struct apic apic_physflat __ro_af =20 .check_apicid_used =3D NULL, .ioapic_phys_id_map =3D NULL, - .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D flat_phys_pkg_id, =20 --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -94,7 +94,6 @@ struct apic apic_noop __ro_after_init =3D =20 .check_apicid_used =3D default_check_apicid_used, .ioapic_phys_id_map =3D default_ioapic_phys_id_map, - .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, =20 .phys_pkg_id =3D noop_phys_pkg_id, --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -253,7 +253,6 @@ static const struct apic apic_numachip1 =20 .check_apicid_used =3D NULL, .ioapic_phys_id_map =3D NULL, - .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D numachip_phys_pkg_id, =20 @@ -296,7 +295,6 @@ static const struct apic apic_numachip2 =20 .check_apicid_used =3D NULL, .ioapic_phys_id_map =3D NULL, - .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D numachip_phys_pkg_id, =20 --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -28,13 +28,6 @@ static bool bigsmp_check_apicid_used(phy return false; } =20 -static void bigsmp_setup_apic_routing(void) -{ - printk(KERN_INFO - "Enabling APIC mode: Physflat. Using %d I/O APICs\n", - nr_ioapics); -} - static void bigsmp_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask= _t *retmap) { /* For clustered we don't have a good way to do this yet - hack */ @@ -101,7 +94,6 @@ static struct apic apic_bigsmp __ro_afte =20 .check_apicid_used =3D bigsmp_check_apicid_used, .ioapic_phys_id_map =3D bigsmp_ioapic_phys_id_map, - .setup_apic_routing =3D bigsmp_setup_apic_routing, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D bigsmp_phys_pkg_id, =20 --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -66,8 +66,10 @@ void default_send_IPI_mask_sequence_logi void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask, = int vector); void default_send_IPI_mask_logical(const struct cpumask *mask, int vector); void x86_32_probe_bigsmp_early(void); +void x86_32_install_bigsmp(void); #else static inline void x86_32_probe_bigsmp_early(void) { } +static inline void x86_32_install_bigsmp(void) { } #endif =20 #ifdef CONFIG_X86_BIGSMP --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -18,15 +18,6 @@ =20 #include "local.h" =20 -static void setup_apic_flat_routing(void) -{ -#ifdef CONFIG_X86_IO_APIC - printk(KERN_INFO - "Enabling APIC mode: Flat. Using %d I/O APICs\n", - nr_ioapics); -#endif -} - static int default_apic_id_registered(void) { return physid_isset(read_apic_id(), phys_cpu_present_map); @@ -58,7 +49,6 @@ static struct apic apic_default __ro_aft .check_apicid_used =3D default_check_apicid_used, .init_apic_ldr =3D default_init_apic_ldr, .ioapic_phys_id_map =3D default_ioapic_phys_id_map, - .setup_apic_routing =3D setup_apic_flat_routing, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D default_phys_pkg_id, =20 @@ -132,16 +122,13 @@ void __init x86_32_probe_bigsmp_early(vo set_nr_cpu_ids(8); } =20 -void __init default_setup_apic_routing(void) +void __init x86_32_install_bigsmp(void) { if (nr_cpu_ids >=3D 8 && !xen_pv_domain()) apic_bigsmp_force(); - - if (apic->setup_apic_routing) - apic->setup_apic_routing(); } =20 -void __init generic_apic_probe(void) +void __init x86_32_probe_apic(void) { if (!cmdline_apic) { struct apic **drv; --- a/arch/x86/kernel/apic/probe_64.c +++ b/arch/x86/kernel/apic/probe_64.c @@ -14,7 +14,7 @@ #include "local.h" =20 /* Select the appropriate APIC driver */ -void __init default_setup_apic_routing(void) +void __init x86_64_probe_apic(void) { struct apic **drv; =20 --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -247,7 +247,6 @@ static struct apic apic_x2apic_cluster _ .check_apicid_used =3D NULL, .init_apic_ldr =3D init_x2apic_ldr, .ioapic_phys_id_map =3D NULL, - .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D x2apic_phys_pkg_id, =20 --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -166,7 +166,6 @@ static struct apic apic_x2apic_phys __ro =20 .check_apicid_used =3D NULL, .ioapic_phys_id_map =3D NULL, - .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D x2apic_phys_pkg_id, =20 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -838,7 +838,6 @@ static struct apic apic_x2apic_uv_x __ro =20 .check_apicid_used =3D NULL, .ioapic_phys_id_map =3D NULL, - .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D uv_phys_pkg_id, =20 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1253,7 +1253,7 @@ void __init setup_arch(char **cmdline_p) =20 map_vsyscall(); =20 - generic_apic_probe(); + x86_32_probe_apic(); =20 early_quirks(); =20 --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -150,7 +150,6 @@ static struct apic xen_pv_apic =3D { =20 .check_apicid_used =3D default_check_apicid_used, /* Used on 32-bit */ .ioapic_phys_id_map =3D default_ioapic_phys_id_map, /* Used on 32-bit */ - .setup_apic_routing =3D NULL, .cpu_present_to_apicid =3D xen_cpu_present_to_apicid, .phys_pkg_id =3D xen_phys_pkg_id, /* detect_ht */ From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8902EB64DC for ; Mon, 17 Jul 2023 23:18:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231600AbjGQXSh (ORCPT ); Mon, 17 Jul 2023 19:18:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231575AbjGQXSf (ORCPT ); Mon, 17 Jul 2023 19:18:35 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4FE6A1BC9 for ; Mon, 17 Jul 2023 16:17:46 -0700 (PDT) Message-ID: <20230717223224.921638275@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635723; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=4cC4gJwVGzfQ/DDJivInGesMRSEte1u8rqPl+IK7uLs=; b=x2OwiovRgP3Ti374y+naWdxFUW4LO15taPJclPM/rV49rWk7ZvNoWMYQKUo2dfpkIBc5wa 7o0oztMttS41xHmMbeQreErz8nFomzmhNOsKyMHyoUp6PTsSMdNt8WdvIKFumkEXG1MSTX 0BtX8u07+2hqv3eKkRbDG0ZXPG6GjoA+b/f1c40Z7eH40+zz4HaIt3bCVdwGUvPP2OPGNm vvfpTqTV3Nil/bJXzHIfaxP/KwTLuHWg6kEG/rLUX1h6Hprv18kfr6W04tJx6qaj4y8j9j 8mKKL3GeokQgmJrcTCp2oj9sDSAH+P1qvKsYpJrFourR74mHFPUQ4AjvvT614g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635723; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=4cC4gJwVGzfQ/DDJivInGesMRSEte1u8rqPl+IK7uLs=; b=VjIPl7Vd9e666BaiIjoAdVALonqvd3jD8zMlLkTKt1bjHB7VdEktjxIJNnneJ3FI39ot23 pUP2cPXigIOWPWDQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 31/58] x86/apic: Mop up apic::apic_id_registered() References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:22 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Really not a hotpath and again no reason for having a gazillion of empty callbacks returning 1. Make it return bool and provide one shared implementation for the remaining users. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 2 +- arch/x86/kernel/apic/apic.c | 7 ++----- arch/x86/kernel/apic/apic_common.c | 5 +++++ arch/x86/kernel/apic/apic_flat_64.c | 14 ++------------ arch/x86/kernel/apic/apic_noop.c | 12 ------------ arch/x86/kernel/apic/apic_numachip.c | 7 ------- arch/x86/kernel/apic/bigsmp_32.c | 6 ------ arch/x86/kernel/apic/local.h | 3 ++- arch/x86/kernel/apic/probe_32.c | 5 ----- arch/x86/kernel/apic/x2apic_cluster.c | 1 - arch/x86/kernel/apic/x2apic_phys.c | 6 ------ arch/x86/kernel/apic/x2apic_uv_x.c | 6 ------ arch/x86/xen/apic.c | 6 ------ 13 files changed, 12 insertions(+), 68 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -295,7 +295,7 @@ struct apic { int (*probe)(void); int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); int (*apic_id_valid)(u32 apicid); - int (*apic_id_registered)(void); + bool (*apic_id_registered)(void); =20 bool (*check_apicid_used)(physid_mask_t *map, int apicid); void (*init_apic_ldr)(void); --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1571,11 +1571,8 @@ static void setup_local_APIC(void) apic_write(APIC_ESR, 0); } #endif - /* - * Double-check whether this APIC is really registered. - * This is meaningless in clustered apic mode, so we skip it. - */ - BUG_ON(!apic->apic_id_registered()); + /* Validate that the APIC is registered if required */ + BUG_ON(apic->apic_id_registered && !apic->apic_id_registered()); =20 /* * Intel recommends to set DFR, LDR and TPR before enabling --- a/arch/x86/kernel/apic/apic_common.c +++ b/arch/x86/kernel/apic/apic_common.c @@ -42,6 +42,11 @@ int default_apic_id_valid(u32 apicid) return (apicid < 255); } =20 +bool default_apic_id_registered(void) +{ + return physid_isset(read_apic_id(), phys_cpu_present_map); +} + /* * Set up the logical destination ID when the APIC operates in logical * destination mode. --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -66,16 +66,6 @@ static u32 set_apic_id(unsigned int id) return (id & 0xFF) << 24; } =20 -static unsigned int read_xapic_id(void) -{ - return flat_get_apic_id(apic_read(APIC_ID)); -} - -static int flat_apic_id_registered(void) -{ - return physid_isset(read_xapic_id(), phys_cpu_present_map); -} - static int flat_phys_pkg_id(int initial_apic_id, int index_msb) { return initial_apic_id >> index_msb; @@ -91,7 +81,7 @@ static struct apic apic_flat __ro_after_ .probe =3D flat_probe, .acpi_madt_oem_check =3D flat_acpi_madt_oem_check, .apic_id_valid =3D default_apic_id_valid, - .apic_id_registered =3D flat_apic_id_registered, + .apic_id_registered =3D default_apic_id_registered, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, .dest_mode_logical =3D true, @@ -168,7 +158,7 @@ static struct apic apic_physflat __ro_af .probe =3D physflat_probe, .acpi_madt_oem_check =3D physflat_acpi_madt_oem_check, .apic_id_valid =3D default_apic_id_valid, - .apic_id_registered =3D flat_apic_id_registered, + .apic_id_registered =3D default_apic_id_registered, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, .dest_mode_logical =3D false, --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -57,17 +57,6 @@ static int noop_probe(void) return 0; } =20 -static int noop_apic_id_registered(void) -{ - /* - * if we would be really "pedantic" - * we should pass read_apic_id() here - * but since NOOP suppose APIC ID =3D 0 - * lets save a few cycles - */ - return physid_isset(0, phys_cpu_present_map); -} - static u32 noop_apic_read(u32 reg) { WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_APIC) && !apic_is_disabled); @@ -85,7 +74,6 @@ struct apic apic_noop __ro_after_init =3D .acpi_madt_oem_check =3D NULL, =20 .apic_id_valid =3D default_apic_id_valid, - .apic_id_registered =3D noop_apic_id_registered, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, .dest_mode_logical =3D true, --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -62,11 +62,6 @@ static int numachip_apic_id_valid(u32 ap return 1; } =20 -static int numachip_apic_id_registered(void) -{ - return 1; -} - static int numachip_phys_pkg_id(int initial_apic_id, int index_msb) { return initial_apic_id >> index_msb; @@ -244,7 +239,6 @@ static const struct apic apic_numachip1 .probe =3D numachip1_probe, .acpi_madt_oem_check =3D numachip1_acpi_madt_oem_check, .apic_id_valid =3D numachip_apic_id_valid, - .apic_id_registered =3D numachip_apic_id_registered, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, .dest_mode_logical =3D false, @@ -286,7 +280,6 @@ static const struct apic apic_numachip2 .probe =3D numachip2_probe, .acpi_madt_oem_check =3D numachip2_acpi_madt_oem_check, .apic_id_valid =3D numachip_apic_id_valid, - .apic_id_registered =3D numachip_apic_id_registered, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, .dest_mode_logical =3D false, --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -18,11 +18,6 @@ static unsigned bigsmp_get_apic_id(unsig return (x >> 24) & 0xFF; } =20 -static int bigsmp_apic_id_registered(void) -{ - return 1; -} - static bool bigsmp_check_apicid_used(physid_mask_t *map, int apicid) { return false; @@ -85,7 +80,6 @@ static struct apic apic_bigsmp __ro_afte .name =3D "bigsmp", .probe =3D probe_bigsmp, .apic_id_valid =3D default_apic_id_valid, - .apic_id_registered =3D bigsmp_apic_id_registered, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, .dest_mode_logical =3D false, --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -15,7 +15,6 @@ =20 /* X2APIC */ int x2apic_apic_id_valid(u32 apicid); -int x2apic_apic_id_registered(void); void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int = dest); unsigned int x2apic_get_apic_id(unsigned long id); u32 x2apic_set_apic_id(unsigned int id); @@ -61,6 +60,8 @@ void default_send_IPI_allbutself(int vec void default_send_IPI_all(int vector); void default_send_IPI_self(int vector); =20 +bool default_apic_id_registered(void); + #ifdef CONFIG_X86_32 void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, in= t vector); void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask, = int vector); --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -18,11 +18,6 @@ =20 #include "local.h" =20 -static int default_apic_id_registered(void) -{ - return physid_isset(read_apic_id(), phys_cpu_present_map); -} - static int default_phys_pkg_id(int cpuid_apic, int index_msb) { return cpuid_apic >> index_msb; --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -237,7 +237,6 @@ static struct apic apic_x2apic_cluster _ .probe =3D x2apic_cluster_probe, .acpi_madt_oem_check =3D x2apic_acpi_madt_oem_check, .apic_id_valid =3D x2apic_apic_id_valid, - .apic_id_registered =3D x2apic_apic_id_registered, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, .dest_mode_logical =3D true, --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -111,11 +111,6 @@ int x2apic_apic_id_valid(u32 apicid) return 1; } =20 -int x2apic_apic_id_registered(void) -{ - return 1; -} - void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int = dest) { unsigned long cfg =3D __prepare_ICR(0, vector, dest); @@ -157,7 +152,6 @@ static struct apic apic_x2apic_phys __ro .probe =3D x2apic_phys_probe, .acpi_madt_oem_check =3D x2apic_acpi_madt_oem_check, .apic_id_valid =3D x2apic_apic_id_valid, - .apic_id_registered =3D x2apic_apic_id_registered, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, .dest_mode_logical =3D false, --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -783,11 +783,6 @@ static int uv_apic_id_valid(u32 apicid) return 1; } =20 -static int uv_apic_id_registered(void) -{ - return 1; -} - static u32 apic_uv_calc_apicid(unsigned int cpu) { return apic_default_calc_apicid(cpu); @@ -829,7 +824,6 @@ static struct apic apic_x2apic_uv_x __ro .probe =3D uv_probe, .acpi_madt_oem_check =3D uv_acpi_madt_oem_check, .apic_id_valid =3D uv_apic_id_valid, - .apic_id_registered =3D uv_apic_id_registered, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, .dest_mode_logical =3D false, --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -115,11 +115,6 @@ static int xen_id_always_valid(u32 apici return 1; } =20 -static int xen_id_always_registered(void) -{ - return 1; -} - static int xen_phys_pkg_id(int initial_apic_id, int index_msb) { return initial_apic_id >> index_msb; @@ -142,7 +137,6 @@ static struct apic xen_pv_apic =3D { .probe =3D xen_apic_probe_pv, .acpi_madt_oem_check =3D xen_madt_oem_check, .apic_id_valid =3D xen_id_always_valid, - .apic_id_registered =3D xen_id_always_registered, =20 /* .delivery_mode and .dest_mode_logical not used by XENPV */ From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BD39EB64DC for ; Mon, 17 Jul 2023 23:17:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231486AbjGQXRf (ORCPT ); Mon, 17 Jul 2023 19:17:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231476AbjGQXRd (ORCPT ); Mon, 17 Jul 2023 19:17:33 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3746219BD for ; Mon, 17 Jul 2023 16:16:47 -0700 (PDT) Message-ID: <20230717223224.979781880@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635724; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Wo3JBTvCQoJQW2SUExSVUktNUCEvCHCZ3yixiHATHeQ=; b=kN5D1+kpe82x5535R+8MyScBmHvOwIfhwiRY786PEZkMcCkCfmvxMhmrhrNL/wIhq9A/w8 sxMc2aLDqmFRTf6KGyBSI3iEOb6lZcgHpkmd6XHREin9xRYcZcCwOhUKcpsXm+cvrLQhSV O4s2LzxAAuaF+G9mEGOy6MHQHQNqN2Egde0OxWwWiCXzwov0iYBqUE9e86v/pmuBoGg534 +YBWXCRADo7zNUT2YFNMGDBFWw6k57F8AG8GMPLco3/2FYgNVMaMwRCxarsTbw1EoGpLCt ItHgfa4eHj1zwK/EVMpfHzGObP6SldEdJ/Jc8Zb5+o1DHpwuRBPhC/nRITHs3Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635724; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Wo3JBTvCQoJQW2SUExSVUktNUCEvCHCZ3yixiHATHeQ=; b=NiGBPNwoOpOk9xZPiJabG49K3ip5AkKaUYnzDrYFQgfCraB9Dk3FmtMJ08POqhhSYmIsJ2 vbxa40csLOvoQpBQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 32/58] x86/apic/ipi: Tidy up the code and fixup comments References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:24 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace the undecodable comment on top of the function, replace the space consuming zero content comments with useful ones and tidy up the implementation to prevent further eye bleed. Make __default_send_IPI_shortcut() static as it has no other users. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/ipi.c | 74 ++++++++++++++++++--------------------= ----- arch/x86/kernel/apic/local.h | 2 - 2 files changed, 32 insertions(+), 44 deletions(-) --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -108,68 +108,58 @@ static inline void __xapic_wait_icr_idle cpu_relax(); } =20 -void __default_send_IPI_shortcut(unsigned int shortcut, int vector) +/* + * This is safe against interruption because it only writes the lower 32 + * bits of the APIC_ICR register. The destination field is ignored for + * short hand IPIs. + * + * wait_icr_idle() + * write(ICR2, dest) + * NMI + * wait_icr_idle() + * write(ICR) + * wait_icr_idle() + * write(ICR) + * + * This function does not need to disable interrupts as there is no ICR2 + * interaction. The memory write is direct except when the machine is + * affected by the 11AP Pentium erratum, which turns the plain write into + * an XCHG operation. + */ +static void __default_send_IPI_shortcut(unsigned int shortcut, int vector) { /* - * Subtle. In the case of the 'never do double writes' workaround - * we have to lock out interrupts to be safe. As we don't care - * of the value read we use an atomic rmw access to avoid costly - * cli/sti. Otherwise we use an even cheaper single atomic write - * to the APIC. - */ - unsigned int cfg; - - /* - * Wait for idle. + * Wait for the previous ICR command to complete. Use + * safe_apic_wait_icr_idle() for the NMI vector as there have been + * issues where otherwise the system hangs when the panic CPU tries + * to stop the others before launching the kdump kernel. */ if (unlikely(vector =3D=3D NMI_VECTOR)) safe_apic_wait_icr_idle(); else __xapic_wait_icr_idle(); =20 - /* - * No need to touch the target chip field. Also the destination - * mode is ignored when a shorthand is used. - */ - cfg =3D __prepare_ICR(shortcut, vector, 0); - - /* - * Send the IPI. The write to APIC_ICR fires this off. - */ - native_apic_mem_write(APIC_ICR, cfg); + /* Destination field (ICR2) and the destination mode are ignored */ + native_apic_mem_write(APIC_ICR, __prepare_ICR(shortcut, vector, 0)); } =20 /* * This is used to send an IPI with no shorthand notation (the destination= is * specified in bits 56 to 63 of the ICR). */ -void __default_send_IPI_dest_field(unsigned int mask, int vector, unsigned= int dest) +void __default_send_IPI_dest_field(unsigned int dest_mask, int vector, + unsigned int dest_mode) { - unsigned long cfg; - - /* - * Wait for idle. - */ + /* See comment in __default_send_IPI_shortcut() */ if (unlikely(vector =3D=3D NMI_VECTOR)) safe_apic_wait_icr_idle(); else __xapic_wait_icr_idle(); =20 - /* - * prepare target chip field - */ - cfg =3D __prepare_ICR2(mask); - native_apic_mem_write(APIC_ICR2, cfg); - - /* - * program the ICR - */ - cfg =3D __prepare_ICR(0, vector, dest); - - /* - * Send the IPI. The write to APIC_ICR fires this off. - */ - native_apic_mem_write(APIC_ICR, cfg); + /* Set the IPI destination field in the ICR */ + native_apic_mem_write(APIC_ICR2, __prepare_ICR2(dest_mask)); + /* Send it with the proper destination mode */ + native_apic_mem_write(APIC_ICR, __prepare_ICR(0, vector, dest_mode)); } =20 void default_send_IPI_single_phys(int cpu, int vector) --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -44,8 +44,6 @@ static inline unsigned int __prepare_ICR =20 void default_init_apic_ldr(void); =20 -void __default_send_IPI_shortcut(unsigned int shortcut, int vector); - /* * This is used to send an IPI with no shorthand notation (the destination= is * specified in bits 56 to 63 of the ICR). From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77C2AEB64DC for ; Mon, 17 Jul 2023 23:18:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231509AbjGQXRy (ORCPT ); Mon, 17 Jul 2023 19:17:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37218 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231493AbjGQXRt (ORCPT ); Mon, 17 Jul 2023 19:17:49 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3123DE47 for ; Mon, 17 Jul 2023 16:16:55 -0700 (PDT) Message-ID: <20230717223225.037396803@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635726; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=NZd5xR1HtDqEMrh0B1hOXEFIalKc6LgOvxIkfivvEsc=; b=4WyKvRD03r1sRefT9H8XV9xm5jc3hbqy6kdcvvRCsdBOXA+DEyWI5yorwbxVLJlrkYY+hl aIM2Tn2ypEqXAcX8j3F5ucE/OF8osNHnG/kiZT3I564AoA7I2IQfW6junat62MBAgeHoVZ M+X6hW/bQnCvkYt8dBbtNG8SCVoA3i/xQ37Yisf9i1dHnypV0+ApTTLDWG7Q4qzvkjVTI6 s/ZkRRibovsdv+tEClU1L8H6V0/r0kRQfel4gcZQvVACXYR0fU4qVmKGIn4IacSekfrBV2 GcdToV5d7Zjnq8ouEspuDCm6g9dRx1Dt9aDv5uLQJ/0rQnp4ujEwZywBjHz1Gg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635726; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=NZd5xR1HtDqEMrh0B1hOXEFIalKc6LgOvxIkfivvEsc=; b=7eC6VKmrXMOHZhBfpJUG/fIFo2F27iX4w5tC0x6K1SjZ0JgoMJQemwCfx2TBWec7aOR2Cs wgTV8TJd36/IBdBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 33/58] x86/apic: Consolidate wait_icr_idle() implementations References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:25 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Two copies and also needlessly public. Move it into ipi.c so it can be inlined. Rename it to apic_mem_wait_icr_idle(). Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 1 - arch/x86/kernel/apic/apic.c | 6 ------ arch/x86/kernel/apic/apic_flat_64.c | 4 ++-- arch/x86/kernel/apic/bigsmp_32.c | 2 +- arch/x86/kernel/apic/ipi.c | 6 +++--- arch/x86/kernel/apic/local.h | 2 ++ arch/x86/kernel/apic/probe_32.c | 2 +- 7 files changed, 9 insertions(+), 14 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -98,7 +98,6 @@ static inline u32 native_apic_mem_read(u return *((volatile u32 *)(APIC_BASE + reg)); } =20 -extern void native_apic_wait_icr_idle(void); extern u32 native_safe_apic_wait_icr_idle(void); extern void native_apic_icr_write(u32 low, u32 id); extern u64 native_apic_icr_read(void); --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -240,12 +240,6 @@ static void __init apic_disable(void) apic =3D &apic_noop; } =20 -void native_apic_wait_icr_idle(void) -{ - while (apic_read(APIC_ICR) & APIC_ICR_BUSY) - cpu_relax(); -} - u32 native_safe_apic_wait_icr_idle(void) { u32 send_status; --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -111,7 +111,7 @@ static struct apic apic_flat __ro_after_ .eoi_write =3D native_apic_mem_write, .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, - .wait_icr_idle =3D native_apic_wait_icr_idle, + .wait_icr_idle =3D apic_mem_wait_icr_idle, .safe_wait_icr_idle =3D native_safe_apic_wait_icr_idle, }; =20 @@ -187,7 +187,7 @@ static struct apic apic_physflat __ro_af .eoi_write =3D native_apic_mem_write, .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, - .wait_icr_idle =3D native_apic_wait_icr_idle, + .wait_icr_idle =3D apic_mem_wait_icr_idle, .safe_wait_icr_idle =3D native_safe_apic_wait_icr_idle, }; =20 --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -108,7 +108,7 @@ static struct apic apic_bigsmp __ro_afte .eoi_write =3D native_apic_mem_write, .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, - .wait_icr_idle =3D native_apic_wait_icr_idle, + .wait_icr_idle =3D apic_mem_wait_icr_idle, .safe_wait_icr_idle =3D native_safe_apic_wait_icr_idle, }; =20 --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -102,7 +102,7 @@ static inline int __prepare_ICR2(unsigne return SET_XAPIC_DEST_FIELD(mask); } =20 -static inline void __xapic_wait_icr_idle(void) +void apic_mem_wait_icr_idle(void) { while (native_apic_mem_read(APIC_ICR) & APIC_ICR_BUSY) cpu_relax(); @@ -137,7 +137,7 @@ static void __default_send_IPI_shortcut( if (unlikely(vector =3D=3D NMI_VECTOR)) safe_apic_wait_icr_idle(); else - __xapic_wait_icr_idle(); + apic_mem_wait_icr_idle(); =20 /* Destination field (ICR2) and the destination mode are ignored */ native_apic_mem_write(APIC_ICR, __prepare_ICR(shortcut, vector, 0)); @@ -154,7 +154,7 @@ void __default_send_IPI_dest_field(unsig if (unlikely(vector =3D=3D NMI_VECTOR)) safe_apic_wait_icr_idle(); else - __xapic_wait_icr_idle(); + apic_mem_wait_icr_idle(); =20 /* Set the IPI destination field in the ICR */ native_apic_mem_write(APIC_ICR2, __prepare_ICR2(dest_mask)); --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -44,6 +44,8 @@ static inline unsigned int __prepare_ICR =20 void default_init_apic_ldr(void); =20 +void apic_mem_wait_icr_idle(void); + /* * This is used to send an IPI with no shorthand notation (the destination= is * specified in bits 56 to 63 of the ICR). --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -64,7 +64,7 @@ static struct apic apic_default __ro_aft .eoi_write =3D native_apic_mem_write, .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, - .wait_icr_idle =3D native_apic_wait_icr_idle, + .wait_icr_idle =3D apic_mem_wait_icr_idle, .safe_wait_icr_idle =3D native_safe_apic_wait_icr_idle, }; From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DED2BC0015E for ; Mon, 17 Jul 2023 23:17:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231503AbjGQXRx (ORCPT ); Mon, 17 Jul 2023 19:17:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229908AbjGQXRr (ORCPT ); Mon, 17 Jul 2023 19:17:47 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C5F81B5 for ; Mon, 17 Jul 2023 16:16:54 -0700 (PDT) Message-ID: <20230717223225.096117007@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635727; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=s4wbt5O4wQYbAqg6kKvi3oCsmzwopLD0vJC7pLObyok=; b=WFlLmFuOKyst8qV7bJZwbtJ0k7Yn8oD8fw4od6p4NQgCSt61dO4gmKqs0gtJf94ZoVdHUM UOnQF2IMM/Lj0meFsCIhl5AYiRFkRfEXOR3O1EJFfKVdjGQjtFV6QrWh+cf3M84bheSLmS vsUn9coI9NfSrELRw0sM26luIrDv97lhfnLlEf4OxRxlziceGJNDTCRwhlv8HIqgoG718x BbIB+SFNBwlJUtrkygFQ69F9Na/niXUEAYHv2e4SbwH1DICJs1KO1q5rXwfJdDw9wI8HZo ME71NSVafHXVOFrZV8N9fa5JJ2kfek41Mj+swXdz+hn0oRGQdx6GISlfRjQGnA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635727; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=s4wbt5O4wQYbAqg6kKvi3oCsmzwopLD0vJC7pLObyok=; b=W4GStyA8Y5TOj5iYcRe9Fem4XzOngNju0S+a8QFd8jTypeSd0UGziWSXrynn053oXRXxnT UwUdkSDk/RF2y/Dw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 34/58] x86/apic: Allow apic::wait_icr_idle() to be NULL References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:27 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Nuke more NOOP callbacks and make the invocation conditional. Will be replaced with a static call later. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 9 ++------- arch/x86/kernel/apic/apic_noop.c | 2 -- arch/x86/kernel/apic/apic_numachip.c | 7 ------- arch/x86/kernel/apic/x2apic_cluster.c | 1 - arch/x86/kernel/apic/x2apic_phys.c | 1 - arch/x86/kernel/apic/x2apic_uv_x.c | 1 - arch/x86/xen/apic.c | 5 ----- 7 files changed, 2 insertions(+), 24 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -206,12 +206,6 @@ static inline u32 native_apic_msr_read(u return (u32)msr; } =20 -static inline void native_x2apic_wait_icr_idle(void) -{ - /* no need to wait for icr idle in x2apic */ - return; -} - static inline u32 native_safe_x2apic_wait_icr_idle(void) { /* no need to wait for icr idle in x2apic */ @@ -376,7 +370,8 @@ static inline void apic_icr_write(u32 lo =20 static inline void apic_wait_icr_idle(void) { - apic->wait_icr_idle(); + if (apic->wait_icr_idle) + apic->wait_icr_idle(); } =20 static inline u32 safe_apic_wait_icr_idle(void) --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -20,7 +20,6 @@ static void noop_send_IPI_mask_allbutsel static void noop_send_IPI_allbutself(int vector) { } static void noop_send_IPI_all(int vector) { } static void noop_send_IPI_self(int vector) { } -static void noop_apic_wait_icr_idle(void) { } static void noop_apic_icr_write(u32 low, u32 id) { } =20 static int noop_wakeup_secondary_cpu(int apicid, unsigned long start_eip) @@ -105,6 +104,5 @@ struct apic apic_noop __ro_after_init =3D .eoi_write =3D noop_apic_write, .icr_read =3D noop_apic_icr_read, .icr_write =3D noop_apic_icr_write, - .wait_icr_idle =3D noop_apic_wait_icr_idle, .safe_wait_icr_idle =3D noop_safe_apic_wait_icr_idle, }; --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -223,11 +223,6 @@ static int numachip2_acpi_madt_oem_check return 1; } =20 -/* APIC IPIs are queued */ -static void numachip_apic_wait_icr_idle(void) -{ -} - /* APIC NMI IPIs are queued */ static u32 numachip_safe_apic_wait_icr_idle(void) { @@ -269,7 +264,6 @@ static const struct apic apic_numachip1 .eoi_write =3D native_apic_mem_write, .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, - .wait_icr_idle =3D numachip_apic_wait_icr_idle, .safe_wait_icr_idle =3D numachip_safe_apic_wait_icr_idle, }; =20 @@ -310,7 +304,6 @@ static const struct apic apic_numachip2 .eoi_write =3D native_apic_mem_write, .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, - .wait_icr_idle =3D numachip_apic_wait_icr_idle, .safe_wait_icr_idle =3D numachip_safe_apic_wait_icr_idle, }; =20 --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -266,7 +266,6 @@ static struct apic apic_x2apic_cluster _ .eoi_write =3D native_apic_msr_eoi_write, .icr_read =3D native_x2apic_icr_read, .icr_write =3D native_x2apic_icr_write, - .wait_icr_idle =3D native_x2apic_wait_icr_idle, .safe_wait_icr_idle =3D native_safe_x2apic_wait_icr_idle, }; =20 --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -180,7 +180,6 @@ static struct apic apic_x2apic_phys __ro .eoi_write =3D native_apic_msr_eoi_write, .icr_read =3D native_x2apic_icr_read, .icr_write =3D native_x2apic_icr_write, - .wait_icr_idle =3D native_x2apic_wait_icr_idle, .safe_wait_icr_idle =3D native_safe_x2apic_wait_icr_idle, }; =20 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -854,7 +854,6 @@ static struct apic apic_x2apic_uv_x __ro .eoi_write =3D native_apic_msr_eoi_write, .icr_read =3D native_x2apic_icr_read, .icr_write =3D native_x2apic_icr_write, - .wait_icr_idle =3D native_x2apic_wait_icr_idle, .safe_wait_icr_idle =3D native_safe_x2apic_wait_icr_idle, }; =20 --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -120,10 +120,6 @@ static int xen_phys_pkg_id(int initial_a return initial_apic_id >> index_msb; } =20 -static void xen_noop(void) -{ -} - static int xen_cpu_present_to_apicid(int cpu) { if (cpu_present(cpu)) @@ -165,7 +161,6 @@ static struct apic xen_pv_apic =3D { =20 .icr_read =3D xen_apic_icr_read, .icr_write =3D xen_apic_icr_write, - .wait_icr_idle =3D xen_noop, .safe_wait_icr_idle =3D xen_safe_apic_wait_icr_idle, }; From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B526C0015E for ; Mon, 17 Jul 2023 23:18:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231524AbjGQXST (ORCPT ); Mon, 17 Jul 2023 19:18:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231496AbjGQXSR (ORCPT ); Mon, 17 Jul 2023 19:18:17 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 309D7172A for ; Mon, 17 Jul 2023 16:17:23 -0700 (PDT) Message-ID: <20230717223225.156587052@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635729; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=X34cmveL8Me/hBK02cEFeh6qWm49lBpmvG/a5va6nks=; b=tcurvsLO1Z2sDkcBbbOc40m0poc21jDMJnyhGRIczV4CuIdgr4zYf33u+9rQutqDfIAofd TpIxSPWbW7z1GS2p9YahX+v7n+8hVXaqzJCkgP7OfblUwP/zlGxcnvnAHkDiRXuNpcPmKP /H2Cet1v8UouW9r2CehjOE56QyDMxrP53QqfTcIxD2oRqUdh2+RHbPl97y7lBvlG//QPCP 6exmGfO4U7YgaddsJOxT2hW1o66TWFvwLTeb9e3ViKChP9OmKMscjF2kSYfum+buLg8fQh cGw5siSoB+4bNNzY7UhmP/KPpSfASMaiM8WVauuOkDRpq6ei0uMNGgnEExh3lQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635729; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=X34cmveL8Me/hBK02cEFeh6qWm49lBpmvG/a5va6nks=; b=DpW4Ja5T5hp5CfsVhrAqaGt+QRZyT1Bdijwy2WeaP87aHEYHESUPwwXwPxf9AlxWGVO1+g ch7z4ToBXjLKBnCg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 35/58] x86/apic: Allow apic::safe_wait_icr_idle() to be NULL References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:28 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove tons of NOOP callbacks by making the invocation of safe_wait_icr_idle() conditional in the inline wrapper. Will be replaced by a static_call_cond() later. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 8 +------- arch/x86/kernel/apic/apic_noop.c | 6 ------ arch/x86/kernel/apic/apic_numachip.c | 8 -------- arch/x86/kernel/apic/x2apic_cluster.c | 1 - arch/x86/kernel/apic/x2apic_phys.c | 1 - arch/x86/kernel/apic/x2apic_uv_x.c | 1 - arch/x86/xen/apic.c | 6 ------ 7 files changed, 1 insertion(+), 30 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -206,12 +206,6 @@ static inline u32 native_apic_msr_read(u return (u32)msr; } =20 -static inline u32 native_safe_x2apic_wait_icr_idle(void) -{ - /* no need to wait for icr idle in x2apic */ - return 0; -} - static inline void native_x2apic_icr_write(u32 low, u32 id) { wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); @@ -376,7 +370,7 @@ static inline void apic_wait_icr_idle(vo =20 static inline u32 safe_apic_wait_icr_idle(void) { - return apic->safe_wait_icr_idle(); + return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0; } =20 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -27,11 +27,6 @@ static int noop_wakeup_secondary_cpu(int return -1; } =20 -static u32 noop_safe_apic_wait_icr_idle(void) -{ - return 0; -} - static u64 noop_apic_icr_read(void) { return 0; @@ -104,5 +99,4 @@ struct apic apic_noop __ro_after_init =3D .eoi_write =3D noop_apic_write, .icr_read =3D noop_apic_icr_read, .icr_write =3D noop_apic_icr_write, - .safe_wait_icr_idle =3D noop_safe_apic_wait_icr_idle, }; --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -223,12 +223,6 @@ static int numachip2_acpi_madt_oem_check return 1; } =20 -/* APIC NMI IPIs are queued */ -static u32 numachip_safe_apic_wait_icr_idle(void) -{ - return 0; -} - static const struct apic apic_numachip1 __refconst =3D { .name =3D "NumaConnect system", .probe =3D numachip1_probe, @@ -264,7 +258,6 @@ static const struct apic apic_numachip1 .eoi_write =3D native_apic_mem_write, .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, - .safe_wait_icr_idle =3D numachip_safe_apic_wait_icr_idle, }; =20 apic_driver(apic_numachip1); @@ -304,7 +297,6 @@ static const struct apic apic_numachip2 .eoi_write =3D native_apic_mem_write, .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, - .safe_wait_icr_idle =3D numachip_safe_apic_wait_icr_idle, }; =20 apic_driver(apic_numachip2); --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -266,7 +266,6 @@ static struct apic apic_x2apic_cluster _ .eoi_write =3D native_apic_msr_eoi_write, .icr_read =3D native_x2apic_icr_read, .icr_write =3D native_x2apic_icr_write, - .safe_wait_icr_idle =3D native_safe_x2apic_wait_icr_idle, }; =20 apic_driver(apic_x2apic_cluster); --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -180,7 +180,6 @@ static struct apic apic_x2apic_phys __ro .eoi_write =3D native_apic_msr_eoi_write, .icr_read =3D native_x2apic_icr_read, .icr_write =3D native_x2apic_icr_write, - .safe_wait_icr_idle =3D native_safe_x2apic_wait_icr_idle, }; =20 apic_driver(apic_x2apic_phys); --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -854,7 +854,6 @@ static struct apic apic_x2apic_uv_x __ro .eoi_write =3D native_apic_msr_eoi_write, .icr_read =3D native_x2apic_icr_read, .icr_write =3D native_x2apic_icr_write, - .safe_wait_icr_idle =3D native_safe_x2apic_wait_icr_idle, }; =20 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3 --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -92,11 +92,6 @@ static void xen_apic_icr_write(u32 low, WARN_ON(1); } =20 -static u32 xen_safe_apic_wait_icr_idle(void) -{ - return 0; -} - static int xen_apic_probe_pv(void) { if (xen_pv_domain()) @@ -161,7 +156,6 @@ static struct apic xen_pv_apic =3D { =20 .icr_read =3D xen_apic_icr_read, .icr_write =3D xen_apic_icr_write, - .safe_wait_icr_idle =3D xen_safe_apic_wait_icr_idle, }; =20 static void __init xen_apic_check(void) From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 324CDC0015E for ; Mon, 17 Jul 2023 23:32:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231669AbjGQXcd (ORCPT ); Mon, 17 Jul 2023 19:32:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230356AbjGQXcX (ORCPT ); Mon, 17 Jul 2023 19:32:23 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 194B810C7 for ; Mon, 17 Jul 2023 16:31:26 -0700 (PDT) Message-ID: <20230717223225.215108043@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635730; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=rgmHkZejpS0qXydJ9Am1q5T6I2ZzaAIkhjBamrktz/k=; b=00T/e6sXThT1a85ZqQWdu4xc7BpHBKIk3Qhl9MSi4pTKDhJ/pMd6BApjqpH2BGrQLrhxxt 1s79dzgkYBcIKnwpf6IGXIfCfZU6AMwqT7dStRocDbGuhg+qqlo1zvgLz5mIJfljLQBza4 xsTvlFgCq6cHXBrSESzgYSMW2CG6bveLkiCdTBgaD/ME0c7CpbLioRHO+WjDiAbS+oyigY /DKRO860dhFktAeMTG/qFGvcMSCWEfv9zFV86X9Aoyats4xyFA8WXp5vyIgxXejShgFqaf djmiJKzZfweQmFHkJdl1+XkzZdxphlUvlKk6NQUTemrAG8p7azBCC39eEvDPxA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635730; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=rgmHkZejpS0qXydJ9Am1q5T6I2ZzaAIkhjBamrktz/k=; b=BcG88HF8RG3MClC7We1N4mClZ4OL32G72fXeOqgkXZZNutvTPHKBw7OJJ5/JBwqHppsCsT ePH+1GPO1XU6v8Dw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 36/58] x86/apic: Move safe wait_icr_idle() next to apic_mem_wait_icr_idle() References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:30 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move it next to apic_mem_wait_icr_idle(), rename it so that it's clear what it does and rewrite it in readable form. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 1 - arch/x86/kernel/apic/apic.c | 17 ----------------- arch/x86/kernel/apic/apic_flat_64.c | 4 ++-- arch/x86/kernel/apic/bigsmp_32.c | 2 +- arch/x86/kernel/apic/ipi.c | 19 +++++++++++++++++-- arch/x86/kernel/apic/local.h | 1 + arch/x86/kernel/apic/probe_32.c | 2 +- 7 files changed, 22 insertions(+), 24 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -98,7 +98,6 @@ static inline u32 native_apic_mem_read(u return *((volatile u32 *)(APIC_BASE + reg)); } =20 -extern u32 native_safe_apic_wait_icr_idle(void); extern void native_apic_icr_write(u32 low, u32 id); extern u64 native_apic_icr_read(void); =20 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -240,23 +240,6 @@ static void __init apic_disable(void) apic =3D &apic_noop; } =20 -u32 native_safe_apic_wait_icr_idle(void) -{ - u32 send_status; - int timeout; - - timeout =3D 0; - do { - send_status =3D apic_read(APIC_ICR) & APIC_ICR_BUSY; - if (!send_status) - break; - inc_irq_stat(icr_read_retry_count); - udelay(100); - } while (timeout++ < 1000); - - return send_status; -} - void native_apic_icr_write(u32 low, u32 id) { unsigned long flags; --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -112,7 +112,7 @@ static struct apic apic_flat __ro_after_ .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, .wait_icr_idle =3D apic_mem_wait_icr_idle, - .safe_wait_icr_idle =3D native_safe_apic_wait_icr_idle, + .safe_wait_icr_idle =3D apic_mem_wait_icr_idle_timeout, }; =20 /* @@ -188,7 +188,7 @@ static struct apic apic_physflat __ro_af .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, .wait_icr_idle =3D apic_mem_wait_icr_idle, - .safe_wait_icr_idle =3D native_safe_apic_wait_icr_idle, + .safe_wait_icr_idle =3D apic_mem_wait_icr_idle_timeout, }; =20 /* --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -109,7 +109,7 @@ static struct apic apic_bigsmp __ro_afte .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, .wait_icr_idle =3D apic_mem_wait_icr_idle, - .safe_wait_icr_idle =3D native_safe_apic_wait_icr_idle, + .safe_wait_icr_idle =3D apic_mem_wait_icr_idle_timeout, }; =20 bool __init apic_bigsmp_possible(bool cmdline_override) --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -1,7 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 =20 #include +#include #include + #include =20 #include "local.h" @@ -102,6 +104,19 @@ static inline int __prepare_ICR2(unsigne return SET_XAPIC_DEST_FIELD(mask); } =20 +u32 apic_mem_wait_icr_idle_timeout(void) +{ + int cnt; + + for (cnt =3D 0; cnt < 1000; cnt++) { + if (!(apic_read(APIC_ICR) & APIC_ICR_BUSY)) + return 0; + inc_irq_stat(icr_read_retry_count); + udelay(100); + } + return APIC_ICR_BUSY; +} + void apic_mem_wait_icr_idle(void) { while (native_apic_mem_read(APIC_ICR) & APIC_ICR_BUSY) @@ -135,7 +150,7 @@ static void __default_send_IPI_shortcut( * to stop the others before launching the kdump kernel. */ if (unlikely(vector =3D=3D NMI_VECTOR)) - safe_apic_wait_icr_idle(); + apic_mem_wait_icr_idle_timeout(); else apic_mem_wait_icr_idle(); =20 @@ -152,7 +167,7 @@ void __default_send_IPI_dest_field(unsig { /* See comment in __default_send_IPI_shortcut() */ if (unlikely(vector =3D=3D NMI_VECTOR)) - safe_apic_wait_icr_idle(); + apic_mem_wait_icr_idle_timeout(); else apic_mem_wait_icr_idle(); =20 --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -45,6 +45,7 @@ static inline unsigned int __prepare_ICR void default_init_apic_ldr(void); =20 void apic_mem_wait_icr_idle(void); +u32 apic_mem_wait_icr_idle_timeout(void); =20 /* * This is used to send an IPI with no shorthand notation (the destination= is --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -65,7 +65,7 @@ static struct apic apic_default __ro_aft .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, .wait_icr_idle =3D apic_mem_wait_icr_idle, - .safe_wait_icr_idle =3D native_safe_apic_wait_icr_idle, + .safe_wait_icr_idle =3D apic_mem_wait_icr_idle_timeout, }; =20 apic_driver(apic_default); From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F14FC0015E for ; Mon, 17 Jul 2023 23:37:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231703AbjGQXg6 (ORCPT ); Mon, 17 Jul 2023 19:36:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51178 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231685AbjGQXgv (ORCPT ); Mon, 17 Jul 2023 19:36:51 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B86751719 for ; Mon, 17 Jul 2023 16:36:03 -0700 (PDT) Message-ID: <20230717223225.273415268@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635732; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=0+V5+gDglWXFOXAl/NKeyplEXp2IefeCUE4Fh7G+n/4=; b=KmKQ0C6ZMTvfEMgWOWKvqJMIcQO3L7KYwm4M44SqqGkqOH2msmDctXcslNo37q98COYsjG 07S6EO1elC3GA+p5bQiQHXM/8k4yka5pcdl2S5mvDJNsZhxVwmT059drPucIR4jysYlhId C7JPTtIBcluvu3sPuF7gFwik4+hY/O87pPgcZ8r7V5GUTNXJRZaUegt8JEwcEx9wtTxgky 4NbMROhWywUFAQzWyWAvwbgTlGskzmamUcc0fqwyNVt7+ay+/TtP3IoSi5msrNH2ytXSfB hkD1nkn5ZQORYTnsqLKGNnP95WTAniZsQ8HWKf4GcItae+rAMAvIdO0a+i10ug== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635732; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=0+V5+gDglWXFOXAl/NKeyplEXp2IefeCUE4Fh7G+n/4=; b=LJkgLnx1AiB7LE4UdEfC/YxcSdmOw+WdxAJOnnMQ5DtxuaNVKgM7lUrO/t2Pw8cojki5fP NAcoDqSF1Z9mQ2Dg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 37/58] x86/apic/uv: Get rid of wrapper callbacks References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:31 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Why on earth makes a wrapper around some common function sense? Just to be able to slap some vendor name on it... Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/x2apic_uv_x.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -783,11 +783,6 @@ static int uv_apic_id_valid(u32 apicid) return 1; } =20 -static u32 apic_uv_calc_apicid(unsigned int cpu) -{ - return apic_default_calc_apicid(cpu); -} - static unsigned int x2apic_get_apic_id(unsigned long id) { return id; @@ -838,7 +833,7 @@ static struct apic apic_x2apic_uv_x __ro .get_apic_id =3D x2apic_get_apic_id, .set_apic_id =3D set_apic_id, =20 - .calc_dest_apicid =3D apic_uv_calc_apicid, + .calc_dest_apicid =3D apic_default_calc_apicid, =20 .send_IPI =3D uv_send_IPI_one, .send_IPI_mask =3D uv_send_IPI_mask, From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C305AC0015E for ; Mon, 17 Jul 2023 23:18:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231601AbjGQXSu (ORCPT ); Mon, 17 Jul 2023 19:18:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231575AbjGQXSm (ORCPT ); Mon, 17 Jul 2023 19:18:42 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 091AEE4F for ; Mon, 17 Jul 2023 16:17:57 -0700 (PDT) Message-ID: <20230717223225.334807697@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635734; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=4BLE3+yKPO5gwc0BMR9mix8xtcjKVx9Oe/w05M3UNgo=; b=qOxr+TxD5+bSVnDx7EcALBZ038LlrFO0DGfArAheniYF+ztj6KV158Wd0YQqVelpmmV/UT iNOK9KeYViRVTAsYFWk6gBzq+FFuTRZH88638kX7qEdvX+LgHcKvYoBKildgmXrqdjrta8 QZaykCZ1jC3OPi7yfOPytJnEADZ8HfdvUtJh76EbzTWmTo9a8HnKqfcWdaXBtK46pv94mb 0imusoafVA5qYwgm62wcBJmOXMGjTeWo1MKNzw1Q2cB0bxqfFpEjgpI02e675DTVeGk627 QVcvjYK1cImRR/wl248VNa+DBpa9Fgn3VInl67UO2HMMbAIwuPUwXh5x+FpqMQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635734; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=4BLE3+yKPO5gwc0BMR9mix8xtcjKVx9Oe/w05M3UNgo=; b=cnDdZ0mfDxo2YlLhWMoPIG2qgSk5TCJnk1FcqhpGJyC5cP0NmesbixwZsa3moIeJ+c0JCE 3tiCxmpEZJOjZYBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 38/58] x86/apic/x2apic: Share all common IPI functions References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:33 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Yet more copy and pasta gone. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/local.h | 4 ++- arch/x86/kernel/apic/x2apic_cluster.c | 10 ------- arch/x86/kernel/apic/x2apic_phys.c | 44 +++++++++++++++++------------= ----- arch/x86/kernel/apic/x2apic_uv_x.c | 14 ++-------- 4 files changed, 28 insertions(+), 44 deletions(-) --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -19,8 +19,10 @@ void __x2apic_send_IPI_dest(unsigned int unsigned int x2apic_get_apic_id(unsigned long id); u32 x2apic_set_apic_id(unsigned int id); int x2apic_phys_pkg_id(int initial_apicid, int index_msb); + +void x2apic_send_IPI_all(int vector); +void x2apic_send_IPI_allbutself(int vector); void x2apic_send_IPI_self(int vector); -void __x2apic_send_IPI_shorthand(int vector, u32 which); =20 /* IPI */ =20 --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -83,16 +83,6 @@ x2apic_send_IPI_mask_allbutself(const st __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT); } =20 -static void x2apic_send_IPI_allbutself(int vector) -{ - __x2apic_send_IPI_shorthand(vector, APIC_DEST_ALLBUT); -} - -static void x2apic_send_IPI_all(int vector) -{ - __x2apic_send_IPI_shorthand(vector, APIC_DEST_ALLINC); -} - static u32 x2apic_calc_apicid(unsigned int cpu) { return x86_cpu_to_logical_apicid[cpu]; --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -81,16 +81,36 @@ static void __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT); } =20 -static void x2apic_send_IPI_allbutself(int vector) +static void __x2apic_send_IPI_shorthand(int vector, u32 which) +{ + unsigned long cfg =3D __prepare_ICR(which, vector, 0); + + /* x2apic MSRs are special and need a special fence: */ + weak_wrmsr_fence(); + native_x2apic_icr_write(cfg, 0); +} + +void x2apic_send_IPI_allbutself(int vector) { __x2apic_send_IPI_shorthand(vector, APIC_DEST_ALLBUT); } =20 -static void x2apic_send_IPI_all(int vector) +void x2apic_send_IPI_all(int vector) { __x2apic_send_IPI_shorthand(vector, APIC_DEST_ALLINC); } =20 +void x2apic_send_IPI_self(int vector) +{ + apic_write(APIC_SELF_IPI, vector); +} + +void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int = dest) +{ + unsigned long cfg =3D __prepare_ICR(0, vector, dest); + native_x2apic_icr_write(cfg, apicid); +} + static int x2apic_phys_probe(void) { if (!x2apic_mode) @@ -111,21 +131,6 @@ int x2apic_apic_id_valid(u32 apicid) return 1; } =20 -void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int = dest) -{ - unsigned long cfg =3D __prepare_ICR(0, vector, dest); - native_x2apic_icr_write(cfg, apicid); -} - -void __x2apic_send_IPI_shorthand(int vector, u32 which) -{ - unsigned long cfg =3D __prepare_ICR(which, vector, 0); - - /* x2apic MSRs are special and need a special fence: */ - weak_wrmsr_fence(); - native_x2apic_icr_write(cfg, 0); -} - unsigned int x2apic_get_apic_id(unsigned long id) { return id; @@ -141,11 +146,6 @@ int x2apic_phys_pkg_id(int initial_apici return initial_apicid >> index_msb; } =20 -void x2apic_send_IPI_self(int vector) -{ - apic_write(APIC_SELF_IPI, vector); -} - static struct apic apic_x2apic_phys __ro_after_init =3D { =20 .name =3D "physical x2apic", --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -25,6 +25,8 @@ #include #include =20 +#include "local.h" + static enum uv_system_type uv_system_type; static int uv_hubbed_system; static int uv_hubless_system; @@ -783,11 +785,6 @@ static int uv_apic_id_valid(u32 apicid) return 1; } =20 -static unsigned int x2apic_get_apic_id(unsigned long id) -{ - return id; -} - static u32 set_apic_id(unsigned int id) { return id; @@ -803,11 +800,6 @@ static int uv_phys_pkg_id(int initial_ap return uv_read_apic_id() >> index_msb; } =20 -static void uv_send_IPI_self(int vector) -{ - apic_write(APIC_SELF_IPI, vector); -} - static int uv_probe(void) { return apic =3D=3D &apic_x2apic_uv_x; @@ -840,7 +832,7 @@ static struct apic apic_x2apic_uv_x __ro .send_IPI_mask_allbutself =3D uv_send_IPI_mask_allbutself, .send_IPI_allbutself =3D uv_send_IPI_allbutself, .send_IPI_all =3D uv_send_IPI_all, - .send_IPI_self =3D uv_send_IPI_self, + .send_IPI_self =3D x2apic_send_IPI_self, =20 .wakeup_secondary_cpu =3D uv_wakeup_secondary, From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1E7AC001B0 for ; Mon, 17 Jul 2023 23:33:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231646AbjGQXdG (ORCPT ); Mon, 17 Jul 2023 19:33:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48636 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230358AbjGQXdC (ORCPT ); Mon, 17 Jul 2023 19:33:02 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F353170B for ; Mon, 17 Jul 2023 16:32:09 -0700 (PDT) Message-ID: <20230717223225.394633265@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635735; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=s19156BZmBKn/+gIefFlMT9NlvbxtvZTdSeLRnjoukg=; b=AWwAwQ1TbJlPno3V2qAdO5g6RApmn7VllVPsrl/7OPR6659zM4BKEJfpKFZfw+TxUZxr8N 5KNw4pbJeD8lt5X1aBHqb1168Xxk6sieVUBDc+DIiioSkkqUlXj/Z8wCRFmyJBODduSL9N 5UVyNpTG+YH5kAOCpIB3FGSuoAXW3PWtRwb5fsqJePV+23OeXsS43kReNA9XEU5Vq/GoYk YxXxqyrGsGoyhPJYBRFPiI7w7gP/P0bVfA5dYxqij9B6LhGFF/eOOUBOkKW0I7RVhLsRvt 6DMXYRsr54FdCXrhmgUz2pB7PqHkXRJZgRn+3MpdCr69VZRUICG1yE7+PE+fCQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635735; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=s19156BZmBKn/+gIefFlMT9NlvbxtvZTdSeLRnjoukg=; b=BgH8Loq6CGCh7V/YU3PyzfQ/I2OtaC9oE8h4mS+YVzQZWiGu8SJrNesSc+PPSfipdXfBvI NpYRqDGn+YCxsDAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 39/58] x86/apic/64: Uncopypaste probing References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:35 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" No need for the same thing twice. Also prepares for simplifying the APIC ID validation checks. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/probe_64.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) --- a/arch/x86/kernel/apic/probe_64.c +++ b/arch/x86/kernel/apic/probe_64.c @@ -13,6 +13,15 @@ =20 #include "local.h" =20 +static __init void apic_install_driver(struct apic *driver) +{ + if (apic =3D=3D driver) + return; + + apic =3D driver; + pr_info("Switched APIC routing to %s:\n", apic->name); +} + /* Select the appropriate APIC driver */ void __init x86_64_probe_apic(void) { @@ -22,11 +31,7 @@ void __init x86_64_probe_apic(void) =20 for (drv =3D __apicdrivers; drv < __apicdrivers_end; drv++) { if ((*drv)->probe && (*drv)->probe()) { - if (apic !=3D *drv) { - apic =3D *drv; - pr_info("Switched APIC routing to %s.\n", - apic->name); - } + apic_install_driver(*drv); break; } } @@ -38,11 +43,7 @@ int __init default_acpi_madt_oem_check(c =20 for (drv =3D __apicdrivers; drv < __apicdrivers_end; drv++) { if ((*drv)->acpi_madt_oem_check(oem_id, oem_table_id)) { - if (apic !=3D *drv) { - apic =3D *drv; - pr_info("Setting APIC routing to %s.\n", - apic->name); - } + apic_install_driver(*drv); return 1; } } From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2256AC0015E for ; Mon, 17 Jul 2023 23:19:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231615AbjGQXTA (ORCPT ); Mon, 17 Jul 2023 19:19:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231612AbjGQXS7 (ORCPT ); Mon, 17 Jul 2023 19:18:59 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47D0F18B for ; Mon, 17 Jul 2023 16:18:14 -0700 (PDT) Message-ID: <20230717223225.455893009@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635737; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=UJGgSk85bCjHVvLP0ge+jZsQpl98WT3tTk4TUIufIuY=; b=34XUGULgjMZnaDR0zYz+a2ScDMU1gMClqjqwfOMIqqvFLURLF0fWGBewpUzjQprH5bGEAN gXL25vmys9ZGKNx2svTpmbTkzSFEGUDis1BFJCXF7IWkCbaVp2PDZjcPy601BjPlVxeFjM j3C0yEgbVpHkPnMmPvSIYyFi/6vqwjn+wVNZOZuB143DhiXJ0PPq9lh+U8Xq+uUw/bY6Dg 8TaquW6QI16PSztszaFX1jkN4AffIvzZILM5aiwJTWm0DY6TEh1g6E+ZbHirvbhIooebur H+7a/8guqbYwJig6huGevK/4YUbkeP+e0YAD6O1u0cpm/0JIvTKODZ4EZ3XTJg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635737; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=UJGgSk85bCjHVvLP0ge+jZsQpl98WT3tTk4TUIufIuY=; b=SyyQCuPOHu36zMqQjGqNhA/yh5lP9vpGv4aV3nUSXYM45fPGbFQXh1L3CnIdZDdBkG6bNF qMaKe780Iu8e8TDQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 40/58] x86/apic: Wrap APIC ID validation into an inline References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:36 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Prepare for removing the callback and making this as simple comparison to an upper limit, which is the obvious solution to do for limit checks... Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 5 +++++ arch/x86/kernel/acpi/boot.c | 2 +- arch/x86/kernel/apic/vector.c | 2 +- arch/x86/kernel/smpboot.c | 5 ++--- arch/x86/mm/srat.c | 5 ++--- 5 files changed, 11 insertions(+), 8 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -372,6 +372,11 @@ static inline u32 safe_apic_wait_icr_idl return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0; } =20 +static inline bool apic_id_valid(u32 apic_id) +{ + return apic->apic_id_valid(apic_id); +} + extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); =20 #else /* CONFIG_X86_LOCAL_APIC */ --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -235,7 +235,7 @@ acpi_parse_x2apic(union acpi_subtable_he * to not preallocating memory for all NR_CPUS * when we use CPU hotplug. */ - if (!apic->apic_id_valid(apic_id)) { + if (!apic_id_valid(apic_id)) { if (enabled) pr_warn("x2apic entry ignored\n"); return 0; --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -680,7 +680,7 @@ static int x86_vector_select(struct irq_ * if IRQ remapping is enabled. APIC IDs above 15 bits are * only permitted if IRQ remapping is enabled, so check that. */ - if (apic->apic_id_valid(32768)) + if (apic_id_valid(32768)) return 0; =20 return x86_fwspec_is_ioapic(fwspec) || x86_fwspec_is_hpet(fwspec); --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1064,9 +1064,8 @@ int native_kick_ap(unsigned int cpu, str =20 pr_debug("++++++++++++++++++++=3D_---CPU UP %u\n", cpu); =20 - if (apicid =3D=3D BAD_APICID || - !physid_isset(apicid, phys_cpu_present_map) || - !apic->apic_id_valid(apicid)) { + if (apicid =3D=3D BAD_APICID || !physid_isset(apicid, phys_cpu_present_ma= p) || + !apic_id_valid(apicid)) { pr_err("%s: bad cpu %d\n", __func__, cpu); return -EINVAL; } --- a/arch/x86/mm/srat.c +++ b/arch/x86/mm/srat.c @@ -40,9 +40,8 @@ acpi_numa_x2apic_affinity_init(struct ac return; pxm =3D pa->proximity_domain; apic_id =3D pa->apic_id; - if (!apic->apic_id_valid(apic_id)) { - printk(KERN_INFO "SRAT: PXM %u -> X2APIC 0x%04x ignored\n", - pxm, apic_id); + if (!apic_id_valid(apic_id)) { + pr_info("SRAT: PXM %u -> X2APIC 0x%04x ignored\n", pxm, apic_id); return; } node =3D acpi_map_pxm_to_node(pxm); From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E168FC0015E for ; Mon, 17 Jul 2023 23:32:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231660AbjGQXc0 (ORCPT ); Mon, 17 Jul 2023 19:32:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229481AbjGQXcX (ORCPT ); Mon, 17 Jul 2023 19:32:23 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AF0410FF for ; Mon, 17 Jul 2023 16:31:25 -0700 (PDT) Message-ID: <20230717223225.515238528@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635738; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=c6/l6FDyGOdgCBOzK6YM6Al7WkOQ1ZlJVvPCzCOr2Oc=; b=PwXUrh0eXPLIe807EceAtbRNsYdNTOdidk7cstYM+s51wVsQiziUIczLzUU/Q98eRqsIaJ UesYZj7Swn1Ys7MoCvfa8vUB9nmG/B2vZbcL4mgoyCDp44BQ9Ij0vXM4MtJ06uzKZl+W7x 1pwbBnWDsUcdQH9VvGGnUveUnRbP4N8MzZpw2nDIOsWY8reGUbFNrpOVHGgMBxD6k+k4ov fNuuJ8w24gz9MlJ+klSVzfk3yhtYwBN75/GfMcF0dsQgK1lu8gAoZtETno4KwltupV5Akm bH1PGY5a+uTJaNgy/2xhZp+XgQNobf4P/bNBgb6RQxmk7gS49HE4GOS+rhNH/A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635738; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=c6/l6FDyGOdgCBOzK6YM6Al7WkOQ1ZlJVvPCzCOr2Oc=; b=tv9bAsob+ud2xRxMgItASl8k6W9hHNoTeFSxcOZqvz/zyhehM2XZdTkA/01XTZEmVUfJOm c434w9zKYSYnBMDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 41/58] x86/apic: Add max_apic_id member References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:38 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There is really no point to have a callback which compares numbers. Add a field which allows each APIC to store the maximum APIC ID supported and fill it in for all APIC incarnations. The next step will remove the callback. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 3 +++ arch/x86/kernel/apic/apic_flat_64.c | 2 ++ arch/x86/kernel/apic/apic_noop.c | 1 + arch/x86/kernel/apic/apic_numachip.c | 2 ++ arch/x86/kernel/apic/bigsmp_32.c | 1 + arch/x86/kernel/apic/probe_32.c | 1 + arch/x86/kernel/apic/x2apic_cluster.c | 1 + arch/x86/kernel/apic/x2apic_phys.c | 1 + arch/x86/kernel/apic/x2apic_uv_x.c | 1 + arch/x86/xen/apic.c | 1 + 10 files changed, 14 insertions(+) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -277,6 +277,9 @@ struct apic { u64 (*icr_read)(void); void (*icr_write)(u32 low, u32 high); =20 + /* The limit of the APIC ID space. */ + u32 max_apic_id; + /* Probe, setup and smpboot functions */ int (*probe)(void); int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -94,6 +94,7 @@ static struct apic apic_flat __ro_after_ .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D flat_phys_pkg_id, =20 + .max_apic_id =3D 0xFE, .get_apic_id =3D flat_get_apic_id, .set_apic_id =3D set_apic_id, =20 @@ -170,6 +171,7 @@ static struct apic apic_physflat __ro_af .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D flat_phys_pkg_id, =20 + .max_apic_id =3D 0xFE, .get_apic_id =3D flat_get_apic_id, .set_apic_id =3D set_apic_id, =20 --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -80,6 +80,7 @@ struct apic apic_noop __ro_after_init =3D =20 .phys_pkg_id =3D noop_phys_pkg_id, =20 + .max_apic_id =3D 0xFE, .get_apic_id =3D noop_get_apic_id, .set_apic_id =3D NULL, =20 --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -239,6 +239,7 @@ static const struct apic apic_numachip1 .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D numachip_phys_pkg_id, =20 + .max_apic_id =3D UINT_MAX, .get_apic_id =3D numachip1_get_apic_id, .set_apic_id =3D numachip1_set_apic_id, =20 @@ -278,6 +279,7 @@ static const struct apic apic_numachip2 .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D numachip_phys_pkg_id, =20 + .max_apic_id =3D UINT_MAX, .get_apic_id =3D numachip2_get_apic_id, .set_apic_id =3D numachip2_set_apic_id, =20 --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -91,6 +91,7 @@ static struct apic apic_bigsmp __ro_afte .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D bigsmp_phys_pkg_id, =20 + .max_apic_id =3D 0xFE, .get_apic_id =3D bigsmp_get_apic_id, .set_apic_id =3D NULL, =20 --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -47,6 +47,7 @@ static struct apic apic_default __ro_aft .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D default_phys_pkg_id, =20 + .max_apic_id =3D 0xFE, .get_apic_id =3D default_get_apic_id, .set_apic_id =3D NULL, =20 --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -239,6 +239,7 @@ static struct apic apic_x2apic_cluster _ .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D x2apic_phys_pkg_id, =20 + .max_apic_id =3D UINT_MAX, .get_apic_id =3D x2apic_get_apic_id, .set_apic_id =3D x2apic_set_apic_id, =20 --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -163,6 +163,7 @@ static struct apic apic_x2apic_phys __ro .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D x2apic_phys_pkg_id, =20 + .max_apic_id =3D UINT_MAX, .get_apic_id =3D x2apic_get_apic_id, .set_apic_id =3D x2apic_set_apic_id, =20 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -822,6 +822,7 @@ static struct apic apic_x2apic_uv_x __ro .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D uv_phys_pkg_id, =20 + .max_apic_id =3D UINT_MAX, .get_apic_id =3D x2apic_get_apic_id, .set_apic_id =3D set_apic_id, =20 --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -138,6 +138,7 @@ static struct apic xen_pv_apic =3D { .cpu_present_to_apicid =3D xen_cpu_present_to_apicid, .phys_pkg_id =3D xen_phys_pkg_id, /* detect_ht */ =20 + .max_apic_id =3D UINT_MAX, .get_apic_id =3D xen_get_apic_id, .set_apic_id =3D xen_set_apic_id, /* Can be NULL on 32-bit. */ From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57D9CEB64DC for ; Mon, 17 Jul 2023 23:40:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230198AbjGQXkZ (ORCPT ); Mon, 17 Jul 2023 19:40:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229625AbjGQXkX (ORCPT ); Mon, 17 Jul 2023 19:40:23 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E3A71BC8 for ; Mon, 17 Jul 2023 16:40:02 -0700 (PDT) Message-ID: <20230717223225.574767249@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635740; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Q1JNQJEMBxAgDkdW0pLI2m/sGBRaEoryy+htOkBQTrI=; b=XVTtGjs7K8KwXqAXQvamTB5j0FI8ZG0Etn3P0nAYb44RxqjvhlSp/ZMS0bTDhd47zD421T KNyKLFg4ir8BlPTfLrXqqVk2afMM57cZg4BVBNQ2m7ARbx4+Li0B3zFwQHqmBDIpzLCZEk eWS64EuDFrq0TnFan+G9UnQ31oTgdewrokNT4L0FUVteWoPDDIuNG9Ttv/XBiO68fEPZmM w95GoK1ph9rrJH7FmgkY9Tn5BQ6qtkgmJhr4ykrP99iENkaYkw0LW9YZ0m+M/a6fyEft+C V7xpiILcDTYOsS/19vI1LjzzCDfsEj/JtuOV8m1pWdkWZjl7Hfkik4V0lMy93Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635740; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Q1JNQJEMBxAgDkdW0pLI2m/sGBRaEoryy+htOkBQTrI=; b=XU+BJFq/bYmMMjorgjZW5KwpaePkOpCDNCYgLXktF/uhc13HDW746lbXxGqxGnZ9sSSM/M UmZoOTTbC187LCCg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 42/58] x86/apic: Simplify X2APIC ID validation References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:40 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" No point in doing the zero equals unlimited check and if not zero compare against the real number. Unlimited is UINT_MAX. So initialize the variable with UINT_MAX and compare less than or equal. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/x2apic_phys.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -8,7 +8,7 @@ int x2apic_phys; =20 static struct apic apic_x2apic_phys; -static u32 x2apic_max_apicid __ro_after_init; +static u32 x2apic_max_apicid __ro_after_init =3D UINT_MAX; =20 void __init x2apic_set_max_apicid(u32 apicid) { @@ -125,10 +125,7 @@ static int x2apic_phys_probe(void) /* Common x2apic functions, also used by x2apic_cluster */ int x2apic_apic_id_valid(u32 apicid) { - if (x2apic_max_apicid && apicid > x2apic_max_apicid) - return 0; - - return 1; + return apicid <=3D x2apic_max_apicid; } =20 unsigned int x2apic_get_apic_id(unsigned long id) From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 117DAEB64DC for ; Mon, 17 Jul 2023 23:24:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231618AbjGQXYr (ORCPT ); Mon, 17 Jul 2023 19:24:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230183AbjGQXYp (ORCPT ); Mon, 17 Jul 2023 19:24:45 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 83227173D for ; Mon, 17 Jul 2023 16:24:07 -0700 (PDT) Message-ID: <20230717223225.634205045@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635742; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=zCuopdE3RQFCHCsf4zrOItotVQ+TGysIbFJ/I2GYtw8=; b=dppNph2lvl/AOCMRGkW5+6iP+zBV6T6fhualr5yM3nTvvGsVHRkvAczwnO5iChrUEZTBLr MPzxLG322AeGzqsLHIL4lC77BEWkGJt0evtw7wNvM39/0e9r3ULKKR7Zit9hFaUE1uj8Ys D//L5k0w6q8X4zMFjlVdWr8AhneziF8A2VOYgW6vRHH6H3uV6JQDO+1p9kX8jabWS+JGdG Q+Sn/dd8s8F4QKFSAZHe7Kf9G4wCTmahDZtMHlQM78GGnRnHIRHj0cfVyEOUlH8kF4WfKi YGMkvlg7YcxM9HqhFrXUKnyQZoItU3nMPjRw+jS2TME8KfxqdewJMzSu+ngFNQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635742; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=zCuopdE3RQFCHCsf4zrOItotVQ+TGysIbFJ/I2GYtw8=; b=X3TZmsQ1KOmKrkLjA6RX6lbC27nGCSpGt7+z4PlXHaB7WPz4d7khssHbEuHP3Mrf/F6XmQ gx147IAen5VtsuDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 43/58] x86/apic: Prepare x2APIC for using apic::max_apic_id References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:41 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to remove the apic::apic_id_valid() callback and switch to checking apic::max_apic_id, it is required to update apic::max_apic_id when the APIC initialization code overrides it via x2apic_set_max_apicid(). Make the existing booleans a bitfield and add a flag which lets the update function and the core code which switches the driver detect whether the apic instance wants to have that update or not and apply it if required. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 7 ++++--- arch/x86/kernel/apic/local.h | 1 + arch/x86/kernel/apic/probe_64.c | 4 ++++ arch/x86/kernel/apic/x2apic_cluster.c | 1 + arch/x86/kernel/apic/x2apic_phys.c | 5 ++++- 5 files changed, 14 insertions(+), 4 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -266,10 +266,11 @@ struct apic { void (*send_IPI_all)(int vector); void (*send_IPI_self)(int vector); =20 - u32 disable_esr; - enum apic_delivery_modes delivery_mode; - bool dest_mode_logical; + + u32 disable_esr : 1, + dest_mode_logical : 1, + x2apic_set_max_apicid : 1; =20 u32 (*calc_dest_apicid)(unsigned int cpu); =20 --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -23,6 +23,7 @@ int x2apic_phys_pkg_id(int initial_apici void x2apic_send_IPI_all(int vector); void x2apic_send_IPI_allbutself(int vector); void x2apic_send_IPI_self(int vector); +extern u32 x2apic_max_apicid; =20 /* IPI */ =20 --- a/arch/x86/kernel/apic/probe_64.c +++ b/arch/x86/kernel/apic/probe_64.c @@ -19,6 +19,10 @@ static __init void apic_install_driver(s return; =20 apic =3D driver; + + if (IS_ENABLED(CONFIG_X86_X2APIC) && apic->x2apic_set_max_apicid) + apic->max_apic_id =3D x2apic_max_apicid; + pr_info("Switched APIC routing to %s:\n", apic->name); } =20 --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -240,6 +240,7 @@ static struct apic apic_x2apic_cluster _ .phys_pkg_id =3D x2apic_phys_pkg_id, =20 .max_apic_id =3D UINT_MAX, + .x2apic_set_max_apicid =3D true, .get_apic_id =3D x2apic_get_apic_id, .set_apic_id =3D x2apic_set_apic_id, =20 --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -8,11 +8,13 @@ int x2apic_phys; =20 static struct apic apic_x2apic_phys; -static u32 x2apic_max_apicid __ro_after_init =3D UINT_MAX; +u32 x2apic_max_apicid __ro_after_init =3D UINT_MAX; =20 void __init x2apic_set_max_apicid(u32 apicid) { x2apic_max_apicid =3D apicid; + if (apic->x2apic_set_max_apicid) + apic->max_apic_id =3D apicid; } =20 static int __init set_x2apic_phys_mode(char *arg) @@ -161,6 +163,7 @@ static struct apic apic_x2apic_phys __ro .phys_pkg_id =3D x2apic_phys_pkg_id, =20 .max_apic_id =3D UINT_MAX, + .x2apic_set_max_apicid =3D true, .get_apic_id =3D x2apic_get_apic_id, .set_apic_id =3D x2apic_set_apic_id, From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24CC0C0015E for ; Mon, 17 Jul 2023 23:24:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231607AbjGQXYR (ORCPT ); Mon, 17 Jul 2023 19:24:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231598AbjGQXYL (ORCPT ); Mon, 17 Jul 2023 19:24:11 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F26301720 for ; Mon, 17 Jul 2023 16:23:32 -0700 (PDT) Message-ID: <20230717223225.693825302@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635743; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=t8GuwcLuogoZNuL5wE48WjFzNkePRlo9xZ30OfxA9Cs=; b=p4BdxmwWCPi2A3Pw0DS1RX+tNbD/uCdVagrVujPn1FIlHv0GvEsyrCDy2wlEJ0OtEYqzGN U4j8Axj5PNVd4W417SV48j5cdGjN1t40ZGM+R4YhRY4qDc7No4BDqDCb26zDCcyAAmcwzS GHRxaiXe30xFkfyxSmUwuhduZLomeBBdEZozA7K+Ic9X7aHlaL1w/HMh0rz8pZCnLuN8Hu emTJk8cbBDq4gOQAknZ4NJEmavyhcf/NjnDW1fl2608/DVoVI/kijdlp2ffUivn6cNpPnA wRzqVkv/BARwKCnzTL/MAkGHLDgIZDI21iHROQI5CW2kkyixfUGlC2RFuL979g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635743; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=t8GuwcLuogoZNuL5wE48WjFzNkePRlo9xZ30OfxA9Cs=; b=76UV29N2lyvyADzADbg1lMUztNYFYETn9m38rmPNnUuJamiuLY/3/bRI/4t5bVxRGZs7T5 SJ7RqMwEawSBwUDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 44/58] x86/apic: Sanitize APID ID range validation References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:43 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that everything has apic::max_apic_id set and the eventual update for the x2APIC case is in place, switch the apic_id_valid() helper to use apic::max_apic_id and remove the apic::apic_id_valid() callback. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 3 +-- arch/x86/kernel/apic/apic_common.c | 5 ----- arch/x86/kernel/apic/apic_flat_64.c | 2 -- arch/x86/kernel/apic/apic_noop.c | 2 -- arch/x86/kernel/apic/apic_numachip.c | 8 -------- arch/x86/kernel/apic/bigsmp_32.c | 1 - arch/x86/kernel/apic/local.h | 1 - arch/x86/kernel/apic/probe_32.c | 1 - arch/x86/kernel/apic/x2apic_cluster.c | 1 - arch/x86/kernel/apic/x2apic_phys.c | 7 ------- arch/x86/kernel/apic/x2apic_uv_x.c | 6 ------ arch/x86/xen/apic.c | 6 ------ 12 files changed, 1 insertion(+), 42 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -284,7 +284,6 @@ struct apic { /* Probe, setup and smpboot functions */ int (*probe)(void); int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); - int (*apic_id_valid)(u32 apicid); bool (*apic_id_registered)(void); =20 bool (*check_apicid_used)(physid_mask_t *map, int apicid); @@ -378,7 +377,7 @@ static inline u32 safe_apic_wait_icr_idl =20 static inline bool apic_id_valid(u32 apic_id) { - return apic->apic_id_valid(apic_id); + return apic_id <=3D apic->max_apic_id; } =20 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); --- a/arch/x86/kernel/apic/apic_common.c +++ b/arch/x86/kernel/apic/apic_common.c @@ -37,11 +37,6 @@ int default_cpu_present_to_apicid(int mp } EXPORT_SYMBOL_GPL(default_cpu_present_to_apicid); =20 -int default_apic_id_valid(u32 apicid) -{ - return (apicid < 255); -} - bool default_apic_id_registered(void) { return physid_isset(read_apic_id(), phys_cpu_present_map); --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -80,7 +80,6 @@ static struct apic apic_flat __ro_after_ .name =3D "flat", .probe =3D flat_probe, .acpi_madt_oem_check =3D flat_acpi_madt_oem_check, - .apic_id_valid =3D default_apic_id_valid, .apic_id_registered =3D default_apic_id_registered, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, @@ -158,7 +157,6 @@ static struct apic apic_physflat __ro_af .name =3D "physical flat", .probe =3D physflat_probe, .acpi_madt_oem_check =3D physflat_acpi_madt_oem_check, - .apic_id_valid =3D default_apic_id_valid, .apic_id_registered =3D default_apic_id_registered, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -67,8 +67,6 @@ struct apic apic_noop __ro_after_init =3D .probe =3D noop_probe, .acpi_madt_oem_check =3D NULL, =20 - .apic_id_valid =3D default_apic_id_valid, - .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, .dest_mode_logical =3D true, =20 --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -56,12 +56,6 @@ static u32 numachip2_set_apic_id(unsigne return id << 24; } =20 -static int numachip_apic_id_valid(u32 apicid) -{ - /* Trust what bootloader passes in MADT */ - return 1; -} - static int numachip_phys_pkg_id(int initial_apic_id, int index_msb) { return initial_apic_id >> index_msb; @@ -227,7 +221,6 @@ static const struct apic apic_numachip1 .name =3D "NumaConnect system", .probe =3D numachip1_probe, .acpi_madt_oem_check =3D numachip1_acpi_madt_oem_check, - .apic_id_valid =3D numachip_apic_id_valid, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, .dest_mode_logical =3D false, @@ -267,7 +260,6 @@ static const struct apic apic_numachip2 .name =3D "NumaConnect2 system", .probe =3D numachip2_probe, .acpi_madt_oem_check =3D numachip2_acpi_madt_oem_check, - .apic_id_valid =3D numachip_apic_id_valid, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, .dest_mode_logical =3D false, --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -79,7 +79,6 @@ static struct apic apic_bigsmp __ro_afte =20 .name =3D "bigsmp", .probe =3D probe_bigsmp, - .apic_id_valid =3D default_apic_id_valid, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, .dest_mode_logical =3D false, --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -14,7 +14,6 @@ #include =20 /* X2APIC */ -int x2apic_apic_id_valid(u32 apicid); void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int = dest); unsigned int x2apic_get_apic_id(unsigned long id); u32 x2apic_set_apic_id(unsigned int id); --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -33,7 +33,6 @@ static struct apic apic_default __ro_aft =20 .name =3D "default", .probe =3D probe_default, - .apic_id_valid =3D default_apic_id_valid, .apic_id_registered =3D default_apic_id_registered, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -226,7 +226,6 @@ static struct apic apic_x2apic_cluster _ .name =3D "cluster x2apic", .probe =3D x2apic_cluster_probe, .acpi_madt_oem_check =3D x2apic_acpi_madt_oem_check, - .apic_id_valid =3D x2apic_apic_id_valid, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, .dest_mode_logical =3D true, --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -124,12 +124,6 @@ static int x2apic_phys_probe(void) return apic =3D=3D &apic_x2apic_phys; } =20 -/* Common x2apic functions, also used by x2apic_cluster */ -int x2apic_apic_id_valid(u32 apicid) -{ - return apicid <=3D x2apic_max_apicid; -} - unsigned int x2apic_get_apic_id(unsigned long id) { return id; @@ -150,7 +144,6 @@ static struct apic apic_x2apic_phys __ro .name =3D "physical x2apic", .probe =3D x2apic_phys_probe, .acpi_madt_oem_check =3D x2apic_acpi_madt_oem_check, - .apic_id_valid =3D x2apic_apic_id_valid, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, .dest_mode_logical =3D false, --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -780,11 +780,6 @@ static void uv_send_IPI_all(int vector) uv_send_IPI_mask(cpu_online_mask, vector); } =20 -static int uv_apic_id_valid(u32 apicid) -{ - return 1; -} - static u32 set_apic_id(unsigned int id) { return id; @@ -810,7 +805,6 @@ static struct apic apic_x2apic_uv_x __ro .name =3D "UV large system", .probe =3D uv_probe, .acpi_madt_oem_check =3D uv_acpi_madt_oem_check, - .apic_id_valid =3D uv_apic_id_valid, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, .dest_mode_logical =3D false, --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -105,11 +105,6 @@ static int xen_madt_oem_check(char *oem_ return xen_pv_domain(); } =20 -static int xen_id_always_valid(u32 apicid) -{ - return 1; -} - static int xen_phys_pkg_id(int initial_apic_id, int index_msb) { return initial_apic_id >> index_msb; @@ -127,7 +122,6 @@ static struct apic xen_pv_apic =3D { .name =3D "Xen PV", .probe =3D xen_apic_probe_pv, .acpi_madt_oem_check =3D xen_madt_oem_check, - .apic_id_valid =3D xen_id_always_valid, =20 /* .delivery_mode and .dest_mode_logical not used by XENPV */ From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34617EB64DC for ; Mon, 17 Jul 2023 23:43:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229766AbjGQXnO (ORCPT ); Mon, 17 Jul 2023 19:43:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231153AbjGQXk6 (ORCPT ); Mon, 17 Jul 2023 19:40:58 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78568170A for ; Mon, 17 Jul 2023 16:40:35 -0700 (PDT) Message-ID: <20230717223225.754957545@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635745; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=AWaEZw8abvCPdN4y6ge3RbIG2SvdzHbMvIezw0K7Xt4=; b=xGjM4LiVIbDvVJpkJPrQjEaRdgsQZ5akQT26sx1478B5xJtClRWnFpiaKg73W7rzbSZpmu 9cb7VLiK5CNVLJ5SHYsYbijnVeRnYRWCVGZPuPNVABGDN6I316EFSYjcFOKx6ciTTNfR3n a4fJw5/BrbUnbDa1uZqrO3gk2aue9kBShZmUFi4KcEScPYmBEcz39LIzG4h+18Tmw0J+AV plvIkhV8AXnsb6I7C/fh75Q1t84rIyI0vtbIOhwrFOs82rOUbvUDPvhEHNC/Ngmc8B3SqC A8zsj2dI2QBlNMn4UuoXUR4vFt2nDiZeJj3AIF9IOED0DEFurHtRBNJcH2cCEw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635745; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=AWaEZw8abvCPdN4y6ge3RbIG2SvdzHbMvIezw0K7Xt4=; b=h2M38jF60O41a5q3PzJBQp7a2b8q3FvZ1CwUp7sKuTEdAmME2dg2o+DJ2A9C7h8M3Z6mqd JhNoR9No5x4mSIAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 45/58] x86/apic: Remove pointless NULL initializations References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:44 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Wasted space for no value. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/apic_flat_64.c | 2 -- arch/x86/kernel/apic/apic_noop.c | 2 -- arch/x86/kernel/apic/apic_numachip.c | 4 ---- arch/x86/kernel/apic/probe_32.c | 1 - arch/x86/kernel/apic/x2apic_phys.c | 2 -- arch/x86/kernel/apic/x2apic_uv_x.c | 2 -- 6 files changed, 13 deletions(-) --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -87,9 +87,7 @@ static struct apic apic_flat __ro_after_ =20 .disable_esr =3D 0, =20 - .check_apicid_used =3D NULL, .init_apic_ldr =3D default_init_apic_ldr, - .ioapic_phys_id_map =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D flat_phys_pkg_id, =20 --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -65,7 +65,6 @@ static void noop_apic_write(u32 reg, u32 struct apic apic_noop __ro_after_init =3D { .name =3D "noop", .probe =3D noop_probe, - .acpi_madt_oem_check =3D NULL, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, .dest_mode_logical =3D true, @@ -80,7 +79,6 @@ struct apic apic_noop __ro_after_init =3D =20 .max_apic_id =3D 0xFE, .get_apic_id =3D noop_get_apic_id, - .set_apic_id =3D NULL, =20 .calc_dest_apicid =3D apic_flat_calc_apicid, =20 --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -227,8 +227,6 @@ static const struct apic apic_numachip1 =20 .disable_esr =3D 0, =20 - .check_apicid_used =3D NULL, - .ioapic_phys_id_map =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D numachip_phys_pkg_id, =20 @@ -266,8 +264,6 @@ static const struct apic apic_numachip2 =20 .disable_esr =3D 0, =20 - .check_apicid_used =3D NULL, - .ioapic_phys_id_map =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D numachip_phys_pkg_id, =20 --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -48,7 +48,6 @@ static struct apic apic_default __ro_aft =20 .max_apic_id =3D 0xFE, .get_apic_id =3D default_get_apic_id, - .set_apic_id =3D NULL, =20 .calc_dest_apicid =3D apic_flat_calc_apicid, =20 --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -150,8 +150,6 @@ static struct apic apic_x2apic_phys __ro =20 .disable_esr =3D 0, =20 - .check_apicid_used =3D NULL, - .ioapic_phys_id_map =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D x2apic_phys_pkg_id, =20 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -811,8 +811,6 @@ static struct apic apic_x2apic_uv_x __ro =20 .disable_esr =3D 0, =20 - .check_apicid_used =3D NULL, - .ioapic_phys_id_map =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, .phys_pkg_id =3D uv_phys_pkg_id, From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6879CEB64DC for ; Mon, 17 Jul 2023 23:32:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231655AbjGQXcf (ORCPT ); Mon, 17 Jul 2023 19:32:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231649AbjGQXcZ (ORCPT ); Mon, 17 Jul 2023 19:32:25 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C035C173A for ; Mon, 17 Jul 2023 16:31:27 -0700 (PDT) Message-ID: <20230717223225.815511531@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635746; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=tK1J3NRXP+lZRakGxXxjlSskh2I2ErwFZpn4/I2Qug8=; b=z+8xD/FiHJ9sr/IZ44QFKo65qGiyCig5Yc9pVVKeRxKO5Om5Susr9bNe7gA/wQoR+WSXo1 sIkwkb2ciVPCECWtrGSkoKg4j15iGKWvESRI0sf1I79+p8I/tHGy9OQHO38rLLhgvwFqhP qhPpCBWARB3+wFKelnZ8IVeRQwPYPsrEQpzBpAe985A5er13fJ0f8z/0eiWtYif/HYaCkm yqw+iMUa0PzuwnqtoBEHqlbPlE1YyGjPKvb5RUdDGt9gT/9TXVKR+GzZCGULxJsSlY62Ri MSgWRww7o0hy7eJd4Xi5Mz76uYfVNtZ6gh6r0FnH2NkPmGG7wftxpgNfDce+4A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635746; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=tK1J3NRXP+lZRakGxXxjlSskh2I2ErwFZpn4/I2Qug8=; b=qQ7Hm4RcJivTCfhDxjNKiu6l+PxZgwY9s/INSRHRjcQSHhxJnOCdVav5b4/dGHJIE4wQhO w4PkOGEA+hvCNEAg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 46/58] x86/apic/noop: Tidy up the code References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:46 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" First of all apic_noop can't be probed because it's not registered. So there is no point for implementing a probe callback. The machine is rightfully to die when that is invoked. Remove the gunk and tidy up the other space consuming dummy callbacks. This gunk should simply die. Nothing should ever invoke APIC callbacks once this is installed, But that's a differrent story for another round of cleanups. The comment on top of this file which was intentionally left in place tells exactly why this is needed: voodoo programming. In fact the kernel of today should just outright refuse to boot on a system with no (functional) local APIC. That would spare tons of #ifdeffery and other nonsense. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/kernel/apic/apic_noop.c | 38 ++++++++--------------------------= ---- 1 file changed, 8 insertions(+), 30 deletions(-) --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -8,6 +8,10 @@ * Though in case if apic is disabled (for some reason) we try * to not uglify the caller's code and allow to call (some) apic routines * like self-ipi, etc... + * + * FIXME: Remove this gunk. The above argument which was intentionally left + * in place is silly to begin with because none of the callbacks except for + * APIC::read/write() have a WARN_ON_ONCE() in them. Sigh... */ #include #include @@ -21,35 +25,10 @@ static void noop_send_IPI_allbutself(int static void noop_send_IPI_all(int vector) { } static void noop_send_IPI_self(int vector) { } static void noop_apic_icr_write(u32 low, u32 id) { } - -static int noop_wakeup_secondary_cpu(int apicid, unsigned long start_eip) -{ - return -1; -} - -static u64 noop_apic_icr_read(void) -{ - return 0; -} - -static int noop_phys_pkg_id(int cpuid_apic, int index_msb) -{ - return 0; -} - -static unsigned int noop_get_apic_id(unsigned long x) -{ - return 0; -} - -static int noop_probe(void) -{ - /* - * NOOP apic should not ever be - * enabled via probe routine - */ - return 0; -} +static int noop_wakeup_secondary_cpu(int apicid, unsigned long start_eip) = { return -1; } +static u64 noop_apic_icr_read(void) { return 0; } +static int noop_phys_pkg_id(int cpuid_apic, int index_msb) { return 0; } +static unsigned int noop_get_apic_id(unsigned long x) { return 0; } =20 static u32 noop_apic_read(u32 reg) { @@ -64,7 +43,6 @@ static void noop_apic_write(u32 reg, u32 =20 struct apic apic_noop __ro_after_init =3D { .name =3D "noop", - .probe =3D noop_probe, =20 .delivery_mode =3D APIC_DELIVERY_MODE_FIXED, .dest_mode_logical =3D true, From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD252C0015E for ; Mon, 17 Jul 2023 23:24:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231612AbjGQXYe (ORCPT ); Mon, 17 Jul 2023 19:24:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42672 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231588AbjGQXYc (ORCPT ); Mon, 17 Jul 2023 19:24:32 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32CB4172B for ; Mon, 17 Jul 2023 16:23:54 -0700 (PDT) Message-ID: <20230717223225.875917164@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635748; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=wxrnNYixn5b66YHMby8R35XHg/cZJKLdob6j5LDKR34=; b=4jbF+loA5MmNcX9xrW2VA1TqlniFCgWOjn2VSmIeFyJROwzIs1VWh7L2OrDZSOKZoTN36a uNU6jSv/ImBp30vC1bCOGXVzjmDpT4D78z9AWgfC5ZJbwIQ3klyiYWmu3tDqO61GdIvo/3 z/MhUoMHIyw1izg+1731m01BxU7wnEw9GKNEh+BP2fPbtJOJVX6RdrSjxyMefwkuufEEws 2x658UcEL/C+zSeBQs1GJJOzKWxTwydOHbjeEaKKAcj9SzngK2tusRhLWx1jYRlNOPL9vb MDtiUYIEy1rRt1gw8FvRDrcgWmQGen618sHW9uDkhq9TKXd6pZB4A52dfO7iaA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635748; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=wxrnNYixn5b66YHMby8R35XHg/cZJKLdob6j5LDKR34=; b=8xP9mF4TT1//H/ZA9IWRe42Gv7ervYBoGOxm491kMFNItU+Dit9gzN4tbijAnY4hCr+PWf 6U9QVME66wQFvcAg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 47/58] x86/apic: Remove pointless arguments from [native_]eoi_write() References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:47 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Every callsite hands in the same constants which is a pointless exercise and cannot be optimized by the compiler due to the indirect calls. Use the constants in the eoi() callbacks and remove the arguments. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) Reviewed-by: Wei Liu --- arch/x86/hyperv/hv_apic.c | 6 +++--- arch/x86/include/asm/apic.h | 17 +++++++++++------ arch/x86/kernel/apic/apic.c | 8 ++++---- arch/x86/kernel/apic/apic_flat_64.c | 4 ++-- arch/x86/kernel/apic/apic_noop.c | 3 ++- arch/x86/kernel/apic/apic_numachip.c | 4 ++-- arch/x86/kernel/apic/bigsmp_32.c | 2 +- arch/x86/kernel/apic/probe_32.c | 2 +- arch/x86/kernel/apic/x2apic_cluster.c | 2 +- arch/x86/kernel/apic/x2apic_phys.c | 2 +- arch/x86/kernel/apic/x2apic_uv_x.c | 2 +- arch/x86/kernel/kvm.c | 6 +++--- arch/x86/xen/apic.c | 7 ++++++- 13 files changed, 38 insertions(+), 27 deletions(-) --- a/arch/x86/hyperv/hv_apic.c +++ b/arch/x86/hyperv/hv_apic.c @@ -86,14 +86,14 @@ static void hv_apic_write(u32 reg, u32 v } } =20 -static void hv_apic_eoi_write(u32 reg, u32 val) +static void hv_apic_eoi_write(void) { struct hv_vp_assist_page *hvp =3D hv_vp_assist_page[smp_processor_id()]; =20 if (hvp && (xchg(&hvp->apic_assist, 0) & 0x1)) return; =20 - wrmsr(HV_X64_MSR_EOI, val, 0); + wrmsr(HV_X64_MSR_EOI, APIC_EOI_ACK, 0); } =20 static bool cpu_is_self(int cpu) @@ -310,7 +310,7 @@ void __init hv_apic_init(void) * lazy EOI when available, but the same accessor works for * both xapic and x2apic because the field layout is the same. */ - apic_set_eoi_write(hv_apic_eoi_write); + apic_set_eoi_cb(hv_apic_eoi_write); if (!x2apic_enabled()) { apic->read =3D hv_apic_read; apic->write =3D hv_apic_write; --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -98,6 +98,11 @@ static inline u32 native_apic_mem_read(u return *((volatile u32 *)(APIC_BASE + reg)); } =20 +static inline void native_apic_mem_eoi(void) +{ + native_apic_mem_write(APIC_EOI, APIC_EOI_ACK); +} + extern void native_apic_icr_write(u32 low, u32 id); extern u64 native_apic_icr_read(void); =20 @@ -189,7 +194,7 @@ static inline void native_apic_msr_write wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); } =20 -static inline void native_apic_msr_eoi_write(u32 reg, u32 v) +static inline void native_apic_msr_eoi(void) { __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); } @@ -250,8 +255,8 @@ struct irq_data; */ struct apic { /* Hotpath functions first */ - void (*eoi_write)(u32 reg, u32 v); - void (*native_eoi_write)(u32 reg, u32 v); + void (*eoi)(void); + void (*native_eoi)(void); void (*write)(u32 reg, u32 v); u32 (*read)(u32 reg); =20 @@ -351,7 +356,7 @@ static inline void apic_write(u32 reg, u =20 static inline void apic_eoi(void) { - apic->eoi_write(APIC_EOI, APIC_EOI_ACK); + apic->eoi(); } =20 static inline u64 apic_icr_read(void) @@ -380,7 +385,7 @@ static inline bool apic_id_valid(u32 api return apic_id <=3D apic->max_apic_id; } =20 -extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); +extern void __init apic_set_eoi_cb(void (*eoi)(void)); =20 #else /* CONFIG_X86_LOCAL_APIC */ =20 @@ -391,7 +396,7 @@ static inline u64 apic_icr_read(void) { static inline void apic_icr_write(u32 low, u32 high) { } static inline void apic_wait_icr_idle(void) { } static inline u32 safe_apic_wait_icr_idle(void) { return 0; } -static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} +static inline void apic_set_eoi(void (*eoi)(void)) {} =20 #endif /* CONFIG_X86_LOCAL_APIC */ =20 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2501,15 +2501,15 @@ void __init acpi_wake_cpu_handler_update * interrupts disabled, so we know this does not race with actual APIC dri= ver * use. */ -void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) +void __init apic_set_eoi_cb(void (*eoi)(void)) { struct apic **drv; =20 for (drv =3D __apicdrivers; drv < __apicdrivers_end; drv++) { /* Should happen once for each apic */ - WARN_ON((*drv)->eoi_write =3D=3D eoi_write); - (*drv)->native_eoi_write =3D (*drv)->eoi_write; - (*drv)->eoi_write =3D eoi_write; + WARN_ON((*drv)->eoi =3D=3D eoi); + (*drv)->native_eoi =3D (*drv)->eoi; + (*drv)->eoi =3D eoi; } } =20 --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -106,7 +106,7 @@ static struct apic apic_flat __ro_after_ =20 .read =3D native_apic_mem_read, .write =3D native_apic_mem_write, - .eoi_write =3D native_apic_mem_write, + .eoi =3D native_apic_mem_eoi, .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, .wait_icr_idle =3D apic_mem_wait_icr_idle, @@ -182,7 +182,7 @@ static struct apic apic_physflat __ro_af =20 .read =3D native_apic_mem_read, .write =3D native_apic_mem_write, - .eoi_write =3D native_apic_mem_write, + .eoi =3D native_apic_mem_eoi, .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, .wait_icr_idle =3D apic_mem_wait_icr_idle, --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -29,6 +29,7 @@ static int noop_wakeup_secondary_cpu(int static u64 noop_apic_icr_read(void) { return 0; } static int noop_phys_pkg_id(int cpuid_apic, int index_msb) { return 0; } static unsigned int noop_get_apic_id(unsigned long x) { return 0; } +static void noop_apic_eoi(void) { } =20 static u32 noop_apic_read(u32 reg) { @@ -71,7 +72,7 @@ struct apic apic_noop __ro_after_init =3D =20 .read =3D noop_apic_read, .write =3D noop_apic_write, - .eoi_write =3D noop_apic_write, + .eoi =3D noop_apic_eoi, .icr_read =3D noop_apic_icr_read, .icr_write =3D noop_apic_icr_write, }; --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -247,7 +247,7 @@ static const struct apic apic_numachip1 =20 .read =3D native_apic_mem_read, .write =3D native_apic_mem_write, - .eoi_write =3D native_apic_mem_write, + .eoi =3D native_apic_mem_eoi, .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, }; @@ -284,7 +284,7 @@ static const struct apic apic_numachip2 =20 .read =3D native_apic_mem_read, .write =3D native_apic_mem_write, - .eoi_write =3D native_apic_mem_write, + .eoi =3D native_apic_mem_eoi, .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, }; --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -105,7 +105,7 @@ static struct apic apic_bigsmp __ro_afte =20 .read =3D native_apic_mem_read, .write =3D native_apic_mem_write, - .eoi_write =3D native_apic_mem_write, + .eoi =3D native_apic_mem_eoi, .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, .wait_icr_idle =3D apic_mem_wait_icr_idle, --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -60,7 +60,7 @@ static struct apic apic_default __ro_aft =20 .read =3D native_apic_mem_read, .write =3D native_apic_mem_write, - .eoi_write =3D native_apic_mem_write, + .eoi =3D native_apic_mem_eoi, .icr_read =3D native_apic_icr_read, .icr_write =3D native_apic_icr_write, .wait_icr_idle =3D apic_mem_wait_icr_idle, --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -254,7 +254,7 @@ static struct apic apic_x2apic_cluster _ =20 .read =3D native_apic_msr_read, .write =3D native_apic_msr_write, - .eoi_write =3D native_apic_msr_eoi_write, + .eoi =3D native_apic_msr_eoi, .icr_read =3D native_x2apic_icr_read, .icr_write =3D native_x2apic_icr_write, }; --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -169,7 +169,7 @@ static struct apic apic_x2apic_phys __ro =20 .read =3D native_apic_msr_read, .write =3D native_apic_msr_write, - .eoi_write =3D native_apic_msr_eoi_write, + .eoi =3D native_apic_msr_eoi, .icr_read =3D native_x2apic_icr_read, .icr_write =3D native_x2apic_icr_write, }; --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -831,7 +831,7 @@ static struct apic apic_x2apic_uv_x __ro =20 .read =3D native_apic_msr_read, .write =3D native_apic_msr_write, - .eoi_write =3D native_apic_msr_eoi_write, + .eoi =3D native_apic_msr_eoi, .icr_read =3D native_x2apic_icr_read, .icr_write =3D native_x2apic_icr_write, }; --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -332,7 +332,7 @@ static void kvm_register_steal_time(void =20 static DEFINE_PER_CPU_DECRYPTED(unsigned long, kvm_apic_eoi) =3D KVM_PV_EO= I_DISABLED; =20 -static notrace void kvm_guest_apic_eoi_write(u32 reg, u32 val) +static notrace void kvm_guest_apic_eoi_write(void) { /** * This relies on __test_and_clear_bit to modify the memory @@ -343,7 +343,7 @@ static notrace void kvm_guest_apic_eoi_w */ if (__test_and_clear_bit(KVM_PV_EOI_BIT, this_cpu_ptr(&kvm_apic_eoi))) return; - apic->native_eoi_write(APIC_EOI, APIC_EOI_ACK); + apic->native_eoi(); } =20 static void kvm_guest_cpu_init(void) @@ -825,7 +825,7 @@ static void __init kvm_guest_init(void) } =20 if (kvm_para_has_feature(KVM_FEATURE_PV_EOI)) - apic_set_eoi_write(kvm_guest_apic_eoi_write); + apic_set_eoi_cb(kvm_guest_apic_eoi_write); =20 if (kvm_para_has_feature(KVM_FEATURE_ASYNC_PF_INT) && kvmapf) { static_branch_enable(&kvm_async_pf_enabled); --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -81,6 +81,11 @@ static void xen_apic_write(u32 reg, u32 WARN(1,"register: %x, value: %x\n", reg, val); } =20 +static void xen_apic_eoi(void) +{ + WARN_ON_ONCE(1); +} + static u64 xen_apic_icr_read(void) { return 0; @@ -147,7 +152,7 @@ static struct apic xen_pv_apic =3D { #endif .read =3D xen_apic_read, .write =3D xen_apic_write, - .eoi_write =3D xen_apic_write, + .eoi =3D xen_apic_eoi, =20 .icr_read =3D xen_apic_icr_read, .icr_write =3D xen_apic_icr_write, From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62BD5EB64DC for ; Mon, 17 Jul 2023 23:36:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231190AbjGQXgv (ORCPT ); Mon, 17 Jul 2023 19:36:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231661AbjGQXgp (ORCPT ); Mon, 17 Jul 2023 19:36:45 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02EFD170D for ; Mon, 17 Jul 2023 16:35:56 -0700 (PDT) Message-ID: <20230717223225.937554398@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635749; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=iCsxfuqhz4Fo6ZGAppoqBTBjAoRzkGry7KPBD+0gZyY=; b=yrod9RYFIU1ubI925w14spnCcuCVMcCr4iYLMcuitbmxUYOOCOL1ggyXrpJaVe7OSOMQV/ GyS0JsyZWVl6ksXYnahXR0Abzz8mTq3oAX2/kMtA9s4gTg2OgmczD3ebZ6HweOQJSy4DVw /sS/a0TuD3wO8u31cQBUUkm/fY5WAp7bo3gnXOanrquEecXvFw/NauyD/bId89VhPlG5jI zPmYqfr3lduc60VMumb0j2KVEUxgqwAj/EpHExbehPyLMhIsT7U4yVHRnXNPSIOkQgWHRs ljZca4pdokvOkv89cmNk9aqmAef14s+HdbZI6zAVu+QFL1iCAjLPAh76XVjZsA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635749; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=iCsxfuqhz4Fo6ZGAppoqBTBjAoRzkGry7KPBD+0gZyY=; b=KgbgIgIjJ3pCo5ngii+ou3DNwDmhvHcKKy4N4E2rxsuUk4EIhVLtXI3Pph1+1f7vZUrpxD k3gVibrpUT4OIKBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 48/58] x86/apic: Nuke ack_APIC_irq() References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:49 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Yet another wrapper of a wrapper gone along with the outdated comment that this compiles to a single instruction. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) Reviewed-by: Wei Liu --- arch/x86/hyperv/hv_init.c | 2 +- arch/x86/include/asm/apic.h | 10 ---------- arch/x86/kernel/apic/apic.c | 10 +++++----- arch/x86/kernel/apic/io_apic.c | 4 ++-- arch/x86/kernel/apic/vector.c | 4 ++-- arch/x86/kernel/cpu/acrn.c | 2 +- arch/x86/kernel/cpu/mce/amd.c | 2 +- arch/x86/kernel/cpu/mce/threshold.c | 2 +- arch/x86/kernel/cpu/mshyperv.c | 4 ++-- arch/x86/kernel/irq.c | 14 +++++++------- arch/x86/kernel/irq_work.c | 2 +- arch/x86/kernel/kvm.c | 2 +- arch/x86/kernel/smp.c | 8 ++++---- arch/x86/xen/enlighten_hvm.c | 2 +- 14 files changed, 29 insertions(+), 39 deletions(-) --- a/arch/x86/hyperv/hv_init.c +++ b/arch/x86/hyperv/hv_init.c @@ -161,7 +161,7 @@ static inline bool hv_reenlightenment_av =20 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_reenlightenment) { - ack_APIC_irq(); + apic_eoi(); inc_irq_stat(irq_hv_reenlightenment_count); schedule_delayed_work(&hv_reenlightenment_work, HZ/10); } --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -402,16 +402,6 @@ static inline void apic_set_eoi(void (*e =20 extern void apic_ack_irq(struct irq_data *data); =20 -static inline void ack_APIC_irq(void) -{ - /* - * ack_APIC_irq() actually gets compiled as a single instruction - * ... yummie. - */ - apic_eoi(); -} - - static inline bool lapic_vector_set_in_irr(unsigned int vector) { u32 irr =3D apic_read(APIC_IRR + (vector / 32 * 0x10)); --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1076,7 +1076,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_apic_timer { struct pt_regs *old_regs =3D set_irq_regs(regs); =20 - ack_APIC_irq(); + apic_eoi(); trace_local_timer_entry(LOCAL_TIMER_VECTOR); local_apic_timer_interrupt(); trace_local_timer_exit(LOCAL_TIMER_VECTOR); @@ -1480,7 +1480,7 @@ static bool apic_check_and_ack(union api * per set bit. */ for_each_set_bit(bit, isr->map, APIC_IR_BITS) - ack_APIC_irq(); + apic_eoi(); return true; } =20 @@ -1492,7 +1492,7 @@ static bool apic_check_and_ack(union api * interrupt from previous kernel might still have ISR bit set. * * Most probably by now the CPU has serviced that pending interrupt and it - * might not have done the ack_APIC_irq() because it thought, interrupt + * might not have done the apic_eoi() because it thought, interrupt * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear * the ISR bit and cpu thinks it has already serviced the interrupt. Hence * a vector might get locked. It was noticed for timer irq (vector @@ -2146,7 +2146,7 @@ static noinline void handle_spurious_int if (v & (1 << (vector & 0x1f))) { pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n", vector, smp_processor_id()); - ack_APIC_irq(); + apic_eoi(); } else { pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n", vector, smp_processor_id()); @@ -2197,7 +2197,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_error_inte if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ apic_write(APIC_ESR, 0); v =3D apic_read(APIC_ESR); - ack_APIC_irq(); + apic_eoi(); atomic_inc(&irq_err_count); =20 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1823,7 +1823,7 @@ static void ioapic_ack_level(struct irq_ * We must acknowledge the irq before we move it or the acknowledge will * not propagate properly. */ - ack_APIC_irq(); + apic_eoi(); =20 /* * Tail end of clearing remote IRR bit (either by delivering the EOI @@ -2046,7 +2046,7 @@ static void unmask_lapic_irq(struct irq_ =20 static void ack_lapic_irq(struct irq_data *data) { - ack_APIC_irq(); + apic_eoi(); } =20 static struct irq_chip lapic_chip __read_mostly =3D { --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -885,7 +885,7 @@ static int apic_retrigger_irq(struct irq void apic_ack_irq(struct irq_data *irqd) { irq_move_irq(irqd); - ack_APIC_irq(); + apic_eoi(); } =20 void apic_ack_edge(struct irq_data *irqd) @@ -940,7 +940,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_irq_move_c struct apic_chip_data *apicd; struct hlist_node *tmp; =20 - ack_APIC_irq(); + apic_eoi(); /* Prevent vectors vanishing under us */ raw_spin_lock(&vector_lock); =20 --- a/arch/x86/kernel/cpu/acrn.c +++ b/arch/x86/kernel/cpu/acrn.c @@ -51,7 +51,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_acrn_hv_ca * will block the interrupt whose vector is lower than * HYPERVISOR_CALLBACK_VECTOR. */ - ack_APIC_irq(); + apic_eoi(); inc_irq_stat(irq_hv_callback_count); =20 if (acrn_intr_handler) --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -759,7 +759,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_e inc_irq_stat(irq_deferred_error_count); deferred_error_int_vector(); trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); - ack_APIC_irq(); + apic_eoi(); } =20 /* --- a/arch/x86/kernel/cpu/mce/threshold.c +++ b/arch/x86/kernel/cpu/mce/threshold.c @@ -27,5 +27,5 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_threshold) inc_irq_stat(irq_threshold_count); mce_threshold_vector(); trace_threshold_apic_exit(THRESHOLD_APIC_VECTOR); - ack_APIC_irq(); + apic_eoi(); } --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -119,7 +119,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_cal vmbus_handler(); =20 if (ms_hyperv.hints & HV_DEPRECATING_AEOI_RECOMMENDED) - ack_APIC_irq(); + apic_eoi(); =20 set_irq_regs(old_regs); } @@ -147,7 +147,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_sti if (hv_stimer0_handler) hv_stimer0_handler(); add_interrupt_randomness(HYPERV_STIMER0_VECTOR); - ack_APIC_irq(); + apic_eoi(); =20 set_irq_regs(old_regs); } --- a/arch/x86/kernel/irq.c +++ b/arch/x86/kernel/irq.c @@ -49,7 +49,7 @@ void ack_bad_irq(unsigned int irq) * completely. * But only ack when the APIC is enabled -AK */ - ack_APIC_irq(); + apic_eoi(); } =20 #define irq_stats(x) (&per_cpu(irq_stat, x)) @@ -256,7 +256,7 @@ DEFINE_IDTENTRY_IRQ(common_interrupt) if (likely(!IS_ERR_OR_NULL(desc))) { handle_irq(desc, regs); } else { - ack_APIC_irq(); + apic_eoi(); =20 if (desc =3D=3D VECTOR_UNUSED) { pr_emerg_ratelimited("%s: %d.%u No irq handler for vector\n", @@ -280,7 +280,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_x86_platfo { struct pt_regs *old_regs =3D set_irq_regs(regs); =20 - ack_APIC_irq(); + apic_eoi(); trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR); inc_irq_stat(x86_platform_ipis); if (x86_platform_ipi_callback) @@ -310,7 +310,7 @@ EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wa */ DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm_posted_intr_ipi) { - ack_APIC_irq(); + apic_eoi(); inc_irq_stat(kvm_posted_intr_ipis); } =20 @@ -319,7 +319,7 @@ DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm */ DEFINE_IDTENTRY_SYSVEC(sysvec_kvm_posted_intr_wakeup_ipi) { - ack_APIC_irq(); + apic_eoi(); inc_irq_stat(kvm_posted_intr_wakeup_ipis); kvm_posted_intr_wakeup_handler(); } @@ -329,7 +329,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_kvm_posted */ DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm_posted_intr_nested_ipi) { - ack_APIC_irq(); + apic_eoi(); inc_irq_stat(kvm_posted_intr_nested_ipis); } #endif @@ -401,6 +401,6 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_thermal) inc_irq_stat(irq_thermal_count); smp_thermal_vector(); trace_thermal_apic_exit(THERMAL_APIC_VECTOR); - ack_APIC_irq(); + apic_eoi(); } #endif --- a/arch/x86/kernel/irq_work.c +++ b/arch/x86/kernel/irq_work.c @@ -16,7 +16,7 @@ #ifdef CONFIG_X86_LOCAL_APIC DEFINE_IDTENTRY_SYSVEC(sysvec_irq_work) { - ack_APIC_irq(); + apic_eoi(); trace_irq_work_entry(IRQ_WORK_VECTOR); inc_irq_stat(apic_irq_work_irqs); irq_work_run(); --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -291,7 +291,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_kvm_asyncp struct pt_regs *old_regs =3D set_irq_regs(regs); u32 token; =20 - ack_APIC_irq(); + apic_eoi(); =20 inc_irq_stat(irq_hv_callback_count); =20 --- a/arch/x86/kernel/smp.c +++ b/arch/x86/kernel/smp.c @@ -135,7 +135,7 @@ static int smp_stop_nmi_callback(unsigne */ DEFINE_IDTENTRY_SYSVEC(sysvec_reboot) { - ack_APIC_irq(); + apic_eoi(); cpu_emergency_disable_virtualization(); stop_this_cpu(NULL); } @@ -268,7 +268,7 @@ static void native_stop_other_cpus(int w */ DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_reschedule_ipi) { - ack_APIC_irq(); + apic_eoi(); trace_reschedule_entry(RESCHEDULE_VECTOR); inc_irq_stat(irq_resched_count); scheduler_ipi(); @@ -277,7 +277,7 @@ DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_res =20 DEFINE_IDTENTRY_SYSVEC(sysvec_call_function) { - ack_APIC_irq(); + apic_eoi(); trace_call_function_entry(CALL_FUNCTION_VECTOR); inc_irq_stat(irq_call_count); generic_smp_call_function_interrupt(); @@ -286,7 +286,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_call_funct =20 DEFINE_IDTENTRY_SYSVEC(sysvec_call_function_single) { - ack_APIC_irq(); + apic_eoi(); trace_call_function_single_entry(CALL_FUNCTION_SINGLE_VECTOR); inc_irq_stat(irq_call_count); generic_smp_call_function_single_interrupt(); --- a/arch/x86/xen/enlighten_hvm.c +++ b/arch/x86/xen/enlighten_hvm.c @@ -132,7 +132,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_xen_hvm_ca struct pt_regs *old_regs =3D set_irq_regs(regs); =20 if (xen_percpu_upcall) - ack_APIC_irq(); + apic_eoi(); =20 inc_irq_stat(irq_hv_callback_count); From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67382C0015E for ; Mon, 17 Jul 2023 23:20:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231532AbjGQXUj (ORCPT ); Mon, 17 Jul 2023 19:20:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231521AbjGQXUe (ORCPT ); Mon, 17 Jul 2023 19:20:34 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BAE591B3 for ; Mon, 17 Jul 2023 16:19:46 -0700 (PDT) Message-ID: <20230717223225.997925757@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635751; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=9TaSlhjUTakFiVj1azrlzZ2xVg2Xkr4O8C5JrwSXaPY=; b=w1ZbVj5JoX+S2m2HtC951EaBUqWGWCI2c5QAVVr2tUm4sfpNycBLzdjLWi4mmhnbD9OxXN 7zIChhVge0gA93t2mlqOtoO7Ki49d8BhlSQizly6WMUwwYQ5gYuOqqXwbwgwKTImc80hxA ufdLZxuiBV2GYtHcSaAYjMnYT5S2T+BliY3239Qt8Y64MKDQTK9DwtAAlnWGV15n/JS00I ftHfyiwOtSyd+pe38RWMjZakYR+7zrnwLr/FHjC0pI9NwaKAKJKqzvJViqLmHb8h4VJAPi y3KsurgSAS760ihHk6YteCeVkJ327STQa9rCsXOe0Q0BOj6D1U2p6aOpqyzA2A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635751; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=9TaSlhjUTakFiVj1azrlzZ2xVg2Xkr4O8C5JrwSXaPY=; b=UyPlwkBARb1hXbyifHDOgDybuzN/RtN64FgVFT9nLzHpECycP0TApiv3hXvGkY1RgpJpps AOsJDS7yQX55yVBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 49/58] x86/apic: Wrap apic->native_eoi() into a helper References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:51 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Prepare for converting the hotpath APIC callbacks to static calls. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 5 +++++ arch/x86/kernel/kvm.c | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -359,6 +359,11 @@ static inline void apic_eoi(void) apic->eoi(); } =20 +static inline void apic_native_eoi(void) +{ + apic->native_eoi(); +} + static inline u64 apic_icr_read(void) { return apic->icr_read(); --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -343,7 +343,7 @@ static notrace void kvm_guest_apic_eoi_w */ if (__test_and_clear_bit(KVM_PV_EOI_BIT, this_cpu_ptr(&kvm_apic_eoi))) return; - apic->native_eoi(); + apic_native_eoi(); } =20 static void kvm_guest_cpu_init(void) From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA837EB64DC for ; Mon, 17 Jul 2023 23:20:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231517AbjGQXU3 (ORCPT ); Mon, 17 Jul 2023 19:20:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231512AbjGQXU0 (ORCPT ); Mon, 17 Jul 2023 19:20:26 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE6C31709 for ; Mon, 17 Jul 2023 16:19:40 -0700 (PDT) Message-ID: <20230717223226.058365439@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635753; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=eXPzx8NJQYkjuBlJm5EN8V5tBON4kRyyGhZ2fdxQVSM=; b=G7xolB3Tb4xUlMmTwsM/swv8QsQ8macQRaBVs6lHmNCcvTdQCYTrT3NklviK1LTFLj4Gn8 HiG2o8xs307dfc14gAwIzW09rBQjV/itHp6k/P9Ex0J+kJtFVCG1vhS3loXE2wrr5ijrbA D08toNl6KosS2gomVDntd80tcxpn714BhD+y0DXtzOAsR+eS9ndNW7K3RJbqpUp6rFBjPS qGcgq4lkHWIljlwHuXa08I2GRq3A4RS5qZHoPkPAL95UT4qhm2EesGKK49iIy5nhVmv2Lt jYbUz1WWZsuNMyyK8XJoovS8WBdBbDgg2j3qe+ELEIyZ3akiI3qZ3zrNSQ06Tg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635753; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=eXPzx8NJQYkjuBlJm5EN8V5tBON4kRyyGhZ2fdxQVSM=; b=jPwIVS4XKP/v+npAc5tlVumfRxehevuONtfWaGqy8Bl6KwoICGE8TDZX/EURHWMx7deC7Y 7cEcCPPwaWx0McDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 50/58] x86/apic: Provide common init infrastructure References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:52 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for converting the hotpath APIC callbacks to static keys, provide common initialization inforastructure. Lift apic_install_drivers() from probe_64.c and convert all places which switch the apic instance by storing the pointer to use apic_install_driver() as a first step. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 2 + arch/x86/kernel/apic/Makefile | 2 - arch/x86/kernel/apic/apic.c | 31 ----------------------- arch/x86/kernel/apic/apic_flat_64.c | 6 ---- arch/x86/kernel/apic/bigsmp_32.c | 6 +--- arch/x86/kernel/apic/init.c | 47 +++++++++++++++++++++++++++++++= +++++ arch/x86/kernel/apic/probe_32.c | 5 +-- arch/x86/kernel/apic/probe_64.c | 13 --------- arch/x86/xen/apic.c | 10 ++----- 9 files changed, 59 insertions(+), 63 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -344,6 +344,8 @@ extern int lapic_can_unplug_cpu(void); =20 #ifdef CONFIG_X86_LOCAL_APIC =20 +void __init apic_install_driver(struct apic *driver); + static inline u32 apic_read(u32 reg) { return apic->read(reg); --- a/arch/x86/kernel/apic/Makefile +++ b/arch/x86/kernel/apic/Makefile @@ -7,7 +7,7 @@ # In particualr, smp_apic_timer_interrupt() is called in random places. KCOV_INSTRUMENT :=3D n =20 -obj-$(CONFIG_X86_LOCAL_APIC) +=3D apic.o apic_common.o apic_noop.o ipi.o v= ector.o +obj-$(CONFIG_X86_LOCAL_APIC) +=3D apic.o apic_common.o apic_noop.o ipi.o v= ector.o init.o obj-y +=3D hw_nmi.o =20 obj-$(CONFIG_X86_IO_APIC) +=3D io_apic.o --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -236,8 +236,7 @@ static int modern_apic(void) */ static void __init apic_disable(void) { - pr_info("APIC: switched to apic NOOP\n"); - apic =3D &apic_noop; + apic_install_driver(&apic_noop); } =20 void native_apic_icr_write(u32 low, u32 id) @@ -2485,34 +2484,6 @@ u32 x86_msi_msg_get_destid(struct msi_ms } EXPORT_SYMBOL_GPL(x86_msi_msg_get_destid); =20 -#ifdef CONFIG_X86_64 -void __init acpi_wake_cpu_handler_update(wakeup_cpu_handler handler) -{ - struct apic **drv; - - for (drv =3D __apicdrivers; drv < __apicdrivers_end; drv++) - (*drv)->wakeup_secondary_cpu_64 =3D handler; -} -#endif - -/* - * Override the generic EOI implementation with an optimized version. - * Only called during early boot when only one CPU is active and with - * interrupts disabled, so we know this does not race with actual APIC dri= ver - * use. - */ -void __init apic_set_eoi_cb(void (*eoi)(void)) -{ - struct apic **drv; - - for (drv =3D __apicdrivers; drv < __apicdrivers_end; drv++) { - /* Should happen once for each apic */ - WARN_ON((*drv)->eoi =3D=3D eoi); - (*drv)->native_eoi =3D (*drv)->eoi; - (*drv)->eoi =3D eoi; - } -} - static void __init apic_bsp_up_setup(void) { #ifdef CONFIG_X86_64 --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -143,11 +143,7 @@ static int physflat_acpi_madt_oem_check( =20 static int physflat_probe(void) { - if (apic =3D=3D &apic_physflat || num_possible_cpus() > 8 || - jailhouse_paravirt()) - return 1; - - return 0; + return apic =3D=3D &apic_physflat || num_possible_cpus() > 8 || jailhouse= _paravirt(); } =20 static struct apic apic_physflat __ro_after_init =3D { --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -119,10 +119,8 @@ bool __init apic_bigsmp_possible(bool cm =20 void __init apic_bigsmp_force(void) { - if (apic !=3D &apic_bigsmp) { - apic =3D &apic_bigsmp; - pr_info("Overriding APIC driver with bigsmp\n"); - } + if (apic !=3D &apic_bigsmp) + apic_install_driver(&apic_noop); } =20 apic_driver(apic_bigsmp); --- /dev/null +++ b/arch/x86/kernel/apic/init.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-only +#define pr_fmt(fmt) "APIC: " fmt + +#include + +#include "local.h" + +void __init apic_install_driver(struct apic *driver) +{ + if (apic =3D=3D driver) + return; + + apic =3D driver; + + if (IS_ENABLED(CONFIG_X86_X2APIC) && apic->x2apic_set_max_apicid) + apic->max_apic_id =3D x2apic_max_apicid; + + pr_info("Switched APIC routing to: %s\n", driver->name); +} + +#ifdef CONFIG_X86_64 +void __init acpi_wake_cpu_handler_update(wakeup_cpu_handler handler) +{ + struct apic **drv; + + for (drv =3D __apicdrivers; drv < __apicdrivers_end; drv++) + (*drv)->wakeup_secondary_cpu_64 =3D handler; +} +#endif + +/* + * Override the generic EOI implementation with an optimized version. + * Only called during early boot when only one CPU is active and with + * interrupts disabled, so we know this does not race with actual APIC dri= ver + * use. + */ +void __init apic_set_eoi_cb(void (*eoi)(void)) +{ + struct apic **drv; + + for (drv =3D __apicdrivers; drv < __apicdrivers_end; drv++) { + /* Should happen once for each apic */ + WARN_ON((*drv)->eoi =3D=3D eoi); + (*drv)->native_eoi =3D (*drv)->eoi; + (*drv)->eoi =3D eoi; + } +} --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -82,7 +82,7 @@ static int __init parse_apic(char *arg) =20 for (drv =3D __apicdrivers; drv < __apicdrivers_end; drv++) { if (!strcmp((*drv)->name, arg)) { - apic =3D *drv; + apic_install_driver(*drv); cmdline_apic =3D 1; return 0; } @@ -129,7 +129,7 @@ void __init x86_32_probe_apic(void) =20 for (drv =3D __apicdrivers; drv < __apicdrivers_end; drv++) { if ((*drv)->probe()) { - apic =3D *drv; + apic_install_driver(*drv); break; } } @@ -137,5 +137,4 @@ void __init x86_32_probe_apic(void) if (drv =3D=3D __apicdrivers_end) panic("Didn't find an APIC driver"); } - printk(KERN_INFO "Using APIC driver %s\n", apic->name); } --- a/arch/x86/kernel/apic/probe_64.c +++ b/arch/x86/kernel/apic/probe_64.c @@ -13,19 +13,6 @@ =20 #include "local.h" =20 -static __init void apic_install_driver(struct apic *driver) -{ - if (apic =3D=3D driver) - return; - - apic =3D driver; - - if (IS_ENABLED(CONFIG_X86_X2APIC) && apic->x2apic_set_max_apicid) - apic->max_apic_id =3D x2apic_max_apicid; - - pr_info("Switched APIC routing to %s:\n", apic->name); -} - /* Select the appropriate APIC driver */ void __init x86_64_probe_apic(void) { --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -160,20 +160,16 @@ static struct apic xen_pv_apic =3D { =20 static void __init xen_apic_check(void) { - if (apic =3D=3D &xen_pv_apic) - return; - - pr_info("Switched APIC routing from %s to %s.\n", apic->name, - xen_pv_apic.name); - apic =3D &xen_pv_apic; + apic_install_driver(&xen_pv_apic); } + void __init xen_init_apic(void) { x86_apic_ops.io_apic_read =3D xen_io_apic_read; /* On PV guests the APIC CPUID bit is disabled so none of the * routines end up executing. */ if (!xen_initial_domain()) - apic =3D &xen_pv_apic; + apic_install_driver(&xen_pv_apic); =20 x86_platform.apic_post_init =3D xen_apic_check; } From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8EEAC001B0 for ; Mon, 17 Jul 2023 23:37:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231733AbjGQXhG (ORCPT ); Mon, 17 Jul 2023 19:37:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51264 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231700AbjGQXg6 (ORCPT ); Mon, 17 Jul 2023 19:36:58 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B72AA171C for ; Mon, 17 Jul 2023 16:36:07 -0700 (PDT) Message-ID: <20230717223226.118922473@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635754; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=SE1iSqYJ4ehwEamqhZ1Qn1Xh1qrFRO76iVIsUZ/pjC8=; b=r9CDm/xw+hI5tPivegSVDw2QhU4sENJsdZjGHyVr2s0woGUJ7h5Kl3iPBR9ksvCHNV+j63 JejyxjeVzibJQbwhS8x2/GWk0Sdkl74tUMa+l+lYxuhgxXuzCSjOqTnAhkCOF9VHgOLg33 LnRutsQEJEpwu1V3EHWTvmyWHJTo5a/B+BI1QR08X1GhiNGME3Z2uFMQvIo8SqfvH/v1Fi RcHIE0h24hqvG88KP8MmiSomsz3t+xV1Cf0kJdW7NLDE8okV9VwXT12lXuR+i1pY6l7CKx 6dJfSSKOIQ9qAcV27Aqybp65znOyEfMn2q6QIWkDgbwc61yGzqoFe5cXyZoqGQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635754; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=SE1iSqYJ4ehwEamqhZ1Qn1Xh1qrFRO76iVIsUZ/pjC8=; b=09GVELt/GpTAFjbYuMVdaAmm3ybHo2iSKr3KLK11c+j2xxCZJh+c8ziFYaC44xOt7Qb6GJ JWYDzE0WRZG3R0CA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 51/58] x86/apic: Provide apic_update_callback() References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:54 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are already two variants of update mechanism for particular callbacks and virtualization just writes into the data structure. Provide an interface and use a shadow data structure to preserve callbacks so they can be reapplied when the APIC driver is replaced. The extra data structure is intentional as any new callback needs to be also updated in the core code. This also prepares for static calls. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 25 +++++++++++++++++++++++++ arch/x86/kernel/apic/init.c | 39 ++++++++++++++++++++++++++++++++++++++- arch/x86/kernel/setup.c | 2 ++ 3 files changed, 65 insertions(+), 1 deletion(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -308,6 +308,23 @@ struct apic { char *name; }; =20 +struct apic_override { + void (*eoi)(void); + void (*native_eoi)(void); + void (*write)(u32 reg, u32 v); + u32 (*read)(u32 reg); + void (*send_IPI)(int cpu, int vector); + void (*send_IPI_mask)(const struct cpumask *mask, int vector); + void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); + void (*send_IPI_allbutself)(int vector); + void (*send_IPI_all)(int vector); + void (*send_IPI_self)(int vector); + u64 (*icr_read)(void); + void (*icr_write)(u32 low, u32 high); + int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); + int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip); +}; + /* * Pointer to the local APIC driver in use on this system (there's * always just one such driver in use - the kernel decides via an @@ -343,9 +360,17 @@ extern int lapic_can_unplug_cpu(void); #endif =20 #ifdef CONFIG_X86_LOCAL_APIC +extern struct apic_override __x86_apic_override; =20 +void __init apic_setup_apic_calls(void); void __init apic_install_driver(struct apic *driver); =20 +#define apic_update_callback(_callback, _fn) { \ + __x86_apic_override._callback =3D _fn; \ + apic->_callback =3D _fn; \ + pr_info("APIC::%s() replaced with %ps()\n", #_callback, _fn); \ +} + static inline u32 apic_read(u32 reg) { return apic->read(reg); --- a/arch/x86/kernel/apic/init.c +++ b/arch/x86/kernel/apic/init.c @@ -5,6 +5,37 @@ =20 #include "local.h" =20 +/* The container for function call overrides */ +struct apic_override __x86_apic_override __initdata; + +#define apply_override(__cb) \ + if (__x86_apic_override.__cb) \ + apic->__cb =3D __x86_apic_override.__cb + +static __init void restore_override_callbacks(void) +{ + apply_override(eoi); + apply_override(native_eoi); + apply_override(write); + apply_override(read); + apply_override(send_IPI); + apply_override(send_IPI_mask); + apply_override(send_IPI_mask_allbutself); + apply_override(send_IPI_allbutself); + apply_override(send_IPI_all); + apply_override(send_IPI_self); + apply_override(icr_read); + apply_override(icr_write); + apply_override(wakeup_secondary_cpu); + apply_override(wakeup_secondary_cpu_64); +} + +void __init apic_setup_apic_calls(void) +{ + /* Ensure that the default APIC has native_eoi populated */ + apic->native_eoi =3D apic->eoi; +} + void __init apic_install_driver(struct apic *driver) { if (apic =3D=3D driver) @@ -15,6 +46,13 @@ void __init apic_install_driver(struct a if (IS_ENABLED(CONFIG_X86_X2APIC) && apic->x2apic_set_max_apicid) apic->max_apic_id =3D x2apic_max_apicid; =20 + /* Copy the original eoi() callback as KVM/HyperV might overwrite it */ + if (!apic->native_eoi) + apic->native_eoi =3D apic->eoi; + + /* Apply any already installed callback overrides */ + restore_override_callbacks(); + pr_info("Switched APIC routing to: %s\n", driver->name); } =20 @@ -41,7 +79,6 @@ void __init apic_set_eoi_cb(void (*eoi)( for (drv =3D __apicdrivers; drv < __apicdrivers_end; drv++) { /* Should happen once for each apic */ WARN_ON((*drv)->eoi =3D=3D eoi); - (*drv)->native_eoi =3D (*drv)->eoi; (*drv)->eoi =3D eoi; } } --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1018,6 +1018,8 @@ void __init setup_arch(char **cmdline_p) =20 x86_report_nx(); =20 + apic_setup_apic_calls(); + if (acpi_mps_check()) { #ifdef CONFIG_X86_LOCAL_APIC apic_is_disabled =3D true; From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5C1AEB64DC for ; Mon, 17 Jul 2023 23:37:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231691AbjGQXhI (ORCPT ); Mon, 17 Jul 2023 19:37:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231709AbjGQXhC (ORCPT ); Mon, 17 Jul 2023 19:37:02 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99D76171E for ; Mon, 17 Jul 2023 16:36:09 -0700 (PDT) Message-ID: <20230717223226.178478466@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635756; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=UsgerkQJ/HhbA2AbXpANMMQuwJxS8UzMeOUa8nnw3cg=; b=LHZGeCb7nf55OTUyQt+8eKj8zeR2DihYQFUGhVGoktuWtOV4acP4pzMDaOeDrygIArkINK mfbXOoiR3rJe69kvbb5gFPf1IlBjn3LUWpMfxkFZPgOfhA60MBz4tkKH6r/RFUuSBewYN3 CqPLE+36Wr/F330F00c2Y6eWkL/91hnlvNh/4zUP3czKP+HbrRDFKvM3cJ8ZxPA+KmdXSo TkQyzZb7cgUzJcOgDETog+Q7XX89wUlS5zzB0ob0p/AqDIrgfGqQPF9+rabFcIDFOshG0W WgTv3RbzBeU08WLY9QUwOvLpDOgOOw2vCvnAJIYCFWRSUJ/vM7e9U8U8gknyMQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635756; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=UsgerkQJ/HhbA2AbXpANMMQuwJxS8UzMeOUa8nnw3cg=; b=qIM43iQoGCywG4fyfcL0617AiK0I9LgvnRCOzpI5eiGyRFKotQFqSDtvTo36EDtea4GmK0 pxON6r6oR5M491Ag== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 52/58] x86/apic: Replace acpi_wake_cpu_handler_update() and apic_set_eoi_cb() References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:55 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Switch them over to apic_update_callback() and remove the code. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) Reviewed-by: Wei Liu --- arch/x86/hyperv/hv_apic.c | 2 +- arch/x86/hyperv/hv_vtl.c | 2 +- arch/x86/include/asm/apic.h | 3 --- arch/x86/kernel/acpi/boot.c | 2 +- arch/x86/kernel/apic/init.c | 27 --------------------------- arch/x86/kernel/kvm.c | 2 +- 6 files changed, 4 insertions(+), 34 deletions(-) --- a/arch/x86/hyperv/hv_apic.c +++ b/arch/x86/hyperv/hv_apic.c @@ -310,7 +310,7 @@ void __init hv_apic_init(void) * lazy EOI when available, but the same accessor works for * both xapic and x2apic because the field layout is the same. */ - apic_set_eoi_cb(hv_apic_eoi_write); + apic_update_callback(eoi, hv_apic_eoi_write); if (!x2apic_enabled()) { apic->read =3D hv_apic_read; apic->write =3D hv_apic_write; --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -222,7 +222,7 @@ static int __init hv_vtl_early_init(void "Please add 'noxsave' to the kernel command line.\n"); =20 real_mode_header =3D &hv_vtl_real_mode_header; - apic->wakeup_secondary_cpu_64 =3D hv_vtl_wakeup_secondary_cpu; + apic_update_callback(wakeup_secondary_cpu_64, hv_vtl_wakeup_secondary_cpu= ); =20 return 0; } --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -417,8 +417,6 @@ static inline bool apic_id_valid(u32 api return apic_id <=3D apic->max_apic_id; } =20 -extern void __init apic_set_eoi_cb(void (*eoi)(void)); - #else /* CONFIG_X86_LOCAL_APIC */ =20 static inline u32 apic_read(u32 reg) { return 0; } @@ -474,7 +472,6 @@ static inline unsigned int read_apic_id( =20 #ifdef CONFIG_X86_64 typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip); -extern void acpi_wake_cpu_handler_update(wakeup_cpu_handler handler); extern int default_acpi_madt_oem_check(char *, char *); extern void x86_64_probe_apic(void); #else --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -1174,7 +1174,7 @@ static int __init acpi_parse_mp_wake(uni =20 acpi_mp_wake_mailbox_paddr =3D mp_wake->base_address; =20 - acpi_wake_cpu_handler_update(acpi_wakeup_cpu); + apic_update_callback(wakeup_secondary_cpu_64, acpi_wakeup_cpu); =20 return 0; } --- a/arch/x86/kernel/apic/init.c +++ b/arch/x86/kernel/apic/init.c @@ -55,30 +55,3 @@ void __init apic_install_driver(struct a =20 pr_info("Switched APIC routing to: %s\n", driver->name); } - -#ifdef CONFIG_X86_64 -void __init acpi_wake_cpu_handler_update(wakeup_cpu_handler handler) -{ - struct apic **drv; - - for (drv =3D __apicdrivers; drv < __apicdrivers_end; drv++) - (*drv)->wakeup_secondary_cpu_64 =3D handler; -} -#endif - -/* - * Override the generic EOI implementation with an optimized version. - * Only called during early boot when only one CPU is active and with - * interrupts disabled, so we know this does not race with actual APIC dri= ver - * use. - */ -void __init apic_set_eoi_cb(void (*eoi)(void)) -{ - struct apic **drv; - - for (drv =3D __apicdrivers; drv < __apicdrivers_end; drv++) { - /* Should happen once for each apic */ - WARN_ON((*drv)->eoi =3D=3D eoi); - (*drv)->eoi =3D eoi; - } -} --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -825,7 +825,7 @@ static void __init kvm_guest_init(void) } =20 if (kvm_para_has_feature(KVM_FEATURE_PV_EOI)) - apic_set_eoi_cb(kvm_guest_apic_eoi_write); + apic_update_callback(eoi, kvm_guest_apic_eoi_write); =20 if (kvm_para_has_feature(KVM_FEATURE_ASYNC_PF_INT) && kvmapf) { static_branch_enable(&kvm_async_pf_enabled); From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE654EB64DC for ; Mon, 17 Jul 2023 23:21:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231545AbjGQXVb (ORCPT ); Mon, 17 Jul 2023 19:21:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40212 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230237AbjGQXV2 (ORCPT ); Mon, 17 Jul 2023 19:21:28 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 718FE10E6 for ; Mon, 17 Jul 2023 16:20:51 -0700 (PDT) Message-ID: <20230717223226.237896259@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635757; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=wkf9cxbN9yugedivD8sL7QgWMpf0hUBTEyuN6MHJ80U=; b=coF5HZJV4lqAYCOI0x2G+gk1jggvNOUYFRaiSC7p/lKyOLLZKnfZMXpV86Hyn3lXE5+VHp ybatAk06keDr7f3cuz22LBVPV7vGXEC/je7DzSUqVT5cqV/pToJLetgUyeZONbZFsMkXQQ JL0FFUava8lwobIOamFi5GMpID/VSIfgyySgc6iUqWrtByMo43awM7eC4xhuO8THhQgHi+ FDaXyFMES6qzHokM53hTbATJBbpXiB4E3q14zvPXr0qMViaGoC6IFP/pbAFtsXyZ0ScrbL sWQEixc98e+h8HPq6I0pYyHBSX2dY1LzBn8GwatXXzRx/9Wq7xi7uEKgZdOx9Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635757; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=wkf9cxbN9yugedivD8sL7QgWMpf0hUBTEyuN6MHJ80U=; b=y/kUV7th0yY9Sc72a2b6dJKP+HSWRlwG2D6jYUjXl1y5Fqw1sVZdtT0jMk4c2hQKvkzOpX BA2Ixn/NetWpRVAg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 53/58] x86/apic: Convert other overrides to apic_update_callback() References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:57 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert all places which just assign a new function directly to the apic callback to use apic_update_callback() which prepares for using static calls. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/hyperv/hv_apic.c | 20 ++++++++++---------- arch/x86/kernel/kvm.c | 4 ++-- arch/x86/kernel/sev.c | 2 +- 3 files changed, 13 insertions(+), 13 deletions(-) --- a/arch/x86/hyperv/hv_apic.c +++ b/arch/x86/hyperv/hv_apic.c @@ -288,12 +288,12 @@ void __init hv_apic_init(void) */ orig_apic =3D *apic; =20 - apic->send_IPI =3D hv_send_ipi; - apic->send_IPI_mask =3D hv_send_ipi_mask; - apic->send_IPI_mask_allbutself =3D hv_send_ipi_mask_allbutself; - apic->send_IPI_allbutself =3D hv_send_ipi_allbutself; - apic->send_IPI_all =3D hv_send_ipi_all; - apic->send_IPI_self =3D hv_send_ipi_self; + apic_update_callback(send_IPI, hv_send_ipi); + apic_update_callback(send_IPI_mask, hv_send_ipi_mask); + apic_update_callback(send_IPI_mask_allbutself, hv_send_ipi_mask_allbutse= lf); + apic_update_callback(send_IPI_allbutself, hv_send_ipi_allbutself); + apic_update_callback(send_IPI_all, hv_send_ipi_all); + apic_update_callback(send_IPI_self, hv_send_ipi_self); } =20 if (ms_hyperv.hints & HV_X64_APIC_ACCESS_RECOMMENDED) { @@ -312,10 +312,10 @@ void __init hv_apic_init(void) */ apic_update_callback(eoi, hv_apic_eoi_write); if (!x2apic_enabled()) { - apic->read =3D hv_apic_read; - apic->write =3D hv_apic_write; - apic->icr_write =3D hv_apic_icr_write; - apic->icr_read =3D hv_apic_icr_read; + apic_update_callback(read, hv_apic_read); + apic_update_callback(write, hv_apic_write); + apic_update_callback(icr_write, hv_apic_icr_write); + apic_update_callback(icr_read, hv_apic_icr_read); } } } --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -624,8 +624,8 @@ late_initcall(setup_efi_kvm_sev_migratio */ static void kvm_setup_pv_ipi(void) { - apic->send_IPI_mask =3D kvm_send_ipi_mask; - apic->send_IPI_mask_allbutself =3D kvm_send_ipi_mask_allbutself; + apic_update_callback(send_IPI_mask, kvm_send_ipi_mask); + apic_update_callback(send_IPI_mask_allbutself, kvm_send_ipi_mask_allbutse= lf); pr_info("setup PV IPIs\n"); } =20 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -1099,7 +1099,7 @@ void snp_set_wakeup_secondary_cpu(void) * required method to start APs under SNP. If the hypervisor does * not support AP creation, then no APs will be started. */ - apic->wakeup_secondary_cpu =3D wakeup_cpu_via_vmgexit; + apic_update_callback(wakeup_secondary_cpu, wakeup_cpu_via_vmgexit); } =20 int __init sev_es_setup_ap_jump_table(struct real_mode_header *rmh) From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4880C0015E for ; Mon, 17 Jul 2023 23:20:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231202AbjGQXUq (ORCPT ); Mon, 17 Jul 2023 19:20:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39576 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231526AbjGQXUp (ORCPT ); Mon, 17 Jul 2023 19:20:45 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D686134 for ; Mon, 17 Jul 2023 16:20:00 -0700 (PDT) Message-ID: <20230717223226.297124390@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635759; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=cOCeYzZlZQBijmmlwD90S/EyiYlmy0xrZba4W3Pw3yw=; b=gaLKj7OKk74d7dKsCAAq7iQL33bF5KOQHpAirffn2nbDIIuBzBtnshkDVGTF32x1xIVXfT LX3O50t4S2wv9IHgf3zrr5gdye+KbDjqzKwAuwiT0zbljANQHJyiJmNm7Qr1V8hP31xQWa bZbK89/vR5cpBemdihkFd0b+8ZAZ1qKKdgsbMR+/eLUdbZBb5t87k8C6sNYIcnutq3UACy T8YUZMvV7eihKLODdI2+oRaEXmt7rLdAzXfmXxDnAdScRZaIxI4thHsPEY6xJtZ2Qrt8IG yOOK9KXY4jTB02SimLzFHp8GNC45fVqza5ArahhrQjrcAMkODa0OeJAYNCIAxA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635759; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=cOCeYzZlZQBijmmlwD90S/EyiYlmy0xrZba4W3Pw3yw=; b=/0Z+SKoUfHQfzCGrNIiYa+mNxhfgHweJlWYXN3rENFQkGK2JhDXuQhwiFm+3p08Oy+yRgU R2Tg+Nr2LiXSuyDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 54/58] x86/xen/apic: Mark apic __ro_after_init References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:15:58 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Nothing can change it post init. While at it mop up the whitespace damage which causes eyebleed due to an editor which is highlighting it. Signed-off-by: Thomas Gleixner Cc: Juergen Gross Acked-by: Peter Zijlstra (Intel) --- arch/x86/xen/apic.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -123,9 +123,9 @@ static int xen_cpu_present_to_apicid(int return BAD_APICID; } =20 -static struct apic xen_pv_apic =3D { - .name =3D "Xen PV", - .probe =3D xen_apic_probe_pv, +static struct apic xen_pv_apic __ro_after_init =3D { + .name =3D "Xen PV", + .probe =3D xen_apic_probe_pv, .acpi_madt_oem_check =3D xen_madt_oem_check, =20 /* .delivery_mode and .dest_mode_logical not used by XENPV */ @@ -138,24 +138,24 @@ static struct apic xen_pv_apic =3D { .phys_pkg_id =3D xen_phys_pkg_id, /* detect_ht */ =20 .max_apic_id =3D UINT_MAX, - .get_apic_id =3D xen_get_apic_id, - .set_apic_id =3D xen_set_apic_id, /* Can be NULL on 32-bit. */ + .get_apic_id =3D xen_get_apic_id, + .set_apic_id =3D xen_set_apic_id, /* Can be NULL on 32-bit. */ =20 .calc_dest_apicid =3D apic_flat_calc_apicid, =20 #ifdef CONFIG_SMP - .send_IPI_mask =3D xen_send_IPI_mask, - .send_IPI_mask_allbutself =3D xen_send_IPI_mask_allbutself, - .send_IPI_allbutself =3D xen_send_IPI_allbutself, - .send_IPI_all =3D xen_send_IPI_all, - .send_IPI_self =3D xen_send_IPI_self, + .send_IPI_mask =3D xen_send_IPI_mask, + .send_IPI_mask_allbutself =3D xen_send_IPI_mask_allbutself, + .send_IPI_allbutself =3D xen_send_IPI_allbutself, + .send_IPI_all =3D xen_send_IPI_all, + .send_IPI_self =3D xen_send_IPI_self, #endif .read =3D xen_apic_read, .write =3D xen_apic_write, .eoi =3D xen_apic_eoi, =20 - .icr_read =3D xen_apic_icr_read, - .icr_write =3D xen_apic_icr_write, + .icr_read =3D xen_apic_icr_read, + .icr_write =3D xen_apic_icr_write, }; =20 static void __init xen_apic_check(void) From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6588CEB64DC for ; Mon, 17 Jul 2023 23:37:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231707AbjGQXhC (ORCPT ); Mon, 17 Jul 2023 19:37:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231691AbjGQXgx (ORCPT ); Mon, 17 Jul 2023 19:36:53 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5047171B for ; Mon, 17 Jul 2023 16:36:07 -0700 (PDT) Message-ID: <20230717223226.358014177@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635760; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=uX/kplLo5CTyEGcDpdLq/uLjlYQ837jWRls5Fa0d2bQ=; b=V2g8TK5/irCDXKjbQaXb1r7SKbrw79jOasZOrc22otmaawYm41oZ4SIYN0FoOb0YNp7rBT GBHawf+UV+/eGE0x/Ibnd426wPBM8PnMKgmDkWPpU1u0xd1pPNJJnmAFjJWudkI07Z1qBN AwfO+tH823Q4kD89cPbCZG3yWVHLDW8taIfeioZdloikGhfK9EaWh0KkpoHpqXVup82ZJT aSDoHi3jbBIsOeJt/WSyaMcX++jfPTHLJlXgfgJlcYk4kK8epMcgNwfT75FLfiSdDdTU5Z AipS3khCPFaeLx+j0Cd4sch+8CN00fp3FFf2ALcvZTEw6Zncv9Q3j43krlN9hg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635760; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=uX/kplLo5CTyEGcDpdLq/uLjlYQ837jWRls5Fa0d2bQ=; b=n7YW14HMPXk/VX1uLMyjlSyd8+xVN0NXKSd1Rst1vDJXz9Qo+q06d7afU296MK6NMy4Wu/ WedSjnxQNdt/fPDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 55/58] x86/apic: Mark all hotpath APIC callback wrappers __always_inline References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:16:00 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There is no value for instrumentation to look at those wrappers and with the upcoming conversion to static calls even less so. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -370,62 +370,62 @@ void __init apic_install_driver(struct a pr_info("APIC::%s() replaced with %ps()\n", #_callback, _fn); \ } =20 -static inline u32 apic_read(u32 reg) +static __always_inline u32 apic_read(u32 reg) { return apic->read(reg); } =20 -static inline void apic_write(u32 reg, u32 val) +static __always_inline void apic_write(u32 reg, u32 val) { apic->write(reg, val); } =20 -static inline void apic_eoi(void) +static __always_inline void apic_eoi(void) { apic->eoi(); } =20 -static inline void apic_native_eoi(void) +static __always_inline void apic_native_eoi(void) { apic->native_eoi(); } =20 -static inline u64 apic_icr_read(void) +static __always_inline u64 apic_icr_read(void) { return apic->icr_read(); } =20 -static inline void apic_icr_write(u32 low, u32 high) +static __always_inline void apic_icr_write(u32 low, u32 high) { apic->icr_write(low, high); } =20 -static inline void apic_wait_icr_idle(void) +static __always_inline void apic_wait_icr_idle(void) { if (apic->wait_icr_idle) apic->wait_icr_idle(); } =20 -static inline u32 safe_apic_wait_icr_idle(void) +static __always_inline u32 safe_apic_wait_icr_idle(void) { return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0; } =20 -static inline bool apic_id_valid(u32 apic_id) +static __always_inline bool apic_id_valid(u32 apic_id) { return apic_id <=3D apic->max_apic_id; } =20 #else /* CONFIG_X86_LOCAL_APIC */ =20 -static inline u32 apic_read(u32 reg) { return 0; } -static inline void apic_write(u32 reg, u32 val) { } -static inline void apic_eoi(void) { } -static inline u64 apic_icr_read(void) { return 0; } -static inline void apic_icr_write(u32 low, u32 high) { } -static inline void apic_wait_icr_idle(void) { } -static inline u32 safe_apic_wait_icr_idle(void) { return 0; } -static inline void apic_set_eoi(void (*eoi)(void)) {} +static __always_inline u32 apic_read(u32 reg) { return 0; } +static __always_inline void apic_write(u32 reg, u32 val) { } +static __always_inline void apic_eoi(void) { } +static __always_inline u64 apic_icr_read(void) { return 0; } +static __always_inline void apic_icr_write(u32 low, u32 high) { } +static __always_inline void apic_wait_icr_idle(void) { } +static __always_inline u32 safe_apic_wait_icr_idle(void) { return 0; } +static __always_inline void apic_set_eoi(void (*eoi)(void)) {} =20 #endif /* CONFIG_X86_LOCAL_APIC */ From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1EB3C001B0 for ; Mon, 17 Jul 2023 23:36:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231695AbjGQXgx (ORCPT ); Mon, 17 Jul 2023 19:36:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51114 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230022AbjGQXgp (ORCPT ); Mon, 17 Jul 2023 19:36:45 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D91E7E48 for ; Mon, 17 Jul 2023 16:35:56 -0700 (PDT) Message-ID: <20230717223226.417564255@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635762; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=yZ0mIAoyX+o+dAiLvWiSm6ygjzxrkLfGxB3sGPnAg2c=; b=j37UAfGl4374PyDMfypHyFZr6u6FXj8Ubc7/jU0U6EzVKvE3VQLhnt5OX6sze5a/o9hJrO NBqQ2wsjnb0rg1qKLks034DHjvhiADDLKNFnBT2D88L8vudqk58u/uXS1SrGyPPRe1Mb0D Cc7RI5G1SS7UPZ7F5qS97y24ZyrIw7LKIlnNxMMMnS/DehhdtBCibL0JNs9GSnew8WYPwy 89Tb8dye/mnCrid+CpXC6NFJ4meINN+7LBV1Iio2vs1sck1gfsWngXZ2agOomzLZMkSqcX FZxAXeSeicpu1YjlFkPWNkUoIy1ZywbDRyQKpmGwIJQI+vm77UMniH4GkqsZGw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635762; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=yZ0mIAoyX+o+dAiLvWiSm6ygjzxrkLfGxB3sGPnAg2c=; b=2ekXGJoztTgdFaxyYJhCvroYnfM6VbnkFbiqK3VbgT2e5qfM8ryqXyv0hO3IlLE8STOBiA 6W68dvkp0I9SiKCQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 56/58] x86/apic: Wrap IPI calls into helper functions References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:16:01 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move them to one place so the static call conversion gets simpler. No functional change. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/hyperv/hv_spinlock.c | 2 +- arch/x86/include/asm/apic.h | 30 ++++++++++++++++++++++++++++++ arch/x86/kernel/apic/apic.c | 2 +- arch/x86/kernel/apic/hw_nmi.c | 4 +++- arch/x86/kernel/apic/ipi.c | 16 ++++++++-------- arch/x86/kernel/apic/vector.c | 6 +++--- arch/x86/kernel/cpu/mce/inject.c | 3 +-- arch/x86/kernel/irq_work.c | 2 +- arch/x86/kernel/nmi_selftest.c | 2 +- arch/x86/kernel/smp.c | 2 +- arch/x86/kvm/vmx/posted_intr.c | 2 +- arch/x86/kvm/vmx/vmx.c | 2 +- arch/x86/platform/uv/uv_nmi.c | 2 +- 13 files changed, 53 insertions(+), 22 deletions(-) --- a/arch/x86/hyperv/hv_spinlock.c +++ b/arch/x86/hyperv/hv_spinlock.c @@ -20,7 +20,7 @@ static bool __initdata hv_pvspin =3D true; =20 static void hv_qlock_kick(int cpu) { - apic->send_IPI(cpu, X86_PLATFORM_IPI_VECTOR); + __apic_send_IPI(cpu, X86_PLATFORM_IPI_VECTOR); } =20 static void hv_qlock_wait(u8 *byte, u8 val) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -401,6 +401,36 @@ static __always_inline void apic_icr_wri apic->icr_write(low, high); } =20 +static __always_inline void __apic_send_IPI(int cpu, int vector) +{ + apic->send_IPI(cpu, vector); +} + +static __always_inline void __apic_send_IPI_mask(const struct cpumask *mas= k, int vector) +{ + apic->send_IPI_mask(mask, vector); +} + +static __always_inline void __apic_send_IPI_mask_allbutself(const struct c= pumask *mask, int vector) +{ + apic->send_IPI_mask_allbutself(mask, vector); +} + +static __always_inline void __apic_send_IPI_allbutself(int vector) +{ + apic->send_IPI_allbutself(vector); +} + +static __always_inline void __apic_send_IPI_all(int vector) +{ + apic->send_IPI_all(vector); +} + +static __always_inline void __apic_send_IPI_self(int vector) +{ + apic->send_IPI_self(vector); +} + static __always_inline void apic_wait_icr_idle(void) { if (apic->wait_icr_idle) --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -502,7 +502,7 @@ static int lapic_timer_set_oneshot(struc static void lapic_timer_broadcast(const struct cpumask *mask) { #ifdef CONFIG_SMP - apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); + __apic_send_IPI_mask(mask, LOCAL_TIMER_VECTOR); #endif } =20 --- a/arch/x86/kernel/apic/hw_nmi.c +++ b/arch/x86/kernel/apic/hw_nmi.c @@ -21,6 +21,8 @@ #include #include =20 +#include "local.h" + #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF u64 hw_nmi_get_sample_period(int watchdog_thresh) { @@ -31,7 +33,7 @@ u64 hw_nmi_get_sample_period(int watchdo #ifdef arch_trigger_cpumask_backtrace static void nmi_raise_cpu_backtrace(cpumask_t *mask) { - apic->send_IPI_mask(mask, NMI_VECTOR); + __apic_send_IPI_mask(mask, NMI_VECTOR); } =20 void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_se= lf) --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -54,9 +54,9 @@ void apic_send_IPI_allbutself(unsigned i return; =20 if (static_branch_likely(&apic_use_ipi_shorthand)) - apic->send_IPI_allbutself(vector); + __apic_send_IPI_allbutself(vector); else - apic->send_IPI_mask_allbutself(cpu_online_mask, vector); + __apic_send_IPI_mask_allbutself(cpu_online_mask, vector); } =20 /* @@ -70,12 +70,12 @@ void native_smp_send_reschedule(int cpu) WARN(1, "sched: Unexpected reschedule of offline CPU#%d!\n", cpu); return; } - apic->send_IPI(cpu, RESCHEDULE_VECTOR); + __apic_send_IPI(cpu, RESCHEDULE_VECTOR); } =20 void native_send_call_func_single_ipi(int cpu) { - apic->send_IPI(cpu, CALL_FUNCTION_SINGLE_VECTOR); + __apic_send_IPI(cpu, CALL_FUNCTION_SINGLE_VECTOR); } =20 void native_send_call_func_ipi(const struct cpumask *mask) @@ -87,14 +87,14 @@ void native_send_call_func_ipi(const str goto sendmask; =20 if (cpumask_test_cpu(cpu, mask)) - apic->send_IPI_all(CALL_FUNCTION_VECTOR); + __apic_send_IPI_all(CALL_FUNCTION_VECTOR); else if (num_online_cpus() > 1) - apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR); + __apic_send_IPI_allbutself(CALL_FUNCTION_VECTOR); return; } =20 sendmask: - apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR); + __apic_send_IPI_mask(mask, CALL_FUNCTION_VECTOR); } =20 #endif /* CONFIG_SMP */ @@ -221,7 +221,7 @@ void default_send_IPI_mask_allbutself_ph */ void default_send_IPI_single(int cpu, int vector) { - apic->send_IPI_mask(cpumask_of(cpu), vector); + __apic_send_IPI_mask(cpumask_of(cpu), vector); } =20 void default_send_IPI_allbutself(int vector) --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -876,7 +876,7 @@ static int apic_retrigger_irq(struct irq unsigned long flags; =20 raw_spin_lock_irqsave(&vector_lock, flags); - apic->send_IPI(apicd->cpu, apicd->vector); + __apic_send_IPI(apicd->cpu, apicd->vector); raw_spin_unlock_irqrestore(&vector_lock, flags); =20 return 1; @@ -958,7 +958,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_irq_move_c */ irr =3D apic_read(APIC_IRR + (vector / 32 * 0x10)); if (irr & (1U << (vector % 32))) { - apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); + __apic_send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); continue; } free_moved_vector(apicd); @@ -976,7 +976,7 @@ static void __send_cleanup_vector(struct cpu =3D apicd->prev_cpu; if (cpu_online(cpu)) { hlist_add_head(&apicd->clist, per_cpu_ptr(&cleanup_list, cpu)); - apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR); + __apic_send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR); } else { apicd->prev_vector =3D 0; } --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -270,8 +270,7 @@ static void __maybe_unused raise_mce(str mce_irq_ipi, NULL, 0); preempt_enable(); } else if (m->inject_flags & MCJ_NMI_BROADCAST) - apic->send_IPI_mask(mce_inject_cpumask, - NMI_VECTOR); + __apic_send_IPI_mask(mce_inject_cpumask, NMI_VECTOR); } start =3D jiffies; while (!cpumask_empty(mce_inject_cpumask)) { --- a/arch/x86/kernel/irq_work.c +++ b/arch/x86/kernel/irq_work.c @@ -28,7 +28,7 @@ void arch_irq_work_raise(void) if (!arch_irq_work_has_interrupt()) return; =20 - apic->send_IPI_self(IRQ_WORK_VECTOR); + __apic_send_IPI_self(IRQ_WORK_VECTOR); apic_wait_icr_idle(); } #endif --- a/arch/x86/kernel/nmi_selftest.c +++ b/arch/x86/kernel/nmi_selftest.c @@ -75,7 +75,7 @@ static void __init test_nmi_ipi(struct c /* sync above data before sending NMI */ wmb(); =20 - apic->send_IPI_mask(mask, NMI_VECTOR); + __apic_send_IPI_mask(mask, NMI_VECTOR); =20 /* Don't wait longer than a second */ timeout =3D USEC_PER_SEC; --- a/arch/x86/kernel/smp.c +++ b/arch/x86/kernel/smp.c @@ -237,7 +237,7 @@ static void native_stop_other_cpus(int w pr_emerg("Shutting down cpus with NMI\n"); =20 for_each_cpu(cpu, &cpus_stop_mask) - apic->send_IPI(cpu, NMI_VECTOR); + __apic_send_IPI(cpu, NMI_VECTOR); } /* * Don't wait longer than 10 ms if the caller didn't --- a/arch/x86/kvm/vmx/posted_intr.c +++ b/arch/x86/kvm/vmx/posted_intr.c @@ -175,7 +175,7 @@ static void pi_enable_wakeup_handler(str * scheduled out). */ if (pi_test_on(&new)) - apic->send_IPI_self(POSTED_INTR_WAKEUP_VECTOR); + __apic_send_IPI_self(POSTED_INTR_WAKEUP_VECTOR); =20 local_irq_restore(flags); } --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -4147,7 +4147,7 @@ static inline void kvm_vcpu_trigger_post */ =20 if (vcpu !=3D kvm_get_running_vcpu()) - apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); + __apic_send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); return; } #endif --- a/arch/x86/platform/uv/uv_nmi.c +++ b/arch/x86/platform/uv/uv_nmi.c @@ -601,7 +601,7 @@ static void uv_nmi_nr_cpus_ping(void) for_each_cpu(cpu, uv_nmi_cpu_mask) uv_cpu_nmi_per(cpu).pinging =3D 1; =20 - apic->send_IPI_mask(uv_nmi_cpu_mask, APIC_DM_NMI); + __apic_send_IPI_mask(uv_nmi_cpu_mask, APIC_DM_NMI); } =20 /* Clean up flags for CPU's that ignored both NMI and ping */ From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 284F6EB64DC for ; Mon, 17 Jul 2023 23:21:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231557AbjGQXVv (ORCPT ); Mon, 17 Jul 2023 19:21:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231512AbjGQXVt (ORCPT ); Mon, 17 Jul 2023 19:21:49 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 880A51985 for ; Mon, 17 Jul 2023 16:21:06 -0700 (PDT) Message-ID: <20230717223226.476875329@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635763; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=uvvFxpQ0CI+6SWZBIuqun6zkxQpCJ5cWHxgeYGNpJp4=; b=R7XXJFQedNE1ITW18jUJikCpSy2EgGM78+g7kuY4J0NjIBXiFLx9LG13GlCoP9aifrsJMh CkHjg1CL3GAAgS3MmlJwjnONKAxcs+AHjux4Ml2ZebTzy8UdjmoBVBqFH7/ZYm+qb58WAo JezrWWHQrlRDlazcIDxlruB2H4vUTLNxqWjaFf/Mr6SESYel0J229UdBhMXcR3VONNNb77 laMAJV5i92KoX4GLlbS13ZUzyP8DkrdFbp8Isq1LJ6Ov2rrLXcLfz/zYlsToU0XVFhep11 mWSU9XiaM43zP5Ues8OyNzyMHGU9mmEKVZcamIsrzMwGxZTuVwnUx3lihvDhjg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635763; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=uvvFxpQ0CI+6SWZBIuqun6zkxQpCJ5cWHxgeYGNpJp4=; b=St1HOkoMMFZWekCyT4k0WO5nKepjmvc+lUlUo1dPEnSWCYqOwWh1wMnaOMExWfWVsBY2uT D29BEcM7++KDrgCQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 57/58] x86/apic: Provide static call infrastructure for APIC callbacks References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:16:03 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Declare and define the static calls for the hotpath APIC callbacks. Note this deliberately uses STATIC_CALL_NULL() because otherwise it would be required to have the definitions in the 32bit and the 64bit default APIC implementations and it's hard to keep the calls in sync. The other option would be to have stub functions for each callback type. Not pretty either So the NULL capable calls are used and filled in during early boot after the static key infrastructure has been initialized. The calls will be static_call() except for the wait_irc_idle() callback which is valid to be NULL for X2APIC systems. Update the calls when a new APIC driver is installed and when a callback override is invoked. Export the trampolines for the two calls which are used in KVM and MCE error inject modules. Test the setup and let the next step convert the inline wrappers to make it effective. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 21 +++++++++++++++++++ arch/x86/kernel/apic/init.c | 47 +++++++++++++++++++++++++++++++++++++++= +++++ 2 files changed, 68 insertions(+) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -3,6 +3,7 @@ #define _ASM_X86_APIC_H =20 #include +#include =20 #include #include @@ -368,9 +369,29 @@ void __init apic_install_driver(struct a #define apic_update_callback(_callback, _fn) { \ __x86_apic_override._callback =3D _fn; \ apic->_callback =3D _fn; \ + static_call_update(apic_call_##_callback, _fn); \ pr_info("APIC::%s() replaced with %ps()\n", #_callback, _fn); \ } =20 +#define DECLARE_APIC_CALL(__cb) \ + DECLARE_STATIC_CALL(apic_call_##__cb, *apic->__cb) + +DECLARE_APIC_CALL(eoi); +DECLARE_APIC_CALL(native_eoi); +DECLARE_APIC_CALL(icr_read); +DECLARE_APIC_CALL(icr_write); +DECLARE_APIC_CALL(read); +DECLARE_APIC_CALL(send_IPI); +DECLARE_APIC_CALL(send_IPI_mask); +DECLARE_APIC_CALL(send_IPI_mask_allbutself); +DECLARE_APIC_CALL(send_IPI_allbutself); +DECLARE_APIC_CALL(send_IPI_all); +DECLARE_APIC_CALL(send_IPI_self); +DECLARE_APIC_CALL(wait_icr_idle); +DECLARE_APIC_CALL(wakeup_secondary_cpu); +DECLARE_APIC_CALL(wakeup_secondary_cpu_64); +DECLARE_APIC_CALL(write); + static __always_inline u32 apic_read(u32 reg) { return apic->read(reg); --- a/arch/x86/kernel/apic/init.c +++ b/arch/x86/kernel/apic/init.c @@ -5,6 +5,28 @@ =20 #include "local.h" =20 +#define DEFINE_APIC_CALL(__cb) \ + DEFINE_STATIC_CALL_NULL(apic_call_##__cb, *apic->__cb) + +DEFINE_APIC_CALL(eoi); +DEFINE_APIC_CALL(native_eoi); +DEFINE_APIC_CALL(icr_read); +DEFINE_APIC_CALL(icr_write); +DEFINE_APIC_CALL(read); +DEFINE_APIC_CALL(send_IPI); +DEFINE_APIC_CALL(send_IPI_mask); +DEFINE_APIC_CALL(send_IPI_mask_allbutself); +DEFINE_APIC_CALL(send_IPI_allbutself); +DEFINE_APIC_CALL(send_IPI_all); +DEFINE_APIC_CALL(send_IPI_self); +DEFINE_APIC_CALL(wait_icr_idle); +DEFINE_APIC_CALL(wakeup_secondary_cpu); +DEFINE_APIC_CALL(wakeup_secondary_cpu_64); +DEFINE_APIC_CALL(write); + +EXPORT_STATIC_CALL_TRAMP_GPL(apic_call_send_IPI_mask); +EXPORT_STATIC_CALL_TRAMP_GPL(apic_call_send_IPI_self); + /* The container for function call overrides */ struct apic_override __x86_apic_override __initdata; =20 @@ -30,10 +52,34 @@ static __init void restore_override_call apply_override(wakeup_secondary_cpu_64); } =20 +#define update_call(__cb) \ + static_call_update(apic_call_##__cb, *apic->__cb) + +static __init void update_static_calls(void) +{ + update_call(eoi); + update_call(native_eoi); + update_call(write); + update_call(read); + update_call(send_IPI); + update_call(send_IPI_mask); + update_call(send_IPI_mask_allbutself); + update_call(send_IPI_allbutself); + update_call(send_IPI_all); + update_call(send_IPI_self); + update_call(icr_read); + update_call(icr_write); + update_call(wait_icr_idle); + update_call(wakeup_secondary_cpu); + update_call(wakeup_secondary_cpu_64); +} + void __init apic_setup_apic_calls(void) { /* Ensure that the default APIC has native_eoi populated */ apic->native_eoi =3D apic->eoi; + update_static_calls(); + pr_info("Static calls initialized\n"); } =20 void __init apic_install_driver(struct apic *driver) @@ -52,6 +98,7 @@ void __init apic_install_driver(struct a =20 /* Apply any already installed callback overrides */ restore_override_callbacks(); + update_static_calls(); =20 pr_info("Switched APIC routing to: %s\n", driver->name); } From nobody Sat Feb 7 22:55:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37D8AC001DE for ; Mon, 17 Jul 2023 23:23:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231576AbjGQXXc (ORCPT ); Mon, 17 Jul 2023 19:23:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231852AbjGQXX2 (ORCPT ); Mon, 17 Jul 2023 19:23:28 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 21BCC10D1 for ; Mon, 17 Jul 2023 16:22:44 -0700 (PDT) Message-ID: <20230717223226.538475803@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1689635765; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=lvMFdpWMYEl6iHAh9VQaIAf2jL32y7ajYh4Uo2YtOzA=; b=zP26Q09tzOOZnXWdUFGaMQFD74L+qpdu5/OQGvyYyiZlRQ5bUEwJc9a8Svzr0wS8GNpvbZ pn24Act9J/RMcTSkWXQtfsI8I+fnlIz8p8i+j0emei5GoLnUzr3k3AoMlqDF1HXGA/v18D vPIMEmawCFpThhaJjspLXUK5kI1WLzA8r2rEf27zychn1pucRO+gONlIWDKebkD+ZXfOmZ t91yZQOsWB6Tc0WFrSG4gp4oETKvug2OuN+JNbnKINIU4u4UByfZJ9461d5hjKjCf5B774 79dlHcsLHI9mdvmMDcfWW0sbmQP7pJ/Ml/NdDhfqoH54tudnOutCc2zqtkkQcA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1689635765; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=lvMFdpWMYEl6iHAh9VQaIAf2jL32y7ajYh4Uo2YtOzA=; b=7JEu7Jpz1sP45XzkyVnLD6yXyYOgSEsQ+LVyXwPbyLst41zW3d69yIstXz1C78ob3B91dy UZExU6MTiMrW32Cw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Andrew Cooper , Tom Lendacky , Paolo Bonzini , Wei Liu , Arjan van de Ven , Juergen Gross Subject: [patch 58/58] x86/apic: Turn on static calls References: <20230717223049.327865981@linutronix.de> MIME-Version: 1.0 Date: Tue, 18 Jul 2023 01:16:05 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert all the APIC callback inline wrappers from apic->foo() to static_call(apic_call_foo)(), except for the safe_wait_icr_idle() one which is only used during SMP bringup when sending INIT/SIPI. That really can do the conditional callback. The regular wait_icr_idle() matters as it is used in irq_work_raise(), so X2APIC machines spare the conditional. Signed-off-by: Thomas Gleixner Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/apic.h | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -397,68 +397,67 @@ EXPORT_STATIC_CALL_TRAMP_GPL(apic_call_s =20 static __always_inline u32 apic_read(u32 reg) { - return apic->read(reg); + return static_call(apic_call_read)(reg); } =20 static __always_inline void apic_write(u32 reg, u32 val) { - apic->write(reg, val); + static_call(apic_call_write)(reg, val); } =20 static __always_inline void apic_eoi(void) { - apic->eoi(); + static_call(apic_call_eoi)(); } =20 static __always_inline void apic_native_eoi(void) { - apic->native_eoi(); + static_call(apic_call_native_eoi)(); } =20 static __always_inline u64 apic_icr_read(void) { - return apic->icr_read(); + return static_call(apic_call_icr_read)(); } =20 static __always_inline void apic_icr_write(u32 low, u32 high) { - apic->icr_write(low, high); + static_call(apic_call_icr_write)(low, high); } =20 static __always_inline void __apic_send_IPI(int cpu, int vector) { - apic->send_IPI(cpu, vector); + static_call(apic_call_send_IPI)(cpu, vector); } =20 static __always_inline void __apic_send_IPI_mask(const struct cpumask *mas= k, int vector) { - apic->send_IPI_mask(mask, vector); + static_call(apic_call_send_IPI_mask)(mask, vector); } =20 static __always_inline void __apic_send_IPI_mask_allbutself(const struct c= pumask *mask, int vector) { - apic->send_IPI_mask_allbutself(mask, vector); + static_call(apic_call_send_IPI_mask_allbutself)(mask, vector); } =20 static __always_inline void __apic_send_IPI_allbutself(int vector) { - apic->send_IPI_allbutself(vector); + static_call(apic_call_send_IPI_allbutself)(vector); } =20 static __always_inline void __apic_send_IPI_all(int vector) { - apic->send_IPI_all(vector); + static_call(apic_call_send_IPI_all)(vector); } =20 static __always_inline void __apic_send_IPI_self(int vector) { - apic->send_IPI_self(vector); + static_call(apic_call_send_IPI_self)(vector); } =20 static __always_inline void apic_wait_icr_idle(void) { - if (apic->wait_icr_idle) - apic->wait_icr_idle(); + static_call_cond(apic_call_wait_icr_idle)(); } =20 static __always_inline u32 safe_apic_wait_icr_idle(void)