From nobody Mon Feb 9 04:45:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EC58C001E0 for ; Mon, 17 Jul 2023 17:36:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230362AbjGQRgB (ORCPT ); Mon, 17 Jul 2023 13:36:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229706AbjGQRf6 (ORCPT ); Mon, 17 Jul 2023 13:35:58 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDE691BE; Mon, 17 Jul 2023 10:35:38 -0700 (PDT) Received: from jupiter.universe (dyndsl-091-248-189-171.ewe-ip-backbone.de [91.248.189.171]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id CD3E566028F5; Mon, 17 Jul 2023 18:35:15 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1689615316; bh=64KeJPG4Zg7KDZinmnbpSO47kNMgAyfiBh+eN2b40rg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B5HBbDB20yXRLoz4slfRfa4dcG7iTPpeXK0IKlVynGXZfrgZ/LTtP0NCtNffMTqp2 53y1ZhTnvb6nxC7WHaZme7TNf4+gjZOb1w7pG4WwffjpLj2HG5r23fVt7C0tOV3O8Z YKWgBBEsTY540MUUQRvdf4+4SlmnZxx8LqfouRU0AwF9FDU9LoToi1Zcl4stwDZkvK cR6MuMrIjixM9Zlc4MTTibxIXGuHxU6j7afd6FpeZrqSvmO+t7HXff2HhQoYiYRBpC Qj7kH3ITX820LlNRz+dt9drHpbb2oJVULN0ijOb8COb5GIdTBGtyYJSPJIn+kx5bYD pNWzNDmnpYOMQ== Received: by jupiter.universe (Postfix, from userid 1000) id D348D480C77; Mon, 17 Jul 2023 19:35:12 +0200 (CEST) From: Sebastian Reichel To: linux-phy@lists.infradead.org, linux-rockchip@lists.infradead.org Cc: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Vinod Koul , Kishon Vijay Abraham I , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Serge Semin , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Lin , Simon Xue , John Clark , Qu Wenruo , devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sebastian Reichel , kernel@collabora.com, Conor Dooley Subject: [PATCH v2 1/2] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy Date: Mon, 17 Jul 2023 19:35:11 +0200 Message-Id: <20230717173512.65169-2-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230717173512.65169-1-sebastian.reichel@collabora.com> References: <20230717173512.65169-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When the RK3568 PCIe v3 PHY supported has been upstreamed, RK3588 support was included, but the DT binding does not reflect this. This adds the missing bits. Reviewed-by: Conor Dooley Signed-off-by: Sebastian Reichel --- .../bindings/phy/rockchip,pcie3-phy.yaml | 33 ++++++++++++++++--- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml = b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml index 9f2d8d2cc7a5..c4fbffcde6e4 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -13,19 +13,18 @@ properties: compatible: enum: - rockchip,rk3568-pcie3-phy + - rockchip,rk3588-pcie3-phy =20 reg: maxItems: 1 =20 clocks: - minItems: 3 + minItems: 1 maxItems: 3 =20 clock-names: - items: - - const: refclk_m - - const: refclk_n - - const: pclk + minItems: 1 + maxItems: 3 =20 data-lanes: description: which lanes (by position) should be mapped to which @@ -61,6 +60,30 @@ required: - rockchip,phy-grf - "#phy-cells" =20 +allOf: + - if: + properties: + compatible: + enum: + - rockchip,rk3588-pcie3-phy + then: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: pclk + else: + properties: + clocks: + minItems: 3 + + clock-names: + items: + - const: refclk_m + - const: refclk_n + - const: pclk + additionalProperties: false =20 examples: --=20 2.40.1 From nobody Mon Feb 9 04:45:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0C6DC001B0 for ; Mon, 17 Jul 2023 17:35:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230263AbjGQRfp (ORCPT ); Mon, 17 Jul 2023 13:35:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230203AbjGQRfl (ORCPT ); Mon, 17 Jul 2023 13:35:41 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC887170D; Mon, 17 Jul 2023 10:35:17 -0700 (PDT) Received: from jupiter.universe (dyndsl-091-248-189-171.ewe-ip-backbone.de [91.248.189.171]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id DB88E660297B; Mon, 17 Jul 2023 18:35:15 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1689615316; bh=8oFJad9r/GlAEavQIAU1wTEML33q2mHg++XmmQwX2kM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DqGDoIY9y0wEE76avTYGCDjg2nvy3cTzIABdofTOtlqWP1xQHEbxkKh2SywY2DXdy I3c0Tyemq4nHkprM5BJmufjc7d5OCgmnE6mzpUL0oMEr0uFgbW/dfdgWj3gisyiJcD QuLNaYfxr79Hu9EvXE9Tf0PAySjLwpCq80Xn5Jiy7Kehe3xYDoNyPlzoy/69QH+aRB AHchTHWkCNtvtTzvR75r59HZfQhYwabEiABq8dqffMvk8iIt6vZ30m1/JRBk8t9bz7 uN4OwQWin4TairUPZKBG/4MEqd698US7snTj8zu4++s/22NMqoIYN+VjDZ3tkrtkSV aHOgrRb5jMZiA== Received: by jupiter.universe (Postfix, from userid 1000) id D4FCD480C78; Mon, 17 Jul 2023 19:35:12 +0200 (CEST) From: Sebastian Reichel To: linux-phy@lists.infradead.org, linux-rockchip@lists.infradead.org Cc: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , Vinod Koul , Kishon Vijay Abraham I , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Serge Semin , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Lin , Simon Xue , John Clark , Qu Wenruo , devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support Date: Mon, 17 Jul 2023 19:35:12 +0200 Message-Id: <20230717173512.65169-3-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230717173512.65169-1-sebastian.reichel@collabora.com> References: <20230717173512.65169-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add both PCIe3 controllers together with the shared PHY. Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts= /rockchip/rk3588.dtsi index 88d702575db2..8f210f002fac 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -7,6 +7,11 @@ #include "rk3588-pinctrl.dtsi" =20 / { + pcie30_phy_grf: syscon@fd5b8000 { + compatible =3D "rockchip,rk3588-pcie3-phy-grf", "syscon"; + reg =3D <0x0 0xfd5b8000 0x0 0x10000>; + }; + pipe_phy1_grf: syscon@fd5c0000 { compatible =3D "rockchip,rk3588-pipe-phy-grf", "syscon"; reg =3D <0x0 0xfd5c0000 0x0 0x100>; @@ -80,6 +85,108 @@ i2s10_8ch: i2s@fde00000 { status =3D "disabled"; }; =20 + pcie3x4: pcie@fe150000 { + compatible =3D "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x00 0x0f>; + clocks =3D <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type =3D "pci"; + interrupts =3D , + , + , + , + ; + interrupt-names =3D "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie3x4_intc 0>, + <0 0 0 2 &pcie3x4_intc 1>, + <0 0 0 3 &pcie3x4_intc 2>, + <0 0 0 4 &pcie3x4_intc 3>; + linux,pci-domain =3D <0>; + max-link-speed =3D <3>; + msi-map =3D <0x0000 &its1 0x0000 0x1000>; + num-lanes =3D <4>; + phys =3D <&pcie30phy>; + phy-names =3D "pcie-phy"; + power-domains =3D <&power RK3588_PD_PCIE>; + ranges =3D <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, + <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; + reg =3D <0xa 0x40000000 0x0 0x00400000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x0 0xf0000000 0x0 0x00100000>; + reg-names =3D "dbi", "apb", "config"; + resets =3D <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names =3D "pwr", "pipe"; + status =3D "disabled"; + + pcie3x4_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + }; + + pcie3x2: pcie@fe160000 { + compatible =3D "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x10 0x1f>; + clocks =3D <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type =3D "pci"; + interrupts =3D , + , + , + , + ; + interrupt-names =3D "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie3x2_intc 0>, + <0 0 0 2 &pcie3x2_intc 1>, + <0 0 0 3 &pcie3x2_intc 2>, + <0 0 0 4 &pcie3x2_intc 3>; + linux,pci-domain =3D <1>; + max-link-speed =3D <3>; + msi-map =3D <0x1000 &its1 0x1000 0x1000>; + num-lanes =3D <2>; + phys =3D <&pcie30phy>; + phy-names =3D "pcie-phy"; + power-domains =3D <&power RK3588_PD_PCIE>; + ranges =3D <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, + <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; + reg =3D <0xa 0x40400000 0x0 0x00400000>, + <0x0 0xfe160000 0x0 0x00010000>, + <0x0 0xf1000000 0x0 0x00100000>; + reg-names =3D "dbi", "apb", "config"; + resets =3D <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; + reset-names =3D "pwr", "pipe"; + status =3D "disabled"; + + pcie3x2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + }; + pcie2x1l0: pcie@fe170000 { compatible =3D "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; #address-cells =3D <3>; @@ -218,4 +325,17 @@ combphy1_ps: phy@fee10000 { rockchip,pipe-phy-grf =3D <&pipe_phy1_grf>; status =3D "disabled"; }; + + pcie30phy: phy@fee80000 { + compatible =3D "rockchip,rk3588-pcie3-phy"; + reg =3D <0x0 0xfee80000 0x0 0x20000>; + #phy-cells =3D <0>; + clocks =3D <&cru PCLK_PCIE_COMBO_PIPE_PHY>; + clock-names =3D "pclk"; + resets =3D <&cru SRST_PCIE30_PHY>; + reset-names =3D "phy"; + rockchip,pipe-grf =3D <&php_grf>; + rockchip,phy-grf =3D <&pcie30_phy_grf>; + status =3D "disabled"; + }; }; --=20 2.40.1