From nobody Tue Feb 10 02:42:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3E7EEB64DC for ; Mon, 17 Jul 2023 17:27:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231320AbjGQR1a (ORCPT ); Mon, 17 Jul 2023 13:27:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230527AbjGQR1M (ORCPT ); Mon, 17 Jul 2023 13:27:12 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B898991; Mon, 17 Jul 2023 10:27:03 -0700 (PDT) Received: from jupiter.universe (dyndsl-091-248-189-171.ewe-ip-backbone.de [91.248.189.171]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id 506E6660701C; Mon, 17 Jul 2023 18:26:58 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1689614818; bh=iJEV5hp8TWN3be/f2X5Jvjfl1ZZIqLvw4EgQ1zURuRM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=amNXOZA5M4AahwkI/tBTxFzARFVnwQTiWDEiZ8aExhCDyIdFSr7pdLtc5OEHL2DZY Ej/3aM/rgiY0HgFFkLcvuooC/xkykLdHKhSp8KiBjw27Qg0FNROV6D/GgTb/sYiQ8G d3LMG7Lb7bFG1uHlmSkKkxCBQuKku2oz6xtdZrSwEzQxj8pXbeSi37dWBT7hPsaAN0 uzyK1y0awcip1zy5y4te9EwYVOu3ER5SAUs0QUznTKED2HkbXyiH8/1IXqDkCAF5Ig MFG04QJ6kpizjL9gtfm+RBP31+UtlYRrkUa6YDkduivEj0qgi+DdGltx9GuxHICqif PdEMC3lvWMPzA== Received: by jupiter.universe (Postfix, from userid 1000) id 208EE480C7B; Mon, 17 Jul 2023 19:26:53 +0200 (CEST) From: Sebastian Reichel To: linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, Serge Semin Cc: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Lin , Simon Xue , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sebastian Reichel , kernel@collabora.com, Kever Yang , Jagan Teki Subject: [PATCH v3 5/5] arm64: dts: rockchip: rk3588: add PCIe2 support Date: Mon, 17 Jul 2023 19:26:51 +0200 Message-Id: <20230717172651.64324-6-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230717172651.64324-1-sebastian.reichel@collabora.com> References: <20230717172651.64324-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add all three PCIe2 IP blocks to the RK3588 DT. Note, that RK3588 also has two PCIe3 IP blocks, that will be handled separately. Co-developed-by: Kever Yang Signed-off-by: Kever Yang Tested-by: Jagan Teki # edgeble-neu6a, 6b Reviewed-by: Jagan Teki Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 51 +++++++++++ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 102 ++++++++++++++++++++++ 2 files changed, 153 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts= /rockchip/rk3588.dtsi index 6be9bf81c09c..88d702575db2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -80,6 +80,57 @@ i2s10_8ch: i2s@fde00000 { status =3D "disabled"; }; =20 + pcie2x1l0: pcie@fe170000 { + compatible =3D "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x20 0x2f>; + clocks =3D <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, + <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, + <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type =3D "pci"; + interrupts =3D , + , + , + , + ; + interrupt-names =3D "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie2x1l0_intc 0>, + <0 0 0 2 &pcie2x1l0_intc 1>, + <0 0 0 3 &pcie2x1l0_intc 2>, + <0 0 0 4 &pcie2x1l0_intc 3>; + linux,pci-domain =3D <2>; + max-link-speed =3D <2>; + msi-map =3D <0x2000 &its0 0x2000 0x1000>; + num-lanes =3D <1>; + phys =3D <&combphy1_ps PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + power-domains =3D <&power RK3588_PD_PCIE>; + ranges =3D <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, + <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; + reg =3D <0xa 0x40800000 0x0 0x00400000>, + <0x0 0xfe170000 0x0 0x00010000>, + <0x0 0xf2000000 0x0 0x00100000>; + reg-names =3D "dbi", "apb", "config"; + resets =3D <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; + reset-names =3D "pwr", "pipe"; + status =3D "disabled"; + + pcie2x1l0_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + }; + gmac0: ethernet@fe1b0000 { compatible =3D "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg =3D <0x0 0xfe1b0000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index c9f9dd2472f5..b9b509257aaa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1227,6 +1227,108 @@ qos_vop_m1: qos@fdf82200 { reg =3D <0x0 0xfdf82200 0x0 0x20>; }; =20 + pcie2x1l1: pcie@fe180000 { + compatible =3D "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x30 0x3f>; + clocks =3D <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, + <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, + <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type =3D "pci"; + interrupts =3D , + , + , + , + ; + interrupt-names =3D "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie2x1l1_intc 0>, + <0 0 0 2 &pcie2x1l1_intc 1>, + <0 0 0 3 &pcie2x1l1_intc 2>, + <0 0 0 4 &pcie2x1l1_intc 3>; + linux,pci-domain =3D <3>; + max-link-speed =3D <2>; + msi-map =3D <0x3000 &its0 0x3000 0x1000>; + num-lanes =3D <1>; + phys =3D <&combphy2_psu PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + power-domains =3D <&power RK3588_PD_PCIE>; + ranges =3D <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, + <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; + reg =3D <0xa 0x40c00000 0x0 0x00400000>, + <0x0 0xfe180000 0x0 0x00010000>, + <0x0 0xf3000000 0x0 0x00100000>; + reg-names =3D "dbi", "apb", "config"; + resets =3D <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; + reset-names =3D "pwr", "pipe"; + status =3D "disabled"; + + pcie2x1l1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + }; + + pcie2x1l2: pcie@fe190000 { + compatible =3D "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x40 0x4f>; + clocks =3D <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, + <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, + <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; + clock-names =3D "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type =3D "pci"; + interrupts =3D , + , + , + , + ; + interrupt-names =3D "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie2x1l2_intc 0>, + <0 0 0 2 &pcie2x1l2_intc 1>, + <0 0 0 3 &pcie2x1l2_intc 2>, + <0 0 0 4 &pcie2x1l2_intc 3>; + linux,pci-domain =3D <4>; + max-link-speed =3D <2>; + msi-map =3D <0x4000 &its0 0x4000 0x1000>; + num-lanes =3D <1>; + phys =3D <&combphy0_ps PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + power-domains =3D <&power RK3588_PD_PCIE>; + ranges =3D <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, + <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; + reg =3D <0xa 0x41000000 0x0 0x00400000>, + <0x0 0xfe190000 0x0 0x00010000>, + <0x0 0xf4000000 0x0 0x00100000>; + reg-names =3D "dbi", "apb", "config"; + resets =3D <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; + reset-names =3D "pwr", "pipe"; + status =3D "disabled"; + + pcie2x1l2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + }; + gmac1: ethernet@fe1c0000 { compatible =3D "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg =3D <0x0 0xfe1c0000 0x0 0x10000>; --=20 2.40.1