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[211.75.219.203]) by smtp.gmail.com with ESMTPSA id i14-20020a17090a2a0e00b00263e59c1a9fsm4625849pjd.34.2023.07.16.22.43.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Jul 2023 22:43:44 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Catalin Marinas , Will Deacon , John Garry , James Clark , Mike Leach , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Adrian Hunter , D Scott Phillips , Marc Zyngier , Anshuman Khandual , German Gomez , Ali Saidi , Jing Zhang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, fissure2010@gmail.com Cc: Leo Yan Subject: [PATCH v1 1/3] arm64: Add Cortex-X4 CPU part definitions Date: Mon, 17 Jul 2023 13:43:25 +0800 Message-Id: <20230717054327.79815-2-leo.yan@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230717054327.79815-1-leo.yan@linaro.org> References: <20230717054327.79815-1-leo.yan@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the part number and MIDR definitions for Cortex-X4. Signed-off-by: Leo Yan Reviewed-by: Ali Saidi Reviewed-by: Anshuman Khandual --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cput= ype.h index 5f6f84837a49..415be1a000c6 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -84,6 +84,7 @@ #define ARM_CPU_PART_CORTEX_X2 0xD48 #define ARM_CPU_PART_NEOVERSE_N2 0xD49 #define ARM_CPU_PART_CORTEX_A78C 0xD4B +#define ARM_CPU_PART_CORTEX_X4 0xD82 =20 #define APM_CPU_PART_POTENZA 0x000 =20 @@ -153,6 +154,7 @@ #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX= _X2) #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOV= ERSE_N2) #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORT= EX_A78C) +#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX= _X4) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_T= HUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_P= ART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_P= ART_THUNDERX_83XX) --=20 2.34.1 From nobody Fri Dec 19 04:36:44 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B23D1EB64DC for ; Mon, 17 Jul 2023 05:44:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231318AbjGQFoO (ORCPT ); Mon, 17 Jul 2023 01:44:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231314AbjGQFoE (ORCPT ); Mon, 17 Jul 2023 01:44:04 -0400 Received: from mail-oi1-x22c.google.com (mail-oi1-x22c.google.com [IPv6:2607:f8b0:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 710F1E6E for ; Sun, 16 Jul 2023 22:43:51 -0700 (PDT) Received: by mail-oi1-x22c.google.com with SMTP id 5614622812f47-3a3b7f992e7so3050608b6e.2 for ; Sun, 16 Jul 2023 22:43:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689572630; x=1692164630; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LsbOtl8L95SdhjWYG9IqPkOwivVCIhS13RLWT0N8NVw=; b=vHh+YxpGgOeFPoUz6LbKohjblFtJ+aagx7LTHqU+6uuuDLEtG6yjzf4YQ7DE5QkgY+ ZJdUlNh5htpZgVKtizGZJ9JLuuGFMTv6fr/zmK8FZnef4x1qw6q9L2vVBjnsqYGQotpK 4DPUJYeRwOGpCw5cuywoWQ8XOzaVnNAA3onCMVooFi1M3CRp0Xa0086m25zw0BTQVOWg ukisL4F12f43EfIe4EHgU/gZlB8H82zLIIm1Sh+70JWJBUe/X6OdS4CQd8BjGtebaaGe n2TooFHDZuO82dSgdxNmMnxS5ngXRJmF4OCX2iAEO9NCzHG/UXoPOJNkUWMwxx01yBII 6Vug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689572630; x=1692164630; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LsbOtl8L95SdhjWYG9IqPkOwivVCIhS13RLWT0N8NVw=; b=aXQ3CWOekuBMly+f4kK5HrOZHG6dyoPR6F6hNzcfOO/8VQkx0b/tEcayDsmBriB/Mq hbCKzwVvAsR0NSh+3Hgj6xT4LfqbPzjGYxJy+5GzoVsJdhDA3Y+ZJjaS9Z4UiPyFzk0F oIgmTIp8PF/B01FpN2FhlxaQsmh7YJGYvvfiFa4ez1sr051XIkllXX13aHJbfVkQmlzW 4lomK56v8gohUuS1ryiLLHG+1M6djJZq4H69PGBb29eHVIFQmH1NfsPfHL3//SIzRf2L kd6+cJVLJxYU6UGRvgm7Hs9pAtngYQwzohCutXIv6K1B26aT6lsggc/zyFbhmwrc0gYg qtCQ== X-Gm-Message-State: ABy/qLYNQOHR4AdSesuvsFmk+fXfv+xfZPegZiiZOwS0EcW0D6oM67Fh uPk/gdXclznRky0j1GlpAj17og== X-Google-Smtp-Source: APBJJlEo6ll+1XbDqr9kcoMe97+yzdfGUxeY4rr02L0hXAIYQalB2a0NK6Q9W4JWbXy/Y8j2jLCDBQ== X-Received: by 2002:a05:6808:f87:b0:3a4:25ab:eecb with SMTP id o7-20020a0568080f8700b003a425abeecbmr11762333oiw.51.1689572630652; Sun, 16 Jul 2023 22:43:50 -0700 (PDT) Received: from leoy-huanghe.lan (211-75-219-203.hinet-ip.hinet.net. [211.75.219.203]) by smtp.gmail.com with ESMTPSA id i14-20020a17090a2a0e00b00263e59c1a9fsm4625849pjd.34.2023.07.16.22.43.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Jul 2023 22:43:50 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Catalin Marinas , Will Deacon , John Garry , James Clark , Mike Leach , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Adrian Hunter , D Scott Phillips , Marc Zyngier , Anshuman Khandual , German Gomez , Ali Saidi , Jing Zhang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, fissure2010@gmail.com Cc: Leo Yan Subject: [PATCH v1 2/3] tools headers arm64: Sync Cortex-X4 CPU part definitions Date: Mon, 17 Jul 2023 13:43:26 +0800 Message-Id: <20230717054327.79815-3-leo.yan@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230717054327.79815-1-leo.yan@linaro.org> References: <20230717054327.79815-1-leo.yan@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Sync Cortex-X4 CPU part number and MIDR definitions with the kernel header. Signed-off-by: Leo Yan Reviewed-by: Ali Saidi --- tools/arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/arch/arm64/include/asm/cputype.h b/tools/arch/arm64/incl= ude/asm/cputype.h index 5f6f84837a49..415be1a000c6 100644 --- a/tools/arch/arm64/include/asm/cputype.h +++ b/tools/arch/arm64/include/asm/cputype.h @@ -84,6 +84,7 @@ #define ARM_CPU_PART_CORTEX_X2 0xD48 #define ARM_CPU_PART_NEOVERSE_N2 0xD49 #define ARM_CPU_PART_CORTEX_A78C 0xD4B +#define ARM_CPU_PART_CORTEX_X4 0xD82 =20 #define APM_CPU_PART_POTENZA 0x000 =20 @@ -153,6 +154,7 @@ #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX= _X2) #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOV= ERSE_N2) #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORT= EX_A78C) +#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX= _X4) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_T= HUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_P= ART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_P= ART_THUNDERX_83XX) --=20 2.34.1 From nobody Fri Dec 19 04:36:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE62EEB64DC for ; Mon, 17 Jul 2023 05:44:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231387AbjGQFoZ (ORCPT ); Mon, 17 Jul 2023 01:44:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231317AbjGQFoH (ORCPT ); Mon, 17 Jul 2023 01:44:07 -0400 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69B3510E6 for ; Sun, 16 Jul 2023 22:43:57 -0700 (PDT) Received: by mail-pg1-x52e.google.com with SMTP id 41be03b00d2f7-55ba5bb0bf3so2421530a12.1 for ; Sun, 16 Jul 2023 22:43:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689572637; x=1692164637; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TyK1Jggty5zZRfu0FmHGDNpSPXcYX18o45hq3r51GJg=; b=iXWppoz1AtZx/m5XFZNR40D+3TcADWNzySwcCoQsC8xOqLO612ZBGmlEsB4fJEs7d6 ax4juD1nPhZsis8SaDw3nR0JT8vIqiq+LCmIVSTLgULfxal42o+la/rk7RIzjcnS6hNZ fuRyo21BSMXpJUlAtAMms6YDtg4a/GX6aX7oxHHXYte15u2Xa16C3wcH8Jqp15iqGjI9 rANF8+UAkRNYlS6flx0FCR1GOrLvMBfHUskPHw+L/pdM5riM7g6iqkiMaWaSB2QxKMl4 ELhTQUasJQ1wdhUzR2b2Iof5GcgwFPloqTGdM4+NvYX06E3mkY7CF8bmLxXuxD/2/w6l OPhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689572637; x=1692164637; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TyK1Jggty5zZRfu0FmHGDNpSPXcYX18o45hq3r51GJg=; b=Y6ueYYud7RyGBrWrbWe2LWlmLJdKUOTMC91c3k/fyOK3X3eUOqaUnhL+aIZwfyXJxK SfERFxodixbnkGwm7K+qqPhItpBMi8IGsrRRlwSkBhf+qW20QS3VrBBRE9ZucY8j9uBH hENqTzJDggtHLoWZbgFhn/V4qhLaEK6+lqd1Uxwazo2qrv1MMDHmjbPqAVReQJk3LUNh Purd0rIDrbWGvM0mbbAD0XBbRoj1FbEejw8bMl/4G9j16pgEjr3KmhwWZvIOSi+1fS9j 6q1dLArD6gDO8kI+fDcHLkFNrEOMmzodMtSvOPUE009u3TgYBmFFuOjE62tdJnvw8hYO orUQ== X-Gm-Message-State: ABy/qLbhv4ZVqHm0BB4e2tCZW8sSLCIaqVwY6wOwCAEo0vR/me6rjsBa RfDi0td78fMVMriccfO+5Vvw5w== X-Google-Smtp-Source: APBJJlFdGZVJYwmzxQ2PK7b0e7+IIasqkbhIeSaSVNpOZTQFe/vbgjUD2wWvkkqgR9tljz/+hAYuRg== X-Received: by 2002:a17:90b:784:b0:267:6fd0:bd31 with SMTP id l4-20020a17090b078400b002676fd0bd31mr11124005pjz.7.1689572636858; Sun, 16 Jul 2023 22:43:56 -0700 (PDT) Received: from leoy-huanghe.lan (211-75-219-203.hinet-ip.hinet.net. [211.75.219.203]) by smtp.gmail.com with ESMTPSA id i14-20020a17090a2a0e00b00263e59c1a9fsm4625849pjd.34.2023.07.16.22.43.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Jul 2023 22:43:56 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Catalin Marinas , Will Deacon , John Garry , James Clark , Mike Leach , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Adrian Hunter , D Scott Phillips , Marc Zyngier , Anshuman Khandual , German Gomez , Ali Saidi , Jing Zhang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, fissure2010@gmail.com Cc: Leo Yan Subject: [PATCH v1 3/3] perf arm-spe: Support data source for Cortex-X4 CPU Date: Mon, 17 Jul 2023 13:43:27 +0800 Message-Id: <20230717054327.79815-4-leo.yan@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230717054327.79815-1-leo.yan@linaro.org> References: <20230717054327.79815-1-leo.yan@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We have a CPU list to maintain Neoverse CPUs (N1/N2/V2), this list is used for parsing data source packet. Since Cortex-x4 CPU shares the same data source format with Neoverse CPUs, this commit adds Cortex-x4 CPU into the CPU list so we can reuse the parsing logic. The CPU list was assumed for only Neoverse CPUs, but now Cortex-X4 has been added into the list. To avoid Neoverse specific naming, this patch renames the variables and function as the default data source format. Signed-off-by: Leo Yan Reviewed-by: Ali Saidi --- tools/perf/util/arm-spe.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index afbd5869f6bf..c2cdb9f2e188 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -409,15 +409,16 @@ static int arm_spe__synth_instruction_sample(struct a= rm_spe_queue *speq, return arm_spe_deliver_synth_event(spe, speq, event, &sample); } =20 -static const struct midr_range neoverse_spe[] =3D { +static const struct midr_range cpus_use_default_data_src[] =3D { MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), {}, }; =20 -static void arm_spe__synth_data_source_neoverse(const struct arm_spe_recor= d *record, - union perf_mem_data_src *data_src) +static void arm_spe__synth_data_source_default(const struct arm_spe_record= *record, + union perf_mem_data_src *data_src) { /* * Even though four levels of cache hierarchy are possible, no known @@ -518,7 +519,8 @@ static void arm_spe__synth_data_source_generic(const st= ruct arm_spe_record *reco static u64 arm_spe__synth_data_source(const struct arm_spe_record *record,= u64 midr) { union perf_mem_data_src data_src =3D { .mem_op =3D PERF_MEM_OP_NA }; - bool is_neoverse =3D is_midr_in_range_list(midr, neoverse_spe); + bool is_default_dc =3D + is_midr_in_range_list(midr, cpus_use_default_data_src); =20 if (record->op & ARM_SPE_OP_LD) data_src.mem_op =3D PERF_MEM_OP_LOAD; @@ -527,8 +529,8 @@ static u64 arm_spe__synth_data_source(const struct arm_= spe_record *record, u64 m else return 0; =20 - if (is_neoverse) - arm_spe__synth_data_source_neoverse(record, &data_src); + if (is_default_dc) + arm_spe__synth_data_source_default(record, &data_src); else arm_spe__synth_data_source_generic(record, &data_src); =20 --=20 2.34.1