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[178.235.179.17]) by smtp.gmail.com with ESMTPSA id es18-20020a056402381200b00554b1d1a934sm3014593edb.27.2024.01.13.06.50.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jan 2024 06:50:58 -0800 (PST) From: Konrad Dybcio Date: Sat, 13 Jan 2024 15:50:50 +0100 Subject: [PATCH v6 01/12] clk: qcom: branch: Add a helper for setting the enable bit Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230717-topic-branch_aon_cleanup-v6-1-46d136a4e8d0@linaro.org> References: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Johan Hovold , Bryan O'Donoghue X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1705157455; l=1413; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Bhpm8sfSCBACZPHOO1eUmAv4id2tp/m4vWhfhP3T9EI=; b=U8t99OE+nuQKV/KjR/tksz8wIitl5avD9kp1LgyS4lurH3E9MqzA2JPAXGXRDJX/IDCa6cSd6 SaAx0i7QOGtDyUV5qS112GadjQlq3T+qOYNNNfQuNbq0DpfgQzc8Sk8 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= We hardcode some clocks to be always-on, as they're essential to the functioning of the SoC / some peripherals. Add a helper to do so to make the writes less magic. Reviewed-by: Johan Hovold Reviewed-by: Bryan O'Donoghue Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-branch.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index 8ffed603c050..0514bc43100b 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -64,6 +64,7 @@ struct clk_mem_branch { #define CBCR_FORCE_MEM_PERIPH_OFF BIT(12) #define CBCR_WAKEUP GENMASK(11, 8) #define CBCR_SLEEP GENMASK(7, 4) +#define CBCR_CLOCK_ENABLE BIT(0) =20 static inline void qcom_branch_set_force_mem_core(struct regmap *regmap, struct clk_branch clk, bool on) @@ -98,6 +99,12 @@ static inline void qcom_branch_set_sleep(struct regmap *= regmap, struct clk_branc FIELD_PREP(CBCR_SLEEP, val)); } =20 +static inline void qcom_branch_set_clk_en(struct regmap *regmap, u32 cbcr) +{ + regmap_update_bits(regmap, cbcr, CBCR_CLOCK_ENABLE, + CBCR_CLOCK_ENABLE); +} + extern const struct clk_ops clk_branch_ops; extern const struct clk_ops clk_branch2_ops; extern const struct clk_ops clk_branch_simple_ops; --=20 2.43.0 From nobody Thu Dec 18 08:52:09 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A392259B for ; Sat, 13 Jan 2024 14:51:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="VLH+GBu5" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-40e63bc90f2so18263715e9.2 for ; Sat, 13 Jan 2024 06:51:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705157461; x=1705762261; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=KKcMhrufSxn2YOt3KsN7/849IvpZn9FSQAc0Hzkvap0=; b=VLH+GBu5Pu6E63DX4YWIrsG5K30iZFt/X5gqK1/yBLVLEAw2P1DS5c4j+J1ye6PUaF mmKMRzqeYz9OUxYoHrdnzlf8m6wHZaNJre57k3lBS4k2m7hRB3pfpQHLPNdO7+uvydKd XUTieQIoVLKkOMI1RaC8JQG137h/zh5yeNC14Pk22HqtHHI/kBfSvEk5SxHbpmOg8Pjv EPjsiSet2cKTUGLpie+Oe+voKvDw5BGG1v2XH/iBiLAVQA0l/4hA5LLPYsCa0Ounik2H Sml++wzFQ01d9wyNXsjGILCgLdTYkSDhFwzJ/69GFRPjZvQaDlydtXt8aLRrXjmTO0Lf wALg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705157461; x=1705762261; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KKcMhrufSxn2YOt3KsN7/849IvpZn9FSQAc0Hzkvap0=; b=Z+q4+YpbgvtEAisYAMzXdyKLnVStlwz8x5d+t7mqokboHqSYPgq2FvvqHd+jiMBw1Z IDyo9tZUhNyqAFiXNB88ZJ1GWv4mvtCA48HsQkgjQWH/YFpl7QeBKNKCd8yO9vkRcSsY erIj3KGqj/a65a2F7dfsTJmJ/uenPGqBj+hVkp3smrHgITklOYkQ6CVkIO3Rs4J6jb30 HwG/CCzHRDquifML2xyJvQBe8Ir91n1BsEKsJEnCl97Y09UFchT7WAx8gR2YQFI9yLL+ HmHW/S4D1k3Rtkky/GYBk/EvQlD5TEvQudtY681btpY4iZVHa0T0Fi3o+u1fkfkWAnaO oegQ== X-Gm-Message-State: AOJu0YxytFuTMQXvsEBYbemwILv7IDEaJQDwVYoYLsrJtUFpa8Ugxp6w aekohq+O81hC2OlJZ+in+b+Qk209JW7V/SIWDy49zofoNP0= X-Google-Smtp-Source: AGHT+IGDYTt1NHkyNJCsNk45Y4PAm9JphkrLE5FHMBBJ7X/4//v1s7TKIkE1DHM2wx/Ac/5O+D9Pdg== X-Received: by 2002:a05:600c:1c0a:b0:40d:6582:4729 with SMTP id j10-20020a05600c1c0a00b0040d65824729mr1767109wms.130.1705157460865; Sat, 13 Jan 2024 06:51:00 -0800 (PST) Received: from [10.167.154.1] (178235179017.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.17]) by smtp.gmail.com with ESMTPSA id es18-20020a056402381200b00554b1d1a934sm3014593edb.27.2024.01.13.06.50.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jan 2024 06:51:00 -0800 (PST) From: Konrad Dybcio Date: Sat, 13 Jan 2024 15:50:51 +0100 Subject: [PATCH v6 02/12] clk: qcom: Use qcom_branch_set_clk_en() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230717-topic-branch_aon_cleanup-v6-2-46d136a4e8d0@linaro.org> References: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Bryan O'Donoghue , Johan Hovold X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1705157455; l=41674; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Hqa/SLNxjNawmEvpnyso/fRmpcjU8j9z348q44Gf+fY=; b=0+4lQEMUKRUd126u0e2A5dJKn643Fr64OHO0mKxTE3ikV7ZmGv3SkksIl3MSZw+eazs4Pdjxq emThN3H86xqBSkiOfO6hFjnCMI7KgIJ6nNgzFwjuj9eUR0hZYN1ZHzx X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Instead of magically poking at the bit0 of branch clocks' CBCR, use the newly introduced helper. Reviewed-by: Bryan O'Donoghue Reviewed-by: Johan Hovold Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/camcc-sc8280xp.c | 6 ++---- drivers/clk/qcom/camcc-sm8550.c | 10 +++------- drivers/clk/qcom/dispcc-qcm2290.c | 4 ++-- drivers/clk/qcom/dispcc-sc7280.c | 7 ++----- drivers/clk/qcom/dispcc-sc8280xp.c | 4 ++-- drivers/clk/qcom/dispcc-sm6115.c | 4 ++-- drivers/clk/qcom/dispcc-sm8250.c | 4 ++-- drivers/clk/qcom/dispcc-sm8450.c | 7 ++----- drivers/clk/qcom/dispcc-sm8550.c | 7 ++----- drivers/clk/qcom/dispcc-sm8650.c | 4 ++-- drivers/clk/qcom/gcc-sa8775p.c | 25 ++++++++++--------------- drivers/clk/qcom/gcc-sc7180.c | 22 +++++++++------------- drivers/clk/qcom/gcc-sc7280.c | 20 ++++++++------------ drivers/clk/qcom/gcc-sc8180x.c | 28 +++++++++++----------------- drivers/clk/qcom/gcc-sc8280xp.c | 25 ++++++++++--------------- drivers/clk/qcom/gcc-sdx55.c | 12 ++++-------- drivers/clk/qcom/gcc-sdx65.c | 13 +++++-------- drivers/clk/qcom/gcc-sdx75.c | 10 +++------- drivers/clk/qcom/gcc-sm4450.c | 28 +++++++++------------------- drivers/clk/qcom/gcc-sm6375.c | 11 ++++------- drivers/clk/qcom/gcc-sm7150.c | 23 +++++++++-------------- drivers/clk/qcom/gcc-sm8250.c | 19 +++++++------------ drivers/clk/qcom/gcc-sm8350.c | 20 ++++++++------------ drivers/clk/qcom/gcc-sm8450.c | 21 ++++++++------------- drivers/clk/qcom/gcc-sm8550.c | 21 ++++++++------------- drivers/clk/qcom/gcc-sm8650.c | 16 ++++++++-------- drivers/clk/qcom/gcc-x1e80100.c | 16 ++++++++-------- drivers/clk/qcom/gpucc-sc7280.c | 9 +++------ drivers/clk/qcom/gpucc-sc8280xp.c | 9 +++------ drivers/clk/qcom/gpucc-sm8550.c | 10 +++------- drivers/clk/qcom/lpasscorecc-sc7180.c | 7 ++----- drivers/clk/qcom/videocc-sm8250.c | 6 +++--- drivers/clk/qcom/videocc-sm8350.c | 10 +++------- drivers/clk/qcom/videocc-sm8450.c | 13 ++++--------- drivers/clk/qcom/videocc-sm8550.c | 13 ++++--------- 35 files changed, 175 insertions(+), 289 deletions(-) diff --git a/drivers/clk/qcom/camcc-sc8280xp.c b/drivers/clk/qcom/camcc-sc8= 280xp.c index 3dcd79b01515..84f9caf3ddbf 100644 --- a/drivers/clk/qcom/camcc-sc8280xp.c +++ b/drivers/clk/qcom/camcc-sc8280xp.c @@ -3010,10 +3010,8 @@ static int camcc_sc8280xp_probe(struct platform_devi= ce *pdev) clk_lucid_pll_configure(&camcc_pll6, regmap, &camcc_pll6_config); clk_lucid_pll_configure(&camcc_pll7, regmap, &camcc_pll7_config); =20 - /* - * Keep camcc_gdsc_clk always enabled: - */ - regmap_update_bits(regmap, 0xc1e4, BIT(0), 1); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0xc1e4); /* CAMCC_GDSC_CLK */ =20 ret =3D qcom_cc_really_probe(pdev, &camcc_sc8280xp_desc, regmap); if (ret) diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm855= 0.c index dd51ba4ea757..1ef59a96f664 100644 --- a/drivers/clk/qcom/camcc-sm8550.c +++ b/drivers/clk/qcom/camcc-sm8550.c @@ -3536,13 +3536,9 @@ static int cam_cc_sm8550_probe(struct platform_devic= e *pdev) clk_lucid_ole_pll_configure(&cam_cc_pll11, regmap, &cam_cc_pll11_config); clk_lucid_ole_pll_configure(&cam_cc_pll12, regmap, &cam_cc_pll12_config); =20 - /* - * Keep clocks always enabled: - * cam_cc_gdsc_clk - * cam_cc_sleep_clk - */ - regmap_update_bits(regmap, 0x1419c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x142cc, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x1419c); /* CAM_CC_GDSC_CLK */ + qcom_branch_set_clk_en(regmap, 0x142cc); /* CAM_CC_SLEEP_CLK */ =20 ret =3D qcom_cc_really_probe(pdev, &cam_cc_sm8550_desc, regmap); =20 diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qc= m2290.c index 9206f0eed446..200f81ac4827 100644 --- a/drivers/clk/qcom/dispcc-qcm2290.c +++ b/drivers/clk/qcom/dispcc-qcm2290.c @@ -519,8 +519,8 @@ static int disp_cc_qcm2290_probe(struct platform_device= *pdev) =20 clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); =20 - /* Keep DISP_CC_XO_CLK always-ON */ - regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */ =20 ret =3D qcom_cc_really_probe(pdev, &disp_cc_qcm2290_desc, regmap); if (ret) { diff --git a/drivers/clk/qcom/dispcc-sc7280.c b/drivers/clk/qcom/dispcc-sc7= 280.c index ad596d567f6a..3ba07f08cbdd 100644 --- a/drivers/clk/qcom/dispcc-sc7280.c +++ b/drivers/clk/qcom/dispcc-sc7280.c @@ -878,11 +878,8 @@ static int disp_cc_sc7280_probe(struct platform_device= *pdev) =20 clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); =20 - /* - * Keep the clocks always-ON - * DISP_CC_XO_CLK - */ - regmap_update_bits(regmap, 0x5008, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x5008); /* DISP_CC_XO_CLK */ =20 return qcom_cc_really_probe(pdev, &disp_cc_sc7280_desc, regmap); } diff --git a/drivers/clk/qcom/dispcc-sc8280xp.c b/drivers/clk/qcom/dispcc-s= c8280xp.c index 30f636b9f0ec..bd1ffb143e0c 100644 --- a/drivers/clk/qcom/dispcc-sc8280xp.c +++ b/drivers/clk/qcom/dispcc-sc8280xp.c @@ -3178,8 +3178,8 @@ static int disp_cc_sc8280xp_probe(struct platform_dev= ice *pdev) goto out_pm_runtime_put; } =20 - /* DISP_CC_XO_CLK always-on */ - regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */ =20 out_pm_runtime_put: pm_runtime_put_sync(&pdev->dev); diff --git a/drivers/clk/qcom/dispcc-sm6115.c b/drivers/clk/qcom/dispcc-sm6= 115.c index 1fab43f08e73..bd07f26af35a 100644 --- a/drivers/clk/qcom/dispcc-sm6115.c +++ b/drivers/clk/qcom/dispcc-sm6115.c @@ -583,8 +583,8 @@ static int disp_cc_sm6115_probe(struct platform_device = *pdev) =20 clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); =20 - /* Keep DISP_CC_XO_CLK always-ON */ - regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */ =20 ret =3D qcom_cc_really_probe(pdev, &disp_cc_sm6115_desc, regmap); if (ret) { diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8= 250.c index e17bb8b543b5..ccf696c74dc3 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -1365,8 +1365,8 @@ static int disp_cc_sm8250_probe(struct platform_devic= e *pdev) /* Enable clock gating for MDP clocks */ regmap_update_bits(regmap, 0x8000, 0x10, 0x10); =20 - /* DISP_CC_XO_CLK always-on */ - regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */ =20 ret =3D qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap); =20 diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8= 450.c index 2c4aecd75186..b358751aba4b 100644 --- a/drivers/clk/qcom/dispcc-sm8450.c +++ b/drivers/clk/qcom/dispcc-sm8450.c @@ -1787,11 +1787,8 @@ static int disp_cc_sm8450_probe(struct platform_devi= ce *pdev) /* Enable clock gating for MDP clocks */ regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); =20 - /* - * Keep clocks always enabled: - * disp_cc_xo_clk - */ - regmap_update_bits(regmap, 0xe05c, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0xe05c); /* DISP_CC_XO_CLK */ =20 ret =3D qcom_cc_really_probe(pdev, &disp_cc_sm8450_desc, regmap); if (ret) diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8= 550.c index f96d8b81fd9a..3d86b20e2062 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -1780,11 +1780,8 @@ static int disp_cc_sm8550_probe(struct platform_devi= ce *pdev) /* Enable clock gating for MDP clocks */ regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); =20 - /* - * Keep clocks always enabled: - * disp_cc_xo_clk - */ - regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */ =20 ret =3D qcom_cc_really_probe(pdev, &disp_cc_sm8550_desc, regmap); if (ret) diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8= 650.c index f3b1d9d16bae..795ac4d93658 100644 --- a/drivers/clk/qcom/dispcc-sm8650.c +++ b/drivers/clk/qcom/dispcc-sm8650.c @@ -1777,8 +1777,8 @@ static int disp_cc_sm8650_probe(struct platform_devic= e *pdev) /* Enable clock gating for MDP clocks */ regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); =20 - /* Keep clocks always enabled */ - regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0)); /* disp_cc_xo_clk */ + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */ =20 ret =3D qcom_cc_really_probe(pdev, &disp_cc_sm8650_desc, regmap); if (ret) diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c index 8171d23c96e6..9dbb68f60d86 100644 --- a/drivers/clk/qcom/gcc-sa8775p.c +++ b/drivers/clk/qcom/gcc-sa8775p.c @@ -4742,21 +4742,16 @@ static int gcc_sa8775p_probe(struct platform_device= *pdev) if (ret) return ret; =20 - /* - * Keep the clocks always-ON - * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP1_AHB_CLK, - * GCC_DISP1_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK, - * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK. - */ - regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x32020, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xc7004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xc7018, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x33004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x33018, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x7d004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x34004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x34024, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x32020); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0xc7004); /* GCC_DISP1_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0xc7018); /* GCC_DISP1_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x33004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x33018); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x7d004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */ =20 return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap); } diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c index a3406aadbd17..6a5f785c0ced 100644 --- a/drivers/clk/qcom/gcc-sc7180.c +++ b/drivers/clk/qcom/gcc-sc7180.c @@ -2443,19 +2443,15 @@ static int gcc_sc7180_probe(struct platform_device = *pdev) regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); regmap_update_bits(regmap, 0x71028, 0x3, 0x3); =20 - /* - * Keep the clocks always-ON - * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, - * GCC_DISP_AHB_CLK, GCC_GPU_CFG_AHB_CLK - */ - regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b02c); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b028); /* GCC_VIDEO_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b030); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ =20 ret =3D qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index 2b661df5de26..f45a8318900c 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -3453,18 +3453,14 @@ static int gcc_sc7280_probe(struct platform_device = *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); =20 - /* - * Keep the clocks always-ON - * GCC_CAMERA_AHB_CLK/XO_CLK, GCC_DISP_AHB_CLK/XO_CLK - * GCC_VIDEO_AHB_CLK/XO_CLK, GCC_GPU_CFG_AHB_CLK - */ - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x2701C, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28014, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x26004);/* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x26028);/* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x27004);/* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x2701c);/* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x28004);/* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x28014);/* GCC_VIDEO_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004);/* GCC_GPU_CFG_AHB_CLK */ regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13)); =20 ret =3D qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c index ae2147381559..c8dfe76f5582 100644 --- a/drivers/clk/qcom/gcc-sc8180x.c +++ b/drivers/clk/qcom/gcc-sc8180x.c @@ -4579,23 +4579,17 @@ static int gcc_sc8180x_probe(struct platform_device= *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); =20 - /* - * Enable the following always-on clocks: - * GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK, - * GCC_VIDEO_XO_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_XO_CLK, - * GCC_CPUSS_GNOC_CLK, GCC_CPUSS_DVM_BUS_CLK, GCC_NPU_CFG_AHB_CLK and - * GCC_GPU_CFG_AHB_CLK - */ - regmap_update_bits(regmap, 0xb004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xb008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xb00c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xb040, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xb044, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xb048, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x48190, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x4d004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0xb004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0xb008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0xb00c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0xb040); /* GCC_VIDEO_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0xb044); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0xb048); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */ + qcom_branch_set_clk_en(regmap, 0x48190); /* GCC_CPUSS_DVM_BUS_CLK */ + qcom_branch_set_clk_en(regmap, 0x4d004); /* GCC_NPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ =20 /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280x= p.c index bfb77931e868..816a06bfedb2 100644 --- a/drivers/clk/qcom/gcc-sc8280xp.c +++ b/drivers/clk/qcom/gcc-sc8280xp.c @@ -7543,21 +7543,16 @@ static int gcc_sc8280xp_probe(struct platform_devic= e *pdev) goto err_put_rpm; } =20 - /* - * Keep the clocks always-ON - * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK, - * GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, - * GCC_VIDEO_XO_CLK, GCC_DISP1_AHB_CLK, GCC_DISP1_XO_CLK - */ - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x26020, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xbb004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xbb028, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x26020); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x27028); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x28004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x28028); /* GCC_VIDEO_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0xbb004); /* GCC_DISP1_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0xbb028); /* GCC_DISP1_XO_CLK */ =20 ret =3D qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_d= fs_clocks)); if (ret) diff --git a/drivers/clk/qcom/gcc-sdx55.c b/drivers/clk/qcom/gcc-sdx55.c index d5e17122698c..26279b8d321a 100644 --- a/drivers/clk/qcom/gcc-sdx55.c +++ b/drivers/clk/qcom/gcc-sdx55.c @@ -1611,14 +1611,10 @@ static int gcc_sdx55_probe(struct platform_device *= pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); =20 - /* - * Keep the clocks always-ON as they are critical to the functioning - * of the system: - * GCC_SYS_NOC_CPUSS_AHB_CLK, GCC_CPUSS_AHB_CLK, GCC_CPUSS_GNOC_CLK - */ - regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); - regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x6d008); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ + regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_C= LK */ + regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_= CLK */ =20 return qcom_cc_really_probe(pdev, &gcc_sdx55_desc, regmap); } diff --git a/drivers/clk/qcom/gcc-sdx65.c b/drivers/clk/qcom/gcc-sdx65.c index ffddbed5a6db..8fde6463574b 100644 --- a/drivers/clk/qcom/gcc-sdx65.c +++ b/drivers/clk/qcom/gcc-sdx65.c @@ -1574,14 +1574,11 @@ static int gcc_sdx65_probe(struct platform_device *= pdev) regmap =3D qcom_cc_map(pdev, &gcc_sdx65_desc); if (IS_ERR(regmap)) return PTR_ERR(regmap); - /* - * Keep the clocks always-ON as they are critical to the functioning - * of the system: - * GCC_SYS_NOC_CPUSS_AHB_CLK, GCC_CPUSS_AHB_CLK, GCC_CPUSS_GNOC_CLK - */ - regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); - regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); + + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x6d008); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ + regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_C= LK */ + regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_= CLK */ =20 return qcom_cc_really_probe(pdev, &gcc_sdx65_desc, regmap); } diff --git a/drivers/clk/qcom/gcc-sdx75.c b/drivers/clk/qcom/gcc-sdx75.c index 573af17bd24c..c51338f08ef1 100644 --- a/drivers/clk/qcom/gcc-sdx75.c +++ b/drivers/clk/qcom/gcc-sdx75.c @@ -2936,13 +2936,9 @@ static int gcc_sdx75_probe(struct platform_device *p= dev) if (ret) return ret; =20 - /* - * Keep clocks always enabled: - * gcc_ahb_pcie_link_clk - * gcc_xo_pcie_link_clk - */ - regmap_update_bits(regmap, 0x3e004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x3e008, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x3e004); /* GCC_AHB_PCIE_LINK_CLK */ + qcom_branch_set_clk_en(regmap, 0x3e008); /* GCC_XO_PCIE_LINK_CLK */ =20 return qcom_cc_really_probe(pdev, &gcc_sdx75_desc, regmap); } diff --git a/drivers/clk/qcom/gcc-sm4450.c b/drivers/clk/qcom/gcc-sm4450.c index 31abe2775fc8..1226d39e6442 100644 --- a/drivers/clk/qcom/gcc-sm4450.c +++ b/drivers/clk/qcom/gcc-sm4450.c @@ -2849,25 +2849,15 @@ static int gcc_sm4450_probe(struct platform_device = *pdev) =20 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); =20 - /* - * Keep clocks always enabled: - * gcc_camera_ahb_clk - * gcc_camera_sleep_clk - * gcc_camera_xo_clk - * gcc_disp_ahb_clk - * gcc_disp_xo_clk - * gcc_gpu_cfg_ahb_clk - * gcc_video_ahb_clk - * gcc_video_xo_clk - */ - regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x36018, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x3601c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x37014, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x42018, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x36018); /* GCC_CAMERA_SLEEP_CLK */ + qcom_branch_set_clk_en(regmap, 0x3601c); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x37004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x37014); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x81004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x42018); /* GCC_VIDEO_XO_CLK */ =20 regmap_update_bits(regmap, 0x4201c, BIT(21), BIT(21)); =20 diff --git a/drivers/clk/qcom/gcc-sm6375.c b/drivers/clk/qcom/gcc-sm6375.c index 3dd15d765b22..84639d5b89bf 100644 --- a/drivers/clk/qcom/gcc-sm6375.c +++ b/drivers/clk/qcom/gcc-sm6375.c @@ -3882,13 +3882,10 @@ static int gcc_sm6375_probe(struct platform_device = *pdev) if (ret) return ret; =20 - /* - * Keep the following clocks always on: - * GCC_CAMERA_XO_CLK, GCC_CPUSS_GNOC_CLK, GCC_DISP_XO_CLK - */ - regmap_update_bits(regmap, 0x17028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x2b004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x1702c, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x17028); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x2b004); /* GCC_CPUSS_GNOC_CLK */ + qcom_branch_set_clk_en(regmap, 0x1702c); /* GCC_DISP_XO_CLK */ =20 clk_lucid_pll_configure(&gpll10, regmap, &gpll10_config); clk_lucid_pll_configure(&gpll11, regmap, &gpll11_config); diff --git a/drivers/clk/qcom/gcc-sm7150.c b/drivers/clk/qcom/gcc-sm7150.c index d9983bb27475..47c25b3d95ad 100644 --- a/drivers/clk/qcom/gcc-sm7150.c +++ b/drivers/clk/qcom/gcc-sm7150.c @@ -3002,20 +3002,15 @@ static int gcc_sm7150_probe(struct platform_device = *pdev) regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); regmap_update_bits(regmap, 0x71028, 0x3, 0x3); =20 - /* - * Keep the critical clocks always-ON - * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, - * GCC_DISP_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_VIDEO_XO_CLK, - * GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK - */ - regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b02c); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b028); /* GCC_VIDEO_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b030); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ =20 ret =3D qcom_cc_register_rcg_dfs(regmap, gcc_sm7150_dfs_desc, ARRAY_SIZE(gcc_sm7150_dfs_desc)); diff --git a/drivers/clk/qcom/gcc-sm8250.c b/drivers/clk/qcom/gcc-sm8250.c index c6c5261264f1..9990931aa172 100644 --- a/drivers/clk/qcom/gcc-sm8250.c +++ b/drivers/clk/qcom/gcc-sm8250.c @@ -3643,18 +3643,13 @@ static int gcc_sm8250_probe(struct platform_device = *pdev) regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); regmap_update_bits(regmap, 0x71028, 0x3, 0x3); =20 - /* - * Keep the clocks always-ON - * GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK, - * GCC_CPUSS_DVM_BUS_CLK, GCC_GPU_CFG_AHB_CLK, - * GCC_SYS_NOC_CPUSS_AHB_CLK - */ - regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x4818c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x52000, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x4818c); /* GCC_CPUSS_DVM_BUS_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x52000); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ =20 ret =3D qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c index 1385a98eb3bb..e83a9facc19b 100644 --- a/drivers/clk/qcom/gcc-sm8350.c +++ b/drivers/clk/qcom/gcc-sm8350.c @@ -3806,18 +3806,14 @@ static int gcc_sm8350_probe(struct platform_device = *pdev) return PTR_ERR(regmap); } =20 - /* - * Keep the critical clock always-On - * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_C= LK, - * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK - */ - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x26018, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x2701c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28020, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x26018); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x2701c); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x28004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x28020); /* GCC_VIDEO_XO_CLK */ =20 ret =3D qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_d= fs_clocks)); if (ret) diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c index 563542982551..43e9c32921f3 100644 --- a/drivers/clk/qcom/gcc-sm8450.c +++ b/drivers/clk/qcom/gcc-sm8450.c @@ -3280,19 +3280,14 @@ static int gcc_sm8450_probe(struct platform_device = *pdev) /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BI= T(14)); =20 - /* - * Keep the critical clock always-On - * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk, - * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk, - * gcc_video_xo_clk - */ - regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x36020, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x3701c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x42028, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x36020); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x37004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x3701c); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x81004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x42028); /* GCC_VIDEO_XO_CLK */ =20 return qcom_cc_really_probe(pdev, &gcc_sm8450_desc, regmap); } diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c index b883dffe5f7a..60895648f281 100644 --- a/drivers/clk/qcom/gcc-sm8550.c +++ b/drivers/clk/qcom/gcc-sm8550.c @@ -3352,19 +3352,14 @@ static int gcc_sm8550_probe(struct platform_device = *pdev) /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BI= T(14)); =20 - /* - * Keep the critical clock always-On - * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk, - * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk, - * gcc_video_xo_clk - */ - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */ =20 /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ regmap_write(regmap, 0x52024, 0x0); diff --git a/drivers/clk/qcom/gcc-sm8650.c b/drivers/clk/qcom/gcc-sm8650.c index 9174dd82308c..c4a6540b1522 100644 --- a/drivers/clk/qcom/gcc-sm8650.c +++ b/drivers/clk/qcom/gcc-sm8650.c @@ -3808,14 +3808,14 @@ static int gcc_sm8650_probe(struct platform_device = *pdev) if (ret) return ret; =20 - /* Keep the critical clock always-On */ - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); /* gcc_camera_ahb_cl= k */ - regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); /* gcc_camera_xo_clk= */ - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); /* gcc_disp_ahb_clk = */ - regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); /* gcc_disp_xo_clk */ - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); /* gcc_gpu_cfg_ahb_c= lk */ - regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); /* gcc_video_ahb_clk= */ - regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); /* gcc_video_xo_clk = */ + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */ =20 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); =20 diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e8010= 0.c index d7182d6e9783..1404017be918 100644 --- a/drivers/clk/qcom/gcc-x1e80100.c +++ b/drivers/clk/qcom/gcc-x1e80100.c @@ -6769,14 +6769,14 @@ static int gcc_x1e80100_probe(struct platform_devic= e *pdev) if (ret) return ret; =20 - /* Keep the critical clock always-On */ - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); /* gcc_camera_ahb_cl= k */ - regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); /* gcc_camera_xo_clk= */ - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); /* gcc_disp_ahb_clk = */ - regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); /* gcc_disp_xo_clk */ - regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); /* gcc_video_ahb_clk= */ - regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); /* gcc_video_xo_clk = */ - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); /* gcc_gpu_cfg_ahb_c= lk */ + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ =20 /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ regmap_write(regmap, 0x52224, 0x0); diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc728= 0.c index 1490cd45a654..293b57080685 100644 --- a/drivers/clk/qcom/gpucc-sc7280.c +++ b/drivers/clk/qcom/gpucc-sc7280.c @@ -457,12 +457,9 @@ static int gpu_cc_sc7280_probe(struct platform_device = *pdev) =20 clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); =20 - /* - * Keep the clocks always-ON - * GPU_CC_CB_CLK, GPUCC_CX_GMU_CLK - */ - regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x1098, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x1170); /* GPU_CC_CB_CLK */ + qcom_branch_set_clk_en(regmap, 0x1098); /* GPUCC_CX_GMU_CLK */ regmap_update_bits(regmap, 0x1098, BIT(13), BIT(13)); =20 return qcom_cc_really_probe(pdev, &gpu_cc_sc7280_desc, regmap); diff --git a/drivers/clk/qcom/gpucc-sc8280xp.c b/drivers/clk/qcom/gpucc-sc8= 280xp.c index 8e147ee294ee..a8ea2143057d 100644 --- a/drivers/clk/qcom/gpucc-sc8280xp.c +++ b/drivers/clk/qcom/gpucc-sc8280xp.c @@ -444,12 +444,9 @@ static int gpu_cc_sc8280xp_probe(struct platform_devic= e *pdev) clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); =20 - /* - * Keep the clocks always-ON - * GPU_CC_CB_CLK, GPU_CC_CXO_CLK - */ - regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x109c, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x1170); /* GPU_CC_CB_CLK */ + qcom_branch_set_clk_en(regmap, 0x109c); /* GPU_CC_CXO_CLK */ =20 ret =3D qcom_cc_really_probe(pdev, &gpu_cc_sc8280xp_desc, regmap); pm_runtime_put(&pdev->dev); diff --git a/drivers/clk/qcom/gpucc-sm8550.c b/drivers/clk/qcom/gpucc-sm855= 0.c index 2fa8673424d7..783d14ef9a0c 100644 --- a/drivers/clk/qcom/gpucc-sm8550.c +++ b/drivers/clk/qcom/gpucc-sm8550.c @@ -575,13 +575,9 @@ static int gpu_cc_sm8550_probe(struct platform_device = *pdev) clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); =20 - /* - * Keep clocks always enabled: - * gpu_cc_cxo_aon_clk - * gpu_cc_demet_clk - */ - regmap_update_bits(regmap, 0x9004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x900c, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x9004); /* GPU_CC_CXO_AON_CLK */ + qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */ =20 return qcom_cc_really_probe(pdev, &gpu_cc_sm8550_desc, regmap); } diff --git a/drivers/clk/qcom/lpasscorecc-sc7180.c b/drivers/clk/qcom/lpass= corecc-sc7180.c index 9051fd567112..fd9cd2e3f956 100644 --- a/drivers/clk/qcom/lpasscorecc-sc7180.c +++ b/drivers/clk/qcom/lpasscorecc-sc7180.c @@ -401,11 +401,8 @@ static int lpass_core_cc_sc7180_probe(struct platform_= device *pdev) goto exit; } =20 - /* - * Keep the CLK always-ON - * LPASS_AUDIO_CORE_SYSNOC_SWAY_CORE_CLK - */ - regmap_update_bits(regmap, 0x24000, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x24000); /* LPASS_AUDIO_CORE_SYSNOC_SWAY_= CORE_CLK */ =20 /* PLL settings */ regmap_write(regmap, 0x1008, 0x20); diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-s= m8250.c index ad46c4014a40..6fd8666813a8 100644 --- a/drivers/clk/qcom/videocc-sm8250.c +++ b/drivers/clk/qcom/videocc-sm8250.c @@ -383,9 +383,9 @@ static int video_cc_sm8250_probe(struct platform_device= *pdev) clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config); clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config); =20 - /* Keep VIDEO_CC_AHB_CLK and VIDEO_CC_XO_CLK ALWAYS-ON */ - regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0xe58); /* VIDEO_CC_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0xeec); /* VIDEO_CC_XO_CLK */ =20 ret =3D qcom_cc_really_probe(pdev, &video_cc_sm8250_desc, regmap); =20 diff --git a/drivers/clk/qcom/videocc-sm8350.c b/drivers/clk/qcom/videocc-s= m8350.c index 7246f3c99492..002e4c0666fa 100644 --- a/drivers/clk/qcom/videocc-sm8350.c +++ b/drivers/clk/qcom/videocc-sm8350.c @@ -558,13 +558,9 @@ static int video_cc_sm8350_probe(struct platform_devic= e *pdev) clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config); clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config); =20 - /* - * Keep clocks always enabled: - * video_cc_ahb_clk - * video_cc_xo_clk - */ - regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); - regmap_update_bits(regmap, video_cc_xo_clk_cbcr, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0xe58); /* VIDEO_CC_AHB_CLK */ + qcom_branch_set_clk_en(regmap, video_cc_xo_clk_cbcr); /* VIDEO_CC_XO_CLK = */ =20 ret =3D qcom_cc_really_probe(pdev, &video_cc_sm8350_desc, regmap); pm_runtime_put(&pdev->dev); diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-s= m8450.c index 16a61146e619..045eee07ea5f 100644 --- a/drivers/clk/qcom/videocc-sm8450.c +++ b/drivers/clk/qcom/videocc-sm8450.c @@ -423,15 +423,10 @@ static int video_cc_sm8450_probe(struct platform_devi= ce *pdev) clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config= ); clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config= ); =20 - /* - * Keep clocks always enabled: - * video_cc_ahb_clk - * video_cc_sleep_clk - * video_cc_xo_clk - */ - regmap_update_bits(regmap, 0x80e4, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x8130, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x8114, BIT(0), BIT(0)); + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x80e4); /* VIDEO_CC_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x8130); /* VIDEO_CC_SLEEP_CLK */ + qcom_branch_set_clk_en(regmap, 0x8114); /* VIDEO_CC_XO_CLK */ =20 ret =3D qcom_cc_really_probe(pdev, &video_cc_sm8450_desc, regmap); =20 diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-s= m8550.c index f3c9dfaee968..fa81e48f83e7 100644 --- a/drivers/clk/qcom/videocc-sm8550.c +++ b/drivers/clk/qcom/videocc-sm8550.c @@ -428,15 +428,10 @@ static int video_cc_sm8550_probe(struct platform_devi= ce *pdev) clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config= ); clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config= ); =20 - /* - * Keep clocks always enabled: - * video_cc_ahb_clk - * video_cc_sleep_clk - * video_cc_xo_clk - */ - regmap_update_bits(regmap, 0x80f4, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x8140, BIT(0), BIT(0)); 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[178.235.179.17]) by smtp.gmail.com with ESMTPSA id es18-20020a056402381200b00554b1d1a934sm3014593edb.27.2024.01.13.06.51.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jan 2024 06:51:01 -0800 (PST) From: Konrad Dybcio Date: Sat, 13 Jan 2024 15:50:52 +0100 Subject: [PATCH v6 03/12] clk: qcom: gcc-sm6375: Unregister critical clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230717-topic-branch_aon_cleanup-v6-3-46d136a4e8d0@linaro.org> References: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1705157455; l=7000; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=n0YeAp3nLuHYh3dXlhgQlSw1jrDIx7K6csG0Cr06aZE=; b=dRbJlqHhaU0iqTlKcwPZTnt1z8e4zVrWoHkn7st9srf3zn65RB/NnRqOF/WEbPqxYIkQQuqM+ hucezenxIYiBDy7pDWgAJfCRlapdW62Kkw2jcnzb+demLtLo5zzpBIH X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sm6375.c | 96 +++------------------------------------= ---- 1 file changed, 6 insertions(+), 90 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm6375.c b/drivers/clk/qcom/gcc-sm6375.c index 84639d5b89bf..1a45d1ae997a 100644 --- a/drivers/clk/qcom/gcc-sm6375.c +++ b/drivers/clk/qcom/gcc-sm6375.c @@ -1743,22 +1743,6 @@ static struct clk_branch gcc_cam_throttle_rt_clk =3D= { }, }; =20 -static struct clk_branch gcc_camera_ahb_clk =3D { - .halt_reg =3D 0x17008, - .halt_check =3D BRANCH_HALT_DELAY, - .hwcg_reg =3D 0x17008, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x17008, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_camera_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_camss_axi_clk =3D { .halt_reg =3D 0x58044, .halt_check =3D BRANCH_HALT, @@ -2309,22 +2293,6 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_c= lk =3D { }, }; =20 -static struct clk_branch gcc_disp_ahb_clk =3D { - .halt_reg =3D 0x1700c, - .halt_check =3D BRANCH_HALT_VOTED, - .hwcg_reg =3D 0x1700c, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x1700c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_disp_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_regmap_div gcc_disp_gpll0_clk_src =3D { .reg =3D 0x17058, .shift =3D 0, @@ -2455,22 +2423,6 @@ static struct clk_branch gcc_gp3_clk =3D { }, }; =20 -static struct clk_branch gcc_gpu_cfg_ahb_clk =3D { - .halt_reg =3D 0x36004, - .halt_check =3D BRANCH_HALT_VOTED, - .hwcg_reg =3D 0x36004, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x36004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_gpu_cfg_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gpu_gpll0_clk_src =3D { .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { @@ -3094,26 +3046,6 @@ static struct clk_branch gcc_sdcc2_apps_clk =3D { }, }; =20 -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk =3D { - .halt_reg =3D 0x2b06c, - .halt_check =3D BRANCH_HALT_VOTED, - .hwcg_reg =3D 0x2b06c, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x79004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_sys_noc_cpuss_ahb_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk =3D { .halt_reg =3D 0x45098, .halt_check =3D BRANCH_HALT, @@ -3433,22 +3365,6 @@ static struct clk_branch gcc_venus_ctl_axi_clk =3D { }, }; =20 -static struct clk_branch gcc_video_ahb_clk =3D { - .halt_reg =3D 0x17004, - .halt_check =3D BRANCH_HALT_DELAY, - .hwcg_reg =3D 0x17004, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x17004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_video_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_video_axi0_clk =3D { .halt_reg =3D 0x1701c, .halt_check =3D BRANCH_HALT_VOTED, @@ -3615,7 +3531,6 @@ static struct clk_regmap *gcc_sm6375_clocks[] =3D { [GCC_BOOT_ROM_AHB_CLK] =3D &gcc_boot_rom_ahb_clk.clkr, [GCC_CAM_THROTTLE_NRT_CLK] =3D &gcc_cam_throttle_nrt_clk.clkr, [GCC_CAM_THROTTLE_RT_CLK] =3D &gcc_cam_throttle_rt_clk.clkr, - [GCC_CAMERA_AHB_CLK] =3D &gcc_camera_ahb_clk.clkr, [GCC_CAMSS_AXI_CLK] =3D &gcc_camss_axi_clk.clkr, [GCC_CAMSS_AXI_CLK_SRC] =3D &gcc_camss_axi_clk_src.clkr, [GCC_CAMSS_CCI_0_CLK] =3D &gcc_camss_cci_0_clk.clkr, @@ -3671,7 +3586,6 @@ static struct clk_regmap *gcc_sm6375_clocks[] =3D { [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] =3D &gcc_cfg_noc_usb3_prim_axi_clk.clkr, [GCC_CPUSS_AHB_CLK_SRC] =3D &gcc_cpuss_ahb_clk_src.clkr, [GCC_CPUSS_AHB_POSTDIV_CLK_SRC] =3D &gcc_cpuss_ahb_postdiv_clk_src.clkr, - [GCC_DISP_AHB_CLK] =3D &gcc_disp_ahb_clk.clkr, [GCC_DISP_GPLL0_CLK_SRC] =3D &gcc_disp_gpll0_clk_src.clkr, [GCC_DISP_GPLL0_DIV_CLK_SRC] =3D &gcc_disp_gpll0_div_clk_src.clkr, [GCC_DISP_HF_AXI_CLK] =3D &gcc_disp_hf_axi_clk.clkr, @@ -3683,7 +3597,6 @@ static struct clk_regmap *gcc_sm6375_clocks[] =3D { [GCC_GP2_CLK_SRC] =3D &gcc_gp2_clk_src.clkr, [GCC_GP3_CLK] =3D &gcc_gp3_clk.clkr, [GCC_GP3_CLK_SRC] =3D &gcc_gp3_clk_src.clkr, - [GCC_GPU_CFG_AHB_CLK] =3D &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_GPLL0_CLK_SRC] =3D &gcc_gpu_gpll0_clk_src.clkr, [GCC_GPU_GPLL0_DIV_CLK_SRC] =3D &gcc_gpu_gpll0_div_clk_src.clkr, [GCC_GPU_MEMNOC_GFX_CLK] =3D &gcc_gpu_memnoc_gfx_clk.clkr, @@ -3739,7 +3652,6 @@ static struct clk_regmap *gcc_sm6375_clocks[] =3D { [GCC_SDCC2_AHB_CLK] =3D &gcc_sdcc2_ahb_clk.clkr, [GCC_SDCC2_APPS_CLK] =3D &gcc_sdcc2_apps_clk.clkr, [GCC_SDCC2_APPS_CLK_SRC] =3D &gcc_sdcc2_apps_clk_src.clkr, - [GCC_SYS_NOC_CPUSS_AHB_CLK] =3D &gcc_sys_noc_cpuss_ahb_clk.clkr, [GCC_SYS_NOC_UFS_PHY_AXI_CLK] =3D &gcc_sys_noc_ufs_phy_axi_clk.clkr, [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] =3D &gcc_sys_noc_usb3_prim_axi_clk.clkr, [GCC_UFS_PHY_AHB_CLK] =3D &gcc_ufs_phy_ahb_clk.clkr, @@ -3766,7 +3678,6 @@ static struct clk_regmap *gcc_sm6375_clocks[] =3D { [GCC_VCODEC0_AXI_CLK] =3D &gcc_vcodec0_axi_clk.clkr, [GCC_VENUS_AHB_CLK] =3D &gcc_venus_ahb_clk.clkr, [GCC_VENUS_CTL_AXI_CLK] =3D &gcc_venus_ctl_axi_clk.clkr, - [GCC_VIDEO_AHB_CLK] =3D &gcc_video_ahb_clk.clkr, [GCC_VIDEO_AXI0_CLK] =3D &gcc_video_axi0_clk.clkr, [GCC_VIDEO_THROTTLE_CORE_CLK] =3D &gcc_video_throttle_core_clk.clkr, [GCC_VIDEO_VCODEC0_SYS_CLK] =3D &gcc_video_vcodec0_sys_clk.clkr, @@ -3883,9 +3794,14 @@ static int gcc_sm6375_probe(struct platform_device *= pdev) return ret; =20 /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x17008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x17004); /* GCC_VIDEO_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x1700c); /* GCC_DISP_AHB_CLK */ qcom_branch_set_clk_en(regmap, 0x17028); /* GCC_CAMERA_XO_CLK */ - qcom_branch_set_clk_en(regmap, 0x2b004); /* GCC_CPUSS_GNOC_CLK */ qcom_branch_set_clk_en(regmap, 0x1702c); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x2b004); /* GCC_CPUSS_GNOC_CLK */ + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_GPU_CFG_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x79004); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ =20 clk_lucid_pll_configure(&gpll10, regmap, &gpll10_config); clk_lucid_pll_configure(&gpll11, regmap, &gpll11_config); --=20 2.43.0 From nobody Thu Dec 18 08:52:09 2025 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A212F4C83 for ; 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[178.235.179.17]) by smtp.gmail.com with ESMTPSA id es18-20020a056402381200b00554b1d1a934sm3014593edb.27.2024.01.13.06.51.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jan 2024 06:51:03 -0800 (PST) From: Konrad Dybcio Date: Sat, 13 Jan 2024 15:50:53 +0100 Subject: [PATCH v6 04/12] clk: qcom: gpucc-sm6375: Unregister critical clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230717-topic-branch_aon_cleanup-v6-4-46d136a4e8d0@linaro.org> References: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Bryan O'Donoghue X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1705157455; l=3066; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=GHhudpM9IAN/Lc38xFu1FTckBvfyQEfeLWFuAx9ceqc=; b=7oE4smrkZnOkrEHHwNnNDswIemR83jy9lAxpc3eCf2/ledvT52eVWjmnEk7MKLoeymLRkn+2H Igs3i9hFDqxD6by9/u36RhN6cPE0GcvaRaarFWx+Om6I0Zvq08J6sdP X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Reviewed-by: Bryan O'Donoghue Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gpucc-sm6375.c | 34 ++++------------------------------ 1 file changed, 4 insertions(+), 30 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm6375.c b/drivers/clk/qcom/gpucc-sm637= 5.c index da24276a018e..07ebe5e139d5 100644 --- a/drivers/clk/qcom/gpucc-sm6375.c +++ b/drivers/clk/qcom/gpucc-sm6375.c @@ -183,20 +183,6 @@ static struct clk_rcg2 gpucc_gx_gfx3d_clk_src =3D { }, }; =20 -static struct clk_branch gpucc_ahb_clk =3D { - .halt_reg =3D 0x1078, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x1078, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gpucc_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gpucc_cx_gfx3d_clk =3D { .halt_reg =3D 0x10a4, .halt_check =3D BRANCH_HALT_DELAY, @@ -294,20 +280,6 @@ static struct clk_branch gpucc_cxo_clk =3D { }, }; =20 -static struct clk_branch gpucc_gx_cxo_clk =3D { - .halt_reg =3D 0x1060, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x1060, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gpucc_gx_cxo_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gpucc_gx_gfx3d_clk =3D { .halt_reg =3D 0x1054, .halt_check =3D BRANCH_HALT_DELAY, @@ -381,7 +353,6 @@ static struct gdsc gpu_gx_gdsc =3D { }; =20 static struct clk_regmap *gpucc_sm6375_clocks[] =3D { - [GPU_CC_AHB_CLK] =3D &gpucc_ahb_clk.clkr, [GPU_CC_CX_GFX3D_CLK] =3D &gpucc_cx_gfx3d_clk.clkr, [GPU_CC_CX_GFX3D_SLV_CLK] =3D &gpucc_cx_gfx3d_slv_clk.clkr, [GPU_CC_CX_GMU_CLK] =3D &gpucc_cx_gmu_clk.clkr, @@ -389,7 +360,6 @@ static struct clk_regmap *gpucc_sm6375_clocks[] =3D { [GPU_CC_CXO_AON_CLK] =3D &gpucc_cxo_aon_clk.clkr, [GPU_CC_CXO_CLK] =3D &gpucc_cxo_clk.clkr, [GPU_CC_GMU_CLK_SRC] =3D &gpucc_gmu_clk_src.clkr, - [GPU_CC_GX_CXO_CLK] =3D &gpucc_gx_cxo_clk.clkr, [GPU_CC_GX_GFX3D_CLK] =3D &gpucc_gx_gfx3d_clk.clkr, [GPU_CC_GX_GFX3D_CLK_SRC] =3D &gpucc_gx_gfx3d_clk_src.clkr, [GPU_CC_GX_GMU_CLK] =3D &gpucc_gx_gmu_clk.clkr, @@ -455,6 +425,10 @@ static int gpucc_sm6375_probe(struct platform_device *= pdev) clk_lucid_pll_configure(&gpucc_pll0, regmap, &gpucc_pll0_config); clk_lucid_pll_configure(&gpucc_pll1, regmap, &gpucc_pll1_config); =20 + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x1078); /* GPUCC_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x1060); /* GPUCC_GX_CXO_CLK */ + ret =3D qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap); pm_runtime_put(&pdev->dev); =20 --=20 2.43.0 From nobody Thu Dec 18 08:52:09 2025 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 716815673 for ; Sat, 13 Jan 2024 14:51:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Q5HzG03Y" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-40e68d0dbf9so12771045e9.2 for ; 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[178.235.179.17]) by smtp.gmail.com with ESMTPSA id es18-20020a056402381200b00554b1d1a934sm3014593edb.27.2024.01.13.06.51.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jan 2024 06:51:05 -0800 (PST) From: Konrad Dybcio Date: Sat, 13 Jan 2024 15:50:54 +0100 Subject: [PATCH v6 05/12] clk: qcom: gpucc-sm6115: Unregister critical clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230717-topic-branch_aon_cleanup-v6-5-46d136a4e8d0@linaro.org> References: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1705157455; l=2984; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=RdTke+2ukdWoXFZFASghqIHvc/0hMwv913x8iK/xxg0=; b=zj3qdXjPhLJXgD1SWGjFwy2rux5JtRFdv4CJUYJqqNPZAxjLsgsEUZg6KlioVyPc8TyGPr/u7 VlPTlZyhYk8BknWVbSPB7CF5zdznxV2g4TIRXwlFKpF75wbwoxl5h3a X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gpucc-sm6115.c | 34 ++++------------------------------ 1 file changed, 4 insertions(+), 30 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm6115.c b/drivers/clk/qcom/gpucc-sm611= 5.c index fb71c21c9a89..2c2c184747b1 100644 --- a/drivers/clk/qcom/gpucc-sm6115.c +++ b/drivers/clk/qcom/gpucc-sm6115.c @@ -234,20 +234,6 @@ static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src =3D { }, }; =20 -static struct clk_branch gpu_cc_ahb_clk =3D { - .halt_reg =3D 0x1078, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x1078, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gpu_cc_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gpu_cc_crc_ahb_clk =3D { .halt_reg =3D 0x107c, .halt_check =3D BRANCH_HALT_DELAY, @@ -336,20 +322,6 @@ static struct clk_branch gpu_cc_cxo_clk =3D { }, }; =20 -static struct clk_branch gpu_cc_gx_cxo_clk =3D { - .halt_reg =3D 0x1060, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x1060, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gpu_cc_gx_cxo_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gpu_cc_gx_gfx3d_clk =3D { .halt_reg =3D 0x1054, .halt_check =3D BRANCH_HALT_SKIP, @@ -418,7 +390,6 @@ static struct gdsc gpu_gx_gdsc =3D { }; =20 static struct clk_regmap *gpu_cc_sm6115_clocks[] =3D { - [GPU_CC_AHB_CLK] =3D &gpu_cc_ahb_clk.clkr, [GPU_CC_CRC_AHB_CLK] =3D &gpu_cc_crc_ahb_clk.clkr, [GPU_CC_CX_GFX3D_CLK] =3D &gpu_cc_cx_gfx3d_clk.clkr, [GPU_CC_CX_GMU_CLK] =3D &gpu_cc_cx_gmu_clk.clkr, @@ -426,7 +397,6 @@ static struct clk_regmap *gpu_cc_sm6115_clocks[] =3D { [GPU_CC_CXO_AON_CLK] =3D &gpu_cc_cxo_aon_clk.clkr, [GPU_CC_CXO_CLK] =3D &gpu_cc_cxo_clk.clkr, [GPU_CC_GMU_CLK_SRC] =3D &gpu_cc_gmu_clk_src.clkr, - [GPU_CC_GX_CXO_CLK] =3D &gpu_cc_gx_cxo_clk.clkr, [GPU_CC_GX_GFX3D_CLK] =3D &gpu_cc_gx_gfx3d_clk.clkr, [GPU_CC_GX_GFX3D_CLK_SRC] =3D &gpu_cc_gx_gfx3d_clk_src.clkr, [GPU_CC_PLL0] =3D &gpu_cc_pll0.clkr, @@ -488,6 +458,10 @@ static int gpu_cc_sm6115_probe(struct platform_device = *pdev) qcom_branch_set_force_mem_core(regmap, gpu_cc_gx_gfx3d_clk, true); qcom_branch_set_force_periph_on(regmap, gpu_cc_gx_gfx3d_clk, true); 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[178.235.179.17]) by smtp.gmail.com with ESMTPSA id es18-20020a056402381200b00554b1d1a934sm3014593edb.27.2024.01.13.06.51.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jan 2024 06:51:06 -0800 (PST) From: Konrad Dybcio Date: Sat, 13 Jan 2024 15:50:55 +0100 Subject: [PATCH v6 06/12] clk: qcom: gpucc-sm6115: Add runtime PM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230717-topic-branch_aon_cleanup-v6-6-46d136a4e8d0@linaro.org> References: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1705157455; l=1935; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=alZr67bLnwqb3yV+3Ojldc2X/6n9g3vN6yGz8GMYLR4=; b=JyJbdesuxMki5pKs7X0S5jt+C5pgrl33I4DZtUq1W2R6eKfAJkqDwXm3URq1GnvOoNT6arqBz aBv71d7sFIIDzKxhmRNM1TnbCmmZbLOXdih6zeJXXKIEFPKdpUZriD7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The GPU_CC block on SM6115 is powered by the VDD_CX rail. We only need to cast an enable vote for it if the GPU blocks are in use. Enable runtime PM to keep the power flowing only when necessary. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gpucc-sm6115.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm6115.c b/drivers/clk/qcom/gpucc-sm611= 5.c index 2c2c184747b1..15cf5d63c9ad 100644 --- a/drivers/clk/qcom/gpucc-sm6115.c +++ b/drivers/clk/qcom/gpucc-sm6115.c @@ -8,6 +8,7 @@ #include #include #include +#include #include =20 #include @@ -443,10 +444,21 @@ MODULE_DEVICE_TABLE(of, gpu_cc_sm6115_match_table); static int gpu_cc_sm6115_probe(struct platform_device *pdev) { struct regmap *regmap; + int ret; + + ret =3D devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret =3D pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; =20 regmap =3D qcom_cc_map(pdev, &gpu_cc_sm6115_desc); - if (IS_ERR(regmap)) + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); return PTR_ERR(regmap); + } =20 clk_alpha_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_alpha_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); @@ -462,7 +474,10 @@ static int gpu_cc_sm6115_probe(struct platform_device = *pdev) qcom_branch_set_clk_en(regmap, 0x1078); /* GPU_CC_AHB_CLK */ qcom_branch_set_clk_en(regmap, 0x1060); /* GPU_CC_GX_CXO_CLK */ =20 - return qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap); + ret =3D qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap); + pm_runtime_put(&pdev->dev); + + return ret; } =20 static struct platform_driver gpu_cc_sm6115_driver =3D { --=20 2.43.0 From nobody Thu Dec 18 08:52:09 2025 Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24C6979E3 for ; Sat, 13 Jan 2024 14:51:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="HKFIBwZ3" Received: by mail-ed1-f43.google.com with SMTP id 4fb4d7f45d1cf-559058418faso297321a12.3 for ; Sat, 13 Jan 2024 06:51:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705157468; x=1705762268; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=W7xS7+izUNzuVlSMQ27hfUhVKMOnBNsD+XhqYWRzbz0=; b=HKFIBwZ307cXjp/i06lWPkvshWse3jdlsax4KQ7wXH/LPZ7wqm32qrF2hoGx5368bL uCWhafsNSk2iphUArTpH7XmHqV36Y1kaLhg4UEKuWBryqBDTIagCB/YasxITMr9rDSRH ENULhhTZznvhKofZFEVrEDUbGi1POh7fEKl2uj3QizikguVCPlFmglgZz1v6dx0FZRAD 8em/Xs834tJH+4Dha4oVpqLjgelRS4bJdmoDCALd4/JjnSPmFVbIiXvEjmBKsfq0265E zY1K3G5h1Xil0fXK0JhsSSOsJDwcKMp+vHl2W1pyRl97LofEq2agHiGNiPM1sHJudhrU +lEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705157468; x=1705762268; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W7xS7+izUNzuVlSMQ27hfUhVKMOnBNsD+XhqYWRzbz0=; b=ptXbcijjZ3x4gOoCHa50FrGw0xx1Bl7c5b4rHrxX5poNJybm02I5ogLIHb/4mWOANt JIKfpp3n7nIqwcp3rX/WPAtVUWoPI0G8VSVEpgbsDWOOMEokwvql+uu8Hgg2pFCApsdW aqR3mkhTYC6zXZ/5cxbur+jmeC+xoSBd8kIvUXTdU4WDTPol6JKfdwdUIhU0RXWTqTbY i0KDyDAerAS1inXvP/EXh46Tzb+Me8F94D+NNtrj4v9QjaWEIHsocdpjcr3h5o1ES6Qj NC6upras151OHijyCWr0zFVunZZ2bde0N6xrCGHav26Nx0uzf+zGDAJ8v6hrDfAW4kw0 7K1Q== X-Gm-Message-State: AOJu0YwUNwl5H9hpjWpAyvLQD2Z1sCkdvy0yzXWNFrOfzpTi86TxUXAm BMn5kMBA2vuW+fuylzkKGCct/XmmY34dCGqgj0UzOS9AhGM= X-Google-Smtp-Source: AGHT+IFxsdVBWr0a+SjOvvo44vZrIK6sNUcCi/8/gxRPS7nQ2JfiJeVmsmDzSkIosm8jAi//nCpmTw== X-Received: by 2002:aa7:dc18:0:b0:558:84d8:e2f with SMTP id b24-20020aa7dc18000000b0055884d80e2fmr1461473edu.46.1705157468196; Sat, 13 Jan 2024 06:51:08 -0800 (PST) Received: from [10.167.154.1] (178235179017.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.17]) by smtp.gmail.com with ESMTPSA id es18-20020a056402381200b00554b1d1a934sm3014593edb.27.2024.01.13.06.51.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jan 2024 06:51:07 -0800 (PST) From: Konrad Dybcio Date: Sat, 13 Jan 2024 15:50:56 +0100 Subject: [PATCH v6 07/12] clk: qcom: gcc-sm6115: Unregister critical clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230717-topic-branch_aon_cleanup-v6-7-46d136a4e8d0@linaro.org> References: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1705157455; l=7187; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=iYyi3pIcadPzcV3JUoNjpiYD91rVmbufz+P6nURn+eI=; b=Mj6T1tBCYTx89nXXVXzUa2AoosHFoSNTuC2FXEg+pph1enF+QcyUzIOfjdp0eA5laBo9w6de/ vljQnmcyd4pAJnQ6AxWgu+KOyApwrh01/Ju5IgIIbmJt4kTGz+l+WDp X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sm6115.c | 124 +++-----------------------------------= ---- 1 file changed, 9 insertions(+), 115 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c index 13e521cd4259..99130508d281 100644 --- a/drivers/clk/qcom/gcc-sm6115.c +++ b/drivers/clk/qcom/gcc-sm6115.c @@ -1586,36 +1586,6 @@ static struct clk_branch gcc_cam_throttle_rt_clk =3D= { }, }; =20 -static struct clk_branch gcc_camera_ahb_clk =3D { - .halt_reg =3D 0x17008, - .halt_check =3D BRANCH_HALT_DELAY, - .hwcg_reg =3D 0x17008, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x17008, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_camera_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_xo_clk =3D { - .halt_reg =3D 0x17028, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x17028, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_camera_xo_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_camss_axi_clk =3D { .halt_reg =3D 0x58044, .halt_check =3D BRANCH_HALT, @@ -2124,38 +2094,6 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_c= lk =3D { }, }; =20 -static struct clk_branch gcc_cpuss_gnoc_clk =3D { - .halt_reg =3D 0x2b004, - .halt_check =3D BRANCH_HALT_VOTED, - .hwcg_reg =3D 0x2b004, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x79004, - .enable_mask =3D BIT(22), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_cpuss_gnoc_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_ahb_clk =3D { - .halt_reg =3D 0x1700c, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x1700c, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x1700c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_disp_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_regmap_div gcc_disp_gpll0_clk_src =3D { .reg =3D 0x17058, .shift =3D 0, @@ -2215,20 +2153,6 @@ static struct clk_branch gcc_disp_throttle_core_clk = =3D { }, }; =20 -static struct clk_branch gcc_disp_xo_clk =3D { - .halt_reg =3D 0x1702c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x1702c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_disp_xo_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gp1_clk =3D { .halt_reg =3D 0x4d000, .halt_check =3D BRANCH_HALT, @@ -2283,22 +2207,6 @@ static struct clk_branch gcc_gp3_clk =3D { }, }; =20 -static struct clk_branch gcc_gpu_cfg_ahb_clk =3D { - .halt_reg =3D 0x36004, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x36004, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x36004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_gpu_cfg_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gpu_gpll0_clk_src =3D { .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { @@ -2771,22 +2679,6 @@ static struct clk_branch gcc_sdcc2_apps_clk =3D { }, }; =20 -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk =3D { - .halt_reg =3D 0x2b06c, - .halt_check =3D BRANCH_HALT_VOTED, - .hwcg_reg =3D 0x2b06c, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x79004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_sys_noc_cpuss_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk =3D { .halt_reg =3D 0x45098, .halt_check =3D BRANCH_HALT, @@ -3272,8 +3164,6 @@ static struct clk_regmap *gcc_sm6115_clocks[] =3D { [GCC_BOOT_ROM_AHB_CLK] =3D &gcc_boot_rom_ahb_clk.clkr, [GCC_CAM_THROTTLE_NRT_CLK] =3D &gcc_cam_throttle_nrt_clk.clkr, [GCC_CAM_THROTTLE_RT_CLK] =3D &gcc_cam_throttle_rt_clk.clkr, - [GCC_CAMERA_AHB_CLK] =3D &gcc_camera_ahb_clk.clkr, - [GCC_CAMERA_XO_CLK] =3D &gcc_camera_xo_clk.clkr, [GCC_CAMSS_AXI_CLK] =3D &gcc_camss_axi_clk.clkr, [GCC_CAMSS_AXI_CLK_SRC] =3D &gcc_camss_axi_clk_src.clkr, [GCC_CAMSS_CAMNOC_ATB_CLK] =3D &gcc_camss_camnoc_atb_clk.clkr, @@ -3322,20 +3212,16 @@ static struct clk_regmap *gcc_sm6115_clocks[] =3D { [GCC_CAMSS_TOP_AHB_CLK] =3D &gcc_camss_top_ahb_clk.clkr, [GCC_CAMSS_TOP_AHB_CLK_SRC] =3D &gcc_camss_top_ahb_clk_src.clkr, [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] =3D &gcc_cfg_noc_usb3_prim_axi_clk.clkr, - [GCC_CPUSS_GNOC_CLK] =3D &gcc_cpuss_gnoc_clk.clkr, - [GCC_DISP_AHB_CLK] =3D &gcc_disp_ahb_clk.clkr, [GCC_DISP_GPLL0_CLK_SRC] =3D &gcc_disp_gpll0_clk_src.clkr, [GCC_DISP_GPLL0_DIV_CLK_SRC] =3D &gcc_disp_gpll0_div_clk_src.clkr, [GCC_DISP_HF_AXI_CLK] =3D &gcc_disp_hf_axi_clk.clkr, [GCC_DISP_THROTTLE_CORE_CLK] =3D &gcc_disp_throttle_core_clk.clkr, - [GCC_DISP_XO_CLK] =3D &gcc_disp_xo_clk.clkr, [GCC_GP1_CLK] =3D &gcc_gp1_clk.clkr, [GCC_GP1_CLK_SRC] =3D &gcc_gp1_clk_src.clkr, [GCC_GP2_CLK] =3D &gcc_gp2_clk.clkr, [GCC_GP2_CLK_SRC] =3D &gcc_gp2_clk_src.clkr, [GCC_GP3_CLK] =3D &gcc_gp3_clk.clkr, [GCC_GP3_CLK_SRC] =3D &gcc_gp3_clk_src.clkr, - [GCC_GPU_CFG_AHB_CLK] =3D &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_GPLL0_CLK_SRC] =3D &gcc_gpu_gpll0_clk_src.clkr, [GCC_GPU_GPLL0_DIV_CLK_SRC] =3D &gcc_gpu_gpll0_div_clk_src.clkr, [GCC_GPU_IREF_CLK] =3D &gcc_gpu_iref_clk.clkr, @@ -3376,7 +3262,6 @@ static struct clk_regmap *gcc_sm6115_clocks[] =3D { [GCC_SDCC2_AHB_CLK] =3D &gcc_sdcc2_ahb_clk.clkr, [GCC_SDCC2_APPS_CLK] =3D &gcc_sdcc2_apps_clk.clkr, [GCC_SDCC2_APPS_CLK_SRC] =3D &gcc_sdcc2_apps_clk_src.clkr, - [GCC_SYS_NOC_CPUSS_AHB_CLK] =3D &gcc_sys_noc_cpuss_ahb_clk.clkr, [GCC_SYS_NOC_UFS_PHY_AXI_CLK] =3D &gcc_sys_noc_ufs_phy_axi_clk.clkr, [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] =3D &gcc_sys_noc_usb3_prim_axi_clk.clkr, [GCC_UFS_CLKREF_CLK] =3D &gcc_ufs_clkref_clk.clkr, @@ -3513,6 +3398,15 @@ static int gcc_sm6115_probe(struct platform_device *= pdev) clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config); clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config); =20 + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x17008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x1700c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x17028); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x1702c); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x2b004); /* GCC_CPUSS_GNOC_CLK */ + qcom_branch_set_clk_en(regmap, 0x2b06c); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_GPU_CFG_AHB_CLK */ + return qcom_cc_really_probe(pdev, &gcc_sm6115_desc, regmap); } =20 --=20 2.43.0 From nobody Thu Dec 18 08:52:09 2025 Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D39B11643E for ; Sat, 13 Jan 2024 14:51:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[178.235.179.17]) by smtp.gmail.com with ESMTPSA id es18-20020a056402381200b00554b1d1a934sm3014593edb.27.2024.01.13.06.51.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jan 2024 06:51:09 -0800 (PST) From: Konrad Dybcio Date: Sat, 13 Jan 2024 15:50:57 +0100 Subject: [PATCH v6 08/12] clk: qcom: gcc-qcm2290: Unregister critical clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230717-topic-branch_aon_cleanup-v6-8-46d136a4e8d0@linaro.org> References: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1705157455; l=6713; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=1E+XbA6wAIFD3Fn0xiIZhPRBVyiQV4eHkv9HIqt0AbM=; b=nePDHV51tjm21DJokck4AsoX3wlGUcUyAnDwmG9WUL9x32OilLO47vI3bU3C0MQk7Z5YaMS+Q LQL4Mk4918FB49nbqt2FaY64TkXfQi81RsEqOEfOZ1n0qb4HGLz8LMt X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-qcm2290.c | 106 ++++---------------------------------= ---- 1 file changed, 8 insertions(+), 98 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcm2290.c b/drivers/clk/qcom/gcc-qcm2290.c index 48995e50c6bd..fd20408d8205 100644 --- a/drivers/clk/qcom/gcc-qcm2290.c +++ b/drivers/clk/qcom/gcc-qcm2290.c @@ -1397,36 +1397,6 @@ static struct clk_branch gcc_cam_throttle_rt_clk =3D= { }, }; =20 -static struct clk_branch gcc_camera_ahb_clk =3D { - .halt_reg =3D 0x17008, - .halt_check =3D BRANCH_HALT_DELAY, - .hwcg_reg =3D 0x17008, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x17008, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_camera_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_xo_clk =3D { - .halt_reg =3D 0x17028, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x17028, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_camera_xo_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_camss_axi_clk =3D { .halt_reg =3D 0x58044, .halt_check =3D BRANCH_HALT, @@ -1825,22 +1795,6 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_c= lk =3D { }, }; =20 -static struct clk_branch gcc_disp_ahb_clk =3D { - .halt_reg =3D 0x1700c, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x1700c, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x1700c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_disp_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_regmap_div gcc_disp_gpll0_clk_src =3D { .reg =3D 0x17058, .shift =3D 0, @@ -1899,20 +1853,6 @@ static struct clk_branch gcc_disp_throttle_core_clk = =3D { }, }; =20 -static struct clk_branch gcc_disp_xo_clk =3D { - .halt_reg =3D 0x1702c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x1702c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_disp_xo_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gp1_clk =3D { .halt_reg =3D 0x4d000, .halt_check =3D BRANCH_HALT, @@ -1964,22 +1904,6 @@ static struct clk_branch gcc_gp3_clk =3D { }, }; =20 -static struct clk_branch gcc_gpu_cfg_ahb_clk =3D { - .halt_reg =3D 0x36004, - .halt_check =3D BRANCH_HALT, - .hwcg_reg =3D 0x36004, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x36004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_gpu_cfg_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gpu_gpll0_clk_src =3D { .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { @@ -2439,22 +2363,6 @@ static struct clk_branch gcc_sdcc2_apps_clk =3D { }, }; =20 -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk =3D { - .halt_reg =3D 0x2b06c, - .halt_check =3D BRANCH_HALT_VOTED, - .hwcg_reg =3D 0x2b06c, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x79004, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gcc_sys_noc_cpuss_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk =3D { .halt_reg =3D 0x1a080, .halt_check =3D BRANCH_HALT, @@ -2774,8 +2682,6 @@ static struct clk_regmap *gcc_qcm2290_clocks[] =3D { [GCC_BOOT_ROM_AHB_CLK] =3D &gcc_boot_rom_ahb_clk.clkr, [GCC_CAM_THROTTLE_NRT_CLK] =3D &gcc_cam_throttle_nrt_clk.clkr, [GCC_CAM_THROTTLE_RT_CLK] =3D &gcc_cam_throttle_rt_clk.clkr, - [GCC_CAMERA_AHB_CLK] =3D &gcc_camera_ahb_clk.clkr, - [GCC_CAMERA_XO_CLK] =3D &gcc_camera_xo_clk.clkr, [GCC_CAMSS_AXI_CLK] =3D &gcc_camss_axi_clk.clkr, [GCC_CAMSS_AXI_CLK_SRC] =3D &gcc_camss_axi_clk_src.clkr, [GCC_CAMSS_CAMNOC_ATB_CLK] =3D &gcc_camss_camnoc_atb_clk.clkr, @@ -2816,19 +2722,16 @@ static struct clk_regmap *gcc_qcm2290_clocks[] =3D { [GCC_CAMSS_TOP_AHB_CLK] =3D &gcc_camss_top_ahb_clk.clkr, [GCC_CAMSS_TOP_AHB_CLK_SRC] =3D &gcc_camss_top_ahb_clk_src.clkr, [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] =3D &gcc_cfg_noc_usb3_prim_axi_clk.clkr, - [GCC_DISP_AHB_CLK] =3D &gcc_disp_ahb_clk.clkr, [GCC_DISP_GPLL0_CLK_SRC] =3D &gcc_disp_gpll0_clk_src.clkr, [GCC_DISP_GPLL0_DIV_CLK_SRC] =3D &gcc_disp_gpll0_div_clk_src.clkr, [GCC_DISP_HF_AXI_CLK] =3D &gcc_disp_hf_axi_clk.clkr, [GCC_DISP_THROTTLE_CORE_CLK] =3D &gcc_disp_throttle_core_clk.clkr, - [GCC_DISP_XO_CLK] =3D &gcc_disp_xo_clk.clkr, [GCC_GP1_CLK] =3D &gcc_gp1_clk.clkr, [GCC_GP1_CLK_SRC] =3D &gcc_gp1_clk_src.clkr, [GCC_GP2_CLK] =3D &gcc_gp2_clk.clkr, [GCC_GP2_CLK_SRC] =3D &gcc_gp2_clk_src.clkr, [GCC_GP3_CLK] =3D &gcc_gp3_clk.clkr, [GCC_GP3_CLK_SRC] =3D &gcc_gp3_clk_src.clkr, - [GCC_GPU_CFG_AHB_CLK] =3D &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_GPLL0_CLK_SRC] =3D &gcc_gpu_gpll0_clk_src.clkr, [GCC_GPU_GPLL0_DIV_CLK_SRC] =3D &gcc_gpu_gpll0_div_clk_src.clkr, [GCC_GPU_IREF_CLK] =3D &gcc_gpu_iref_clk.clkr, @@ -2869,7 +2772,6 @@ static struct clk_regmap *gcc_qcm2290_clocks[] =3D { [GCC_SDCC2_AHB_CLK] =3D &gcc_sdcc2_ahb_clk.clkr, [GCC_SDCC2_APPS_CLK] =3D &gcc_sdcc2_apps_clk.clkr, [GCC_SDCC2_APPS_CLK_SRC] =3D &gcc_sdcc2_apps_clk_src.clkr, - [GCC_SYS_NOC_CPUSS_AHB_CLK] =3D &gcc_sys_noc_cpuss_ahb_clk.clkr, [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] =3D &gcc_sys_noc_usb3_prim_axi_clk.clkr, [GCC_USB30_PRIM_MASTER_CLK] =3D &gcc_usb30_prim_master_clk.clkr, [GCC_USB30_PRIM_MASTER_CLK_SRC] =3D &gcc_usb30_prim_master_clk_src.clkr, @@ -2994,6 +2896,14 @@ static int gcc_qcm2290_probe(struct platform_device = *pdev) clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config); clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config); =20 + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x17008); /* GCC_CAMERA_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x1700c); /* GCC_DISP_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x17028); /* GCC_CAMERA_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x1702c); /* GCC_DISP_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x2b06c); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_GPU_CFG_AHB_CLK */ + return qcom_cc_really_probe(pdev, &gcc_qcm2290_desc, regmap); } =20 --=20 2.43.0 From nobody Thu Dec 18 08:52:09 2025 Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BC531805F for ; Sat, 13 Jan 2024 14:51:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; 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[178.235.179.17]) by smtp.gmail.com with ESMTPSA id es18-20020a056402381200b00554b1d1a934sm3014593edb.27.2024.01.13.06.51.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jan 2024 06:51:11 -0800 (PST) From: Konrad Dybcio Date: Sat, 13 Jan 2024 15:50:58 +0100 Subject: [PATCH v6 09/12] arm64: dts: qcom: sm6375: Add VDD_CX to GCC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230717-topic-branch_aon_cleanup-v6-9-46d136a4e8d0@linaro.org> References: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1705157455; l=718; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Gc/yH23ZENvzGFFViZ7/qVCV3FeiRMp+LehbPO3k6Xw=; b=86Y6jsKpcQ18sYal3Sp2bgI3EzGdyaVzQ0SdqKkhquJh1U19a52aWW5Z78Iz2gydwopmhuQUk bV1u+K9XqfuCQ8u0ROtbZ7F44chBxbV9h/S5B2rNjUgi4UUnxb1C5qd X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The GCC block is mainly powered by VDD_CX. Describe that. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qco= m/sm6375.dtsi index 7ac8bf26dda3..f578d110f36b 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -954,6 +954,7 @@ gcc: clock-controller@1400000 { clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&sleep_clk>; + power-domains =3D <&rpmpd SM6375_VDDCX>; #power-domain-cells =3D <1>; #clock-cells =3D <1>; #reset-cells =3D <1>; --=20 2.43.0 From nobody Thu Dec 18 08:52:09 2025 Received: from mail-ed1-f50.google.com (mail-ed1-f50.google.com [209.85.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38CB818626 for ; Sat, 13 Jan 2024 14:51:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="n/zVgn0x" Received: by mail-ed1-f50.google.com with SMTP id 4fb4d7f45d1cf-554fe147ddeso8234306a12.3 for ; Sat, 13 Jan 2024 06:51:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705157473; x=1705762273; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=EIS8BVV6xMe2SYH6GmTY+cChP0QmWaX59VMotnHi2Jo=; b=n/zVgn0xg8MuNQql8BimPcwAihQ6GQPFhwgTrAM7RmaTHkMKPu58w4GpFRY4p4FiYR 2Y745g0Afx3wKQWPvhEFX4GuaKK79kgwm/wcr9mTJvYv0vMquQas1/D0x3zYqCuaJyJ8 Z513zQtNNuusD3eA48tdBqWIt9f7+mexQSzMT4+eBiDNpZgDpCK25aIbDu5lIxz8fDDR AwCe0gYWfKmbBr4fe+zJdg2jECw/ta4IOFwi3eFqVjvm1FcCtD1Fm3vbEqHo5J4nlFJm A59FIXeukW00m3j/yofa8gn55nTb0tobkcKLneS9je0gZpn2twz2tNnhRs27G/eGiD2X z11A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705157473; x=1705762273; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EIS8BVV6xMe2SYH6GmTY+cChP0QmWaX59VMotnHi2Jo=; b=TUThKFw0nH9Kiz8csLVK3PTjcUyqgzmB0VGTV5kBpj1+reycrPThPsVJFuydQ1ofhQ /VVD/ADveF8Aq5HWi/Q5zsPz12xpZe5j+mfrPUuAvd3K9HATrAZh2mCygqpUU6b9ygAV f464hkArUye4iBC5VMHnZ9k8iGCbX1ur7oX80hhHlctqT9/JFPDUpWvXr1uWM9GsUWJu uR38ohRxQ3Fsz2GbA5XCvAxQ8T7vkBC0YNJruYjXUCA/0G0ipuAZt3eEjn3APYb7NZ5b mkUWgM+o26kS1ZMw/JUF0b1LDOdmqXyuMySSk42Ytvo0PgvK/SPros5/s2uy4KNlrc1j WKlg== X-Gm-Message-State: AOJu0Yy5aVTjWi+rGu8/K4GJpYfOo/qlo4SwD6Kw1z5QUcqZU4VPv+L1 OFg3YFhGAieK7UTesqlqwwp9MnMGynECi35Yyf2Kh8mRHy0= X-Google-Smtp-Source: AGHT+IH1BKgAHHlwIVJSmDL9mfv9JDP1cYjB2BWYyC5LsgCmdVmCPaEC9EbZK60iCEI1e107KNKtTw== X-Received: by 2002:a05:6402:22b1:b0:556:d6ea:4305 with SMTP id cx17-20020a05640222b100b00556d6ea4305mr786770edb.13.1705157473315; Sat, 13 Jan 2024 06:51:13 -0800 (PST) Received: from [10.167.154.1] (178235179017.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.17]) by smtp.gmail.com with ESMTPSA id es18-20020a056402381200b00554b1d1a934sm3014593edb.27.2024.01.13.06.51.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jan 2024 06:51:12 -0800 (PST) From: Konrad Dybcio Date: Sat, 13 Jan 2024 15:50:59 +0100 Subject: [PATCH v6 10/12] arm64: dts: qcom: qcm2290: Add VDD_CX to GCC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230717-topic-branch_aon_cleanup-v6-10-46d136a4e8d0@linaro.org> References: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1705157455; l=764; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=HEE3DdJ4zQzS/Foajh/2RBi9l8ssp2UwDgoH6XqPOSE=; b=BhgjiV2lxdGarm82hkVqbXo9xFXjVzGMqv+A7qOkRqNXlz3BeYj8cJ0UtDUiuZrKxIk3ivmOR uXL4exR9yUCAd9+C1qvAzE7+7/K0Fa09GUMZhK2F8ntlrkzeqsTyTKP X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The GCC block is mainly powered by VDD_CX. Describe that. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qc= om/qcm2290.dtsi index 0911fb08ed63..51b05019ee25 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -647,6 +647,7 @@ gcc: clock-controller@1400000 { reg =3D <0x0 0x01400000 0x0 0x1f0000>; clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; clock-names =3D "bi_tcxo", "sleep_clk"; + power-domains =3D <&rpmpd QCM2290_VDDCX>; #clock-cells =3D <1>; #reset-cells =3D <1>; #power-domain-cells =3D <1>; --=20 2.43.0 From nobody Thu Dec 18 08:52:09 2025 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1380B18AFA for ; Sat, 13 Jan 2024 14:51:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="sBic1Hpy" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-40d6b4e2945so85260715e9.0 for ; Sat, 13 Jan 2024 06:51:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705157475; x=1705762275; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Tm7vsf6UZKbMh6cnZmrwv/W/K4dUYmjWU07UgTkkSLk=; b=sBic1HpyIgN2on8PLFxEjUGNl693vFoM0TIBCvuoLdhpqD1vRyp60GI0iW8awk1a45 RFhVwL1hRvwsY6ROvesmSvvlG37BxBJSri/NqBuLvWOPMsPDr6MIcG2U9rEp/3LO6cLJ buuIaxBJLWthGY+3lyK4Ex+knfQMs/R4LYADDLJKdMh6h8rjUVgNjdpfWLrjkmFusy38 6/z+lQ6pjj6LOOy99vm2E/iMehfNoGx+9+FuhP6HEFvZ7+Excgu7lz7ZgeuC0IA9Xbq/ Z/YRAgN8Ix1jixp6MGqBhS6wwR/w6oLfNJl1ypFQF1BskIf7rzeh1WEkyQAl1K5HCpKd XU0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705157475; x=1705762275; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Tm7vsf6UZKbMh6cnZmrwv/W/K4dUYmjWU07UgTkkSLk=; b=vjvE/wHT4REbOxsajsNo+BjoaBg6NFj8BF20D7r7ax4OIX7C1L31nci4uTeM72tqJb OY6LQZwZkONYxUGzu/B2Y04jrsm4f8DflGY+DGYUcwRyHmGOuT887BruyKqvh0NgSe2s a49wLi2FW6GcFAaPzu9wAcN/HrVoDH/4qeXr4QqGNz6JLNvmr6ELYwixYo3XlHPDQylx 3reNxYWutZ1zMFgfbIIgZi8Yn+WgjaDU7yv5BB9rxg/H+JKO5uWkA1ZnLN7RC2orOde8 qZpgJEgCEHcmz4u31heZBCuUmBGpzCdStknkmjc8I23HnKm0q8XkkhG2eul/tMvUO1GJ GEqw== X-Gm-Message-State: AOJu0Ywwjfb4sHD17EhF+8LudFC0yA4JmApotZc6GEehCRnSxJdNPrUF +HPp8+yTh+UiMwS4kMIfZ6QGqJanGSkC3+WFDigMUYAtMZU= X-Google-Smtp-Source: AGHT+IEpYOKZRZpChUhrhMpu7k911R5aockRo+r3s32gqMdG3CL5hFueLl6AcHkaWl7ldfH53yo8Gg== X-Received: by 2002:a05:600c:d7:b0:40e:498d:91d2 with SMTP id u23-20020a05600c00d700b0040e498d91d2mr1079390wmm.185.1705157475077; Sat, 13 Jan 2024 06:51:15 -0800 (PST) Received: from [10.167.154.1] (178235179017.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.17]) by smtp.gmail.com with ESMTPSA id es18-20020a056402381200b00554b1d1a934sm3014593edb.27.2024.01.13.06.51.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jan 2024 06:51:14 -0800 (PST) From: Konrad Dybcio Date: Sat, 13 Jan 2024 15:51:00 +0100 Subject: [PATCH v6 11/12] arm64: dts: qcom: sm6115: Add VDD_CX to GCC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230717-topic-branch_aon_cleanup-v6-11-46d136a4e8d0@linaro.org> References: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1705157455; l=758; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=L7WLthXykOxwSCjhfTNvX8JtR2g4GIz2oFPri6fp1uU=; b=9YnjNkc73g4vw24D5TH8RrweyjC2rmeKm7e9SMxa7AqPeFTKrpGm8fAIS9P64amRdSDVudf7u 1oGH3d7+FqNDstnBsI+NnOZTiFKLsgSO4xOlIp2+9oWTHfBysBCBHqg X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The GCC block is mainly powered by VDD_CX. Describe that. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qco= m/sm6115.dtsi index 160e098f1075..30b140e1cec0 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -807,6 +807,7 @@ gcc: clock-controller@1400000 { reg =3D <0x0 0x01400000 0x0 0x1f0000>; clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; clock-names =3D "bi_tcxo", "sleep_clk"; + power-domains =3D <&rpmpd SM6115_VDDCX>; #clock-cells =3D <1>; #reset-cells =3D <1>; #power-domain-cells =3D <1>; --=20 2.43.0 From nobody Thu Dec 18 08:52:09 2025 Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACB9518E12 for ; Sat, 13 Jan 2024 14:51:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="C805GElg" Received: by mail-ed1-f52.google.com with SMTP id 4fb4d7f45d1cf-55783b7b47aso7686773a12.0 for ; Sat, 13 Jan 2024 06:51:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705157477; x=1705762277; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=RUTCpmfzsSKDHjYlRAYYiQ/aykX/VSlVLVDx9q/aHss=; b=C805GElgMCsq5N3rhzJBZMwTtpcv6KXklRX5HZzb1Gg7jhb9JdQx4DWT+/VsJ3Szmk cGCUjQY3fQw71LlrIPFA9vSTKYAYcq8KmWq7Q4xzKZ1MGgqMwHJaGD6jFQpIiajEsViG biee6/8uvuKWmnsa9viWzrtoDkRjOa52IR4bWlpC/F7nthFpZQzyx/8pLHdswSTNlObn HG4fH0fiiDuo9P/BgX2lWlRK6GHAB8L6W40MTybBTwqj3lqz9QON38Arhpx/3CbmVgE/ f4+TICpR6LbDenbiuLS/QqlJLC9TB3gi7si4UqoQ3wAClCD6y9Ii7h7nIx4Z8B1U/Wx4 2ugw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705157477; x=1705762277; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RUTCpmfzsSKDHjYlRAYYiQ/aykX/VSlVLVDx9q/aHss=; b=w9bbILKotse83HWawoId+UNFJZUnNJphxcOh2+Ea8p17Dc1kMrAlXuvbwC41Gf/ZvF ZNDJQcXkpxTWxhYXQILwVKM+t7dQSBZSqtwsbMSotfApna2UceDbkWuHeJEQ4msORt9L kLrmTnJv5g0fNE/2z3mAgCsiINBJ9gIao2pQ6zSn2/Ht93XFXMccrtvY66M7EIVAisKI d8IN4LFblcHwhcI93Q+LYnGOrhYBO5f4iHmmmLCmlLRKHIQnoto2bSIAvxOwcEKM/Klb d6xMMBrF4A1g+tNNNe7kxtSghW2KLF5JXiCK0TnlQgg5xhxHVPKbGZTRlKbH521UUZel PTfQ== X-Gm-Message-State: AOJu0YyDWZMw+PJC+JMdRFIef6nDTdvxUrMyeeLhHl1dUkGaUhDquoUf dj86Ucqj9g1kYnlrcfnrZKNgConopOcwyt7kfdF1jYygJ98= X-Google-Smtp-Source: AGHT+IETAequHzfAwgHF8QsK/gBIn4BSDyAY0yftCXAhJQJM0qG8OILiUEsNbSoyObZt6WLoT++NLA== X-Received: by 2002:aa7:c602:0:b0:558:2cf:b7f3 with SMTP id h2-20020aa7c602000000b0055802cfb7f3mr1362760edq.70.1705157476826; Sat, 13 Jan 2024 06:51:16 -0800 (PST) Received: from [10.167.154.1] (178235179017.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.17]) by smtp.gmail.com with ESMTPSA id es18-20020a056402381200b00554b1d1a934sm3014593edb.27.2024.01.13.06.51.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jan 2024 06:51:16 -0800 (PST) From: Konrad Dybcio Date: Sat, 13 Jan 2024 15:51:01 +0100 Subject: [PATCH v6 12/12] arm64: dts: qcom: sm6115: Add VDD_CX to GPU_CC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230717-topic-branch_aon_cleanup-v6-12-46d136a4e8d0@linaro.org> References: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1705157455; l=911; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=WDI26IliceRlW0YgN7X8GrPWGyVd7988pOYar0kAAss=; b=QkTIudk9bwX/+NypRGqOTPXGV2soTD0F/pgSW+rfGeoOYUJvfu6xMrq9N9B54gSGyfZfAOYfu PMG412v8x9ODGvD+GYIFf8ufxxA4ySNYDB/TNcmJ62+5QHMNcTVJIr+ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The GPU_CC block is powered by VDD_CX. Link the power domain and provide a reasonable minimum vote (lowest available on the platform) to ensure the registers within are accessible. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qco= m/sm6115.dtsi index 30b140e1cec0..ec9a74acc69c 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1723,6 +1723,8 @@ gpucc: clock-controller@5990000 { clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + power-domains =3D <&rpmpd SM6115_VDDCX>; + required-opps =3D <&rpmpd_opp_low_svs>; #clock-cells =3D <1>; #reset-cells =3D <1>; #power-domain-cells =3D <1>; --=20 2.43.0