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[178.235.187.166]) by smtp.gmail.com with ESMTPSA id o11-20020a1709061d4b00b009faca59cf38sm8160232ejh.182.2023.11.29.10.59.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Nov 2023 10:59:36 -0800 (PST) From: Konrad Dybcio Date: Wed, 29 Nov 2023 19:59:24 +0100 Subject: [PATCH v2 05/15] clk: qcom: gpucc-sm6375: Unregister critical clocks MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230717-topic-branch_aon_cleanup-v2-5-2a583460ef26@linaro.org> References: <20230717-topic-branch_aon_cleanup-v2-0-2a583460ef26@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v2-0-2a583460ef26@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701284367; l=2968; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=LUWIogmP6OeDvx1GjND0Am0UQ+6einhHWh1HpqaW4UI=; b=yQzFMJrhML7Y5IYoegSAF6IeVpUCzfIPsfrVm05xdBsTdVnFLOOzF1l8znsi7qjH8Xpj6+xGI YKvvl6fJ0RtAyEzXytX9eeGB375rfVMq5z4XGKhvIB6SxO6ELJcSaNB X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Signed-off-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue --- drivers/clk/qcom/gpucc-sm6375.c | 33 +++------------------------------ 1 file changed, 3 insertions(+), 30 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm6375.c b/drivers/clk/qcom/gpucc-sm637= 5.c index da24276a018e..6d85936dd441 100644 --- a/drivers/clk/qcom/gpucc-sm6375.c +++ b/drivers/clk/qcom/gpucc-sm6375.c @@ -183,20 +183,6 @@ static struct clk_rcg2 gpucc_gx_gfx3d_clk_src =3D { }, }; =20 -static struct clk_branch gpucc_ahb_clk =3D { - .halt_reg =3D 0x1078, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x1078, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gpucc_ahb_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gpucc_cx_gfx3d_clk =3D { .halt_reg =3D 0x10a4, .halt_check =3D BRANCH_HALT_DELAY, @@ -294,20 +280,6 @@ static struct clk_branch gpucc_cxo_clk =3D { }, }; =20 -static struct clk_branch gpucc_gx_cxo_clk =3D { - .halt_reg =3D 0x1060, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x1060, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "gpucc_gx_cxo_clk", - .flags =3D CLK_IS_CRITICAL, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gpucc_gx_gfx3d_clk =3D { .halt_reg =3D 0x1054, .halt_check =3D BRANCH_HALT_DELAY, @@ -381,7 +353,6 @@ static struct gdsc gpu_gx_gdsc =3D { }; =20 static struct clk_regmap *gpucc_sm6375_clocks[] =3D { - [GPU_CC_AHB_CLK] =3D &gpucc_ahb_clk.clkr, [GPU_CC_CX_GFX3D_CLK] =3D &gpucc_cx_gfx3d_clk.clkr, [GPU_CC_CX_GFX3D_SLV_CLK] =3D &gpucc_cx_gfx3d_slv_clk.clkr, [GPU_CC_CX_GMU_CLK] =3D &gpucc_cx_gmu_clk.clkr, @@ -389,7 +360,6 @@ static struct clk_regmap *gpucc_sm6375_clocks[] =3D { [GPU_CC_CXO_AON_CLK] =3D &gpucc_cxo_aon_clk.clkr, [GPU_CC_CXO_CLK] =3D &gpucc_cxo_clk.clkr, [GPU_CC_GMU_CLK_SRC] =3D &gpucc_gmu_clk_src.clkr, - [GPU_CC_GX_CXO_CLK] =3D &gpucc_gx_cxo_clk.clkr, [GPU_CC_GX_GFX3D_CLK] =3D &gpucc_gx_gfx3d_clk.clkr, [GPU_CC_GX_GFX3D_CLK_SRC] =3D &gpucc_gx_gfx3d_clk_src.clkr, [GPU_CC_GX_GMU_CLK] =3D &gpucc_gx_gmu_clk.clkr, @@ -455,6 +425,9 @@ static int gpucc_sm6375_probe(struct platform_device *p= dev) clk_lucid_pll_configure(&gpucc_pll0, regmap, &gpucc_pll0_config); clk_lucid_pll_configure(&gpucc_pll1, regmap, &gpucc_pll1_config); =20 + qcom_branch_set_clk_en(regmap, 0x1078); /* GPUCC_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x1060); /* GPUCC_GX_CXO_CLK */ + ret =3D qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap); pm_runtime_put(&pdev->dev); =20 --=20 2.43.0