From nobody Sun Feb 8 04:30:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A76E7EB64DA for ; Fri, 14 Jul 2023 10:45:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236242AbjGNKpk (ORCPT ); Fri, 14 Jul 2023 06:45:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235017AbjGNKp3 (ORCPT ); Fri, 14 Jul 2023 06:45:29 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 856E22D7D; Fri, 14 Jul 2023 03:45:25 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 4291A24E226; Fri, 14 Jul 2023 18:45:24 +0800 (CST) Received: from EXMBX062.cuchost.com (172.16.6.62) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 14 Jul 2023 18:45:24 +0800 Received: from starfive-sdk.starfivetech.com (171.223.208.138) by EXMBX062.cuchost.com (172.16.6.62) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 14 Jul 2023 18:45:22 +0800 From: Samin Guo To: , , , CC: Emil Renner Berthing , Emil Renner Berthing , Conor Dooley , "Rob Herring" , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Richard Cochran , "David S . Miller" , Eric Dumazet , "Jakub Kicinski" , Paolo Abeni , Jose Abreu , Andrew Lunn , Heiner Kallweit , Peter Geis , Yanhong Wang , Samin Guo , Tommaso Merciai Subject: [PATCH v1 1/2] riscv: dts: starfive: jh7110: Add ethernet device nodes Date: Fri, 14 Jul 2023 18:45:20 +0800 Message-ID: <20230714104521.18751-2-samin.guo@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230714104521.18751-1-samin.guo@starfivetech.com> References: <20230714104521.18751-1-samin.guo@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX062.cuchost.com (172.16.6.62) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add JH7110 ethernet device node to support gmac driver for the JH7110 RISC-V SoC. Tested-by: Tommaso Merciai Signed-off-by: Yanhong Wang Signed-off-by: Samin Guo --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 69 ++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index 06a08c39c671..857e61a216ac 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -263,6 +263,13 @@ #clock-cells =3D <0>; }; =20 + stmmac_axi_setup: stmmac-axi-config { + snps,lpi_en; + snps,wr_osr_lmt =3D <4>; + snps,rd_osr_lmt =3D <4>; + snps,blen =3D <256 128 64 32 0 0 0>; + }; + tdm_ext: tdm-ext-clock { compatible =3D "fixed-clock"; clock-output-names =3D "tdm_ext"; @@ -522,6 +529,68 @@ <&syscrg JH7110_SYSRST_WDT_CORE>; }; =20 + gmac0: ethernet@16030000 { + compatible =3D "starfive,jh7110-dwmac", "snps,dwmac-5.20"; + reg =3D <0x0 0x16030000 0x0 0x10000>; + clocks =3D <&aoncrg JH7110_AONCLK_GMAC0_AXI>, + <&aoncrg JH7110_AONCLK_GMAC0_AHB>, + <&syscrg JH7110_SYSCLK_GMAC0_PTP>, + <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>, + <&syscrg JH7110_SYSCLK_GMAC0_GTXC>; + clock-names =3D "stmmaceth", "pclk", "ptp_ref", + "tx", "gtx"; + resets =3D <&aoncrg JH7110_AONRST_GMAC0_AXI>, + <&aoncrg JH7110_AONRST_GMAC0_AHB>; + reset-names =3D "stmmaceth", "ahb"; + interrupts =3D <7>, <6>, <5>; + interrupt-names =3D "macirq", "eth_wake_irq", "eth_lpi"; + rx-fifo-depth =3D <2048>; + tx-fifo-depth =3D <2048>; + snps,multicast-filter-bins =3D <64>; + snps,perfect-filter-entries =3D <8>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,tso; + snps,en-tx-lpi-clockgating; + snps,txpbl =3D <16>; + snps,rxpbl =3D <16>; + starfive,syscon =3D <&aon_syscon 0xc 0x12>; + status =3D "disabled"; + }; + + gmac1: ethernet@16040000 { + compatible =3D "starfive,jh7110-dwmac", "snps,dwmac-5.20"; + reg =3D <0x0 0x16040000 0x0 0x10000>; + clocks =3D <&syscrg JH7110_SYSCLK_GMAC1_AXI>, + <&syscrg JH7110_SYSCLK_GMAC1_AHB>, + <&syscrg JH7110_SYSCLK_GMAC1_PTP>, + <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>, + <&syscrg JH7110_SYSCLK_GMAC1_GTXC>; + clock-names =3D "stmmaceth", "pclk", "ptp_ref", + "tx", "gtx"; + resets =3D <&syscrg JH7110_SYSRST_GMAC1_AXI>, + <&syscrg JH7110_SYSRST_GMAC1_AHB>; + reset-names =3D "stmmaceth", "ahb"; + interrupts =3D <78>, <77>, <76>; + interrupt-names =3D "macirq", "eth_wake_irq", "eth_lpi"; + rx-fifo-depth =3D <2048>; + tx-fifo-depth =3D <2048>; + snps,multicast-filter-bins =3D <64>; + snps,perfect-filter-entries =3D <8>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,tso; + snps,en-tx-lpi-clockgating; + snps,txpbl =3D <16>; + snps,rxpbl =3D <16>; + starfive,syscon =3D <&sys_syscon 0x90 0x2>; + status =3D "disabled"; + }; + aoncrg: clock-controller@17000000 { compatible =3D "starfive,jh7110-aoncrg"; reg =3D <0x0 0x17000000 0x0 0x10000>; --=20 2.17.1 From nobody Sun Feb 8 04:30:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E16DCEB64DA for ; Fri, 14 Jul 2023 10:45:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235360AbjGNKpf (ORCPT ); Fri, 14 Jul 2023 06:45:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235212AbjGNKpa (ORCPT ); Fri, 14 Jul 2023 06:45:30 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EAAFD30EF; Fri, 14 Jul 2023 03:45:26 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 8916024DD81; Fri, 14 Jul 2023 18:45:25 +0800 (CST) Received: from EXMBX062.cuchost.com (172.16.6.62) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 14 Jul 2023 18:45:25 +0800 Received: from starfive-sdk.starfivetech.com (171.223.208.138) by EXMBX062.cuchost.com (172.16.6.62) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 14 Jul 2023 18:45:23 +0800 From: Samin Guo To: , , , CC: Emil Renner Berthing , Emil Renner Berthing , Conor Dooley , "Rob Herring" , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Richard Cochran , "David S . Miller" , Eric Dumazet , "Jakub Kicinski" , Paolo Abeni , Jose Abreu , Andrew Lunn , Heiner Kallweit , Peter Geis , Yanhong Wang , Samin Guo , Tommaso Merciai Subject: [PATCH v1 2/2] riscv: dts: starfive: visionfive 2: Add configuration of gmac and phy Date: Fri, 14 Jul 2023 18:45:21 +0800 Message-ID: <20230714104521.18751-3-samin.guo@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230714104521.18751-1-samin.guo@starfivetech.com> References: <20230714104521.18751-1-samin.guo@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX062.cuchost.com (172.16.6.62) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" v1.3B: v1.3B uses motorcomm YT8531(rgmii-id phy) x2, need delay and inverse configurations. The tx_clk of v1.3B uses an external clock and needs to be switched to an external clock source. v1.2A: v1.2A gmac0 uses motorcomm YT8531(rgmii-id) PHY, and needs delay configurations. v1.2A gmac1 uses motorcomm YT8512(rmii) PHY, and needs to switch rx and rx to external clock sources. Tested-by: Tommaso Merciai Signed-off-by: Samin Guo --- .../jh7110-starfive-visionfive-2-v1.2a.dts | 13 +++++++ .../jh7110-starfive-visionfive-2-v1.3b.dts | 31 +++++++++++++++++ .../jh7110-starfive-visionfive-2.dtsi | 34 +++++++++++++++++++ 3 files changed, 78 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2= a.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts index 4af3300f3cf3..205a13d8c8b1 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts @@ -11,3 +11,16 @@ model =3D "StarFive VisionFive 2 v1.2A"; compatible =3D "starfive,visionfive-2-v1.2a", "starfive,jh7110"; }; + +&gmac1 { + phy-mode =3D "rmii"; + assigned-clocks =3D <&syscrg JH7110_SYSCLK_GMAC1_TX>, + <&syscrg JH7110_SYSCLK_GMAC1_RX>; + assigned-clock-parents =3D <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>, + <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>; +}; + +&phy0 { + rx-internal-delay-ps =3D <1900>; + tx-internal-delay-ps =3D <1350>; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3= b.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts index 9230cc3d8946..36f74d4eda01 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts @@ -11,3 +11,34 @@ model =3D "StarFive VisionFive 2 v1.3B"; compatible =3D "starfive,visionfive-2-v1.3b", "starfive,jh7110"; }; + +&gmac0 { + starfive,tx-use-rgmii-clk; + assigned-clocks =3D <&aoncrg JH7110_AONCLK_GMAC0_TX>; + assigned-clock-parents =3D <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; +}; + +&gmac1 { + starfive,tx-use-rgmii-clk; + assigned-clocks =3D <&syscrg JH7110_SYSCLK_GMAC1_TX>; + assigned-clock-parents =3D <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>; +}; + +&phy0 { + motorcomm,tx-clk-adj-enabled; + motorcomm,tx-clk-100-inverted; + motorcomm,tx-clk-1000-inverted; + motorcomm,rx-clk-driver-strength =3D <3970>; + motorcomm,rx-data-driver-strength =3D <2910>; + rx-internal-delay-ps =3D <1500>; + tx-internal-delay-ps =3D <1500>; +}; + +&phy1 { + motorcomm,tx-clk-adj-enabled; + motorcomm,tx-clk-100-inverted; + motorcomm,rx-clk-driver-strength =3D <3970>; + motorcomm,rx-data-driver-strength =3D <2910>; + rx-internal-delay-ps =3D <300>; + tx-internal-delay-ps =3D <0>; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi= b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index fa0061eb33a7..fcb45db42df5 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -11,6 +11,8 @@ =20 / { aliases { + ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; i2c0 =3D &i2c0; i2c2 =3D &i2c2; i2c5 =3D &i2c5; @@ -86,6 +88,38 @@ clock-frequency =3D <49152000>; }; =20 +&gmac0 { + phy-handle =3D <&phy0>; + phy-mode =3D "rgmii-id"; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + + phy0: ethernet-phy@0 { + reg =3D <0>; + }; + }; +}; + +&gmac1 { + phy-handle =3D <&phy1>; + phy-mode =3D "rgmii-id"; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + + phy1: ethernet-phy@1 { + reg =3D <0>; + }; + }; +}; + &i2c0 { clock-frequency =3D <100000>; i2c-sda-hold-time-ns =3D <300>; --=20 2.17.1