From nobody Sun Sep 14 05:38:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 804CDC0015E for ; Thu, 13 Jul 2023 16:33:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234884AbjGMQdQ (ORCPT ); Thu, 13 Jul 2023 12:33:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234076AbjGMQcg (ORCPT ); Thu, 13 Jul 2023 12:32:36 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4FA3E273F; Thu, 13 Jul 2023 09:32:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689265955; x=1720801955; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QLPVmH8OKhS156FijxUUbjl5TQT038tMDl99vshP4rU=; b=M1gczokT+uUBuUD4ZoLQG6uPnJV3HheA4kBcSKXqSKNjjdAgyTNO4VSq cIFv4lQmR11LW/V/wMceBfYrrJ+X9Zns7v2LnwCf6PYQ98rvDl9GOPRvV hI7NPmdRQWJSpjaK429NjlZEclnZlLLZsT6pDG7Q6EHDEuvERbxrhTqIw 5j41eGvxDAmNsmzjWQKf4yLGI/H8dNzUG2Ml3UOorgJBqEJXZLOUl1Sl8 DyiOAOloSjfk+1d0u1wrzLVYFa6r9OFuycUZYFpHJTHg77RfjRPX6Djcr etJchpisEV7bxqcpamNM2HrsaJGHYlMbuwXZzFi1n4aNPN69VOwqphcIh w==; X-IronPort-AV: E=McAfee;i="6600,9927,10770"; a="362707678" X-IronPort-AV: E=Sophos;i="6.01,203,1684825200"; d="scan'208";a="362707678" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 09:32:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10770"; a="722046397" X-IronPort-AV: E=Sophos;i="6.01,203,1684825200"; d="scan'208";a="722046397" Received: from agluck-desk3.sc.intel.com ([172.25.222.74]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 09:32:23 -0700 From: Tony Luck To: Fenghua Yu , Reinette Chatre , Peter Newman , Jonathan Corbet , Shuah Khan , x86@kernel.org Cc: Shaopeng Tan , James Morse , Jamie Iles , Babu Moger , Randy Dunlap , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v3 8/8] selftests/resctrl: Adjust effective L3 cache size when SNC enabled Date: Thu, 13 Jul 2023 09:32:07 -0700 Message-Id: <20230713163207.219710-9-tony.luck@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713163207.219710-1-tony.luck@intel.com> References: <20230713163207.219710-1-tony.luck@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Sub-NUMA Cluster divides CPUs sharing an L3 cache into separate NUMA nodes. Systems may support splitting into either two or four nodes. When SNC mode is enabled the effective amount of L3 cache available for allocation is divided by the number of nodes per L3. Detect which SNC mode is active by comparing the number of CPUs that share a cache with CPU0, with the number of CPUs on node0. Reported-by: "Shaopeng Tan (Fujitsu)" Closes: https://lore.kernel.org/r/TYAPR01MB6330B9B17686EF426D2C3F308B25A@TY= APR01MB6330.jpnprd01.prod.outlook.com Signed-off-by: Tony Luck --- tools/testing/selftests/resctrl/resctrl.h | 1 + tools/testing/selftests/resctrl/resctrlfs.c | 57 +++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/self= tests/resctrl/resctrl.h index 87e39456dee0..a8b43210b573 100644 --- a/tools/testing/selftests/resctrl/resctrl.h +++ b/tools/testing/selftests/resctrl/resctrl.h @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include diff --git a/tools/testing/selftests/resctrl/resctrlfs.c b/tools/testing/se= lftests/resctrl/resctrlfs.c index fb00245dee92..79eecbf9f863 100644 --- a/tools/testing/selftests/resctrl/resctrlfs.c +++ b/tools/testing/selftests/resctrl/resctrlfs.c @@ -130,6 +130,61 @@ int get_resource_id(int cpu_no, int *resource_id) return 0; } =20 +/* + * Count number of CPUs in a /sys bit map + */ +static int count_sys_bitmap_bits(char *name) +{ + FILE *fp =3D fopen(name, "r"); + int count =3D 0, c; + + if (!fp) + return 0; + + while ((c =3D fgetc(fp)) !=3D EOF) { + if (!isxdigit(c)) + continue; + switch (c) { + case 'f': + count++; + case '7': case 'b': case 'd': case 'e': + count++; + case '3': case '5': case '6': case '9': case 'a': case 'c': + count++; + case '1': case '2': case '4': case '8': + count++; + } + } + fclose(fp); + + return count; +} + +/* + * Detect SNC by compating #CPUs in node0 with #CPUs sharing LLC with CPU0 + * Try to get this right, even if a few CPUs are offline so that the number + * of CPUs in node0 is not exactly half or a quarter of the CPUs sharing t= he + * LLC of CPU0. + */ +static int snc_ways(void) +{ + int node_cpus, cache_cpus; + + node_cpus =3D count_sys_bitmap_bits("/sys/devices/system/node/node0/cpuma= p"); + cache_cpus =3D count_sys_bitmap_bits("/sys/devices/system/cpu/cpu0/cache/= index3/shared_cpu_map"); + + if (!node_cpus || !cache_cpus) { + fprintf(stderr, "Warning could not determine Sub-NUMA Cluster mode\n"); + return 1; + } + + if (4 * node_cpus >=3D cache_cpus) + return 4; + else if (2 * node_cpus >=3D cache_cpus) + return 2; + return 1; +} + /* * get_cache_size - Get cache size for a specified CPU * @cpu_no: CPU number @@ -190,6 +245,8 @@ int get_cache_size(int cpu_no, char *cache_type, unsign= ed long *cache_size) break; } =20 + if (cache_num =3D=3D 3) + *cache_size /=3D snc_ways(); return 0; } =20 --=20 2.40.1