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[2.34.24.242]) by smtp.gmail.com with ESMTPSA id u17-20020a0cf1d1000000b00637873ff0f3sm3206582qvl.15.2023.07.13.09.27.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jul 2023 09:27:59 -0700 (PDT) From: Marco Pagani To: Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix Cc: Marco Pagani , linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org Subject: [PATCH v9 3/4] fpga: add an initial KUnit suite for the FPGA Region Date: Thu, 13 Jul 2023 18:27:30 +0200 Message-ID: <20230713162731.211669-4-marpagan@redhat.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230713162731.211669-1-marpagan@redhat.com> References: <20230713162731.211669-1-marpagan@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The suite tests the basic behaviors of the FPGA Region including the programming and the function for finding a specific region. Signed-off-by: Marco Pagani Acked-by: Xu Yilun --- drivers/fpga/tests/fpga-region-test.c | 211 ++++++++++++++++++++++++++ 1 file changed, 211 insertions(+) create mode 100644 drivers/fpga/tests/fpga-region-test.c diff --git a/drivers/fpga/tests/fpga-region-test.c b/drivers/fpga/tests/fpg= a-region-test.c new file mode 100644 index 000000000000..9f9d50ee7871 --- /dev/null +++ b/drivers/fpga/tests/fpga-region-test.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * KUnit test for the FPGA Region + * + * Copyright (C) 2023 Red Hat, Inc. + * + * Author: Marco Pagani + */ + +#include +#include +#include +#include +#include +#include +#include + +struct mgr_stats { + u32 write_count; +}; + +struct bridge_stats { + bool enable; + u32 cycles_count; +}; + +struct test_ctx { + struct fpga_manager *mgr; + struct platform_device *mgr_pdev; + struct fpga_bridge *bridge; + struct platform_device *bridge_pdev; + struct fpga_region *region; + struct platform_device *region_pdev; + struct bridge_stats bridge_stats; + struct mgr_stats mgr_stats; +}; + +static int op_write(struct fpga_manager *mgr, const char *buf, size_t coun= t) +{ + struct mgr_stats *stats =3D mgr->priv; + + stats->write_count++; + + return 0; +} + +/* + * Fake FPGA manager that implements only the write op to count the number + * of programming cycles. The internals of the programming sequence are + * tested in the Manager suite since they are outside the responsibility + * of the Region. + */ +static const struct fpga_manager_ops fake_mgr_ops =3D { + .write =3D op_write, +}; + +static int op_enable_set(struct fpga_bridge *bridge, bool enable) +{ + struct bridge_stats *stats =3D bridge->priv; + + if (!stats->enable && enable) + stats->cycles_count++; + + stats->enable =3D enable; + + return 0; +} + +/* + * Fake FPGA bridge that implements only enable_set op to count the number + * of activation cycles. + */ +static const struct fpga_bridge_ops fake_bridge_ops =3D { + .enable_set =3D op_enable_set, +}; + +static int fake_region_get_bridges(struct fpga_region *region) +{ + struct fpga_bridge *bridge =3D region->priv; + + return fpga_bridge_get_to_list(bridge->dev.parent, region->info, ®ion-= >bridge_list); +} + +static int fake_region_match(struct device *dev, const void *data) +{ + return dev->parent =3D=3D data; +} + +static void fpga_region_test_class_find(struct kunit *test) +{ + struct test_ctx *ctx =3D test->priv; + struct fpga_region *region; + + region =3D fpga_region_class_find(NULL, &ctx->region_pdev->dev, fake_regi= on_match); + KUNIT_EXPECT_PTR_EQ(test, region, ctx->region); +} + +/* + * FPGA Region programming test. The Region must call get_bridges() to get + * and control the bridges, and then the Manager for the actual programmin= g. + */ +static void fpga_region_test_program_fpga(struct kunit *test) +{ + struct test_ctx *ctx =3D test->priv; + struct fpga_image_info *img_info; + char img_buf[4]; + int ret; + + img_info =3D fpga_image_info_alloc(&ctx->mgr_pdev->dev); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, img_info); + + img_info->buf =3D img_buf; + img_info->count =3D sizeof(img_buf); + + ctx->region->info =3D img_info; + ret =3D fpga_region_program_fpga(ctx->region); + KUNIT_ASSERT_EQ(test, ret, 0); + + KUNIT_EXPECT_EQ(test, 1, ctx->mgr_stats.write_count); + KUNIT_EXPECT_EQ(test, 1, ctx->bridge_stats.cycles_count); + + fpga_bridges_put(&ctx->region->bridge_list); + + ret =3D fpga_region_program_fpga(ctx->region); + KUNIT_ASSERT_EQ(test, ret, 0); + + KUNIT_EXPECT_EQ(test, 2, ctx->mgr_stats.write_count); + KUNIT_EXPECT_EQ(test, 2, ctx->bridge_stats.cycles_count); + + fpga_bridges_put(&ctx->region->bridge_list); + + fpga_image_info_free(img_info); +} + +/* + * The configuration used in this test suite uses a single bridge to + * limit the code under test to a single unit. The functions used by the + * Region for getting and controlling bridges are tested (with a list of + * multiple bridges) in the Bridge suite. + */ +static int fpga_region_test_init(struct kunit *test) +{ + struct test_ctx *ctx; + struct fpga_region_info region_info =3D { 0 }; + + ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx); + + ctx->mgr_pdev =3D platform_device_register_simple("mgr_pdev", PLATFORM_DE= VID_AUTO, NULL, 0); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->mgr_pdev); + + ctx->mgr =3D devm_fpga_mgr_register(&ctx->mgr_pdev->dev, "Fake FPGA Manag= er", &fake_mgr_ops, + &ctx->mgr_stats); + KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->mgr)); + + ctx->bridge_pdev =3D platform_device_register_simple("bridge_pdev", PLATF= ORM_DEVID_AUTO, + NULL, 0); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->bridge_pdev); + + ctx->bridge =3D fpga_bridge_register(&ctx->bridge_pdev->dev, "Fake FPGA B= ridge", + &fake_bridge_ops, &ctx->bridge_stats); + KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->bridge)); + + ctx->bridge_stats.enable =3D true; + + ctx->region_pdev =3D platform_device_register_simple("region_pdev", PLATF= ORM_DEVID_AUTO, + NULL, 0); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->region_pdev); + + region_info.mgr =3D ctx->mgr; + region_info.priv =3D ctx->bridge; + region_info.get_bridges =3D fake_region_get_bridges; + + ctx->region =3D fpga_region_register_full(&ctx->region_pdev->dev, ®ion= _info); + KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->region)); + + test->priv =3D ctx; + + return 0; +} + +static void fpga_region_test_exit(struct kunit *test) +{ + struct test_ctx *ctx =3D test->priv; + + fpga_region_unregister(ctx->region); + platform_device_unregister(ctx->region_pdev); + + fpga_bridge_unregister(ctx->bridge); + platform_device_unregister(ctx->bridge_pdev); + + platform_device_unregister(ctx->mgr_pdev); +} + +static struct kunit_case fpga_region_test_cases[] =3D { + KUNIT_CASE(fpga_region_test_class_find), + KUNIT_CASE(fpga_region_test_program_fpga), + + {} +}; + +static struct kunit_suite fpga_region_suite =3D { + .name =3D "fpga_mgr", + .init =3D fpga_region_test_init, + .exit =3D fpga_region_test_exit, + .test_cases =3D fpga_region_test_cases, +}; + +kunit_test_suite(fpga_region_suite); + +MODULE_LICENSE("GPL"); --=20 2.41.0