From nobody Fri Sep 20 13:38:22 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F919C0015E for ; Thu, 13 Jul 2023 15:04:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232593AbjGMPEe (ORCPT ); Thu, 13 Jul 2023 11:04:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39862 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232561AbjGMPEa (ORCPT ); Thu, 13 Jul 2023 11:04:30 -0400 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67A01106 for ; Thu, 13 Jul 2023 08:04:29 -0700 (PDT) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-98df3dea907so120526366b.3 for ; Thu, 13 Jul 2023 08:04:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20221208.gappssmtp.com; s=20221208; t=1689260668; x=1691852668; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J0qTvBf5FgaTyQcfbl+e1xRZRJHDSVi0KUDZ9vhIQHg=; b=4VNzRyteYrFfKexzB8Qn3VbI/bFDU4Kbe4VCy941Q3FmJcywE04PS//wnYk82YJRO/ fblUk8CEjBGspi5ROwN2cN/mi//wecUfx04FbbjDK0c4Lurm0EJHU639KPMhk+6HNUre /LmmSjbTpYsyPyrWZXTjKV5E7YyRYyD8HQFsci9vkjD9a/U/YfDl9FihdflLMEzMT0lZ Ws+c2K/5Pxs7k0g1j8CLlIkXldxa/Aa4b8oJbyjbixem46i/hfM7n6PCFOrFKGXH+R8Q M6X4ZnBoC1fVBOtk6dSlr+QX9q0gkGTf3Adi09kYYxgsEVDTsQnoYqLCR4unc79PJ1wy rz/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689260668; x=1691852668; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J0qTvBf5FgaTyQcfbl+e1xRZRJHDSVi0KUDZ9vhIQHg=; b=cSiu3IsELC+IZQ7/WEfOqyMRnVU4eC6idpC473SqN5HMDeBo9O2O5muk8h57VqeJBx pSZjPxVGMzKW2jqLKFoSf3/ahKL6K0jDuKv2KR1idNkA4iIGo9riOG7BP+eI9kDEN6TJ pRbmYi8Gg7d6h5vIXWE67rI/HGPuy5rPUxjQ4BJ7F9Vh2BkJju8NCJqAVxPcWkrm68Vz svI5EDw8vVUthZ2Hubkf0OAT1Vs1maO7Y679tBHQGLBs9ymKdb1r0brUGn9mBxt3LrGK NNXFWFp84+JGaOdpXW2FKZWXLdsaNwYNOwrqS3/+nV6KLftuNxxcD7QfBIHBtoOHjlSw tvtw== X-Gm-Message-State: ABy/qLYzlXWijIFFt0Yo+YQwTsH9U+Zi7fVf4LEOu2GYAc8ggwP9Le30 Gyl11wE8pnHZQsvV98dAeRAkhQ== X-Google-Smtp-Source: APBJJlGmB6PaFatY8+84gJNEQfODAH4Hsrd1Jkh+iEMF5Q8ud/aawSFeHhlV64SUdDYXtjlA8AoMZA== X-Received: by 2002:a17:906:224a:b0:991:caa8:fc3a with SMTP id 10-20020a170906224a00b00991caa8fc3amr1704354ejr.72.1689260667614; Thu, 13 Jul 2023 08:04:27 -0700 (PDT) Received: from blmsp.fritz.box ([2001:4091:a247:82fa:1d6d:d215:e7c4:dd5e]) by smtp.gmail.com with ESMTPSA id cd26-20020a170906b35a00b009929c39d5c4sm4102939ejb.36.2023.07.13.08.04.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jul 2023 08:04:27 -0700 (PDT) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Tinghan Shen , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Fabien Parent , Markus Schneider-Pargmann , Krzysztof Kozlowski , Rob Herring , Alexandre Mergnat Subject: [PATCH v7 1/8] dt-bindings: power: Add MT8365 power domains Date: Thu, 13 Jul 2023 17:04:07 +0200 Message-Id: <20230713150414.891893-2-msp@baylibre.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713150414.891893-1-msp@baylibre.com> References: <20230713150414.891893-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fabien Parent Add power domains dt-bindings for MT8365. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Acked-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat --- .../power/mediatek,power-controller.yaml | 6 ++++++ .../dt-bindings/power/mediatek,mt8365-power.h | 19 +++++++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 include/dt-bindings/power/mediatek,mt8365-power.h diff --git a/Documentation/devicetree/bindings/power/mediatek,power-control= ler.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controlle= r.yaml index c9acef80f452..8985e2df8a56 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -31,6 +31,7 @@ properties: - mediatek,mt8188-power-controller - mediatek,mt8192-power-controller - mediatek,mt8195-power-controller + - mediatek,mt8365-power-controller =20 '#power-domain-cells': const: 1 @@ -88,6 +89,7 @@ $defs: "include/dt-bindings/power/mediatek,mt8188-power.h" - for MT= 8188 type power domain. "include/dt-bindings/power/mt8192-power.h" - for MT8192 type= power domain. "include/dt-bindings/power/mt8195-power.h" - for MT8195 type= power domain. + "include/dt-bindings/power/mediatek,mt8365-power.h" - for MT= 8365 type power domain. maxItems: 1 =20 clocks: @@ -115,6 +117,10 @@ $defs: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the INFRACFG registe= r range. =20 + mediatek,infracfg-nao: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the device containing the INFRACFG-NAO reg= ister range. + mediatek,smi: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the SMI register ran= ge. diff --git a/include/dt-bindings/power/mediatek,mt8365-power.h b/include/dt= -bindings/power/mediatek,mt8365-power.h new file mode 100644 index 000000000000..e6cfd0ec7871 --- /dev/null +++ b/include/dt-bindings/power/mediatek,mt8365-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_POWER_MT8365_POWER_H +#define _DT_BINDINGS_POWER_MT8365_POWER_H + +#define MT8365_POWER_DOMAIN_MM 0 +#define MT8365_POWER_DOMAIN_CONN 1 +#define MT8365_POWER_DOMAIN_MFG 2 +#define MT8365_POWER_DOMAIN_AUDIO 3 +#define MT8365_POWER_DOMAIN_CAM 4 +#define MT8365_POWER_DOMAIN_DSP 5 +#define MT8365_POWER_DOMAIN_VDEC 6 +#define MT8365_POWER_DOMAIN_VENC 7 +#define MT8365_POWER_DOMAIN_APU 8 + +#endif /* _DT_BINDINGS_POWER_MT8365_POWER_H */ --=20 2.40.1 From nobody Fri Sep 20 13:38:22 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 970D9C0015E for ; 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Thu, 13 Jul 2023 08:04:28 -0700 (PDT) Received: from blmsp.fritz.box ([2001:4091:a247:82fa:1d6d:d215:e7c4:dd5e]) by smtp.gmail.com with ESMTPSA id cd26-20020a170906b35a00b009929c39d5c4sm4102939ejb.36.2023.07.13.08.04.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jul 2023 08:04:28 -0700 (PDT) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Tinghan Shen , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Markus Schneider-Pargmann , Alexandre Mergnat Subject: [PATCH v7 2/8] soc: mediatek: pm-domains: Move bools to a flags field Date: Thu, 13 Jul 2023 17:04:08 +0200 Message-Id: <20230713150414.891893-3-msp@baylibre.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713150414.891893-1-msp@baylibre.com> References: <20230713150414.891893-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To simplify the macros, use a flags field for simple bools. This is in preparation for more flags. Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat --- drivers/soc/mediatek/mtk-pm-domains.c | 6 +++--- drivers/soc/mediatek/mtk-pm-domains.h | 19 +++++++++++-------- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index 354249cc1b12..aa9ab413479e 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -128,7 +128,7 @@ static int _scpsys_bus_protect_enable(const struct scps= ys_bus_prot_data *bpd, st if (!mask) break; =20 - if (bpd[i].bus_prot_reg_update) + if (bpd[i].flags & BUS_PROT_REG_UPDATE) regmap_set_bits(regmap, bpd[i].bus_prot_set, mask); else regmap_write(regmap, bpd[i].bus_prot_set, mask); @@ -165,12 +165,12 @@ static int _scpsys_bus_protect_disable(const struct s= cpsys_bus_prot_data *bpd, if (!mask) continue; =20 - if (bpd[i].bus_prot_reg_update) + if (bpd[i].flags & BUS_PROT_REG_UPDATE) regmap_clear_bits(regmap, bpd[i].bus_prot_clr, mask); else regmap_write(regmap, bpd[i].bus_prot_clr, mask); =20 - if (bpd[i].ignore_clr_ack) + if (bpd[i].flags & BUS_PROT_IGNORE_CLR_ACK) continue; =20 ret =3D regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/m= tk-pm-domains.h index 5ec53ee073c4..d8c0c299dd45 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -42,23 +42,27 @@ =20 #define SPM_MAX_BUS_PROT_DATA 6 =20 -#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \ +enum scpsys_bus_prot_flags { + BUS_PROT_REG_UPDATE =3D BIT(1), + BUS_PROT_IGNORE_CLR_ACK =3D BIT(2), +}; + +#define _BUS_PROT(_mask, _set, _clr, _sta, _flags) { \ .bus_prot_mask =3D (_mask), \ .bus_prot_set =3D _set, \ .bus_prot_clr =3D _clr, \ .bus_prot_sta =3D _sta, \ - .bus_prot_reg_update =3D _update, \ - .ignore_clr_ack =3D _ignore, \ + .flags =3D _flags \ } =20 #define BUS_PROT_WR(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, false, false) + _BUS_PROT(_mask, _set, _clr, _sta, 0) =20 #define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, false, true) + _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_IGNORE_CLR_ACK) =20 #define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, true, false) + _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_REG_UPDATE) =20 #define BUS_PROT_UPDATE_TOPAXI(_mask) \ BUS_PROT_UPDATE(_mask, \ @@ -71,8 +75,7 @@ struct scpsys_bus_prot_data { u32 bus_prot_set; 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charset="utf-8" bus_prot_mask is used for all operations, set clear and acknowledge. In preparation of m8365 power domain support split this one mask into two, one mask for set and clear, another one for acknowledge. Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat --- drivers/soc/mediatek/mtk-pm-domains.c | 24 ++++++++++++++---------- drivers/soc/mediatek/mtk-pm-domains.h | 14 ++++++++------ 2 files changed, 22 insertions(+), 16 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index aa9ab413479e..a2c8f5313124 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -123,18 +123,20 @@ static int _scpsys_bus_protect_enable(const struct sc= psys_bus_prot_data *bpd, st int i, ret; =20 for (i =3D 0; i < SPM_MAX_BUS_PROT_DATA; i++) { - u32 val, mask =3D bpd[i].bus_prot_mask; + u32 set_clr_mask =3D bpd[i].bus_prot_set_clr_mask; + u32 sta_mask =3D bpd[i].bus_prot_sta_mask; + u32 val; =20 - if (!mask) + if (!set_clr_mask) break; =20 if (bpd[i].flags & BUS_PROT_REG_UPDATE) - regmap_set_bits(regmap, bpd[i].bus_prot_set, mask); + regmap_set_bits(regmap, bpd[i].bus_prot_set, set_clr_mask); else - regmap_write(regmap, bpd[i].bus_prot_set, mask); + regmap_write(regmap, bpd[i].bus_prot_set, set_clr_mask); =20 ret =3D regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, (val & mask) =3D=3D mask, + val, (val & sta_mask) =3D=3D sta_mask, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); if (ret) return ret; @@ -160,21 +162,23 @@ static int _scpsys_bus_protect_disable(const struct s= cpsys_bus_prot_data *bpd, int i, ret; =20 for (i =3D SPM_MAX_BUS_PROT_DATA - 1; i >=3D 0; i--) { - u32 val, mask =3D bpd[i].bus_prot_mask; + u32 set_clr_mask =3D bpd[i].bus_prot_set_clr_mask; + u32 sta_mask =3D bpd[i].bus_prot_sta_mask; + u32 val; =20 - if (!mask) + if (!set_clr_mask) continue; =20 if (bpd[i].flags & BUS_PROT_REG_UPDATE) - regmap_clear_bits(regmap, bpd[i].bus_prot_clr, mask); + regmap_clear_bits(regmap, bpd[i].bus_prot_clr, set_clr_mask); else - regmap_write(regmap, bpd[i].bus_prot_clr, mask); + regmap_write(regmap, bpd[i].bus_prot_clr, set_clr_mask); =20 if (bpd[i].flags & BUS_PROT_IGNORE_CLR_ACK) continue; =20 ret =3D regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, !(val & mask), + val, !(val & sta_mask), MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); if (ret) return ret; diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/m= tk-pm-domains.h index d8c0c299dd45..4c3ab72a907b 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -47,22 +47,23 @@ enum scpsys_bus_prot_flags { BUS_PROT_IGNORE_CLR_ACK =3D BIT(2), }; =20 -#define _BUS_PROT(_mask, _set, _clr, _sta, _flags) { \ - .bus_prot_mask =3D (_mask), \ +#define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \ + .bus_prot_set_clr_mask =3D (_set_clr_mask), \ .bus_prot_set =3D _set, \ .bus_prot_clr =3D _clr, \ + .bus_prot_sta_mask =3D (_sta_mask), \ .bus_prot_sta =3D _sta, \ .flags =3D _flags \ } =20 #define BUS_PROT_WR(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, 0) + _BUS_PROT(_mask, _set, _clr, _mask, _sta, 0) =20 #define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_IGNORE_CLR_ACK) + _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_IGNORE_CLR_ACK) =20 #define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, BUS_PROT_REG_UPDATE) + _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_REG_UPDATE) =20 #define BUS_PROT_UPDATE_TOPAXI(_mask) \ BUS_PROT_UPDATE(_mask, \ @@ -71,9 +72,10 @@ enum scpsys_bus_prot_flags { INFRA_TOPAXI_PROTECTSTA1) =20 struct scpsys_bus_prot_data { - u32 bus_prot_mask; + u32 bus_prot_set_clr_mask; u32 bus_prot_set; u32 bus_prot_clr; + u32 bus_prot_sta_mask; u32 bus_prot_sta; u8 flags; }; --=20 2.40.1 From nobody Fri Sep 20 13:38:22 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E5CAC00528 for ; Thu, 13 Jul 2023 15:04:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232741AbjGMPEo (ORCPT ); Thu, 13 Jul 2023 11:04:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232568AbjGMPEd (ORCPT ); Thu, 13 Jul 2023 11:04:33 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E24431B6 for ; Thu, 13 Jul 2023 08:04:31 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-992b27e1c55so120604066b.2 for ; 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charset="utf-8" Separate the register access used for bus protection enable/disable into their own functions. These will be used later for WAY_EN support. Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat --- drivers/soc/mediatek/mtk-pm-domains.c | 68 +++++++++++++++------------ 1 file changed, 39 insertions(+), 29 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index a2c8f5313124..a7a46fb132ee 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -118,26 +118,50 @@ static int scpsys_sram_disable(struct scpsys_domain *= pd) MTK_POLL_TIMEOUT); } =20 +static int scpsys_bus_protect_clear(const struct scpsys_bus_prot_data *bpd, + struct regmap *regmap) +{ + u32 sta_mask =3D bpd->bus_prot_sta_mask; + u32 val; + + if (bpd->flags & BUS_PROT_REG_UPDATE) + regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask); + else + regmap_write(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask); + + if (bpd->flags & BUS_PROT_IGNORE_CLR_ACK) + return 0; + + return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, + val, !(val & sta_mask), + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); +} + +static int scpsys_bus_protect_set(const struct scpsys_bus_prot_data *bpd, + struct regmap *regmap) +{ + u32 sta_mask =3D bpd->bus_prot_sta_mask; + u32 val; + + if (bpd->flags & BUS_PROT_REG_UPDATE) + regmap_set_bits(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask); + else + regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask); + + return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, + val, (val & sta_mask) =3D=3D sta_mask, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); +} + static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *b= pd, struct regmap *regmap) { int i, ret; =20 for (i =3D 0; i < SPM_MAX_BUS_PROT_DATA; i++) { - u32 set_clr_mask =3D bpd[i].bus_prot_set_clr_mask; - u32 sta_mask =3D bpd[i].bus_prot_sta_mask; - u32 val; - - if (!set_clr_mask) + if (!bpd[i].bus_prot_set_clr_mask) break; =20 - if (bpd[i].flags & BUS_PROT_REG_UPDATE) - regmap_set_bits(regmap, bpd[i].bus_prot_set, set_clr_mask); - else - regmap_write(regmap, bpd[i].bus_prot_set, set_clr_mask); - - ret =3D regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, (val & sta_mask) =3D=3D sta_mask, - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + ret =3D scpsys_bus_protect_set(&bpd[i], regmap); if (ret) return ret; } @@ -162,24 +186,10 @@ static int _scpsys_bus_protect_disable(const struct s= cpsys_bus_prot_data *bpd, int i, ret; =20 for (i =3D SPM_MAX_BUS_PROT_DATA - 1; i >=3D 0; i--) { - u32 set_clr_mask =3D bpd[i].bus_prot_set_clr_mask; - u32 sta_mask =3D bpd[i].bus_prot_sta_mask; - u32 val; - - if (!set_clr_mask) - continue; - - if (bpd[i].flags & BUS_PROT_REG_UPDATE) - regmap_clear_bits(regmap, bpd[i].bus_prot_clr, set_clr_mask); - else - regmap_write(regmap, bpd[i].bus_prot_clr, set_clr_mask); - - if (bpd[i].flags & BUS_PROT_IGNORE_CLR_ACK) + if (!bpd[i].bus_prot_set_clr_mask) continue; =20 - ret =3D regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, - val, !(val & sta_mask), - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + ret =3D scpsys_bus_protect_clear(&bpd[i], regmap); if (ret) return ret; } --=20 2.40.1 From nobody Fri Sep 20 13:38:22 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1CD7C0015E for ; Thu, 13 Jul 2023 15:04:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232435AbjGMPE6 (ORCPT ); Thu, 13 Jul 2023 11:04:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232628AbjGMPEi (ORCPT ); Thu, 13 Jul 2023 11:04:38 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D23ABE4F for ; Thu, 13 Jul 2023 08:04:33 -0700 (PDT) Received: by mail-lj1-x232.google.com with SMTP id 38308e7fff4ca-2b71ae5fa2fso12459581fa.0 for ; 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charset="utf-8" Use flags to distinguish between infracfg and smi subsystem for a bus protection configuration. It simplifies enabling/disabling and prepares the driver for the use of another regmap for mt8365. Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat --- drivers/soc/mediatek/mt6795-pm-domains.h | 16 +- drivers/soc/mediatek/mt8167-pm-domains.h | 20 +- drivers/soc/mediatek/mt8173-pm-domains.h | 16 +- drivers/soc/mediatek/mt8183-pm-domains.h | 125 +++++++----- drivers/soc/mediatek/mt8186-pm-domains.h | 236 +++++++++++++---------- drivers/soc/mediatek/mt8188-pm-domains.h | 223 +++++++++++++-------- drivers/soc/mediatek/mt8192-pm-domains.h | 112 +++++++---- drivers/soc/mediatek/mt8195-pm-domains.h | 199 ++++++++++++------- drivers/soc/mediatek/mtk-pm-domains.c | 64 +++--- drivers/soc/mediatek/mtk-pm-domains.h | 26 +-- 10 files changed, 612 insertions(+), 425 deletions(-) diff --git a/drivers/soc/mediatek/mt6795-pm-domains.h b/drivers/soc/mediate= k/mt6795-pm-domains.h index ef07c9dfdd9b..a3f7785b04bd 100644 --- a/drivers/soc/mediatek/mt6795-pm-domains.h +++ b/drivers/soc/mediatek/mt6795-pm-domains.h @@ -46,9 +46,9 @@ static const struct scpsys_domain_data scpsys_domain_data= _mt6795[] =3D { .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, .sram_pdn_bits =3D GENMASK(11, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 | - MT8173_TOP_AXI_PROT_EN_MM_M1), + .bp_cfg =3D { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 | + MT8173_TOP_AXI_PROT_EN_MM_M1), }, }, [MT6795_POWER_DOMAIN_MJC] =3D { @@ -95,11 +95,11 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt6795[] =3D { .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, .sram_pdn_bits =3D GENMASK(13, 8), .sram_pdn_ack_bits =3D GENMASK(21, 16), - .bp_infracfg =3D { - BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S | - MT8173_TOP_AXI_PROT_EN_MFG_M0 | - MT8173_TOP_AXI_PROT_EN_MFG_M1 | - MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), + .bp_cfg =3D { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S | + MT8173_TOP_AXI_PROT_EN_MFG_M0 | + MT8173_TOP_AXI_PROT_EN_MFG_M1 | + MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), }, }, }; diff --git a/drivers/soc/mediatek/mt8167-pm-domains.h b/drivers/soc/mediate= k/mt8167-pm-domains.h index 4d6c32759606..8a0e898b79ab 100644 --- a/drivers/soc/mediatek/mt8167-pm-domains.h +++ b/drivers/soc/mediatek/mt8167-pm-domains.h @@ -22,9 +22,9 @@ static const struct scpsys_domain_data scpsys_domain_data= _mt8167[] =3D { .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, .sram_pdn_bits =3D GENMASK(11, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI | - MT8167_TOP_AXI_PROT_EN_MCU_MM), + .bp_cfg =3D { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI | + MT8167_TOP_AXI_PROT_EN_MCU_MM), }, .caps =3D MTK_SCPD_ACTIVE_WAKEUP, }, @@ -56,9 +56,9 @@ static const struct scpsys_domain_data scpsys_domain_data= _mt8167[] =3D { .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, .sram_pdn_bits =3D 0, .sram_pdn_ack_bits =3D 0, - .bp_infracfg =3D { - BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG | - MT8167_TOP_AXI_PROT_EN_MFG_EMI), + .bp_cfg =3D { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG | + MT8167_TOP_AXI_PROT_EN_MFG_EMI), }, }, [MT8167_POWER_DOMAIN_MFG_2D] =3D { @@ -88,10 +88,10 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8167[] =3D { .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D 0, .caps =3D MTK_SCPD_ACTIVE_WAKEUP, - .bp_infracfg =3D { - BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI | - MT8167_TOP_AXI_PROT_EN_CONN_MCU | - MT8167_TOP_AXI_PROT_EN_MCU_CONN), + .bp_cfg =3D { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI | + MT8167_TOP_AXI_PROT_EN_CONN_MCU | + MT8167_TOP_AXI_PROT_EN_MCU_CONN), }, }, }; diff --git a/drivers/soc/mediatek/mt8173-pm-domains.h b/drivers/soc/mediate= k/mt8173-pm-domains.h index 1a5dc63b7357..7be0f47f5214 100644 --- a/drivers/soc/mediatek/mt8173-pm-domains.h +++ b/drivers/soc/mediatek/mt8173-pm-domains.h @@ -46,9 +46,9 @@ static const struct scpsys_domain_data scpsys_domain_data= _mt8173[] =3D { .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, .sram_pdn_bits =3D GENMASK(11, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 | - MT8173_TOP_AXI_PROT_EN_MM_M1), + .bp_cfg =3D { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 | + MT8173_TOP_AXI_PROT_EN_MM_M1), }, }, [MT8173_POWER_DOMAIN_VENC_LT] =3D { @@ -106,11 +106,11 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8173[] =3D { .pwr_sta2nd_offs =3D SPM_PWR_STATUS_2ND, .sram_pdn_bits =3D GENMASK(13, 8), .sram_pdn_ack_bits =3D GENMASK(21, 16), - .bp_infracfg =3D { - BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S | - MT8173_TOP_AXI_PROT_EN_MFG_M0 | - MT8173_TOP_AXI_PROT_EN_MFG_M1 | - MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), + .bp_cfg =3D { + BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S | + MT8173_TOP_AXI_PROT_EN_MFG_M0 | + MT8173_TOP_AXI_PROT_EN_MFG_M1 | + MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), }, }, }; diff --git a/drivers/soc/mediatek/mt8183-pm-domains.h b/drivers/soc/mediate= k/mt8183-pm-domains.h index 99de67fe5de8..c4c1b63d85b1 100644 --- a/drivers/soc/mediatek/mt8183-pm-domains.h +++ b/drivers/soc/mediatek/mt8183-pm-domains.h @@ -28,9 +28,12 @@ static const struct scpsys_domain_data scpsys_domain_dat= a_mt8183[] =3D { .pwr_sta2nd_offs =3D 0x0184, .sram_pdn_bits =3D 0, .sram_pdn_ack_bits =3D 0, - .bp_infracfg =3D { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CONN, MT8183_TOP_AXI_PROT_EN_SET, - MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_CONN, + MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, + MT8183_TOP_AXI_PROT_EN_STA1), }, }, [MT8183_POWER_DOMAIN_MFG_ASYNC] =3D { @@ -79,11 +82,17 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8183[] =3D { .pwr_sta2nd_offs =3D 0x0184, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_MFG, MT8183_TOP_AXI_PROT_EN_1_SET, - MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MFG, MT8183_TOP_AXI_PROT_EN_SET, - MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_1_MFG, + MT8183_TOP_AXI_PROT_EN_1_SET, + MT8183_TOP_AXI_PROT_EN_1_CLR, + MT8183_TOP_AXI_PROT_EN_STA1_1), + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MFG, + MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, + MT8183_TOP_AXI_PROT_EN_STA1), }, }, [MT8183_POWER_DOMAIN_DISP] =3D { @@ -94,14 +103,19 @@ static const struct scpsys_domain_data scpsys_domain_d= ata_mt8183[] =3D { .pwr_sta2nd_offs =3D 0x0184, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_DISP, MT8183_TOP_AXI_PROT_EN_1_SET, - MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_DISP, MT8183_TOP_AXI_PROT_EN_SET, - MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), - }, - .bp_smi =3D { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_DISP, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_1_DISP, + MT8183_TOP_AXI_PROT_EN_1_SET, + MT8183_TOP_AXI_PROT_EN_1_CLR, + MT8183_TOP_AXI_PROT_EN_STA1_1), + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_DISP, + MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, + MT8183_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(SMI, + MT8183_SMI_COMMON_SMI_CLAMP_DISP, MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN), @@ -115,18 +129,24 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8183[] =3D { .pwr_sta2nd_offs =3D 0x0184, .sram_pdn_bits =3D GENMASK(9, 8), .sram_pdn_ack_bits =3D GENMASK(13, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_CAM, MT8183_TOP_AXI_PROT_EN_MM_SE= T, - MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CAM, MT8183_TOP_AXI_PROT_EN_SET, - MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MM_CAM, + MT8183_TOP_AXI_PROT_EN_MM_SET, + MT8183_TOP_AXI_PROT_EN_MM_CLR, + MT8183_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_CAM, + MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, + MT8183_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR_IGN(INFRA, + MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND, MT8183_TOP_AXI_PROT_EN_MM_SET, MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), - }, - .bp_smi =3D { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_CAM, + BUS_PROT_WR(SMI, + MT8183_SMI_COMMON_SMI_CLAMP_CAM, MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN), @@ -140,18 +160,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8183[] =3D { .pwr_sta2nd_offs =3D 0x0184, .sram_pdn_bits =3D GENMASK(9, 8), .sram_pdn_ack_bits =3D GENMASK(13, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_ISP, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MM_ISP, MT8183_TOP_AXI_PROT_EN_MM_SET, MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND, + BUS_PROT_WR_IGN(INFRA, + MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND, MT8183_TOP_AXI_PROT_EN_MM_SET, MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), - }, - .bp_smi =3D { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_ISP, + BUS_PROT_WR(SMI, + MT8183_SMI_COMMON_SMI_CLAMP_ISP, MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN), @@ -165,8 +186,9 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8183[] =3D { .pwr_sta2nd_offs =3D 0x0184, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_smi =3D { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VDEC, + .bp_cfg =3D { + BUS_PROT_WR(SMI, + MT8183_SMI_COMMON_SMI_CLAMP_VDEC, MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN), @@ -180,8 +202,9 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8183[] =3D { .pwr_sta2nd_offs =3D 0x0184, .sram_pdn_bits =3D GENMASK(11, 8), .sram_pdn_ack_bits =3D GENMASK(15, 12), - .bp_smi =3D { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VENC, + .bp_cfg =3D { + BUS_PROT_WR(SMI, + MT8183_SMI_COMMON_SMI_CLAMP_VENC, MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN), @@ -195,22 +218,24 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8183[] =3D { .pwr_sta2nd_offs =3D 0x0184, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP, MT8183_TOP_AXI_PROT_EN_MM_SET, MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_VPU_TOP, + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_VPU_TOP, MT8183_TOP_AXI_PROT_EN_SET, MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND, + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND, MT8183_TOP_AXI_PROT_EN_MM_SET, MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), - }, - .bp_smi =3D { - BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP, + BUS_PROT_WR(SMI, + MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP, MT8183_SMI_COMMON_CLAMP_EN_SET, MT8183_SMI_COMMON_CLAMP_EN_CLR, MT8183_SMI_COMMON_CLAMP_EN), @@ -224,12 +249,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8183[] =3D { .pwr_sta2nd_offs =3D 0x0184, .sram_pdn_bits =3D GENMASK(11, 8), .sram_pdn_ack_bits =3D GENMASK(13, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0, MT8183_TOP_AXI_PROT_EN_MCU_SET, MT8183_TOP_AXI_PROT_EN_MCU_CLR, MT8183_TOP_AXI_PROT_EN_MCU_STA1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND, + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND, MT8183_TOP_AXI_PROT_EN_MCU_SET, MT8183_TOP_AXI_PROT_EN_MCU_CLR, MT8183_TOP_AXI_PROT_EN_MCU_STA1), @@ -244,12 +271,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8183[] =3D { .pwr_sta2nd_offs =3D 0x0184, .sram_pdn_bits =3D GENMASK(11, 8), .sram_pdn_ack_bits =3D GENMASK(13, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1, MT8183_TOP_AXI_PROT_EN_MCU_SET, MT8183_TOP_AXI_PROT_EN_MCU_CLR, MT8183_TOP_AXI_PROT_EN_MCU_STA1), - BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND, + BUS_PROT_WR(INFRA, + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND, MT8183_TOP_AXI_PROT_EN_MCU_SET, MT8183_TOP_AXI_PROT_EN_MCU_CLR, MT8183_TOP_AXI_PROT_EN_MCU_STA1), diff --git a/drivers/soc/mediatek/mt8186-pm-domains.h b/drivers/soc/mediate= k/mt8186-pm-domains.h index fce86f79c505..cbac715c38fa 100644 --- a/drivers/soc/mediatek/mt8186-pm-domains.h +++ b/drivers/soc/mediatek/mt8186-pm-domains.h @@ -33,23 +33,27 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8186[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP2, - MT8186_TOP_AXI_PROT_EN_SET, - MT8186_TOP_AXI_PROT_EN_CLR, - MT8186_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP3, - MT8186_TOP_AXI_PROT_EN_SET, - MT8186_TOP_AXI_PROT_EN_CLR, - MT8186_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), + .bp_cfg =3D { + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_MFG1_STEP2, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_MFG1_STEP3, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, }, @@ -101,15 +105,17 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8186[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_DIS_STEP2, - MT8186_TOP_AXI_PROT_EN_SET, - MT8186_TOP_AXI_PROT_EN_CLR, - MT8186_TOP_AXI_PROT_EN_STA), + .bp_cfg =3D { + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_DIS_STEP2, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), }, }, [MT8186_POWER_DOMAIN_IMG] =3D { @@ -120,15 +126,17 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8186[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), + .bp_cfg =3D { + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -150,15 +158,17 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8186[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), + .bp_cfg =3D { + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -170,15 +180,17 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8186[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), + .bp_cfg =3D { + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -210,15 +222,17 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8186[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), + .bp_cfg =3D { + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -230,15 +244,17 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8186[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), + .bp_cfg =3D { + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -250,15 +266,17 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8186[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1, - MT8186_TOP_AXI_PROT_EN_2_SET, - MT8186_TOP_AXI_PROT_EN_2_CLR, - MT8186_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2, - MT8186_TOP_AXI_PROT_EN_2_SET, - MT8186_TOP_AXI_PROT_EN_2_CLR, - MT8186_TOP_AXI_PROT_EN_2_STA), + .bp_cfg =3D { + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1, + MT8186_TOP_AXI_PROT_EN_2_SET, + MT8186_TOP_AXI_PROT_EN_2_CLR, + MT8186_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2, + MT8186_TOP_AXI_PROT_EN_2_SET, + MT8186_TOP_AXI_PROT_EN_2_CLR, + MT8186_TOP_AXI_PROT_EN_2_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF, }, @@ -268,23 +286,27 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8186[] =3D { .ctl_offs =3D 0x304, .pwr_sta_offs =3D 0x16C, .pwr_sta2nd_offs =3D 0x170, - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1, - MT8186_TOP_AXI_PROT_EN_1_SET, - MT8186_TOP_AXI_PROT_EN_1_CLR, - MT8186_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2, - MT8186_TOP_AXI_PROT_EN_SET, - MT8186_TOP_AXI_PROT_EN_CLR, - MT8186_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3, - MT8186_TOP_AXI_PROT_EN_SET, - MT8186_TOP_AXI_PROT_EN_CLR, - MT8186_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4, - MT8186_TOP_AXI_PROT_EN_SET, - MT8186_TOP_AXI_PROT_EN_CLR, - MT8186_TOP_AXI_PROT_EN_STA), + .bp_cfg =3D { + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), }, .caps =3D MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, }, @@ -320,15 +342,17 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8186[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1, - MT8186_TOP_AXI_PROT_EN_3_SET, - MT8186_TOP_AXI_PROT_EN_3_CLR, - MT8186_TOP_AXI_PROT_EN_3_STA), - BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2, - MT8186_TOP_AXI_PROT_EN_3_SET, - MT8186_TOP_AXI_PROT_EN_3_CLR, - MT8186_TOP_AXI_PROT_EN_3_STA), + .bp_cfg =3D { + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1, + MT8186_TOP_AXI_PROT_EN_3_SET, + MT8186_TOP_AXI_PROT_EN_3_CLR, + MT8186_TOP_AXI_PROT_EN_3_STA), + BUS_PROT_WR_IGN(INFRA, + MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2, + MT8186_TOP_AXI_PROT_EN_3_SET, + MT8186_TOP_AXI_PROT_EN_3_CLR, + MT8186_TOP_AXI_PROT_EN_3_STA), }, .caps =3D MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP, }, diff --git a/drivers/soc/mediatek/mt8188-pm-domains.h b/drivers/soc/mediate= k/mt8188-pm-domains.h index 0692cb444ed0..06834ab6597c 100644 --- a/drivers/soc/mediatek/mt8188-pm-domains.h +++ b/drivers/soc/mediatek/mt8188-pm-domains.h @@ -33,28 +33,34 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x178, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MFG1_STEP1, MT8188_TOP_AXI_PROT_EN_SET, MT8188_TOP_AXI_PROT_EN_CLR, MT8188_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3, MT8188_TOP_AXI_PROT_EN_1_SET, MT8188_TOP_AXI_PROT_EN_1_CLR, MT8188_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP5, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MFG1_STEP5, MT8188_TOP_AXI_PROT_EN_SET, MT8188_TOP_AXI_PROT_EN_CLR, MT8188_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6, MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), @@ -99,12 +105,14 @@ static const struct scpsys_domain_data scpsys_domain_d= ata_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x178, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1, MT8188_TOP_AXI_PROT_EN_SET, MT8188_TOP_AXI_PROT_EN_CLR, MT8188_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), @@ -135,8 +143,9 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), @@ -151,8 +160,9 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), @@ -165,12 +175,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .ctl_offs =3D 0x35C, .pwr_sta_offs =3D 0x16C, .pwr_sta2nd_offs =3D 0x170, - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), @@ -185,12 +197,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), @@ -205,12 +219,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), @@ -225,12 +241,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), @@ -245,12 +263,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), @@ -265,24 +285,29 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1, MT8188_TOP_AXI_PROT_EN_SET, MT8188_TOP_AXI_PROT_EN_CLR, MT8188_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3, MT8188_TOP_AXI_PROT_EN_SET, MT8188_TOP_AXI_PROT_EN_CLR, MT8188_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5, MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), @@ -296,16 +321,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2, MT8188_TOP_AXI_PROT_EN_SET, MT8188_TOP_AXI_PROT_EN_CLR, MT8188_TOP_AXI_PROT_EN_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3, MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), @@ -319,16 +347,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), @@ -342,8 +373,9 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), @@ -358,8 +390,9 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), @@ -374,16 +407,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), @@ -397,12 +433,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), @@ -417,12 +455,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), @@ -437,12 +477,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), @@ -457,16 +499,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), @@ -479,16 +524,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .ctl_offs =3D 0x3A4, .pwr_sta_offs =3D 0x16C, .pwr_sta2nd_offs =3D 0x170, - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), @@ -503,12 +551,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), @@ -541,24 +591,29 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .ctl_offs =3D 0x3A0, .pwr_sta_offs =3D 0x16C, .pwr_sta2nd_offs =3D 0x170, - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3, MT8188_TOP_AXI_PROT_EN_1_SET, MT8188_TOP_AXI_PROT_EN_1_CLR, MT8188_TOP_AXI_PROT_EN_1_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4, MT8188_TOP_AXI_PROT_EN_MM_SET, MT8188_TOP_AXI_PROT_EN_MM_CLR, MT8188_TOP_AXI_PROT_EN_MM_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), @@ -573,20 +628,24 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8188[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D BIT(8), .sram_pdn_ack_bits =3D BIT(12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3, MT8188_TOP_AXI_PROT_EN_MM_2_SET, MT8188_TOP_AXI_PROT_EN_MM_2_CLR, MT8188_TOP_AXI_PROT_EN_MM_2_STA), - BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4, + BUS_PROT_WR(INFRA, + MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4, MT8188_TOP_AXI_PROT_EN_2_SET, MT8188_TOP_AXI_PROT_EN_2_CLR, MT8188_TOP_AXI_PROT_EN_2_STA), diff --git a/drivers/soc/mediatek/mt8192-pm-domains.h b/drivers/soc/mediate= k/mt8192-pm-domains.h index b97b2051920f..6f139eed3769 100644 --- a/drivers/soc/mediatek/mt8192-pm-domains.h +++ b/drivers/soc/mediatek/mt8192-pm-domains.h @@ -19,8 +19,9 @@ static const struct scpsys_domain_data scpsys_domain_data= _mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_AUDIO, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_2_AUDIO, MT8192_TOP_AXI_PROT_EN_2_SET, MT8192_TOP_AXI_PROT_EN_2_CLR, MT8192_TOP_AXI_PROT_EN_2_STA1), @@ -34,16 +35,19 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D 0, .sram_pdn_ack_bits =3D 0, - .bp_infracfg =3D { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_CONN, MT8192_TOP_AXI_PROT_EN_SET, MT8192_TOP_AXI_PROT_EN_CLR, MT8192_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_CONN_2ND, MT8192_TOP_AXI_PROT_EN_SET, MT8192_TOP_AXI_PROT_EN_CLR, MT8192_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CONN, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_1_CONN, MT8192_TOP_AXI_PROT_EN_1_SET, MT8192_TOP_AXI_PROT_EN_1_CLR, MT8192_TOP_AXI_PROT_EN_1_STA1), @@ -68,20 +72,24 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_MFG1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_1_MFG1, MT8192_TOP_AXI_PROT_EN_1_SET, MT8192_TOP_AXI_PROT_EN_1_CLR, MT8192_TOP_AXI_PROT_EN_1_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_2_MFG1, MT8192_TOP_AXI_PROT_EN_2_SET, MT8192_TOP_AXI_PROT_EN_2_CLR, MT8192_TOP_AXI_PROT_EN_2_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MFG1, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MFG1, MT8192_TOP_AXI_PROT_EN_SET, MT8192_TOP_AXI_PROT_EN_CLR, MT8192_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND, MT8192_TOP_AXI_PROT_EN_2_SET, MT8192_TOP_AXI_PROT_EN_2_CLR, MT8192_TOP_AXI_PROT_EN_2_STA1), @@ -141,24 +149,29 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_DISP, + .bp_cfg =3D { + BUS_PROT_WR_IGN(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_DISP, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_2_DISP, + BUS_PROT_WR_IGN(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_2_DISP, MT8192_TOP_AXI_PROT_EN_MM_2_SET, MT8192_TOP_AXI_PROT_EN_MM_2_CLR, MT8192_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_DISP, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_DISP, MT8192_TOP_AXI_PROT_EN_SET, MT8192_TOP_AXI_PROT_EN_CLR, MT8192_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND, MT8192_TOP_AXI_PROT_EN_MM_2_SET, MT8192_TOP_AXI_PROT_EN_MM_2_CLR, MT8192_TOP_AXI_PROT_EN_MM_2_STA1), @@ -172,12 +185,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_IPE, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), @@ -191,12 +206,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_2_ISP, MT8192_TOP_AXI_PROT_EN_MM_2_SET, MT8192_TOP_AXI_PROT_EN_MM_2_CLR, MT8192_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND, MT8192_TOP_AXI_PROT_EN_MM_2_SET, MT8192_TOP_AXI_PROT_EN_MM_2_CLR, MT8192_TOP_AXI_PROT_EN_MM_2_STA1), @@ -210,12 +227,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_ISP2, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), @@ -229,12 +248,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_2_MDP, MT8192_TOP_AXI_PROT_EN_MM_2_SET, MT8192_TOP_AXI_PROT_EN_MM_2_CLR, MT8192_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND, MT8192_TOP_AXI_PROT_EN_MM_2_SET, MT8192_TOP_AXI_PROT_EN_MM_2_CLR, MT8192_TOP_AXI_PROT_EN_MM_2_STA1), @@ -248,12 +269,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_VENC, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), @@ -267,12 +290,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_VDEC, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), @@ -295,24 +320,29 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8192[] =3D { .pwr_sta2nd_offs =3D 0x0170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_CAM, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_2_CAM, MT8192_TOP_AXI_PROT_EN_2_SET, MT8192_TOP_AXI_PROT_EN_2_CLR, MT8192_TOP_AXI_PROT_EN_2_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_CAM, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CAM, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_1_CAM, MT8192_TOP_AXI_PROT_EN_1_SET, MT8192_TOP_AXI_PROT_EN_1_CLR, MT8192_TOP_AXI_PROT_EN_1_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND, MT8192_TOP_AXI_PROT_EN_MM_SET, MT8192_TOP_AXI_PROT_EN_MM_CLR, MT8192_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_VDNR_CAM, + BUS_PROT_WR(INFRA, + MT8192_TOP_AXI_PROT_EN_VDNR_CAM, MT8192_TOP_AXI_PROT_EN_VDNR_SET, MT8192_TOP_AXI_PROT_EN_VDNR_CLR, MT8192_TOP_AXI_PROT_EN_VDNR_STA1), diff --git a/drivers/soc/mediatek/mt8195-pm-domains.h b/drivers/soc/mediate= k/mt8195-pm-domains.h index d7387ea1b9c9..59aa031ae632 100644 --- a/drivers/soc/mediatek/mt8195-pm-domains.h +++ b/drivers/soc/mediatek/mt8195-pm-domains.h @@ -23,12 +23,14 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x178, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0, MT8195_TOP_AXI_PROT_EN_VDNR_SET, MT8195_TOP_AXI_PROT_EN_VDNR_CLR, MT8195_TOP_AXI_PROT_EN_VDNR_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0, MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), @@ -42,12 +44,14 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x178, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1, MT8195_TOP_AXI_PROT_EN_VDNR_SET, MT8195_TOP_AXI_PROT_EN_VDNR_CLR, MT8195_TOP_AXI_PROT_EN_VDNR_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1, MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), @@ -95,8 +99,9 @@ static const struct scpsys_domain_data scpsys_domain_data= _mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_ADSP, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_2_ADSP, MT8195_TOP_AXI_PROT_EN_2_SET, MT8195_TOP_AXI_PROT_EN_2_CLR, MT8195_TOP_AXI_PROT_EN_2_STA1), @@ -111,8 +116,9 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_AUDIO, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_2_AUDIO, MT8195_TOP_AXI_PROT_EN_2_SET, MT8195_TOP_AXI_PROT_EN_2_CLR, MT8195_TOP_AXI_PROT_EN_2_STA1), @@ -136,28 +142,34 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x178, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MFG1, MT8195_TOP_AXI_PROT_EN_SET, MT8195_TOP_AXI_PROT_EN_CLR, MT8195_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_2_MFG1, MT8195_TOP_AXI_PROT_EN_2_SET, MT8195_TOP_AXI_PROT_EN_2_CLR, MT8195_TOP_AXI_PROT_EN_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_MFG1, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_1_MFG1, MT8195_TOP_AXI_PROT_EN_1_SET, MT8195_TOP_AXI_PROT_EN_1_CLR, MT8195_TOP_AXI_PROT_EN_1_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND, MT8195_TOP_AXI_PROT_EN_2_SET, MT8195_TOP_AXI_PROT_EN_2_CLR, MT8195_TOP_AXI_PROT_EN_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MFG1_2ND, MT8195_TOP_AXI_PROT_EN_SET, MT8195_TOP_AXI_PROT_EN_CLR, MT8195_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), @@ -222,24 +234,29 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VPPSYS0, MT8195_TOP_AXI_PROT_EN_SET, MT8195_TOP_AXI_PROT_EN_CLR, MT8195_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND, MT8195_TOP_AXI_PROT_EN_SET, MT8195_TOP_AXI_PROT_EN_CLR, MT8195_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), @@ -253,16 +270,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDOSYS0, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VDOSYS0, MT8195_TOP_AXI_PROT_EN_SET, MT8195_TOP_AXI_PROT_EN_CLR, MT8195_TOP_AXI_PROT_EN_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), @@ -276,16 +296,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -299,16 +322,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -322,8 +348,9 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX, MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), @@ -338,8 +365,9 @@ static const struct scpsys_domain_data scpsys_domain_da= ta_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX, MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), @@ -364,16 +392,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_WPESYS, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_WPESYS, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -387,20 +418,24 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VDEC0, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -415,12 +450,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VDEC1, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), @@ -435,12 +472,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -455,16 +494,19 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VENC, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VENC, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -479,12 +521,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -499,12 +543,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_IMG, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), @@ -529,12 +575,14 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IPE, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_IPE, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_IPE, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_IPE, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), @@ -549,24 +597,29 @@ static const struct scpsys_domain_data scpsys_domain_= data_mt8195[] =3D { .pwr_sta2nd_offs =3D 0x170, .sram_pdn_bits =3D GENMASK(8, 8), .sram_pdn_ack_bits =3D GENMASK(12, 12), - .bp_infracfg =3D { - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_CAM, + .bp_cfg =3D { + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_2_CAM, MT8195_TOP_AXI_PROT_EN_2_SET, MT8195_TOP_AXI_PROT_EN_2_CLR, MT8195_TOP_AXI_PROT_EN_2_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_CAM, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_CAM, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_1_CAM, MT8195_TOP_AXI_PROT_EN_1_SET, MT8195_TOP_AXI_PROT_EN_1_CLR, MT8195_TOP_AXI_PROT_EN_1_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND, MT8195_TOP_AXI_PROT_EN_MM_SET, MT8195_TOP_AXI_PROT_EN_MM_CLR, MT8195_TOP_AXI_PROT_EN_MM_STA1), - BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_CAM, + BUS_PROT_WR(INFRA, + MT8195_TOP_AXI_PROT_EN_MM_2_CAM, MT8195_TOP_AXI_PROT_EN_MM_2_SET, MT8195_TOP_AXI_PROT_EN_MM_2_CLR, MT8195_TOP_AXI_PROT_EN_MM_2_STA1), diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index a7a46fb132ee..5d10a363e435 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -118,9 +118,19 @@ static int scpsys_sram_disable(struct scpsys_domain *p= d) MTK_POLL_TIMEOUT); } =20 -static int scpsys_bus_protect_clear(const struct scpsys_bus_prot_data *bpd, - struct regmap *regmap) +static struct regmap *scpsys_bus_protect_get_regmap(struct scpsys_domain *= pd, + const struct scpsys_bus_prot_data *bpd) { + if (bpd->flags & BUS_PROT_COMPONENT_SMI) + return pd->smi; + else + return pd->infracfg; +} + +static int scpsys_bus_protect_clear(struct scpsys_domain *pd, + const struct scpsys_bus_prot_data *bpd) +{ + struct regmap *regmap =3D scpsys_bus_protect_get_regmap(pd, bpd); u32 sta_mask =3D bpd->bus_prot_sta_mask; u32 val; =20 @@ -137,9 +147,10 @@ static int scpsys_bus_protect_clear(const struct scpsy= s_bus_prot_data *bpd, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } =20 -static int scpsys_bus_protect_set(const struct scpsys_bus_prot_data *bpd, - struct regmap *regmap) +static int scpsys_bus_protect_set(struct scpsys_domain *pd, + const struct scpsys_bus_prot_data *bpd) { + struct regmap *regmap =3D scpsys_bus_protect_get_regmap(pd, bpd); u32 sta_mask =3D bpd->bus_prot_sta_mask; u32 val; =20 @@ -153,15 +164,16 @@ static int scpsys_bus_protect_set(const struct scpsys= _bus_prot_data *bpd, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } =20 -static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *b= pd, struct regmap *regmap) +static int scpsys_bus_protect_enable(struct scpsys_domain *pd) { - int i, ret; + for (int i =3D 0; i < SPM_MAX_BUS_PROT_DATA; i++) { + const struct scpsys_bus_prot_data *bpd =3D &pd->data->bp_cfg[i]; + int ret; =20 - for (i =3D 0; i < SPM_MAX_BUS_PROT_DATA; i++) { - if (!bpd[i].bus_prot_set_clr_mask) + if (!bpd->bus_prot_set_clr_mask) break; =20 - ret =3D scpsys_bus_protect_set(&bpd[i], regmap); + ret =3D scpsys_bus_protect_set(pd, bpd); if (ret) return ret; } @@ -169,27 +181,16 @@ static int _scpsys_bus_protect_enable(const struct sc= psys_bus_prot_data *bpd, st return 0; } =20 -static int scpsys_bus_protect_enable(struct scpsys_domain *pd) -{ - int ret; - - ret =3D _scpsys_bus_protect_enable(pd->data->bp_infracfg, pd->infracfg); - if (ret) - return ret; - - return _scpsys_bus_protect_enable(pd->data->bp_smi, pd->smi); -} - -static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *= bpd, - struct regmap *regmap) +static int scpsys_bus_protect_disable(struct scpsys_domain *pd) { - int i, ret; + for (int i =3D SPM_MAX_BUS_PROT_DATA - 1; i >=3D 0; i--) { + const struct scpsys_bus_prot_data *bpd =3D &pd->data->bp_cfg[i]; + int ret; =20 - for (i =3D SPM_MAX_BUS_PROT_DATA - 1; i >=3D 0; i--) { - if (!bpd[i].bus_prot_set_clr_mask) + if (!bpd->bus_prot_set_clr_mask) continue; =20 - ret =3D scpsys_bus_protect_clear(&bpd[i], regmap); + ret =3D scpsys_bus_protect_clear(pd, bpd); if (ret) return ret; } @@ -197,17 +198,6 @@ static int _scpsys_bus_protect_disable(const struct sc= psys_bus_prot_data *bpd, return 0; } =20 -static int scpsys_bus_protect_disable(struct scpsys_domain *pd) -{ - int ret; - - ret =3D _scpsys_bus_protect_disable(pd->data->bp_smi, pd->smi); - if (ret) - return ret; - - return _scpsys_bus_protect_disable(pd->data->bp_infracfg, pd->infracfg); -} - static int scpsys_regulator_enable(struct regulator *supply) { return supply ? regulator_enable(supply) : 0; diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/m= tk-pm-domains.h index 4c3ab72a907b..209f68dcaeac 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -45,6 +45,8 @@ enum scpsys_bus_prot_flags { BUS_PROT_REG_UPDATE =3D BIT(1), BUS_PROT_IGNORE_CLR_ACK =3D BIT(2), + BUS_PROT_COMPONENT_INFRA =3D BIT(4), + BUS_PROT_COMPONENT_SMI =3D BIT(5), }; =20 #define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \ @@ -56,17 +58,19 @@ enum scpsys_bus_prot_flags { .flags =3D _flags \ } =20 -#define BUS_PROT_WR(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _mask, _sta, 0) +#define BUS_PROT_WR(_hwip, _mask, _set, _clr, _sta) \ + _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_##_hwip) =20 -#define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_IGNORE_CLR_ACK) +#define BUS_PROT_WR_IGN(_hwip, _mask, _set, _clr, _sta) \ + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \ + BUS_PROT_COMPONENT_##_hwip | BUS_PROT_IGNORE_CLR_ACK) =20 -#define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_REG_UPDATE) +#define BUS_PROT_UPDATE(_hwip, _mask, _set, _clr, _sta) \ + _BUS_PROT(_mask, _set, _clr, _mask, _sta, \ + BUS_PROT_COMPONENT_##_hwip | BUS_PROT_REG_UPDATE) =20 -#define BUS_PROT_UPDATE_TOPAXI(_mask) \ - BUS_PROT_UPDATE(_mask, \ +#define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \ + BUS_PROT_UPDATE(INFRA, _mask, \ INFRA_TOPAXI_PROTECTEN, \ INFRA_TOPAXI_PROTECTEN, \ INFRA_TOPAXI_PROTECTSTA1) @@ -90,8 +94,7 @@ struct scpsys_bus_prot_data { * @ext_buck_iso_offs: The offset for external buck isolation * @ext_buck_iso_mask: The mask for external buck isolation * @caps: The flag for active wake-up action. - * @bp_infracfg: bus protection for infracfg subsystem - * @bp_smi: bus protection for smi subsystem + * @bp_cfg: bus protection configuration for any subsystem */ struct scpsys_domain_data { const char *name; @@ -102,8 +105,7 @@ struct scpsys_domain_data { int ext_buck_iso_offs; u32 ext_buck_iso_mask; u8 caps; - const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA]; - const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA]; + const struct scpsys_bus_prot_data bp_cfg[SPM_MAX_BUS_PROT_DATA]; int pwr_sta_offs; int pwr_sta2nd_offs; }; --=20 2.40.1 From nobody Fri Sep 20 13:38:22 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AFB8C0015E for ; Thu, 13 Jul 2023 15:04:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232662AbjGMPEs (ORCPT ); Thu, 13 Jul 2023 11:04:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232601AbjGMPEg (ORCPT ); Thu, 13 Jul 2023 11:04:36 -0400 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32DA4171D for ; Thu, 13 Jul 2023 08:04:34 -0700 (PDT) Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-9741caaf9d4so112597666b.0 for ; Thu, 13 Jul 2023 08:04:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20221208.gappssmtp.com; s=20221208; t=1689260672; x=1691852672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CwOgY7arZQoD9h63g66frjyHGnfB6U24ntym8yk4GhQ=; b=pg4Y6nPC9XR3k2s7akLzXuxkJX/iY4DWEw7l20/UXuQn5urHVoEQMpCEr3nDkLPD3Z RfmleBoYnH0yq+MolsXj0MXezzT2L5xPLp9uDiCUwwvooN9Dbye81UucFVkGD7GWVIZp poQQx/+n2Fu0fF8O/6Vpk9Hep9w3z2L52X1kpsA7kgoEgznWTmBLqPmqTQ+sJ4oDFkAQ LInn93Gx4ho6TTd/qR2mvxZcLd7/IKr+Dc3AjeyfiuK74k2vYghNrpcMSSVOQbQEjsah cMrYSdiC6NwacLYprhBTdwp7xpMhz1AADA4wimWUJfjb/aGoqjWqAE29SVn+FKmUyuhs VEAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689260672; x=1691852672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CwOgY7arZQoD9h63g66frjyHGnfB6U24ntym8yk4GhQ=; b=BZmlnyBIt7348062A049dhD45pyjjyQRok/XQPdyMfC7tK9dQr7utkf59Ug+iGbXm0 ZE3keW6eUHBcB//QkSp5A28z51YgZkkAiO0/7LVg8K/rLuwn0sjfh5azroxYVgwTxP8/ KAEQs+VIlPxyNT4DtsVD+VCYWaFWoA+8m6rceiB1nMosuBHdyt4qkK3x6Zs4/2kk0g2U OY34Pjq2JTz91oRL6hs/5c/VDZNrbg8VWuHIZeLEY64r7pXK12LvhGYzOcckjCVPPuJU Awg6VrgW8/0Na2+0Xi2MeDGrNB9+r9CO9Cv4qmC7RdBEigDF2vfi7Zl/bRC2sayEta19 SP0g== X-Gm-Message-State: ABy/qLZ2xcC74ObD0ACDdG45/vWfUxLeTxzUHKtyd1dEzN/UEMJupCDm QbqEBkIzmxG3Kn+h3KO27D3+1Q== X-Google-Smtp-Source: APBJJlHZc/uqfeCZE6Ejq3/nXF8F3WRbm2b3JzEmpq/zW8o8yySGkieRjMIEYx68o1+24z4k4BybPg== X-Received: by 2002:a17:906:cd0e:b0:992:a90a:5d1f with SMTP id oz14-20020a170906cd0e00b00992a90a5d1fmr1805125ejb.68.1689260672579; Thu, 13 Jul 2023 08:04:32 -0700 (PDT) Received: from blmsp.fritz.box ([2001:4091:a247:82fa:1d6d:d215:e7c4:dd5e]) by smtp.gmail.com with ESMTPSA id cd26-20020a170906b35a00b009929c39d5c4sm4102939ejb.36.2023.07.13.08.04.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jul 2023 08:04:32 -0700 (PDT) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Tinghan Shen , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Alexandre Bailon , Fabien Parent , Markus Schneider-Pargmann , Alexandre Mergnat Subject: [PATCH v7 6/8] soc: mediatek: Add support for WAY_EN operations Date: Thu, 13 Jul 2023 17:04:12 +0200 Message-Id: <20230713150414.891893-7-msp@baylibre.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713150414.891893-1-msp@baylibre.com> References: <20230713150414.891893-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexandre Bailon This updates the power domain to support WAY_EN operations. WAY_EN operations on mt8365 are using a different component to check for the acknowledgment, namely the infracfg-nao component. Also to enable a way it the bit needs to be cleared while disabling a way needs a bit to be set. To support these two operations two flags are added, BUS_PROT_INVERTED and BUS_PROT_STA_COMPONENT_INFRA_NAO. Additionally another regmap is created if the INFRA_NAO capability is set. This operation is required by the mt8365 for the MM power domain. Signed-off-by: Alexandre Bailon Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat --- drivers/soc/mediatek/mtk-pm-domains.c | 39 +++++++++++++++++++++++---- drivers/soc/mediatek/mtk-pm-domains.h | 3 +++ 2 files changed, 37 insertions(+), 5 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index 5d10a363e435..a9ac79e5c295 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -44,6 +44,7 @@ struct scpsys_domain { struct clk_bulk_data *clks; int num_subsys_clks; struct clk_bulk_data *subsys_clks; + struct regmap *infracfg_nao; struct regmap *infracfg; struct regmap *smi; struct regulator *supply; @@ -127,13 +128,26 @@ static struct regmap *scpsys_bus_protect_get_regmap(s= truct scpsys_domain *pd, return pd->infracfg; } =20 +static struct regmap *scpsys_bus_protect_get_sta_regmap(struct scpsys_doma= in *pd, + const struct scpsys_bus_prot_data *bpd) +{ + if (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO) + return pd->infracfg_nao; + else + return scpsys_bus_protect_get_regmap(pd, bpd); +} + static int scpsys_bus_protect_clear(struct scpsys_domain *pd, const struct scpsys_bus_prot_data *bpd) { + struct regmap *sta_regmap =3D scpsys_bus_protect_get_sta_regmap(pd, bpd); struct regmap *regmap =3D scpsys_bus_protect_get_regmap(pd, bpd); u32 sta_mask =3D bpd->bus_prot_sta_mask; + u32 expected_ack; u32 val; =20 + expected_ack =3D (bpd->flags & BUS_PROT_STA_COMPONENT_INFRA_NAO ? sta_mas= k : 0); + if (bpd->flags & BUS_PROT_REG_UPDATE) regmap_clear_bits(regmap, bpd->bus_prot_clr, bpd->bus_prot_set_clr_mask); else @@ -142,14 +156,15 @@ static int scpsys_bus_protect_clear(struct scpsys_dom= ain *pd, if (bpd->flags & BUS_PROT_IGNORE_CLR_ACK) return 0; =20 - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, - val, !(val & sta_mask), + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta, + val, (val & sta_mask) =3D=3D expected_ack, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } =20 static int scpsys_bus_protect_set(struct scpsys_domain *pd, const struct scpsys_bus_prot_data *bpd) { + struct regmap *sta_regmap =3D scpsys_bus_protect_get_sta_regmap(pd, bpd); struct regmap *regmap =3D scpsys_bus_protect_get_regmap(pd, bpd); u32 sta_mask =3D bpd->bus_prot_sta_mask; u32 val; @@ -159,7 +174,7 @@ static int scpsys_bus_protect_set(struct scpsys_domain = *pd, else regmap_write(regmap, bpd->bus_prot_set, bpd->bus_prot_set_clr_mask); =20 - return regmap_read_poll_timeout(regmap, bpd->bus_prot_sta, + return regmap_read_poll_timeout(sta_regmap, bpd->bus_prot_sta, val, (val & sta_mask) =3D=3D sta_mask, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } @@ -173,7 +188,10 @@ static int scpsys_bus_protect_enable(struct scpsys_dom= ain *pd) if (!bpd->bus_prot_set_clr_mask) break; =20 - ret =3D scpsys_bus_protect_set(pd, bpd); + if (bpd->flags & BUS_PROT_INVERTED) + ret =3D scpsys_bus_protect_clear(pd, bpd); + else + ret =3D scpsys_bus_protect_set(pd, bpd); if (ret) return ret; } @@ -190,7 +208,10 @@ static int scpsys_bus_protect_disable(struct scpsys_do= main *pd) if (!bpd->bus_prot_set_clr_mask) continue; =20 - ret =3D scpsys_bus_protect_clear(pd, bpd); + if (bpd->flags & BUS_PROT_INVERTED) + ret =3D scpsys_bus_protect_set(pd, bpd); + else + ret =3D scpsys_bus_protect_clear(pd, bpd); if (ret) return ret; } @@ -377,6 +398,14 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys= *scpsys, struct device_no return ERR_CAST(pd->smi); } =20 + if (MTK_SCPD_CAPS(pd, MTK_SCPD_HAS_INFRA_NAO)) { + pd->infracfg_nao =3D syscon_regmap_lookup_by_phandle(node, "mediatek,inf= racfg-nao"); + if (IS_ERR(pd->infracfg_nao)) + return ERR_CAST(pd->infracfg_nao); + } else { + pd->infracfg_nao =3D NULL; + } + num_clks =3D of_clk_get_parent_count(node); if (num_clks > 0) { /* Calculate number of subsys_clks */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/m= tk-pm-domains.h index 209f68dcaeac..17c033217704 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -11,6 +11,7 @@ /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */ #define MTK_SCPD_ALWAYS_ON BIT(5) #define MTK_SCPD_EXT_BUCK_ISO BIT(6) +#define MTK_SCPD_HAS_INFRA_NAO BIT(7) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) =20 #define SPM_VDE_PWR_CON 0x0210 @@ -45,8 +46,10 @@ enum scpsys_bus_prot_flags { BUS_PROT_REG_UPDATE =3D BIT(1), BUS_PROT_IGNORE_CLR_ACK =3D BIT(2), + BUS_PROT_INVERTED =3D BIT(3), BUS_PROT_COMPONENT_INFRA =3D BIT(4), BUS_PROT_COMPONENT_SMI =3D BIT(5), + BUS_PROT_STA_COMPONENT_INFRA_NAO =3D BIT(6), }; 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charset="utf-8" From: Alexandre Bailon This adds support for MTK_SCPD_STRICT_BUS_PROTECTION capability. It is a strict bus protection policy that requires the bus protection to be disabled before accessing the bus. This is required by the mt8365, for the MM power domain. Signed-off-by: Alexandre Bailon Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat --- drivers/soc/mediatek/mtk-pm-domains.c | 27 +++++++++++++++++++++++---- drivers/soc/mediatek/mtk-pm-domains.h | 3 ++- 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index a9ac79e5c295..cf45e29420b2 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -262,9 +262,17 @@ static int scpsys_power_on(struct generic_pm_domain *g= enpd) regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); =20 - ret =3D clk_bulk_prepare_enable(pd->num_subsys_clks, pd->subsys_clks); - if (ret) - goto err_pwr_ack; + /* + * In few Mediatek platforms(e.g. MT6779), the bus protect policy is + * stricter, which leads to bus protect release must be prior to bus + * access. + */ + if (!MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) { + ret =3D clk_bulk_prepare_enable(pd->num_subsys_clks, + pd->subsys_clks); + if (ret) + goto err_pwr_ack; + } =20 ret =3D scpsys_sram_enable(pd); if (ret < 0) @@ -274,12 +282,23 @@ static int scpsys_power_on(struct generic_pm_domain *= genpd) if (ret < 0) goto err_disable_sram; =20 + if (MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) { + ret =3D clk_bulk_prepare_enable(pd->num_subsys_clks, + pd->subsys_clks); + if (ret) + goto err_enable_bus_protect; + } + return 0; =20 +err_enable_bus_protect: + scpsys_bus_protect_enable(pd); err_disable_sram: scpsys_sram_disable(pd); err_disable_subsys_clks: - clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); + if (!MTK_SCPD_CAPS(pd, MTK_SCPD_STRICT_BUS_PROTECTION)) + clk_bulk_disable_unprepare(pd->num_subsys_clks, + pd->subsys_clks); err_pwr_ack: clk_bulk_disable_unprepare(pd->num_clks, pd->clks); err_reg: diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/m= tk-pm-domains.h index 17c033217704..aaba5e6b0536 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -12,6 +12,7 @@ #define MTK_SCPD_ALWAYS_ON BIT(5) #define MTK_SCPD_EXT_BUCK_ISO BIT(6) #define MTK_SCPD_HAS_INFRA_NAO BIT(7) +#define MTK_SCPD_STRICT_BUS_PROTECTION BIT(8) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) =20 #define SPM_VDE_PWR_CON 0x0210 @@ -107,7 +108,7 @@ struct scpsys_domain_data { u32 sram_pdn_ack_bits; int ext_buck_iso_offs; u32 ext_buck_iso_mask; - u8 caps; + u16 caps; const struct scpsys_bus_prot_data bp_cfg[SPM_MAX_BUS_PROT_DATA]; int pwr_sta_offs; int pwr_sta2nd_offs; --=20 2.40.1 From nobody Fri Sep 20 13:38:22 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFF55C001B0 for ; Thu, 13 Jul 2023 15:05:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232840AbjGMPFB (ORCPT ); Thu, 13 Jul 2023 11:05:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232672AbjGMPEj (ORCPT ); Thu, 13 Jul 2023 11:04:39 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 736D52712 for ; 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Thu, 13 Jul 2023 08:04:34 -0700 (PDT) From: Markus Schneider-Pargmann To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger Cc: Chun-Jie Chen , AngeloGioacchino Del Regno , Tinghan Shen , Fabien Parent , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Fabien Parent , Markus Schneider-Pargmann , Alexandre Mergnat Subject: [PATCH v7 8/8] soc: mediatek: pm-domains: Add support for MT8365 Date: Thu, 13 Jul 2023 17:04:14 +0200 Message-Id: <20230713150414.891893-9-msp@baylibre.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713150414.891893-1-msp@baylibre.com> References: <20230713150414.891893-1-msp@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fabien Parent Add the needed board data to support MT8365 SoC. Signed-off-by: Fabien Parent Signed-off-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat --- drivers/soc/mediatek/mt8365-pm-domains.h | 197 +++++++++++++++++++++++ drivers/soc/mediatek/mtk-pm-domains.c | 5 + include/linux/soc/mediatek/infracfg.h | 41 +++++ 3 files changed, 243 insertions(+) create mode 100644 drivers/soc/mediatek/mt8365-pm-domains.h diff --git a/drivers/soc/mediatek/mt8365-pm-domains.h b/drivers/soc/mediate= k/mt8365-pm-domains.h new file mode 100644 index 000000000000..3d83d49eaa7c --- /dev/null +++ b/drivers/soc/mediatek/mt8365-pm-domains.h @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8365_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT8365_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include + +/* + * MT8365 power domain support + */ + +#define MT8365_BUS_PROT_INFRA_WR_TOPAXI(_mask) \ + BUS_PROT_WR(INFRA, _mask, \ + MT8365_INFRA_TOPAXI_PROTECTEN_SET, \ + MT8365_INFRA_TOPAXI_PROTECTEN_CLR, \ + MT8365_INFRA_TOPAXI_PROTECTEN_STA1) + +#define MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(_mask) \ + BUS_PROT_WR(INFRA, _mask, \ + MT8365_INFRA_TOPAXI_PROTECTEN_1_SET, \ + MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR, \ + MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1) + +#define MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(port) \ + BUS_PROT_WR(SMI, BIT(port), \ + MT8365_SMI_COMMON_CLAMP_EN_SET, \ + MT8365_SMI_COMMON_CLAMP_EN_CLR, \ + MT8365_SMI_COMMON_CLAMP_EN) + +#define MT8365_BUS_PROT_WAY_EN(_set_mask, _set, _sta_mask, _sta) \ + _BUS_PROT(_set_mask, _set, _set, _sta_mask, _sta, \ + BUS_PROT_COMPONENT_INFRA | \ + BUS_PROT_STA_COMPONENT_INFRA_NAO | \ + BUS_PROT_INVERTED | \ + BUS_PROT_REG_UPDATE) + +static const struct scpsys_domain_data scpsys_domain_data_mt8365[] =3D { + [MT8365_POWER_DOMAIN_MM] =3D { + .name =3D "mm", + .sta_mask =3D PWR_STATUS_DISP, + .ctl_offs =3D 0x30c, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_cfg =3D { + MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( + MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 | + MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1), + MT8365_BUS_PROT_INFRA_WR_TOPAXI( + MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 | + MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 | + MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 | + MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1), + MT8365_BUS_PROT_WAY_EN( + MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S, + MT8365_INFRA_TOPAXI_SI0_CTL, + MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED, + MT8365_INFRA_NAO_TOPAXI_SI0_STA), + MT8365_BUS_PROT_WAY_EN( + MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1, + MT8365_INFRA_TOPAXI_SI2_CTL, + MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED, + MT8365_INFRA_NAO_TOPAXI_SI2_STA), + MT8365_BUS_PROT_INFRA_WR_TOPAXI( + MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S), + }, + .caps =3D MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_INFRA_NAO, + }, + [MT8365_POWER_DOMAIN_VENC] =3D { + .name =3D "venc", + .sta_mask =3D PWR_STATUS_VENC, + .ctl_offs =3D 0x0304, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_cfg =3D { + MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(1), + }, + }, + [MT8365_POWER_DOMAIN_AUDIO] =3D { + .name =3D "audio", + .sta_mask =3D PWR_STATUS_AUDIO, + .ctl_offs =3D 0x0314, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(12, 8), + .sram_pdn_ack_bits =3D GENMASK(17, 13), + .bp_cfg =3D { + MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( + MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO | + MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M), + }, + .caps =3D MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8365_POWER_DOMAIN_CONN] =3D { + .name =3D "conn", + .sta_mask =3D PWR_STATUS_CONN, + .ctl_offs =3D 0x032c, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D 0, + .sram_pdn_ack_bits =3D 0, + .bp_cfg =3D { + MT8365_BUS_PROT_INFRA_WR_TOPAXI( + MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB), + MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( + MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST), + MT8365_BUS_PROT_INFRA_WR_TOPAXI( + MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB), + MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( + MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV), + }, + .caps =3D MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8365_POWER_DOMAIN_MFG] =3D { + .name =3D "mfg", + .sta_mask =3D PWR_STATUS_MFG, + .ctl_offs =3D 0x0338, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(9, 8), + .sram_pdn_ack_bits =3D GENMASK(13, 12), + .bp_cfg =3D { + MT8365_BUS_PROT_INFRA_WR_TOPAXI(BIT(25)), + MT8365_BUS_PROT_INFRA_WR_TOPAXI( + MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 | + MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG), + }, + }, + [MT8365_POWER_DOMAIN_CAM] =3D { + .name =3D "cam", + .sta_mask =3D BIT(25), + .ctl_offs =3D 0x0344, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(9, 8), + .sram_pdn_ack_bits =3D GENMASK(13, 12), + .bp_cfg =3D { + MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( + MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST), + MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(2), + }, + }, + [MT8365_POWER_DOMAIN_VDEC] =3D { + .name =3D "vdec", + .sta_mask =3D BIT(31), + .ctl_offs =3D 0x0370, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_cfg =3D { + MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(3), + }, + }, + [MT8365_POWER_DOMAIN_APU] =3D { + .name =3D "apu", + .sta_mask =3D BIT(16), + .ctl_offs =3D 0x0378, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(14, 8), + .sram_pdn_ack_bits =3D GENMASK(21, 15), + .bp_cfg =3D { + MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( + MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP | + MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST), + MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(4), + }, + }, + [MT8365_POWER_DOMAIN_DSP] =3D { + .name =3D "dsp", + .sta_mask =3D BIT(17), + .ctl_offs =3D 0x037C, + .pwr_sta_offs =3D 0x0180, + .pwr_sta2nd_offs =3D 0x0184, + .sram_pdn_bits =3D GENMASK(11, 8), + .sram_pdn_ack_bits =3D GENMASK(15, 12), + .bp_cfg =3D { + MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( + MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB | + MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M | + MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S), + }, + .caps =3D MTK_SCPD_ACTIVE_WAKEUP, + }, +}; + +static const struct scpsys_soc_data mt8365_scpsys_data =3D { + .domains_data =3D scpsys_domain_data_mt8365, + .num_domains =3D ARRAY_SIZE(scpsys_domain_data_mt8365), +}; + +#endif /* __SOC_MEDIATEK_MT8365_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/m= tk-pm-domains.c index cf45e29420b2..4215ddef6d36 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -24,6 +24,7 @@ #include "mt8188-pm-domains.h" #include "mt8192-pm-domains.h" #include "mt8195-pm-domains.h" +#include "mt8365-pm-domains.h" =20 #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC @@ -652,6 +653,10 @@ static const struct of_device_id scpsys_of_match[] =3D= { .compatible =3D "mediatek,mt8195-power-controller", .data =3D &mt8195_scpsys_data, }, + { + .compatible =3D "mediatek,mt8365-power-controller", + .data =3D &mt8365_scpsys_data, + }, { } }; =20 diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/medi= atek/infracfg.h index 07f67b3d8e97..6c6cccc848f4 100644 --- a/include/linux/soc/mediatek/infracfg.h +++ b/include/linux/soc/mediatek/infracfg.h @@ -2,6 +2,47 @@ #ifndef __SOC_MEDIATEK_INFRACFG_H #define __SOC_MEDIATEK_INFRACFG_H =20 +#define MT8365_INFRA_TOPAXI_PROTECTEN_STA1 0x228 +#define MT8365_INFRA_TOPAXI_PROTECTEN_SET 0x2a0 +#define MT8365_INFRA_TOPAXI_PROTECTEN_CLR 0x2a4 +#define MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 BIT(1) +#define MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 BIT(2) +#define MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S BIT(6) +#define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 BIT(10) +#define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1 BIT(11) +#define MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB BIT(13) +#define MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB BIT(14) +#define MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 BIT(21) +#define MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG BIT(22) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1 0x258 +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_SET 0x2a8 +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR 0x2ac +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP BIT(2) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 BIT(16) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1 BIT(17) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST BIT(18) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST BIT(19) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST BIT(20) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV BIT(21) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB BIT(24) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO BIT(27) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M BIT(28) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M BIT(30) +#define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S BIT(31) + +#define MT8365_INFRA_NAO_TOPAXI_SI0_STA 0x0 +#define MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED BIT(24) +#define MT8365_INFRA_NAO_TOPAXI_SI2_STA 0x28 +#define MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED BIT(14) +#define MT8365_INFRA_TOPAXI_SI0_CTL 0x200 +#define MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S BIT(6) +#define MT8365_INFRA_TOPAXI_SI2_CTL 0x234 +#define MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1 BIT(5) + +#define MT8365_SMI_COMMON_CLAMP_EN 0x3c0 +#define MT8365_SMI_COMMON_CLAMP_EN_SET 0x3c4 +#define MT8365_SMI_COMMON_CLAMP_EN_CLR 0x3c8 + #define MT8195_TOP_AXI_PROT_EN_STA1 0x228 #define MT8195_TOP_AXI_PROT_EN_1_STA1 0x258 #define MT8195_TOP_AXI_PROT_EN_SET 0x2a0 --=20 2.40.1