From nobody Sat Feb 7 21:30:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22C96EB64DA for ; Wed, 12 Jul 2023 16:12:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233443AbjGLQL6 (ORCPT ); Wed, 12 Jul 2023 12:11:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46076 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231723AbjGLQLz (ORCPT ); Wed, 12 Jul 2023 12:11:55 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 766EC2697 for ; Wed, 12 Jul 2023 09:11:29 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1b89b75dc1cso6570825ad.1 for ; Wed, 12 Jul 2023 09:11:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1689178288; x=1691770288; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mmAdt18zp6t4Zhgiqm8zC0JEDWTldiIyDdHXaTHo/h0=; b=kQkQUlSShEQrgDlX6aIxC7vQH9LcEtlGV0uGQCn6b057ZS+SXc6XNnSW8/ZN3WobJE pGekJOd/AaW89tvlhFIywJf2d99HhqH1Am/O0aszingM1caqHb/btaE+IFccIYRbSmag 5EFUc9uhQoisGTOVWtt2iJBhQWVoPZx7If0IS7eUanEi6trVA8tRHdFXsZdhRV5KK6Bk RyxNOlGCOU8Eg5VUdYs/xJEYLb6t9eNA4swZ5LwJcBtwp3lSfY895jeJu21rzNVly5jk oXW3QoE475K/klVUJXHXxZfjugv4/qMeWeRc2l6PJgF+6BBQWZP308x8O7cZyD5TUxTs QNuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689178288; x=1691770288; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mmAdt18zp6t4Zhgiqm8zC0JEDWTldiIyDdHXaTHo/h0=; b=kl5MiAtn8S5qyE/SuJXU4mn438PYpJcT+3I6UaEETP/JAPCQCdHJW1M38JYnnAlmLq 8FvnS/YKUMlIMvfOaA5uhNYmzPATzsULuttbSTFE2fAb5nqF3KWPiwkGIl9IVJvx5Tn0 8QoTImaQZfHcnQzVrefwUhwc4TCIg4qd8Kj9jSOZgY2dBa0ETLdXIzUkSlmfs6y3jlXh DvZHGRhxmdbKasPiPCHgOOuIZqlHSaq/HlmO/2DxIzFSMAzICVv22tNl9OWN6+ItIQqm ZVUIn7ZdGVz5h7O3QvfX17qR9qstJ9ObMVBsc/CvaO7IfvzUBlWAQ/ujRCZRMx9SXkaa 95nA== X-Gm-Message-State: ABy/qLaFc0B5Y0fE1VlUHKgbcJmrFF8UmtPWIB6N16PhQ1F4/gtO4zeW DmL4CPVuLZ5Z8SbOkxaxydmYNg== X-Google-Smtp-Source: APBJJlHAwaBqYGiIZmjm5nXgjudHpZLu+aIM3EZuURNmVtDG80/PswBUaHV1/MXHja9nt8wuObYMWQ== X-Received: by 2002:a17:902:ea02:b0:1b9:d335:1b7d with SMTP id s2-20020a170902ea0200b001b9d3351b7dmr3023742plg.6.1689178288003; Wed, 12 Jul 2023 09:11:28 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.82.173]) by smtp.gmail.com with ESMTPSA id bc2-20020a170902930200b001b9f032bb3dsm3811650plb.3.2023.07.12.09.11.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jul 2023 09:11:27 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra Cc: Palmer Dabbelt , Paul Walmsley , Andrew Jones , Heiko Stuebner , Samuel Ortiz , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 7/7] RISC-V: KVM: Allow Zvb* and Zvk* extensions for Guest/VM Date: Wed, 12 Jul 2023 21:40:47 +0530 Message-Id: <20230712161047.1764756-8-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230712161047.1764756-1-apatel@ventanamicro.com> References: <20230712161047.1764756-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zvb* and Zvk* extensions for Guest/VM. Signed-off-by: Anup Patel --- arch/riscv/include/uapi/asm/kvm.h | 9 +++++++++ arch/riscv/kvm/vcpu_onereg.c | 18 ++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index 182e7bdfc842..3929d3a7bd24 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -141,6 +141,15 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZKSED, KVM_RISCV_ISA_EXT_ZKSH, KVM_RISCV_ISA_EXT_ZKT, + KVM_RISCV_ISA_EXT_ZVBB, + KVM_RISCV_ISA_EXT_ZVBC, + KVM_RISCV_ISA_EXT_ZVKG, + KVM_RISCV_ISA_EXT_ZVKNED, + KVM_RISCV_ISA_EXT_ZVKNHA, + KVM_RISCV_ISA_EXT_ZVKNHB, + KVM_RISCV_ISA_EXT_ZVKSED, + KVM_RISCV_ISA_EXT_ZVKSH, + KVM_RISCV_ISA_EXT_ZVKT, KVM_RISCV_ISA_EXT_MAX, }; =20 diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 08e077260214..89efa5e3e3f1 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -59,6 +59,15 @@ static const unsigned long kvm_isa_ext_arr[] =3D { KVM_ISA_EXT_ARR(ZKSED), KVM_ISA_EXT_ARR(ZKSH), KVM_ISA_EXT_ARR(ZKT), + KVM_ISA_EXT_ARR(ZVBB), + KVM_ISA_EXT_ARR(ZVBC), + KVM_ISA_EXT_ARR(ZVKG), + KVM_ISA_EXT_ARR(ZVKNED), + KVM_ISA_EXT_ARR(ZVKNHA), + KVM_ISA_EXT_ARR(ZVKNHB), + KVM_ISA_EXT_ARR(ZVKSED), + KVM_ISA_EXT_ARR(ZVKSH), + KVM_ISA_EXT_ARR(ZVKT), }; =20 static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext) @@ -117,6 +126,15 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigne= d long ext) case KVM_RISCV_ISA_EXT_ZKSED: case KVM_RISCV_ISA_EXT_ZKSH: case KVM_RISCV_ISA_EXT_ZKT: + case KVM_RISCV_ISA_EXT_ZVBB: + case KVM_RISCV_ISA_EXT_ZVBC: + case KVM_RISCV_ISA_EXT_ZVKG: + case KVM_RISCV_ISA_EXT_ZVKNED: + case KVM_RISCV_ISA_EXT_ZVKNHA: + case KVM_RISCV_ISA_EXT_ZVKNHB: + case KVM_RISCV_ISA_EXT_ZVKSED: + case KVM_RISCV_ISA_EXT_ZVKSH: + case KVM_RISCV_ISA_EXT_ZVKT: return false; default: break; --=20 2.34.1