From nobody Sat Feb 7 15:40:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DE4FC001B0 for ; Wed, 12 Jul 2023 08:41:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232767AbjGLIlv (ORCPT ); Wed, 12 Jul 2023 04:41:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232008AbjGLIlo (ORCPT ); Wed, 12 Jul 2023 04:41:44 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E601A2 for ; Wed, 12 Jul 2023 01:41:42 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-3fbf1b82dc7so68407215e9.2 for ; Wed, 12 Jul 2023 01:41:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1689151300; x=1691743300; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MwVmOO+8zu0+umd4x+8Tiq0imXaPOfW0Ttf7ThfdmAQ=; b=Lk+iEr5exl+WAIOetqNerHgEnWpVsnw0s/Md0KlTTXqxPaWWvnQzstvYlOZhhXvE96 8dr/r6DterFNCaquw/O5q83reNwFEg5JZDzmv2ubocDSARnRuVm3YPC6KhivZAApgavH nCE8+S0WkyVK4q99VBRu/d0yRibTRzpWWESiXwDxUn/mXR9WhLMLgR+DiP2titQk468N jl+hbLwHIsTs2+THMeXDez38EMmvl/Pc9KzBiwt0Tg2l0Jgmvxe4WdWZeNznJVCAR5za LDV0rP2BBBDiGBT3tFVOpz/ds8cxQAGaSpghqhpBmOD3Je98JNOnEmHeGhvfm3UitHrw ULtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689151300; x=1691743300; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MwVmOO+8zu0+umd4x+8Tiq0imXaPOfW0Ttf7ThfdmAQ=; b=igAlmEMEtqeSb4asiSVa467Kjy6r1UuKWbD3/gs2L1r2ICRw3U6BDkKSrADBwKCL1O Gf/XTKCjD0avc97AZKS1hzWJmvgmbBaWKHdLVXlr2qAjSntzRjvHSAq3U2nT4noXMXWO 7oINdAblJhV7FOJhTVvRAO/xGI2AYh7Wz76JG4vTyjyoNe5g/s2b47NQ67y/YN6p2HYx 4P9ZAxiTErgxmaM+c7Wi1eZ6zrNk5UCpBY1jd4MqufIXqmHJiUmVDjuXHvBHaO9gSqBa qK9GNuQpNMv4oAEiV68leUSJDFd3ga6uQcLZlcCNkctevavAwmnwm4Y/MMHXIw08ZrpH 9mnQ== X-Gm-Message-State: ABy/qLZ1ngix6M3nnn5+GIIYE2/KEsuZWkSq4EFakbrbRmcZsJp7dpua YDuPAF824d17z7zPuvhMmWWwDA== X-Google-Smtp-Source: APBJJlHeXQQGzIzDvfFmNDNGDs4DJEMJhJOFbTFM+a1ROVJJGd8YW3Q5SHb8WGx5KjdxkXHBWA2eOA== X-Received: by 2002:a5d:674b:0:b0:312:8e63:71c with SMTP id l11-20020a5d674b000000b003128e63071cmr18335292wrw.32.1689151300275; Wed, 12 Jul 2023 01:41:40 -0700 (PDT) Received: from vermeer.tail79c99.ts.net ([2a01:cb1d:81a9:dd00:b570:b34c:ffd4:c805]) by smtp.gmail.com with ESMTPSA id z13-20020adfe54d000000b003143ac73fd0sm4496122wrm.1.2023.07.12.01.41.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jul 2023 01:41:39 -0700 (PDT) From: Samuel Ortiz To: Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org Cc: "Hongren (Zenithal) Zheng" , linux@rivosinc.com, Conor Dooley , Andrew Jones , Heiko Stuebner , Anup Patel , linux-kernel@vger.kernel.org, Guo Ren , Atish Patra , Samuel Ortiz , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Evan Green , devicetree@vger.kernel.org, sorear@fastmail.com, Jiatai He Subject: [PATCH v4 1/4] RISC-V: Add Bitmanip/Scalar Crypto parsing from DT Date: Wed, 12 Jul 2023 10:41:17 +0200 Message-ID: <20230712084134.1648008-2-sameo@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230712084134.1648008-1-sameo@rivosinc.com> References: <20230712084134.1648008-1-sameo@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "Hongren (Zenithal) Zheng" Parse Zb/Zk related string from DT and output them to cpuinfo. It is worth noting that the Scalar Crypto extension defines "zk" as a shorthand for the Zkn, Zkr and Zkt extensions. Since the Zkn one also implies the Zbkb, Zbkc and Zbkx extensions, simply passing the valid "zk" extension name through a DT will enable all of the Zbkb, Zbkc, Zbkx, Zkn, Zkr and Zkt extensions. Also, since there currently is no mechanism to merge all enabled extensions, the generated cpuinfo output could be relatively large. For example, setting the "riscv,isa" DT property to "rv64imafdc_zk_zks" will generate the following cpuinfo output: "rv64imafdc_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed_zksh_zkt". Tested-by: Jiatai He Tested-by: Heiko Stuebner Reviewed-by: Evan Green Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Signed-off-by: Hongren (Zenithal) Zheng Signed-off-by: Samuel Ortiz --- arch/riscv/include/asm/hwcap.h | 11 +++++++++++ arch/riscv/kernel/cpu.c | 11 +++++++++++ arch/riscv/kernel/cpufeature.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 52 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index f041bfa7f6a0..b80ca6e77088 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -53,6 +53,17 @@ #define RISCV_ISA_EXT_ZICSR 40 #define RISCV_ISA_EXT_ZIFENCEI 41 #define RISCV_ISA_EXT_ZIHPM 42 +#define RISCV_ISA_EXT_ZBC 43 +#define RISCV_ISA_EXT_ZBKB 44 +#define RISCV_ISA_EXT_ZBKC 45 +#define RISCV_ISA_EXT_ZBKX 46 +#define RISCV_ISA_EXT_ZKND 47 +#define RISCV_ISA_EXT_ZKNE 48 +#define RISCV_ISA_EXT_ZKNH 49 +#define RISCV_ISA_EXT_ZKR 50 +#define RISCV_ISA_EXT_ZKSED 51 +#define RISCV_ISA_EXT_ZKSH 52 +#define RISCV_ISA_EXT_ZKT 53 =20 #define RISCV_ISA_EXT_MAX 64 #define RISCV_ISA_EXT_NAME_LEN_MAX 32 diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index a2fc952318e9..10524322a4c0 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -215,7 +215,18 @@ static struct riscv_isa_ext_data isa_ext_arr[] =3D { __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), + __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), + __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB), + __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC), + __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX), __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), + __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND), + __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE), + __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH), + __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR), + __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), + __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), + __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index bdcf460ea53d..9a872a2007a5 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -309,10 +309,40 @@ void __init riscv_fill_hwcap(void) SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA); SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB); + SET_ISA_EXT_MAP("zbc", RISCV_ISA_EXT_ZBC); + SET_ISA_EXT_MAP("zbkb", RISCV_ISA_EXT_ZBKB); + SET_ISA_EXT_MAP("zbkc", RISCV_ISA_EXT_ZBKC); + SET_ISA_EXT_MAP("zbkx", RISCV_ISA_EXT_ZBKX); SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS); SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ); SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZBKB); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZBKC); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZBKX); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKND); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKNE); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKNH); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKR); + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKT); + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZBKB); + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZBKC); + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZBKX); + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZKND); + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZKNE); + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZKNH); + SET_ISA_EXT_MAP("zknd", RISCV_ISA_EXT_ZKND); + SET_ISA_EXT_MAP("zkne", RISCV_ISA_EXT_ZKNE); + SET_ISA_EXT_MAP("zknh", RISCV_ISA_EXT_ZKNH); + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZBKB); + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZBKC); + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZBKX); + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZKSED); + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZKSH); + SET_ISA_EXT_MAP("zksed", RISCV_ISA_EXT_ZKSED); + SET_ISA_EXT_MAP("zksh", RISCV_ISA_EXT_ZKSH); + SET_ISA_EXT_MAP("zkr", RISCV_ISA_EXT_ZKR); + SET_ISA_EXT_MAP("zkt", RISCV_ISA_EXT_ZKT); } #undef SET_ISA_EXT_MAP } --=20 2.41.0 From nobody Sat Feb 7 15:40:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8903CEB64D9 for ; Wed, 12 Jul 2023 08:41:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230399AbjGLIly (ORCPT ); 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Wed, 12 Jul 2023 01:41:42 -0700 (PDT) From: Samuel Ortiz To: Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org Cc: Samuel Ortiz , linux@rivosinc.com, Conor Dooley , Andrew Jones , Heiko Stuebner , Anup Patel , linux-kernel@vger.kernel.org, "Hongren (Zenithal) Zheng" , Guo Ren , Atish Patra , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Evan Green , devicetree@vger.kernel.org, sorear@fastmail.com Subject: [PATCH v4 2/4] dt-bindings: riscv: Document the 1.0 scalar cryptography extensions Date: Wed, 12 Jul 2023 10:41:18 +0200 Message-ID: <20230712084134.1648008-3-sameo@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230712084134.1648008-1-sameo@rivosinc.com> References: <20230712084134.1648008-1-sameo@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The RISC-V cryptography extensions define a set of instructions, CSR definitions, architectural interfaces and also extension shorthands for running scalar and vector based cryptography operations on RISC-V systems. This documents all the dt-bindings for the scalar cryptography extensions, including the Zk, Zkn and Zks shorthands. Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Signed-off-by: Samuel Ortiz --- .../devicetree/bindings/riscv/extensions.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index cc1f546fdbdc..3d3d0d2f71e7 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -190,6 +190,24 @@ properties: instructions as ratified at commit 6d33919 ("Merge pull reques= t #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. =20 + - const: zbkb + description: | + The standard Zbkb cryptography extension for bit-manipulation + instructions, as ratified at commit 73de909 + ("Zvk: Update AES instruction specs") of riscv-crypto. + + - const: zbkc + description: | + The standard Zbkc cryptography extension for carry-less multip= ly + instructions, as ratified at commit 73de909 + ("Zvk: Update AES instruction specs") of riscv-crypto. + + - const: zbkx + description: | + The standard Zbkx cryptography extension for crossbar permutat= ion + instructions, as ratified at commit 73de909 + ("Zvk: Update AES instruction specs") of riscv-crypto. + - const: zicbom description: The standard Zicbom extension for base cache management operat= ions as @@ -240,6 +258,75 @@ properties: ratified in the 20191213 version of the unprivileged ISA specification. =20 + - const: zk + description: | + The standard Zk cryptography extension is a shorthand for the + union of the Zkn, Zkr and Zkt cryptography extensions, as rati= fied + at commit 73de909 ("Zvk: Update AES instruction specs") of + riscv-crypto. + + - const: zkn + description: | + The standard Zkn cryptography extension covers the NIST algori= thm + suite that other cryptography extensions support. It is the un= ion of + the Zbkb, Zbkc, Zbkx, Zknd, Zkne and Zknh extensions, as ratif= ied at + commit 73de909 ("Zvk: Update AES instruction specs") of riscv-= crypto. + + - const: zknd + description: | + The standard Zknd cryptography extension for AES block cipher + decryption acceleration instructions, as ratified at commit 73= de909 + ("Zvk: Update AES instruction specs") of riscv-crypto. + + - const: zkne + description: | + The standard Zkne cryptography extension for AES block cipher + encryption acceleration instructions, as ratified at commit 73= de909 + ("Zvk: Update AES instruction specs") of riscv-crypto. + + - const: zknh + description: | + The standard Zknh cryptography extension for SHA2 hash algorit= hm + functions acceleration instructions as ratified at commit 73de= 909 + ("Zvk: Update AES instruction specs") of riscv-crypto. + + - const: zkr + description: | + The standard Zkr cryptography extension for the entropy source= CSR + definitions, as ratified at commit 73de909 + ("Zvk: Update AES instruction specs") of riscv-crypto. + Systems with the Zkr extension enabled must set the MSECCFG SS= EED + bit to 1 in order for the Linux kernel to access the SEED CSR. + As userspace access to the entropy source is usually carefully + controlled and exclusively managed by the Linux kernel, M-mode + should set USEED to 0. + + - const: zks + description: | + The standard Zks cryptography extension covers the ShangMi alg= orithm + suite that other cryptography extensions support. It is the un= ion of + the Zbkb, Zbkc, Zbkx, Zksed and Zksh extensions, as ratified at + commit 73de909 ("Zvk: Update AES instruction specs") of riscv-= crypto. + + - const: zksed + description: | + The standard Zksed cryptography extension for SM4 block cipher + acceleration instructions, as ratified at commit 73de909 + ("Zvk: Update AES instruction specs") of riscv-crypto. + + - const: zksh + description: | + The standard Zksh cryptography extension for SM3 hash algorithm + funstions acceleration instructions, as ratified at commit 73d= e909 + ("Zvk: Update AES instruction specs") of riscv-crypto. + + - const: zkt + description: | + The standard Zkt cryptography extension for data independent + execution latency attestation, for a safe subset of instructio= ns, + as ratified at commit 73de909 ("Zvk: Update AES instruction sp= ecs") + of riscv-crypto. + - const: ztso description: The standard Ztso extension for total store ordering, as ratif= ied --=20 2.41.0 From nobody Sat Feb 7 15:40:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 428B2EB64DA for ; Wed, 12 Jul 2023 08:41:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232351AbjGLIl4 (ORCPT ); Wed, 12 Jul 2023 04:41:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231891AbjGLIlr (ORCPT ); Wed, 12 Jul 2023 04:41:47 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD80EB7 for ; Wed, 12 Jul 2023 01:41:45 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-3159da54e95so2927187f8f.3 for ; Wed, 12 Jul 2023 01:41:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1689151304; x=1691743304; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v1czZOouN4R8rvhecyOdxS/fUEZ430UatGfS2CvREC4=; b=gwIEGJSQC2lc733QUx0mL7EQanAHivGO25GBSLLMgQRoYPRXALoEAYGOLEivj17mmI Nj4adO3RRLQUuocWBGImYB6bGtYnORM9NlRikeifzi0PQ0IL1dGto2Q2nnMlqxqS7sSY /tiCrbAcHJHjDDEqAycahauO/NFvxTeu1wiIo6sKj1MQQElsuFtRfiCMi/z7JDe6TuTk uKm8BiXX0T2jk24G4j1SqFYu3QCPjEyUSCW5PTT9HPR2Fx3KCavu9WNXTJfq2LZ+GIrJ BRO4mnmHVIfy31z+Cq4z1XI2Z8QYYQ/2mKSBLUY16RN5ZOn6IK9aSxkzbWIt0AQOqrhD U+OQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689151304; x=1691743304; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v1czZOouN4R8rvhecyOdxS/fUEZ430UatGfS2CvREC4=; b=Rv6+vuBE+p0i5PyL5d/FQDB2x2Mp6pXVud4hmwQkxxKimpONlhnWjVP9zF32lom8Ko MhNNbWpbqjEuNC4dPaPYxaqQV6uP+3N/uSLmV1qYFg8x/EP0n36DOMcguyuyEYzVdDPF 5lWjAEGX0OwORvn1XPeVR/Z97NCozDWCB0yC6hs2HxqshoutKAjvMjvIdzzGtiT9JOdc 059wQ+wtc1rYdQtvX18SwnK+F+Zzt6YiHYLZzSyThWUI814UeXg82+1INYJtv/YCB0cm koH2LWOsLb8ci0q/CsaDr7zhVc+fEis6qy21sdvVmscZOgXPpxJpiusOk0uH3CH039Lz EuEA== X-Gm-Message-State: ABy/qLZ+GO7xk8U9CcqK/EryiQxz/gsiTni5+OjQyPeClRyGpblALZn4 y+qOjng3RbjZg9WigmQBckXN/w== X-Google-Smtp-Source: APBJJlGg+rsqRu4BTGL/I9uL08XG6vx+bsh+ed8/X0b+TdypKH3GEvF2pa6eJu2t24MkEFtNLOKYDQ== X-Received: by 2002:adf:e7c1:0:b0:314:1270:8fc with SMTP id e1-20020adfe7c1000000b00314127008fcmr17540498wrn.0.1689151304363; Wed, 12 Jul 2023 01:41:44 -0700 (PDT) Received: from vermeer.tail79c99.ts.net ([2a01:cb1d:81a9:dd00:b570:b34c:ffd4:c805]) by smtp.gmail.com with ESMTPSA id z13-20020adfe54d000000b003143ac73fd0sm4496122wrm.1.2023.07.12.01.41.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jul 2023 01:41:44 -0700 (PDT) From: Samuel Ortiz To: Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org Cc: Samuel Ortiz , linux@rivosinc.com, Conor Dooley , Andrew Jones , Heiko Stuebner , Anup Patel , linux-kernel@vger.kernel.org, "Hongren (Zenithal) Zheng" , Guo Ren , Atish Patra , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Evan Green , devicetree@vger.kernel.org, sorear@fastmail.com Subject: [PATCH v4 3/4] RISC-V: hwprobe: Expose Zbc and the scalar crypto extensions Date: Wed, 12 Jul 2023 10:41:19 +0200 Message-ID: <20230712084134.1648008-4-sameo@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230712084134.1648008-1-sameo@rivosinc.com> References: <20230712084134.1648008-1-sameo@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Zbc was missing from a previous Bit-Manipulation extension hwprobe patch. Add all scalar crypto extensions bits, and define a macro for setting the hwprobe key/pair in a more readable way. Reviewed-by: Evan Green Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Signed-off-by: Samuel Ortiz --- Documentation/riscv/hwprobe.rst | 35 ++++++++++++++++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 11 ++++++++ arch/riscv/kernel/sys_riscv.c | 36 ++++++++++++++++----------- 3 files changed, 68 insertions(+), 14 deletions(-) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.= rst index 19165ebd82ba..105b59e2e780 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -72,11 +72,46 @@ The following keys are defined: extensions. =20 * :c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as d= efined + in version 1.0 of the Bit-Manipulation ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZBC`: The Zbc extension is supported, as d= efined in version 1.0 of the Bit-Manipulation ISA extensions. =20 * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as d= efined in version 1.0 of the Bit-Manipulation ISA extensions. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZBKB`: The Zbkb extension is supported, as= defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZBKC`: The Zbkc extension is supported, as= defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZBKX`: The Zbkx extension is supported, as= defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKND`: The Zknd extension is supported, as= defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKNE`: The Zkne extension is supported, as= defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKNH`: The Zknh extension is supported, as= defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKR`: The Zkr extension is supported, as d= efined + in version 1.0 of the Scalar Cryptography ISA extensions. Depending on= the + M-mode `mseccfg` CSR configuration, userspace may not be allowed to di= rectly + access the Zkr-defined `seed` CSR. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKSED`: The Zksed extension is supported, = as defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKSH`: The Zksh extension is supported, as= defined + in version 1.0 of the Scalar Cryptography ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZKT`: The Zkt extension is supported, as d= efined + in version 1.0 of the Scalar Cryptography ISA extensions. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 006bfb48343d..8357052061b3 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -29,6 +29,17 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZBA (1 << 3) #define RISCV_HWPROBE_EXT_ZBB (1 << 4) #define RISCV_HWPROBE_EXT_ZBS (1 << 5) +#define RISCV_HWPROBE_EXT_ZBC (1 << 6) +#define RISCV_HWPROBE_EXT_ZBKB (1 << 7) +#define RISCV_HWPROBE_EXT_ZBKC (1 << 8) +#define RISCV_HWPROBE_EXT_ZBKX (1 << 9) +#define RISCV_HWPROBE_EXT_ZKND (1 << 10) +#define RISCV_HWPROBE_EXT_ZKNE (1 << 11) +#define RISCV_HWPROBE_EXT_ZKNH (1 << 12) +#define RISCV_HWPROBE_EXT_ZKR (1 << 13) +#define RISCV_HWPROBE_EXT_ZKSED (1 << 14) +#define RISCV_HWPROBE_EXT_ZKSH (1 << 15) +#define RISCV_HWPROBE_EXT_ZKT (1 << 16) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 26ef5526bfb4..df15926196b6 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -145,20 +145,28 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pa= ir, for_each_cpu(cpu, cpus) { struct riscv_isainfo *isainfo =3D &hart_isa[cpu]; =20 - if (riscv_isa_extension_available(isainfo->isa, ZBA)) - pair->value |=3D RISCV_HWPROBE_EXT_ZBA; - else - missing |=3D RISCV_HWPROBE_EXT_ZBA; - - if (riscv_isa_extension_available(isainfo->isa, ZBB)) - pair->value |=3D RISCV_HWPROBE_EXT_ZBB; - else - missing |=3D RISCV_HWPROBE_EXT_ZBB; - - if (riscv_isa_extension_available(isainfo->isa, ZBS)) - pair->value |=3D RISCV_HWPROBE_EXT_ZBS; - else - missing |=3D RISCV_HWPROBE_EXT_ZBS; +#define SET_HWPROBE_EXT_PAIR(ext) \ + do { \ + if (riscv_isa_extension_available(isainfo->isa, ext)) \ + pair->value |=3D RISCV_HWPROBE_EXT_## ext; \ + else \ + missing |=3D RISCV_HWPROBE_EXT_## ext; \ + } while (false) \ + + SET_HWPROBE_EXT_PAIR(ZBA); + SET_HWPROBE_EXT_PAIR(ZBB); + SET_HWPROBE_EXT_PAIR(ZBC); + SET_HWPROBE_EXT_PAIR(ZBS); + SET_HWPROBE_EXT_PAIR(ZBKB); + SET_HWPROBE_EXT_PAIR(ZBKC); + SET_HWPROBE_EXT_PAIR(ZBKX); + SET_HWPROBE_EXT_PAIR(ZKND); + SET_HWPROBE_EXT_PAIR(ZKNE); + SET_HWPROBE_EXT_PAIR(ZKNH); + SET_HWPROBE_EXT_PAIR(ZKR); + SET_HWPROBE_EXT_PAIR(ZKSED); + SET_HWPROBE_EXT_PAIR(ZKSH); + SET_HWPROBE_EXT_PAIR(ZKT); } =20 /* Now turn off reporting features if any CPU is missing it. */ --=20 2.41.0 From nobody Sat Feb 7 15:40:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9C81EB64D9 for ; Wed, 12 Jul 2023 08:42:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232923AbjGLImB (ORCPT ); Wed, 12 Jul 2023 04:42:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232810AbjGLIlu (ORCPT ); Wed, 12 Jul 2023 04:41:50 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15D2DBE for ; Wed, 12 Jul 2023 01:41:48 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-3fb4146e8fcso2845835e9.0 for ; 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charset="utf-8" The Zkr extension is ratified and provides 16 bits of entropy seed when reading the SEED CSR. We can implement arch_get_random_seed_longs() by doing multiple csrrw to that CSR and filling an unsigned long with valid entropy bits. Acked-by: Conor Dooley Signed-off-by: Samuel Ortiz --- arch/riscv/include/asm/archrandom.h | 70 +++++++++++++++++++++++++++++ arch/riscv/include/asm/csr.h | 9 ++++ 2 files changed, 79 insertions(+) create mode 100644 arch/riscv/include/asm/archrandom.h diff --git a/arch/riscv/include/asm/archrandom.h b/arch/riscv/include/asm/a= rchrandom.h new file mode 100644 index 000000000000..38f3cced0fd0 --- /dev/null +++ b/arch/riscv/include/asm/archrandom.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Kernel interface for the RISCV arch_random_* functions + * + * Copyright (c) 2023 by Rivos Inc. + * + */ + +#ifndef ASM_RISCV_ARCHRANDOM_H +#define ASM_RISCV_ARCHRANDOM_H + +#include + +#define SEED_RETRY_LOOPS 100 + +static inline bool __must_check csr_seed_long(unsigned long *v) +{ + unsigned int retry =3D SEED_RETRY_LOOPS, valid_seeds =3D 0; + const int needed_seeds =3D sizeof(long) / sizeof(u16); + u16 *entropy =3D (u16 *)v; + + do { + /* + * The SEED CSR (0x015) must be accessed with a read-write + * instruction. + */ + unsigned long csr_seed =3D csr_swap(CSR_SEED, 0); + + switch (csr_seed & SEED_OPST_MASK) { + case SEED_OPST_ES16: + entropy[valid_seeds++] =3D csr_seed & SEED_ENTROPY_MASK; + if (valid_seeds =3D=3D needed_seeds) + return true; + break; + + case SEED_OPST_DEAD: + pr_err_once("archrandom: Unrecoverable error\n"); + return false; + + case SEED_OPST_BIST: + case SEED_OPST_WAIT: + default: + continue; + } + } while (--retry); + + return false; +} + +static inline size_t __must_check arch_get_random_longs(unsigned long *v, = size_t max_longs) +{ + return 0; +} + +static inline size_t __must_check arch_get_random_seed_longs(unsigned long= *v, size_t max_longs) +{ + if (!max_longs) + return 0; + + /* + * If Zkr is supported and csr_seed_long succeeds, we return one long + * worth of entropy. + */ + if (riscv_has_extension_likely(RISCV_ISA_EXT_ZKR) && csr_seed_long(v)) + return 1; + + return 0; +} + +#endif /* ASM_RISCV_ARCHRANDOM_H */ diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 7bac43a3176e..ff6f570487b9 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -391,6 +391,15 @@ #define CSR_VTYPE 0xc21 #define CSR_VLENB 0xc22 =20 +/* Scalar Crypto Extension - Entropy */ +#define CSR_SEED 0x015 +#define SEED_OPST_MASK _AC(0xC0000000, UL) +#define SEED_OPST_BIST _AC(0x00000000, UL) +#define SEED_OPST_WAIT _AC(0x40000000, UL) +#define SEED_OPST_ES16 _AC(0x80000000, UL) +#define SEED_OPST_DEAD _AC(0xC0000000, UL) +#define SEED_ENTROPY_MASK _AC(0xFFFF, UL) + #ifdef CONFIG_RISCV_M_MODE # define CSR_STATUS CSR_MSTATUS # define CSR_IE CSR_MIE --=20 2.41.0