From nobody Fri Sep 20 13:41:09 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39958EB64D9 for ; Tue, 11 Jul 2023 02:39:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230200AbjGKCjy (ORCPT ); Mon, 10 Jul 2023 22:39:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39362 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229886AbjGKCju (ORCPT ); Mon, 10 Jul 2023 22:39:50 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 916451A7; Mon, 10 Jul 2023 19:39:47 -0700 (PDT) X-UUID: 3111e5341f9411ee9cb5633481061a41-20230711 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=hSKenHqHk4SnkzETMsc5fhZOH0K/HS/Ef7FZfrvVwHQ=; b=dvJqSnDCORpPxFLOFCPcCw6aEdB/eOjrM9ELTUv2pmx1YLqRngVHFsqE6ul4FegMJv8KHTu6Dk8W2HIqyfmAh8gbKlKrpwDhmmqTuEuS3+lYaHuovIs+4ni7/0VxS97LDU9NBDZt25objclh588vuOixeuXz1P16bGHZnZC3XAE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.28,REQID:252ee88d-a008-4f97-9296-ea435f126a61,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:100 X-CID-INFO: VERSION:1.1.28,REQID:252ee88d-a008-4f97-9296-ea435f126a61,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:100 X-CID-META: VersionHash:176cd25,CLOUDID:f343160e-c22b-45ab-8a43-3004e9216b56,B ulkID:230711103943LRK1IHCB,BulkQuantity:0,Recheck:0,SF:28|17|19|48|38|29,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_SDM,TF_CID_SPAM_ASC,TF_CID_SPAM_FAS, TF_CID_SPAM_FSD X-UUID: 3111e5341f9411ee9cb5633481061a41-20230711 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 358432928; Tue, 11 Jul 2023 10:39:43 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 11 Jul 2023 10:39:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 11 Jul 2023 10:39:42 +0800 From: Jason-ch Chen To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , Chen-Yu Tsai , , , , , , jason-ch chen Subject: [PATCH v2 1/4] dt-bindings: arm: Add compatible for MediaTek MT8188 Date: Tue, 11 Jul 2023 10:39:26 +0800 Message-ID: <20230711023929.14381-2-jason-ch.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230711023929.14381-1-jason-ch.chen@mediatek.com> References: <20230711023929.14381-1-jason-ch.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: jason-ch chen This commit adds dt-binding documentation for the MediaTek MT8188 reference board. Signed-off-by: jason-ch chen Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Document= ation/devicetree/bindings/arm/mediatek.yaml index ae12b1cab9fb..4f4910d7a1e9 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -163,6 +163,10 @@ properties: - enum: - mediatek,mt8186-evb - const: mediatek,mt8186 + - items: + - enum: + - mediatek,mt8188-evb + - const: mediatek,mt8188 - items: - enum: - mediatek,mt8192-evb --=20 2.18.0 From nobody Fri Sep 20 13:41:09 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C16AEB64D9 for ; Tue, 11 Jul 2023 02:40:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230175AbjGKCkJ (ORCPT ); Mon, 10 Jul 2023 22:40:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230236AbjGKCkC (ORCPT ); Mon, 10 Jul 2023 22:40:02 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F219FE49; Mon, 10 Jul 2023 19:39:53 -0700 (PDT) X-UUID: 33cb2bd21f9411eeb20a276fd37b9834-20230711 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=E4JZXGwaqgiVk9kx6+mbob/fL/CJEEXGEBYv/EI5zPY=; b=rFkJmzeWXlQ4b67VN5UCrAIfnDSUwQcw9SQk86i9Iom/0tulqUNxvZiG4AMovSPAOPaGWptiorjqwZnWNQbN0lCaK00fLXQV8+PtdSuMRTxdVVOl+yv+gq5jwKhs6Dea6odhUEJPLj0p+xQ+0pjyF6oC2A/UtxkG+QQ1Zr+tuL4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.28,REQID:b66f351b-165d-4eaa-a3e8-51791c8aefeb,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:176cd25,CLOUDID:d7941568-314d-4083-81b6-6a74159151eb,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 33cb2bd21f9411eeb20a276fd37b9834-20230711 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1176753313; Tue, 11 Jul 2023 10:39:47 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 11 Jul 2023 10:39:46 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 11 Jul 2023 10:39:46 +0800 From: Jason-ch Chen To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , Chen-Yu Tsai , , , , , , jason-ch chen Subject: [PATCH v2 2/4] dt-bindings: arm: mediatek: Add mt8188 pericfg compatible Date: Tue, 11 Jul 2023 10:39:27 +0800 Message-ID: <20230711023929.14381-3-jason-ch.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230711023929.14381-1-jason-ch.chen@mediatek.com> References: <20230711023929.14381-1-jason-ch.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: jason-ch chen Add mt8188 pericfg compatible to binding document. Signed-off-by: jason-ch chen Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring --- .../devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericf= g.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.ya= ml index 26158d0d72f3..33c94c491828 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml @@ -28,6 +28,7 @@ properties: - mediatek,mt8173-pericfg - mediatek,mt8183-pericfg - mediatek,mt8186-pericfg + - mediatek,mt8188-pericfg - mediatek,mt8195-pericfg - mediatek,mt8516-pericfg - const: syscon --=20 2.18.0 From nobody Fri Sep 20 13:41:09 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC0BFEB64D9 for ; Tue, 11 Jul 2023 02:40:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230363AbjGKCkV (ORCPT ); Mon, 10 Jul 2023 22:40:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230195AbjGKCkD (ORCPT ); Mon, 10 Jul 2023 22:40:03 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08A43E60; Mon, 10 Jul 2023 19:39:56 -0700 (PDT) X-UUID: 34fd32341f9411eeb20a276fd37b9834-20230711 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=OOLKL9NJa0BDY/y3Vru7MJtGMdTwIgCiyE/U5u/zfS0=; b=nmgWow6hJkVWGY5IJo+w5gP8gt7AH1yVxA+qvLzRf5ls35C5Z7Xw8uAypgVZfv0ehaKD+JslRaPshSsrA7inX6QC2uRUxA7mPtl1o/pw80X4QdDudnfZOSUIhKdZKX5I9Q0YK1Esg4UuVO6kQ33wlE2wEfOSS4IRAUR+MTZ5tr0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.28,REQID:a298a13a-21c3-4df5-9926-0ac5bbbb0be2,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:176cd25,CLOUDID:6844160e-c22b-45ab-8a43-3004e9216b56,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 34fd32341f9411eeb20a276fd37b9834-20230711 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1968549299; Tue, 11 Jul 2023 10:39:49 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 11 Jul 2023 10:39:48 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 11 Jul 2023 10:39:48 +0800 From: Jason-ch Chen To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , Chen-Yu Tsai , , , , , , jason-ch chen Subject: [PATCH v2 3/4] dt-bindings: soc: mediatek: pwrap: Add compatible for MT8188 Date: Tue, 11 Jul 2023 10:39:28 +0800 Message-ID: <20230711023929.14381-4-jason-ch.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230711023929.14381-1-jason-ch.chen@mediatek.com> References: <20230711023929.14381-1-jason-ch.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: jason-ch chen Add MT8188 PMIC Wrapper compatible to binding document. Signed-off-by: jason-ch chen --- .../devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.= yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml index a06ac2177444..c2f22e7dbcfb 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml @@ -50,6 +50,11 @@ properties: - mediatek,mt8186-pwrap - mediatek,mt8195-pwrap - const: syscon + - items: + - enum: + - mediatek,mt8188-pwrap + - const: mediatek,mt8195-pwrap + - const: syscon =20 reg: minItems: 1 --=20 2.18.0 From nobody Fri Sep 20 13:41:09 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80396EB64D9 for ; Tue, 11 Jul 2023 02:40:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229831AbjGKCkR (ORCPT ); Mon, 10 Jul 2023 22:40:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229886AbjGKCkD (ORCPT ); Mon, 10 Jul 2023 22:40:03 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E409E5D; Mon, 10 Jul 2023 19:39:56 -0700 (PDT) X-UUID: 368a7e861f9411ee9cb5633481061a41-20230711 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=5WyZWDb9YBzdUJk6bBRkaipkBQcm9ATd33dfLIAZChE=; b=mlbafHrmjYPhJTow2yl8R+pmA8RgkVkrm/5FD6NCkNBnJkREZcVKgGsoI4vIRcxJflciq42ntg1oIVNdVlzMCUtErdXVvn848u18sdIc8E0IJyCXcq57n2txcaBRr+bce+DS4gTy42N14tN3cyhy59jmdsVi9MPLK2raJCEqMn8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.28,REQID:5b1130c6-af1a-4343-a20a-c5c2b5af80f3,IP:0,U RL:0,TC:0,Content:-5,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:-35 X-CID-META: VersionHash:176cd25,CLOUDID:6abfd9da-b4fa-43c8-9c3e-0d3fabd03ec0,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:2,IP:nil,UR L:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO,D KR:0,DKP:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 368a7e861f9411ee9cb5633481061a41-20230711 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 566681834; Tue, 11 Jul 2023 10:39:52 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 11 Jul 2023 10:39:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 11 Jul 2023 10:39:51 +0800 From: Jason-ch Chen To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , Chen-Yu Tsai , , , , , , jason-ch chen Subject: [PATCH v2 4/4] arm64: dts: Add MediaTek MT8188 dts and evaluation board and Makefile Date: Tue, 11 Jul 2023 10:39:29 +0800 Message-ID: <20230711023929.14381-5-jason-ch.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230711023929.14381-1-jason-ch.chen@mediatek.com> References: <20230711023929.14381-1-jason-ch.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: jason-ch chen MT8188 is a SoC based on 64bit ARMv8 architecture. It contains 6 CA55 and 2 CA78 cores. MT8188 share many HW IP with MT65xx series. We add basic chip support for MediaTek MT8188 on evaluation board. Signed-off-by: jason-ch chen --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8188-evb.dts | 401 +++++++++ arch/arm64/boot/dts/mediatek/mt8188.dtsi | 951 ++++++++++++++++++++ 3 files changed, 1353 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8188-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8188.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index c99c3372a4b5..9bd2324259a3 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -44,6 +44,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-kukui-krane-sku0.= dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-kukui-krane-sku176.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8186-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8188-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-asurada-hayato-r1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-asurada-spherion-r0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-evb.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8188-evb.dts b/arch/arm64/boot/= dts/mediatek/mt8188-evb.dts new file mode 100644 index 000000000000..6c1e829f7df6 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188-evb.dts @@ -0,0 +1,401 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + */ +/dts-v1/; +#include "mt8188.dtsi" +#include "mt6359.dtsi" + +/ { + model =3D "MediaTek MT8188 evaluation board"; + compatible =3D "mediatek,mt8188-evb", "mediatek,mt8188"; + + aliases { + serial0 =3D &uart0; + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + i2c4 =3D &i2c4; + i2c5 =3D &i2c5; + i2c6 =3D &i2c6; + mmc0 =3D &mmc0; + }; + + chosen: chosen { + stdout-path =3D "serial0:115200n8"; + kaslr-seed =3D <0 0>; + }; + + memory@40000000 { + device_type =3D "memory"; + reg =3D <0 0x40000000 0 0x80000000>; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + scp_mem_reserved: scp_mem_region { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x50000000 0 0x2900000>; + no-map; + }; + }; +}; + +&auxadc { + status =3D "okay"; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c4_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c5_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c6 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c6_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&mmc0 { + status =3D "okay"; + pinctrl-names =3D "default", "state_uhs"; + pinctrl-0 =3D <&mmc0_default_pins>; + pinctrl-1 =3D <&mmc0_uhs_pins>; + bus-width =3D <8>; + max-frequency =3D <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + supports-cqe; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay =3D <0x1481b>; + vmmc-supply =3D <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply =3D <&mt6359_vufs_ldo_reg>; + non-removable; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn33_2_bt_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcore_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +&mt6359_vufs_ldo_reg { + regulator-always-on; +}; + +&nor_flash { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&nor_pins_default>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <52000000>; + }; +}; + +&pio { + adsp_uart_pins: adsp-uart-pins { + pins-adsp-uart { + pinmux =3D , + ; + }; + }; + + i2c0_pins: i2c0-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D ; + }; + }; + + i2c1_pins: i2c1-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D ; + }; + }; + + i2c2_pins: i2c2-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D ; + }; + }; + + i2c3_pins: i2c3-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D ; + }; + }; + + i2c4_pins: i2c4-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D ; + }; + }; + + i2c5_pins: i2c5-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D ; + }; + }; + + i2c6_pins: i2c6-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D ; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D <6>; + bias-pull-up =3D ; + }; + + pins-clk { + pinmux =3D ; + drive-strength =3D <6>; + bias-pull-down =3D ; + }; + + pins-rst { + pinmux =3D ; + drive-strength =3D <6>; + bias-pull-up =3D ; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D <8>; + bias-pull-up =3D ; + }; + + pins-clk { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + + pins-ds { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + + pins-rst { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-up =3D ; + }; + }; + + nor_pins_default: nor-pins { + pins0 { + pinmux =3D , + , + ; + bias-pull-down; + }; + + pins1 { + pinmux =3D , + , + ; + bias-pull-up; + }; + }; + + spi0_pins: spi0-pins { + pins-spi { + pinmux =3D , + , + , + ; + bias-disable; + }; + }; + + spi1_pins: spi1-pins { + pins-spi { + pinmux =3D , + , + , + ; + bias-disable; + }; + }; + + spi2_pins: spi2-pins { + pins-spi { + pinmux =3D , + , + , + ; + bias-disable; + }; + }; + + uart0_pins: uart0-pins { + pins-uart0 { + pinmux =3D , + ; + bias-pull-up; + }; + }; +}; + +&pmic { + interrupts-extended =3D <&pio 222 IRQ_TYPE_LEVEL_HIGH>; +}; + +&scp { + memory-region =3D <&scp_mem_reserved>; + status =3D "okay"; +}; + +&spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0_pins>; + status =3D "okay"; +}; + +&spi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi1_pins>; + status =3D "okay"; +}; + +&spi2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi2_pins>; + status =3D "okay"; +}; + +&u3phy0 { + status=3D"okay"; +}; + +&u3phy1 { + status=3D"okay"; +}; + +&u3phy2 { + status=3D"okay"; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pins>; + status =3D "okay"; +}; + +&xhci0 { + status =3D "okay"; +}; + +&xhci1 { + status =3D "okay"; +}; + +&xhci2 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts= /mediatek/mt8188.dtsi new file mode 100644 index 000000000000..37343297e392 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -0,0 +1,951 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2023 MediaTek Inc. + * + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include + +/ { + compatible =3D "mediatek,mt8188"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x000>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <282>; + cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x100>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <282>; + cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x200>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <282>; + cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x300>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <282>; + cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x400>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <282>; + cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x500>; + enable-method =3D "psci"; + clock-frequency =3D <2000000000>; + capacity-dmips-mhz =3D <282>; + cpu-idle-states =3D <&cpu_off_l &cluster_off_l>; + i-cache-size =3D <32768>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <128>; + d-cache-size =3D <32768>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + }; + + cpu6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x600>; + enable-method =3D "psci"; + clock-frequency =3D <2600000000>; + capacity-dmips-mhz =3D <1024>; + cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_1>; + #cooling-cells =3D <2>; + }; + + cpu7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78"; + reg =3D <0x700>; + enable-method =3D "psci"; + clock-frequency =3D <2600000000>; + capacity-dmips-mhz =3D <1024>; + cpu-idle-states =3D <&cpu_off_b &cluster_off_b>; + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_1>; + #cooling-cells =3D <2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + + core4 { + cpu =3D <&cpu4>; + }; + + core5 { + cpu =3D <&cpu5>; + }; + + core6 { + cpu =3D <&cpu6>; + }; + + core7 { + cpu =3D <&cpu7>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + cpu_off_l: cpu-off-l { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x00010000>; + local-timer-stop; + entry-latency-us =3D <50>; + exit-latency-us =3D <95>; + min-residency-us =3D <580>; + }; + + cpu_off_b: cpu-off-b { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x00010000>; + local-timer-stop; + entry-latency-us =3D <45>; + exit-latency-us =3D <140>; + min-residency-us =3D <740>; + }; + + cluster_off_l: cluster-off-l { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x01010010>; + local-timer-stop; + entry-latency-us =3D <55>; + exit-latency-us =3D <155>; + min-residency-us =3D <840>; + }; + + cluster_off_b: cluster-off-b { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x01010010>; + local-timer-stop; + entry-latency-us =3D <50>; + exit-latency-us =3D <200>; + min-residency-us =3D <1000>; + }; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + cache-level =3D <2>; + next-level-cache =3D <&l3_0>; + cache-unified; + }; + + l2_1: l2-cache1 { + compatible =3D "cache"; + cache-level =3D <2>; + next-level-cache =3D <&l3_0>; + cache-unified; + }; + + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-unified; + }; + }; + + clk13m: oscillator-13m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <13000000>; + clock-output-names =3D "clk13m"; + }; + + clk26m: oscillator-26m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + clock-output-names =3D "clk26m"; + }; + + clk32k: oscillator-32k { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + clock-output-names =3D "clk32k"; + }; + + pmu-a55 { + compatible =3D "arm,cortex-a55-pmu"; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + pmu-a78 { + compatible =3D "arm,cortex-a78-pmu"; + interrupt-parent =3D <&gic>; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + timer: timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + clock-frequency =3D <13000000>; + }; + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible =3D "arm,gic-v3"; + #interrupt-cells =3D <4>; + #address-cells =3D <2>; + #size-cells =3D <2>; + #redistributor-regions =3D <1>; + interrupt-parent =3D <&gic>; + interrupt-controller; + reg =3D <0 0x0c000000 0 0x40000>, + <0 0x0c040000 0 0x200000>; + interrupts =3D ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity =3D <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity =3D <&cpu6 &cpu7>; + }; + }; + }; + + topckgen: syscon@10000000 { + compatible =3D "mediatek,mt8188-topckgen", "syscon"; + reg =3D <0 0x10000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + infracfg_ao: syscon@10001000 { + compatible =3D "mediatek,mt8188-infracfg-ao", "syscon"; + reg =3D <0 0x10001000 0 0x1000>; + #clock-cells =3D <1>; + }; + + pericfg: syscon@10003000 { + compatible =3D "mediatek,mt8188-pericfg", "syscon"; + reg =3D <0 0x10003000 0 0x1000>; + #clock-cells =3D <1>; + }; + + pio: pinctrl@10005000 { + compatible =3D "mediatek,mt8188-pinctrl"; + reg =3D <0 0x10005000 0 0x1000>, + <0 0x11c00000 0 0x1000>, + <0 0x11e10000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11ea0000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names =3D "iocfg0", "iocfg_rm", + "iocfg_lt", "iocfg_lm", "iocfg_rt", + "eint"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pio 0 0 176>; + interrupt-controller; + interrupts =3D ; + #interrupt-cells =3D <2>; + }; + + watchdog: watchdog@10007000 { + compatible =3D "mediatek,mt8188-wdt"; + mediatek,disable-extrst; + reg =3D <0 0x10007000 0 0x100>; + #reset-cells =3D <1>; + }; + + apmixedsys: syscon@1000c000 { + compatible =3D "mediatek,mt8188-apmixedsys", "syscon"; + reg =3D <0 0x1000c000 0 0x1000>; + #clock-cells =3D <1>; + }; + + systimer: timer@10017000 { + compatible =3D "mediatek,mt8188-timer", "mediatek,mt6765-timer"; + reg =3D <0 0x10017000 0 0x1000>; + reg-names =3D "sys_timer_base"; + interrupts =3D ; + clocks =3D <&clk13m>; + }; + + pwrap: pwrap@10024000 { + compatible =3D "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap", "sysco= n"; + reg =3D <0 0x10024000 0 0x1000>; + reg-names =3D "pwrap"; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; + clock-names =3D "spi", "wrap"; + }; + + scp: scp@10500000 { + compatible =3D "mediatek,mt8188-scp"; + reg =3D <0 0x10500000 0 0x100000>, + <0 0x10720000 0 0xe0000>; + reg-names =3D "sram", "cfg"; + interrupts =3D ; + }; + + adsp_audio26m: clock-controller@10b91100 { + compatible =3D "mediatek,mt8188-adsp-audio26m"; + reg =3D <0 0x10b91100 0 0x100>; + #clock-cells =3D <1>; + }; + + uart0: serial@11001100 { + compatible =3D "mediatek,mt8188-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11001100 0 0x100>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; + clock-names =3D "baud", "bus"; + status =3D "disabled"; + }; + + uart1: serial@11001200 { + compatible =3D "mediatek,mt8188-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11001200 0 0x100>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; + clock-names =3D "baud", "bus"; + status =3D "disabled"; + }; + + uart2: serial@11001300 { + compatible =3D "mediatek,mt8188-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11001300 0 0x100>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; + clock-names =3D "baud", "bus"; + status =3D "disabled"; + }; + + uart3: serial@11001400 { + compatible =3D "mediatek,mt8188-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11001400 0 0x100>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; + clock-names =3D "baud", "bus"; + status =3D "disabled"; + }; + + auxadc: adc@11002000 { + compatible =3D "mediatek,mt8188-auxadc", "mediatek,mt8173-auxadc"; + reg =3D <0 0x11002000 0 0x1000>; + clocks =3D <&infracfg_ao CLK_INFRA_AO_AUXADC>; + clock-names =3D "main"; + #io-channel-cells =3D <1>; + status =3D "disabled"; + }; + + pericfg_ao: syscon@11003000 { + compatible =3D "mediatek,mt8188-pericfg-ao", "syscon"; + reg =3D <0 0x11003000 0 0x1000>; + #clock-cells =3D <1>; + }; + + spi0: spi@1100a000 { + compatible =3D "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x1100a000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI0>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + spi1: spi@11010000 { + compatible =3D "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x11010000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI1>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + spi2: spi@11012000 { + compatible =3D "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x11012000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI2>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + spi3: spi@11013000 { + compatible =3D "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x11013000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI3>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + spi4: spi@11018000 { + compatible =3D "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x11018000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI4>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + spi5: spi@11019000 { + compatible =3D "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x11019000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI5>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + xhci1: usb@11200000 { + compatible =3D "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; + reg =3D <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts =3D ; + phys =3D <&u2port1 PHY_TYPE_USB2>, + <&u3port1 PHY_TYPE_USB3>; + assigned-clocks =3D <&topckgen CLK_TOP_USB_TOP>, + <&topckgen CLK_TOP_SSUSB_XHCI>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks =3D <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>, + <&topckgen CLK_TOP_SSUSB_TOP_REF>, + <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck"; + mediatek,syscon-wakeup =3D <&pericfg 0x468 2>; + wakeup-source; + status =3D "disabled"; + }; + + mmc0: mmc@11230000 { + compatible =3D "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; + reg =3D <0 0x11230000 0 0x10000>, + <0 0x11f50000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_MSDC50_0>, + <&infracfg_ao CLK_INFRA_AO_MSDC0>, + <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, + <&infracfg_ao CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P>; + clock-names =3D "source", "hclk", "source_cg", "crypto_clk"; + status =3D "disabled"; + }; + + mmc1: mmc@11240000 { + compatible =3D "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; + reg =3D <0 0x11240000 0 0x1000>, + <0 0x11eb0000 0 0x1000>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_MSDC30_1>, + <&infracfg_ao CLK_INFRA_AO_MSDC1>, + <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; + clock-names =3D "source", "hclk", "source_cg"; + assigned-clocks =3D <&topckgen CLK_TOP_MSDC30_1>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MSDCPLL_D2>; + status =3D "disabled"; + }; + + i2c0: i2c@11280000 { + compatible =3D "mediatek,mt8188-i2c"; + reg =3D <0 0x11280000 0 0x1000>, + <0 0x10220080 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0>, + <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c2: i2c@11281000 { + compatible =3D "mediatek,mt8188-i2c"; + reg =3D <0 0x11281000 0 0x1000>, + <0 0x10220180 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2>, + <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c3: i2c@11282000 { + compatible =3D "mediatek,mt8188-i2c"; + reg =3D <0 0x11282000 0 0x1000>, + <0 0x10220280 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3>, + <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + imp_iic_wrap_c: clock-controller@11283000 { + compatible =3D "mediatek,mt8188-imp-iic-wrap-c"; + reg =3D <0 0x11283000 0 0x1000>; + #clock-cells =3D <1>; + }; + + xhci2: usb@112a0000 { + compatible =3D "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; + reg =3D <0 0x112a0000 0 0x1000>, + <0 0x112a3e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts =3D ; + phys =3D <&u2port2 PHY_TYPE_USB2>; + assigned-clocks =3D <&topckgen CLK_TOP_SSUSB_XHCI_3P>, + <&topckgen CLK_TOP_USB_TOP_3P>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks =3D <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, + <&topckgen CLK_TOP_SSUSB_TOP_P3_REF>, + <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck"; + status =3D "disabled"; + }; + + xhci0: usb@112b0000 { + compatible =3D "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; + reg =3D <0 0x112b0000 0 0x1000>, + <0 0x112b3e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts =3D ; + phys =3D <&u2port0 PHY_TYPE_USB2>; + assigned-clocks =3D <&topckgen CLK_TOP_SSUSB_XHCI_2P>, + <&topckgen CLK_TOP_USB_TOP_2P>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks =3D <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, + <&topckgen CLK_TOP_SSUSB_TOP_P2_REF>, + <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck"; + mediatek,syscon-wakeup =3D <&pericfg 0x460 2>; + wakeup-source; + status =3D "disabled"; + }; + + nor_flash: spi@1132c000 { + compatible =3D "mediatek,mt8188-nor", "mediatek,mt8186-nor"; + reg =3D <0 0x1132c000 0 0x1000>; + clocks =3D <&topckgen CLK_TOP_SPINOR>, + <&pericfg_ao CLK_PERI_AO_FLASHIFLASHCK>, + <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; + clock-names =3D "spi", "sf", "axi"; + assigned-clocks =3D <&topckgen CLK_TOP_SPINOR>; + interrupts =3D ; + status =3D "disabled"; + }; + + i2c1: i2c@11e00000 { + compatible =3D "mediatek,mt8188-i2c"; + reg =3D <0 0x11e00000 0 0x1000>, + <0 0x10220100 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1>, + <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c4: i2c@11e01000 { + compatible =3D "mediatek,mt8188-i2c"; + reg =3D <0 0x11e01000 0 0x1000>, + <0 0x10220380 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4>, + <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + imp_iic_wrap_w: clock-controller@11e02000 { + compatible =3D "mediatek,mt8188-imp-iic-wrap-w"; + reg =3D <0 0x11e02000 0 0x1000>; + #clock-cells =3D <1>; + }; + + u3phy0: t-phy@11e30000 { + compatible =3D "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x11e30000 0x1000>; + status =3D "disabled"; + + u2port0: usb-phy@0 { + reg =3D <0x0 0x700>; + clocks =3D <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>, + <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; + clock-names =3D "ref", "da_ref"; + #phy-cells =3D <1>; + }; + }; + + u3phy1: t-phy@11e40000 { + compatible =3D "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x11e40000 0x1000>; + status =3D "disabled"; + + u2port1: usb-phy@0 { + reg =3D <0x0 0x700>; + clocks =3D <&topckgen CLK_TOP_SSUSB_PHY_REF>, + <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; + clock-names =3D "ref", "da_ref"; + #phy-cells =3D <1>; + }; + + u3port1: usb-phy@700 { + reg =3D <0x700 0x700>; + clocks =3D <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>, + <&clk26m>; + clock-names =3D "ref", "da_ref"; + #phy-cells =3D <1>; + status =3D "disabled"; + }; + }; + + u3phy2: t-phy@11e80000 { + compatible =3D "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x11e80000 0x1000>; + status =3D "disabled"; + + u2port2: usb-phy@0 { + reg =3D <0x0 0x700>; + clocks =3D <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>, + <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>; + clock-names =3D "ref", "da_ref"; + #phy-cells =3D <1>; + }; + }; + + i2c5: i2c@11ec0000 { + compatible =3D "mediatek,mt8188-i2c"; + reg =3D <0 0x11ec0000 0 0x1000>, + <0 0x10220480 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5>, + <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c6: i2c@11ec1000 { + compatible =3D "mediatek,mt8188-i2c"; + reg =3D <0 0x11ec1000 0 0x1000>, + <0 0x10220600 0 0x80>; + interrupts =3D ; + clock-div =3D <1>; + clocks =3D <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6>, + <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; + clock-names =3D "main", "dma"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + imp_iic_wrap_en: clock-controller@11ec2000 { + compatible =3D "mediatek,mt8188-imp-iic-wrap-en"; + reg =3D <0 0x11ec2000 0 0x1000>; + #clock-cells =3D <1>; + }; + + mfgcfg: clock-controller@13fbf000 { + compatible =3D "mediatek,mt8188-mfgcfg"; + reg =3D <0 0x13fbf000 0 0x1000>; + #clock-cells =3D <1>; + }; + + vppsys0: clock-controller@14000000 { + compatible =3D "mediatek,mt8188-vppsys0"; + reg =3D <0 0x14000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + wpesys: clock-controller@14e00000 { + compatible =3D "mediatek,mt8188-wpesys"; + reg =3D <0 0x14e00000 0 0x1000>; + #clock-cells =3D <1>; + }; + + wpesys_vpp0: clock-controller@14e02000 { + compatible =3D "mediatek,mt8188-wpesys-vpp0"; + reg =3D <0 0x14e02000 0 0x1000>; + #clock-cells =3D <1>; + }; + + vppsys1: clock-controller@14f00000 { + compatible =3D "mediatek,mt8188-vppsys1"; + reg =3D <0 0x14f00000 0 0x1000>; + #clock-cells =3D <1>; + }; + + imgsys: clock-controller@15000000 { + compatible =3D "mediatek,mt8188-imgsys"; + reg =3D <0 0x15000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + imgsys1_dip_top: clock-controller@15110000 { + compatible =3D "mediatek,mt8188-imgsys1-dip-top"; + reg =3D <0 0x15110000 0 0x1000>; + #clock-cells =3D <1>; + }; + + imgsys1_dip_nr: clock-controller@15130000 { + compatible =3D "mediatek,mt8188-imgsys1-dip-nr"; + reg =3D <0 0x15130000 0 0x1000>; + #clock-cells =3D <1>; + }; + + imgsys_wpe1: clock-controller@15220000 { + compatible =3D "mediatek,mt8188-imgsys-wpe1"; + reg =3D <0 0x15220000 0 0x1000>; + #clock-cells =3D <1>; + }; + + ipesys: clock-controller@15330000 { + compatible =3D "mediatek,mt8188-ipesys"; + reg =3D <0 0x15330000 0 0x1000>; + #clock-cells =3D <1>; + }; + + imgsys_wpe2: clock-controller@15520000 { + compatible =3D "mediatek,mt8188-imgsys-wpe2"; + reg =3D <0 0x15520000 0 0x1000>; + #clock-cells =3D <1>; + }; + + imgsys_wpe3: clock-controller@15620000 { + compatible =3D "mediatek,mt8188-imgsys-wpe3"; + reg =3D <0 0x15620000 0 0x1000>; + #clock-cells =3D <1>; + }; + + camsys: clock-controller@16000000 { + compatible =3D "mediatek,mt8188-camsys"; + reg =3D <0 0x16000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + camsys_rawa: clock-controller@1604f000 { + compatible =3D "mediatek,mt8188-camsys-rawa"; + reg =3D <0 0x1604f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + camsys_yuva: clock-controller@1606f000 { + compatible =3D "mediatek,mt8188-camsys-yuva"; + reg =3D <0 0x1606f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + camsys_rawb: clock-controller@1608f000 { + compatible =3D "mediatek,mt8188-camsys-rawb"; + reg =3D <0 0x1608f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + camsys_yuvb: clock-controller@160af000 { + compatible =3D "mediatek,mt8188-camsys-yuvb"; + reg =3D <0 0x160af000 0 0x1000>; + #clock-cells =3D <1>; + }; + + ccusys: clock-controller@17200000 { + compatible =3D "mediatek,mt8188-ccusys"; + reg =3D <0 0x17200000 0 0x1000>; + #clock-cells =3D <1>; + }; + + vdecsys_soc: clock-controller@1800f000 { + compatible =3D "mediatek,mt8188-vdecsys-soc"; + reg =3D <0 0x1800f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + vdecsys: clock-controller@1802f000 { + compatible =3D "mediatek,mt8188-vdecsys"; + reg =3D <0 0x1802f000 0 0x1000>; + #clock-cells =3D <1>; + }; + + vencsys: clock-controller@1a000000 { + compatible =3D "mediatek,mt8188-vencsys"; + reg =3D <0 0x1a000000 0 0x1000>; + #clock-cells =3D <1>; + }; + }; +}; --=20 2.18.0