From nobody Sat Feb 7 11:30:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 847ABEB64D9 for ; Mon, 10 Jul 2023 09:49:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231307AbjGJJtT (ORCPT ); Mon, 10 Jul 2023 05:49:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233263AbjGJJsM (ORCPT ); Mon, 10 Jul 2023 05:48:12 -0400 Received: from mail-io1-xd33.google.com (mail-io1-xd33.google.com [IPv6:2607:f8b0:4864:20::d33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84C1F49C4 for ; Mon, 10 Jul 2023 02:43:46 -0700 (PDT) Received: by mail-io1-xd33.google.com with SMTP id ca18e2360f4ac-78363cc070aso206104839f.1 for ; Mon, 10 Jul 2023 02:43:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1688982225; x=1691574225; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vWvqokmp7r4qpLb1zZr/K+Grf5K67mplcBtMET9ZvCc=; b=GuLbKlzbbm4+IQ1CE2fG/Sh0nv+IuRFqdVmE9lHlCnzZvCYcJ+fNJwYSnPgIzs+2LV 0IumeDVWpjLHWIAwGn8ZjRZ0r1R1/9vJRUN9TaFiD3zMurfzY5FyomAvdQdAftRrvSlC 72NrgVLlgcFtJggqHFSs+M/7UafyA2H+VYl6h8Yf78Hd3q4y5NOQ7MzGdq0rbQXFNHYo 1NHVjpf9Dy3tZWu5EWaO88c/SG2Q7jQlqvSa6npE0kZuPIOt2Vl03C8cwLz1ojq3wVsL lBJfnTyUc+N4gS4/WzoxhxqCjVAfxLl19R5srAdH//IlLNZqP53SsgxbqhNDM/8ZvGcJ eWrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688982225; x=1691574225; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vWvqokmp7r4qpLb1zZr/K+Grf5K67mplcBtMET9ZvCc=; b=I8Ny7/zkEv1cDQWrs9xsj+h22nvq4BEhI35NzDZARmN0PPBkGn7EI/PhL8JrO+qH2z uaZ6M6rFZNwY8swbzjmYDq87WUamCAhRcS9/QmAQUH97lx5kow6kLk9mvLhwECC/lEIk hxDID7VYMPNwnvSEY93jRXdZ4qbcWHmGFFV/Kahv36brdPCyq+lVcAVhfto5GfK+P7hg VaR4YbqPzM+zIFwhINepqI6VXi/nQ5YABh0IuWRe8JkxnwgHHA3ob6DDqBbMLzuF5zxu GPhtHVFMRL0ANQzUcyqSFjnMymNjKKBL2ZLpsyNetdKCMWaq6i6f1Sh+S2i47E4Sd+ak tiEw== X-Gm-Message-State: ABy/qLbDKMt7wmZIEFDGvKIsjlcd9JpDkBkzwmRzD5V8A8qduOq4sEL7 hZzplvyyi+cR37nUwtGbpKkasw== X-Google-Smtp-Source: APBJJlFEyLkIuL8Wq3Jqu7Z6swRF/VIvMb80OEnwDuIryYk6JE6AjqCkbB4cESzshC7MW2kIN8b3BA== X-Received: by 2002:a5e:df01:0:b0:786:fff8:13c2 with SMTP id f1-20020a5edf01000000b00786fff813c2mr5491462ioq.11.1688982225538; Mon, 10 Jul 2023 02:43:45 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id k1-20020a6b7a41000000b007870c56387dsm936938iop.49.2023.07.10.02.43.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jul 2023 02:43:45 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski Cc: Atish Patra , Andrew Jones , Sunil V L , Conor Dooley , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v5 1/9] RISC-V: Add riscv_fw_parent_hartid() function Date: Mon, 10 Jul 2023 15:13:13 +0530 Message-Id: <20230710094321.1378351-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230710094321.1378351-1-apatel@ventanamicro.com> References: <20230710094321.1378351-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We add common riscv_fw_parent_hartid() which help device drivers to get parent hartid of the INTC (i.e. local interrupt controller) fwnode. This should work for both DT and ACPI. Signed-off-by: Anup Patel --- arch/riscv/include/asm/processor.h | 3 +++ arch/riscv/kernel/cpu.c | 16 ++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index c950a8d9edef..39dc23a18f88 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -81,6 +81,9 @@ int riscv_of_processor_hartid(struct device_node *node, u= nsigned long *hartid); int riscv_early_of_processor_hartid(struct device_node *node, unsigned lon= g *hartid); int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid= ); =20 +struct fwnode_handle; +int riscv_fw_parent_hartid(struct fwnode_handle *node, unsigned long *hart= id); + extern void riscv_fill_hwcap(void); extern int arch_dup_task_struct(struct task_struct *dst, struct task_struc= t *src); =20 diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index a2fc952318e9..9be9b3b1f333 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -96,6 +96,22 @@ int riscv_of_parent_hartid(struct device_node *node, uns= igned long *hartid) return -1; } =20 +/* Find hart ID of the CPU fwnode under which given fwnode falls. */ +int riscv_fw_parent_hartid(struct fwnode_handle *node, unsigned long *hart= id) +{ + int rc; + u64 temp; + + if (!is_of_node(node)) { + rc =3D fwnode_property_read_u64_array(node, "hartid", &temp, 1); + if (!rc) + *hartid =3D temp; + } else + rc =3D riscv_of_parent_hartid(to_of_node(node), hartid); + + return rc; +} + DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); =20 unsigned long riscv_cached_mvendorid(unsigned int cpu_id) --=20 2.34.1 From nobody Sat Feb 7 11:30:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E11BEB64D9 for ; Mon, 10 Jul 2023 09:49:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229795AbjGJJt3 (ORCPT ); Mon, 10 Jul 2023 05:49:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35268 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233362AbjGJJsX (ORCPT ); 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Mon, 10 Jul 2023 02:43:51 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski Cc: Atish Patra , Andrew Jones , Sunil V L , Conor Dooley , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v5 2/9] irqchip/riscv-intc: Add support for RISC-V AIA Date: Mon, 10 Jul 2023 15:13:14 +0530 Message-Id: <20230710094321.1378351-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230710094321.1378351-1-apatel@ventanamicro.com> References: <20230710094321.1378351-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The RISC-V advanced interrupt architecture (AIA) extends the per-HART local interrupts in following ways: 1. Minimum 64 local interrupts for both RV32 and RV64 2. Ability to process multiple pending local interrupts in same interrupt handler 3. Priority configuration for each local interrupts 4. Special CSRs to configure/access the per-HART MSI controller This patch adds support for RISC-V AIA in the RISC-V intc driver. Signed-off-by: Anup Patel --- drivers/irqchip/irq-riscv-intc.c | 36 ++++++++++++++++++++++++++------ 1 file changed, 30 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index 4adeee1bc391..e235bf1708a4 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -17,6 +17,7 @@ #include #include #include +#include =20 static struct irq_domain *intc_domain; =20 @@ -30,6 +31,15 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *re= gs) generic_handle_domain_irq(intc_domain, cause); } =20 +static asmlinkage void riscv_intc_aia_irq(struct pt_regs *regs) +{ + unsigned long topi; + + while ((topi =3D csr_read(CSR_TOPI))) + generic_handle_domain_irq(intc_domain, + topi >> TOPI_IID_SHIFT); +} + /* * On RISC-V systems local interrupts are masked or unmasked by writing * the SIE (Supervisor Interrupt Enable) CSR. As CSRs can only be written @@ -39,12 +49,18 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *r= egs) =20 static void riscv_intc_irq_mask(struct irq_data *d) { - csr_clear(CSR_IE, BIT(d->hwirq)); + if (d->hwirq < BITS_PER_LONG) + csr_clear(CSR_IE, BIT(d->hwirq)); + else + csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); } =20 static void riscv_intc_irq_unmask(struct irq_data *d) { - csr_set(CSR_IE, BIT(d->hwirq)); + if (d->hwirq < BITS_PER_LONG) + csr_set(CSR_IE, BIT(d->hwirq)); + else + csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); } =20 static void riscv_intc_irq_eoi(struct irq_data *d) @@ -115,16 +131,22 @@ static struct fwnode_handle *riscv_intc_hwnode(void) =20 static int __init riscv_intc_init_common(struct fwnode_handle *fn) { - int rc; + int rc, nr_irqs =3D BITS_PER_LONG; + + if (riscv_isa_extension_available(NULL, SxAIA) && BITS_PER_LONG =3D=3D 32) + nr_irqs =3D nr_irqs * 2; =20 - intc_domain =3D irq_domain_create_linear(fn, BITS_PER_LONG, + intc_domain =3D irq_domain_create_linear(fn, nr_irqs, &riscv_intc_domain_ops, NULL); if (!intc_domain) { pr_err("unable to add IRQ domain\n"); return -ENXIO; } =20 - rc =3D set_handle_irq(&riscv_intc_irq); + if (riscv_isa_extension_available(NULL, SxAIA)) + rc =3D set_handle_irq(&riscv_intc_aia_irq); + else + rc =3D set_handle_irq(&riscv_intc_irq); if (rc) { pr_err("failed to set irq handler\n"); return rc; @@ -132,7 +154,9 @@ static int __init riscv_intc_init_common(struct fwnode_= handle *fn) =20 riscv_set_intc_hwnode_fn(riscv_intc_hwnode); =20 - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); + pr_info("%d local interrupts mapped%s\n", + nr_irqs, (riscv_isa_extension_available(NULL, SxAIA)) ? + " using AIA" : ""); =20 return 0; } --=20 2.34.1 From nobody Sat Feb 7 11:30:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D5ECEB64D9 for ; Mon, 10 Jul 2023 09:49:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233084AbjGJJte (ORCPT ); Mon, 10 Jul 2023 05:49:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35114 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233454AbjGJJsg (ORCPT ); Mon, 10 Jul 2023 05:48:36 -0400 Received: from mail-io1-xd2a.google.com (mail-io1-xd2a.google.com [IPv6:2607:f8b0:4864:20::d2a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33F99358E for ; Mon, 10 Jul 2023 02:44:00 -0700 (PDT) Received: by mail-io1-xd2a.google.com with SMTP id ca18e2360f4ac-783544a1c90so217869539f.1 for ; Mon, 10 Jul 2023 02:44:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1688982239; x=1691574239; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZOjDepVi55uZJQ1rIBBnqb1diEnF/zfemFV4q9wl2F4=; b=TItx1NTaItcbGalOkM+2DtGF38dO5Is0Sz55vPOVYuCEb5iOuzkejSBRCQadQ2aOH6 ggJhDh+MQ2RXv44yMCNP/9DOMrv3K9u687j+DPZ10ZTynl6Yjo1Uaw2vfkXWPtmOVbTh 7m2GqB9Z28z+hFDl8VJxVhIOVh64Bd8COFRmZfkPiaWhUuGiTKn87E674VBT4oexPjcz J/8BtNDmqEBune6vt+mJ3OrN5+mlHIcwGH6E1zYakDGJWe+JwWCQLcPTYmAFIngtaTnK +IzUHI8FaOKpjMZwjAWmdue6t0PecJF78EDXeHps3IxpQjvMEJyzin/M5uIN3+1hQ0hO GUfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688982239; x=1691574239; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZOjDepVi55uZJQ1rIBBnqb1diEnF/zfemFV4q9wl2F4=; b=iRQPkJA/awIqouFDy9XtvUzc/vYbWMtgDvg/cTX637qGeWwJ6CUR5If+BQ15coLIbv Bbd2+rrBbveVkNmp+7iausbSueG6naZKcnmYKzY2gvwUHMQTyeFN9xEk+cF7erg+uhgd CbblAX2NYJMM/OUf7b3sVB92Cp/aRbaKkZpwQC1XYjLy/L55QbMzfIZ/GtU8DNk6H8UE H4rH20oHwTQRmSb5Xm9SMV2eQt9YgZ7f16r/+FRWNb4ufpkkcuvssOeHyJD3gGNb9gOU 4ISnheDb+lHuQh9nhm+btm839X54bKJS4+KyLwsWHlxOg6ubEWTcJViYHHz86XVs1ipw 384A== X-Gm-Message-State: ABy/qLbilwRZvNtcj+Qe329XSqOPG/ZxRG+QW0XNmMLyOsvGoUlr+Jn9 lXNaRTLeMZVuUZFhN7p7MPqRCw== X-Google-Smtp-Source: APBJJlEetliisBeYFLwVNWfsYiEWtus4obFenvGr0al6lWkhxRcmF2mCqU/dJ3UK3jtGqjIaBm5obg== X-Received: by 2002:a5d:9f14:0:b0:783:71b1:50cf with SMTP id q20-20020a5d9f14000000b0078371b150cfmr15398581iot.11.1688982239495; Mon, 10 Jul 2023 02:43:59 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id k1-20020a6b7a41000000b007870c56387dsm936938iop.49.2023.07.10.02.43.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jul 2023 02:43:59 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski Cc: Atish Patra , Andrew Jones , Sunil V L , Conor Dooley , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel , Conor Dooley , Krzysztof Kozlowski Subject: [PATCH v5 3/9] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Date: Mon, 10 Jul 2023 15:13:15 +0530 Message-Id: <20230710094321.1378351-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230710094321.1378351-1-apatel@ventanamicro.com> References: <20230710094321.1378351-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We add DT bindings document for the RISC-V incoming MSI controller (IMSIC) defined by the RISC-V advanced interrupt architecture (AIA) specification. Signed-off-by: Anup Patel Reviewed-by: Conor Dooley Acked-by: Krzysztof Kozlowski --- .../interrupt-controller/riscv,imsics.yaml | 172 ++++++++++++++++++ 1 file changed, 172 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= riscv,imsics.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,i= msics.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,i= msics.yaml new file mode 100644 index 000000000000..84976f17a4a1 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.y= aml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Incoming MSI Controller (IMSIC) + +maintainers: + - Anup Patel + +description: | + The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incom= ing + MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V + AIA specification can be found at https://github.com/riscv/riscv-aia. + + The IMSIC is a per-CPU (or per-HART) device with separate interrupt file + for each privilege level (machine or supervisor). The configuration of + a IMSIC interrupt file is done using AIA CSRs and it also has a 4KB MMIO + space to receive MSIs from devices. Each IMSIC interrupt file supports a + fixed number of interrupt identities (to distinguish MSIs from devices) + which is same for given privilege level across CPUs (or HARTs). + + The device tree of a RISC-V platform will have one IMSIC device tree node + for each privilege level (machine or supervisor) which collectively desc= ribe + IMSIC interrupt files at that privilege level across CPUs (or HARTs). + + The arrangement of IMSIC interrupt files in MMIO space of a RISC-V platf= orm + follows a particular scheme defined by the RISC-V AIA specification. A I= MSIC + group is a set of IMSIC interrupt files co-located in MMIO space and we = can + have multiple IMSIC groups (i.e. clusters, sockets, chiplets, etc) in a + RISC-V platform. The MSI target address of a IMSIC interrupt file at giv= en + privilege level (machine or supervisor) encodes group index, HART index, + and guest index (shown below). + + XLEN-1 > (HART Index MSB) 12 0 + | | | | + ------------------------------------------------------------- + |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 | + ------------------------------------------------------------- + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + items: + - enum: + - qemu,imsics + - const: riscv,imsics + + reg: + minItems: 1 + maxItems: 16384 + description: + Base address of each IMSIC group. + + interrupt-controller: true + + "#interrupt-cells": + const: 0 + + msi-controller: true + + "#msi-cells": + const: 0 + + interrupts-extended: + minItems: 1 + maxItems: 16384 + description: + This property represents the set of CPUs (or HARTs) for which given + device tree node describes the IMSIC interrupt files. Each node poin= ted + to should be a riscv,cpu-intc node, which has a CPU node (i.e. RISC-V + HART) as parent. + + riscv,num-ids: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 63 + maximum: 2047 + description: + Number of interrupt identities supported by IMSIC interrupt file. + + riscv,num-guest-ids: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 63 + maximum: 2047 + description: + Number of interrupt identities are supported by IMSIC guest interrupt + file. When not specified it is assumed to be same as specified by the + riscv,num-ids property. + + riscv,guest-index-bits: + minimum: 0 + maximum: 7 + default: 0 + description: + Number of guest index bits in the MSI target address. + + riscv,hart-index-bits: + minimum: 0 + maximum: 15 + description: + Number of HART index bits in the MSI target address. When not + specified it is calculated based on the interrupts-extended property. + + riscv,group-index-bits: + minimum: 0 + maximum: 7 + default: 0 + description: + Number of group index bits in the MSI target address. + + riscv,group-index-shift: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 55 + default: 24 + description: + The least significant bit position of the group index bits in the + MSI target address. + +required: + - compatible + - reg + - interrupt-controller + - msi-controller + - "#msi-cells" + - interrupts-extended + - riscv,num-ids + +unevaluatedProperties: false + +examples: + - | + // Example 1 (Machine-level IMSIC files with just one group): + + interrupt-controller@24000000 { + compatible =3D "qemu,imsics", "riscv,imsics"; + interrupts-extended =3D <&cpu1_intc 11>, + <&cpu2_intc 11>, + <&cpu3_intc 11>, + <&cpu4_intc 11>; + reg =3D <0x28000000 0x4000>; + interrupt-controller; + #interrupt-cells =3D <0>; + msi-controller; + #msi-cells =3D <0>; + riscv,num-ids =3D <127>; + }; + + - | + // Example 2 (Supervisor-level IMSIC files with two groups): + + interrupt-controller@28000000 { + compatible =3D "qemu,imsics", "riscv,imsics"; + interrupts-extended =3D <&cpu1_intc 9>, + <&cpu2_intc 9>, + <&cpu3_intc 9>, + <&cpu4_intc 9>; + reg =3D <0x28000000 0x2000>, /* Group0 IMSICs */ + <0x29000000 0x2000>; /* Group1 IMSICs */ + interrupt-controller; + #interrupt-cells =3D <0>; + msi-controller; + #msi-cells =3D <0>; + riscv,num-ids =3D <127>; + riscv,group-index-bits =3D <1>; + riscv,group-index-shift =3D <24>; + }; +... --=20 2.34.1 From nobody Sat Feb 7 11:30:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DA5EEB64DA for ; Mon, 10 Jul 2023 09:50:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230322AbjGJJuG (ORCPT ); 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Mon, 10 Jul 2023 02:44:05 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski Cc: Atish Patra , Andrew Jones , Sunil V L , Conor Dooley , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v5 4/9] irqchip: Add RISC-V incoming MSI controller driver Date: Mon, 10 Jul 2023 15:13:16 +0530 Message-Id: <20230710094321.1378351-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230710094321.1378351-1-apatel@ventanamicro.com> References: <20230710094321.1378351-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The RISC-V advanced interrupt architecture (AIA) specification defines a new MSI controller for managing MSIs and IPIs on a RISC-V platform. This new MSI controller is referred to as incoming message signalled interrupt controller (IMSIC) which manages MSI on per-HART (or per-CPU) basis. (For more details refer https://github.com/riscv/riscv-aia) This patch adds an irqchip driver for RISC-V IMSIC which provides IPIs and platform MSIs to the Linux RISC-V kernel. Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 7 +- drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-riscv-imsic.c | 1011 +++++++++++++++++++++++++++ include/linux/irqchip/riscv-imsic.h | 86 +++ 4 files changed, 1104 insertions(+), 1 deletion(-) create mode 100644 drivers/irqchip/irq-riscv-imsic.c create mode 100644 include/linux/irqchip/riscv-imsic.h diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 09e422da482f..8ef18be5f37b 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -30,7 +30,6 @@ config ARM_GIC_V2M =20 config GIC_NON_BANKED bool - config ARM_GIC_V3 bool select IRQ_DOMAIN_HIERARCHY @@ -545,6 +544,12 @@ config SIFIVE_PLIC select IRQ_DOMAIN_HIERARCHY select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP =20 +config RISCV_IMSIC + bool + depends on RISCV + select IRQ_DOMAIN_HIERARCHY + select GENERIC_MSI_IRQ + config EXYNOS_IRQ_COMBINER bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index ffd945fe71aa..577bde3e986b 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -95,6 +95,7 @@ obj-$(CONFIG_QCOM_MPM) +=3D irq-qcom-mpm.o obj-$(CONFIG_CSKY_MPINTC) +=3D irq-csky-mpintc.o obj-$(CONFIG_CSKY_APB_INTC) +=3D irq-csky-apb-intc.o obj-$(CONFIG_RISCV_INTC) +=3D irq-riscv-intc.o +obj-$(CONFIG_RISCV_IMSIC) +=3D irq-riscv-imsic.o obj-$(CONFIG_SIFIVE_PLIC) +=3D irq-sifive-plic.o obj-$(CONFIG_IMX_IRQSTEER) +=3D irq-imx-irqsteer.o obj-$(CONFIG_IMX_INTMUX) +=3D irq-imx-intmux.o diff --git a/drivers/irqchip/irq-riscv-imsic.c b/drivers/irqchip/irq-riscv-= imsic.c new file mode 100644 index 000000000000..ceb5e0fc883c --- /dev/null +++ b/drivers/irqchip/irq-riscv-imsic.c @@ -0,0 +1,1011 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#define pr_fmt(fmt) "riscv-imsic: " fmt +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IMSIC_DISABLE_EIDELIVERY 0 +#define IMSIC_ENABLE_EIDELIVERY 1 +#define IMSIC_DISABLE_EITHRESHOLD 1 +#define IMSIC_ENABLE_EITHRESHOLD 0 + +/* + * The IMSIC driver uses 1 IPI for ID synchronization and + * arch/riscv/kernel/smp.c require 6 IPIs so we fix the + * total number of IPIs to 8. + */ +#define IMSIC_NR_IPI 8 + +#define imsic_csr_write(__c, __v) \ +do { \ + csr_write(CSR_ISELECT, __c); \ + csr_write(CSR_IREG, __v); \ +} while (0) + +#define imsic_csr_read(__c) \ +({ \ + unsigned long __v; \ + csr_write(CSR_ISELECT, __c); \ + __v =3D csr_read(CSR_IREG); \ + __v; \ +}) + +#define imsic_csr_set(__c, __v) \ +do { \ + csr_write(CSR_ISELECT, __c); \ + csr_set(CSR_IREG, __v); \ +} while (0) + +#define imsic_csr_clear(__c, __v) \ +do { \ + csr_write(CSR_ISELECT, __c); \ + csr_clear(CSR_IREG, __v); \ +} while (0) + +struct imsic_priv { + /* Global configuration common for all HARTs */ + struct imsic_global_config global; + + /* Global state of interrupt identities */ + raw_spinlock_t ids_lock; + unsigned long *ids_used_bimap; + unsigned long *ids_enabled_bimap; + unsigned int *ids_target_cpu; + + /* Mask for connected CPUs */ + struct cpumask lmask; + + /* IPI interrupt identity and synchronization */ + u32 ipi_id; + int ipi_virq; + struct irq_desc *ipi_lsync_desc; + + /* IRQ domains */ + struct irq_domain *base_domain; + struct irq_domain *plat_domain; +}; + +static struct imsic_priv *imsic; +static int imsic_parent_irq; + +const struct imsic_global_config *imsic_get_global_config(void) +{ + return (imsic) ? &imsic->global : NULL; +} +EXPORT_SYMBOL_GPL(imsic_get_global_config); + +static int imsic_cpu_page_phys(unsigned int cpu, + unsigned int guest_index, + phys_addr_t *out_msi_pa) +{ + struct imsic_global_config *global; + struct imsic_local_config *local; + + global =3D &imsic->global; + local =3D per_cpu_ptr(global->local, cpu); + + if (BIT(global->guest_index_bits) <=3D guest_index) + return -EINVAL; + + if (out_msi_pa) + *out_msi_pa =3D local->msi_pa + + (guest_index * IMSIC_MMIO_PAGE_SZ); + + return 0; +} + +static int imsic_get_cpu(const struct cpumask *mask_val, bool force, + unsigned int *out_target_cpu) +{ + struct cpumask amask; + unsigned int cpu; + + cpumask_and(&amask, &imsic->lmask, mask_val); + + if (force) + cpu =3D cpumask_first(&amask); + else + cpu =3D cpumask_any_and(&amask, cpu_online_mask); + + if (cpu >=3D nr_cpu_ids) + return -EINVAL; + + if (out_target_cpu) + *out_target_cpu =3D cpu; + + return 0; +} + +static void imsic_id_set_target(unsigned int id, unsigned int target_cpu) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&imsic->ids_lock, flags); + imsic->ids_target_cpu[id] =3D target_cpu; + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); +} + +static unsigned int imsic_id_get_target(unsigned int id) +{ + unsigned int ret; + unsigned long flags; + + raw_spin_lock_irqsave(&imsic->ids_lock, flags); + ret =3D imsic->ids_target_cpu[id]; + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); + + return ret; +} + +static void __imsic_eix_update(unsigned long base_id, + unsigned long num_id, bool pend, bool val) +{ + unsigned long i, isel, ireg; + unsigned long id =3D base_id, last_id =3D base_id + num_id; + + while (id < last_id) { + isel =3D id / BITS_PER_LONG; + isel *=3D BITS_PER_LONG / IMSIC_EIPx_BITS; + isel +=3D (pend) ? IMSIC_EIP0 : IMSIC_EIE0; + + ireg =3D 0; + for (i =3D id & (__riscv_xlen - 1); + (id < last_id) && (i < __riscv_xlen); i++) { + ireg |=3D BIT(i); + id++; + } + + /* + * The IMSIC EIEx and EIPx registers are indirectly + * accessed via using ISELECT and IREG CSRs so we + * need to access these CSRs without getting preempted. + * + * All existing users of this function call this + * function with local IRQs disabled so we don't + * need to do anything special here. + */ + if (val) + imsic_csr_set(isel, ireg); + else + imsic_csr_clear(isel, ireg); + } +} + +#define __imsic_id_enable(__id) \ + __imsic_eix_update((__id), 1, false, true) +#define __imsic_id_disable(__id) \ + __imsic_eix_update((__id), 1, false, false) + +static void imsic_ids_local_sync(void) +{ + int i; + unsigned long flags; + + raw_spin_lock_irqsave(&imsic->ids_lock, flags); + for (i =3D 1; i <=3D imsic->global.nr_ids; i++) { + if (imsic->ipi_id =3D=3D i) + continue; + + if (test_bit(i, imsic->ids_enabled_bimap)) + __imsic_id_enable(i); + else + __imsic_id_disable(i); + } + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); +} + +static void imsic_ids_local_delivery(bool enable) +{ + if (enable) { + imsic_csr_write(IMSIC_EITHRESHOLD, IMSIC_ENABLE_EITHRESHOLD); + imsic_csr_write(IMSIC_EIDELIVERY, IMSIC_ENABLE_EIDELIVERY); + } else { + imsic_csr_write(IMSIC_EIDELIVERY, IMSIC_DISABLE_EIDELIVERY); + imsic_csr_write(IMSIC_EITHRESHOLD, IMSIC_DISABLE_EITHRESHOLD); + } +} + +#ifdef CONFIG_SMP +static irqreturn_t imsic_ids_sync_handler(int irq, void *data) +{ + imsic_ids_local_sync(); + return IRQ_HANDLED; +} + +static void imsic_ids_remote_sync(void) +{ + struct cpumask amask; + + /* + * We simply inject ID synchronization IPI to all target CPUs + * except current CPU. The ipi_send_mask() implementation of + * IPI mux will inject ID synchronization IPI only for CPUs + * that have enabled it so offline CPUs won't receive IPI. + * An offline CPU will unconditionally synchronize IDs through + * imsic_starting_cpu() when the CPU is brought up. + */ + cpumask_andnot(&amask, &imsic->lmask, cpumask_of(smp_processor_id())); + __ipi_send_mask(imsic->ipi_lsync_desc, &amask); +} +#else +#define imsic_ids_remote_sync() +#endif + +static int imsic_ids_alloc(unsigned int order) +{ + int ret; + unsigned long flags; + + raw_spin_lock_irqsave(&imsic->ids_lock, flags); + ret =3D bitmap_find_free_region(imsic->ids_used_bimap, + imsic->global.nr_ids + 1, order); + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); + + return ret; +} + +static void imsic_ids_free(unsigned int base_id, unsigned int order) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&imsic->ids_lock, flags); + bitmap_release_region(imsic->ids_used_bimap, base_id, order); + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); +} + +static int __init imsic_ids_init(void) +{ + int i; + struct imsic_global_config *global =3D &imsic->global; + + raw_spin_lock_init(&imsic->ids_lock); + + /* Allocate used bitmap */ + imsic->ids_used_bimap =3D bitmap_zalloc(global->nr_ids + 1, GFP_KERNEL); + if (!imsic->ids_used_bimap) + return -ENOMEM; + + /* Allocate enabled bitmap */ + imsic->ids_enabled_bimap =3D bitmap_zalloc(global->nr_ids + 1, + GFP_KERNEL); + if (!imsic->ids_enabled_bimap) { + kfree(imsic->ids_used_bimap); + return -ENOMEM; + } + + /* Allocate target CPU array */ + imsic->ids_target_cpu =3D kcalloc(global->nr_ids + 1, + sizeof(unsigned int), GFP_KERNEL); + if (!imsic->ids_target_cpu) { + bitmap_free(imsic->ids_enabled_bimap); + bitmap_free(imsic->ids_used_bimap); + return -ENOMEM; + } + for (i =3D 0; i <=3D global->nr_ids; i++) + imsic->ids_target_cpu[i] =3D UINT_MAX; + + /* Reserve ID#0 because it is special and never implemented */ + bitmap_set(imsic->ids_used_bimap, 0, 1); + + return 0; +} + +static void __init imsic_ids_cleanup(void) +{ + kfree(imsic->ids_target_cpu); + bitmap_free(imsic->ids_enabled_bimap); + bitmap_free(imsic->ids_used_bimap); +} + +#ifdef CONFIG_SMP +static void imsic_ipi_send(unsigned int cpu) +{ + struct imsic_local_config *local =3D + per_cpu_ptr(imsic->global.local, cpu); + + writel(imsic->ipi_id, local->msi_va); +} + +static void imsic_ipi_starting_cpu(void) +{ + /* Enable IPIs for current CPU. */ + __imsic_id_enable(imsic->ipi_id); + + /* Enable virtual IPI used for IMSIC ID synchronization */ + enable_percpu_irq(imsic->ipi_virq, 0); +} + +static void imsic_ipi_dying_cpu(void) +{ + /* + * Disable virtual IPI used for IMSIC ID synchronization so + * that we don't receive ID synchronization requests. + */ + disable_percpu_irq(imsic->ipi_virq); +} + +static int __init imsic_ipi_domain_init(void) +{ + int virq; + + /* Allocate interrupt identity for IPIs */ + virq =3D imsic_ids_alloc(get_count_order(1)); + if (virq < 0) + return virq; + imsic->ipi_id =3D virq; + + /* Create IMSIC IPI multiplexing */ + virq =3D ipi_mux_create(IMSIC_NR_IPI, imsic_ipi_send); + if (virq <=3D 0) { + imsic_ids_free(imsic->ipi_id, get_count_order(1)); + return (virq < 0) ? virq : -ENOMEM; + } + imsic->ipi_virq =3D virq; + + /* First vIRQ is used for IMSIC ID synchronization */ + virq =3D request_percpu_irq(imsic->ipi_virq, imsic_ids_sync_handler, + "riscv-imsic-lsync", imsic->global.local); + if (virq) { + imsic_ids_free(imsic->ipi_id, get_count_order(1)); + return virq; + } + irq_set_status_flags(imsic->ipi_virq, IRQ_HIDDEN); + imsic->ipi_lsync_desc =3D irq_to_desc(imsic->ipi_virq); + + /* Set vIRQ range */ + riscv_ipi_set_virq_range(imsic->ipi_virq + 1, IMSIC_NR_IPI - 1, true); + + return 0; +} + +static void __init imsic_ipi_domain_cleanup(void) +{ + if (imsic->ipi_lsync_desc) + free_percpu_irq(imsic->ipi_virq, imsic->global.local); + imsic_ids_free(imsic->ipi_id, get_count_order(1)); +} +#else +static void imsic_ipi_starting_cpu(void) +{ +} + +static void imsic_ipi_dying_cpu(void) +{ +} + +static int __init imsic_ipi_domain_init(void) +{ + /* Clear the IPI id because we are not using IPIs */ + imsic->ipi_id =3D 0; + return 0; +} + +static void __init imsic_ipi_domain_cleanup(void) +{ +} +#endif + +static void imsic_irq_mask(struct irq_data *d) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&imsic->ids_lock, flags); + bitmap_clear(imsic->ids_enabled_bimap, d->hwirq, 1); + __imsic_id_disable(d->hwirq); + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); + + imsic_ids_remote_sync(); +} + +static void imsic_irq_unmask(struct irq_data *d) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&imsic->ids_lock, flags); + bitmap_set(imsic->ids_enabled_bimap, d->hwirq, 1); + __imsic_id_enable(d->hwirq); + raw_spin_unlock_irqrestore(&imsic->ids_lock, flags); + + imsic_ids_remote_sync(); +} + +static void imsic_irq_compose_msi_msg(struct irq_data *d, + struct msi_msg *msg) +{ + phys_addr_t msi_addr; + unsigned int cpu; + int err; + + cpu =3D imsic_id_get_target(d->hwirq); + if (WARN_ON(cpu =3D=3D UINT_MAX)) + return; + + err =3D imsic_cpu_page_phys(cpu, 0, &msi_addr); + if (WARN_ON(err)) + return; + + msg->address_hi =3D upper_32_bits(msi_addr); + msg->address_lo =3D lower_32_bits(msi_addr); + msg->data =3D d->hwirq; +} + +#ifdef CONFIG_SMP +static int imsic_irq_set_affinity(struct irq_data *d, + const struct cpumask *mask_val, + bool force) +{ + unsigned int target_cpu; + int rc; + + rc =3D imsic_get_cpu(mask_val, force, &target_cpu); + if (rc) + return rc; + + imsic_id_set_target(d->hwirq, target_cpu); + irq_data_update_effective_affinity(d, cpumask_of(target_cpu)); + + return IRQ_SET_MASK_OK; +} +#endif + +static struct irq_chip imsic_irq_base_chip =3D { + .name =3D "RISC-V IMSIC-BASE", + .irq_mask =3D imsic_irq_mask, + .irq_unmask =3D imsic_irq_unmask, +#ifdef CONFIG_SMP + .irq_set_affinity =3D imsic_irq_set_affinity, +#endif + .irq_compose_msi_msg =3D imsic_irq_compose_msi_msg, + .flags =3D IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND, +}; + +static int imsic_irq_domain_alloc(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs, + void *args) +{ + int i, hwirq, err =3D 0; + unsigned int cpu; + + err =3D imsic_get_cpu(&imsic->lmask, false, &cpu); + if (err) + return err; + + hwirq =3D imsic_ids_alloc(get_count_order(nr_irqs)); + if (hwirq < 0) + return hwirq; + + for (i =3D 0; i < nr_irqs; i++) { + imsic_id_set_target(hwirq + i, cpu); + irq_domain_set_info(domain, virq + i, hwirq + i, + &imsic_irq_base_chip, imsic, + handle_simple_irq, NULL, NULL); + irq_set_noprobe(virq + i); + irq_set_affinity(virq + i, &imsic->lmask); + /* + * IMSIC does not implement irq_disable() so Linux interrupt + * subsystem will take a lazy approach for disabling an IMSIC + * interrupt. This means IMSIC interrupts are left unmasked + * upon system suspend and interrupts are not processed + * immediately upon system wake up. To tackle this, we disable + * the lazy approach for all IMSIC interrupts. + */ + irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY); + } + + return 0; +} + +static void imsic_irq_domain_free(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs) +{ + struct irq_data *d =3D irq_domain_get_irq_data(domain, virq); + + imsic_ids_free(d->hwirq, get_count_order(nr_irqs)); + irq_domain_free_irqs_parent(domain, virq, nr_irqs); +} + +static const struct irq_domain_ops imsic_base_domain_ops =3D { + .alloc =3D imsic_irq_domain_alloc, + .free =3D imsic_irq_domain_free, +}; + +static struct irq_chip imsic_plat_irq_chip =3D { + .name =3D "RISC-V IMSIC-PLAT", +}; + +static struct msi_domain_ops imsic_plat_domain_ops =3D { +}; + +static struct msi_domain_info imsic_plat_domain_info =3D { + .flags =3D (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), + .ops =3D &imsic_plat_domain_ops, + .chip =3D &imsic_plat_irq_chip, +}; + +static int __init imsic_irq_domains_init(struct fwnode_handle *fwnode) +{ + /* Create Base IRQ domain */ + imsic->base_domain =3D irq_domain_create_tree(fwnode, + &imsic_base_domain_ops, imsic); + if (!imsic->base_domain) { + pr_err("Failed to create IMSIC base domain\n"); + return -ENOMEM; + } + irq_domain_update_bus_token(imsic->base_domain, DOMAIN_BUS_NEXUS); + + /* Create Platform MSI domain */ + imsic->plat_domain =3D platform_msi_create_irq_domain(fwnode, + &imsic_plat_domain_info, + imsic->base_domain); + if (!imsic->plat_domain) { + pr_err("Failed to create IMSIC platform domain\n"); + irq_domain_remove(imsic->base_domain); + return -ENOMEM; + } + + return 0; +} + +/* + * To handle an interrupt, we read the TOPEI CSR and write zero in one + * instruction. If TOPEI CSR is non-zero then we translate TOPEI.ID to + * Linux interrupt number and let Linux IRQ subsystem handle it. + */ +static void imsic_handle_irq(struct irq_desc *desc) +{ + struct irq_chip *chip =3D irq_desc_get_chip(desc); + irq_hw_number_t hwirq; + int err; + + chained_irq_enter(chip, desc); + + while ((hwirq =3D csr_swap(CSR_TOPEI, 0))) { + hwirq =3D hwirq >> TOPEI_ID_SHIFT; + + if (hwirq =3D=3D imsic->ipi_id) { +#ifdef CONFIG_SMP + ipi_mux_process(); +#endif + continue; + } + + err =3D generic_handle_domain_irq(imsic->base_domain, hwirq); + if (unlikely(err)) + pr_warn_ratelimited( + "hwirq %lu mapping not found\n", hwirq); + } + + chained_irq_exit(chip, desc); +} + +static int imsic_starting_cpu(unsigned int cpu) +{ + /* Enable per-CPU parent interrupt */ + enable_percpu_irq(imsic_parent_irq, + irq_get_trigger_type(imsic_parent_irq)); + + /* Setup IPIs */ + imsic_ipi_starting_cpu(); + + /* + * Interrupts identities might have been enabled/disabled while + * this CPU was not running so sync-up local enable/disable state. + */ + imsic_ids_local_sync(); + + /* Enable local interrupt delivery */ + imsic_ids_local_delivery(true); + + return 0; +} + +static int imsic_dying_cpu(unsigned int cpu) +{ + /* Cleanup IPIs */ + imsic_ipi_dying_cpu(); + + return 0; +} + +static int __init imsic_get_parent_hartid(struct fwnode_handle *fwnode, + u32 index, unsigned long *hartid) +{ + int rc; + struct fwnode_reference_args parent; + + rc =3D fwnode_property_get_reference_args(fwnode, + "interrupts-extended", "#interrupt-cells", + 0, index, &parent); + if (rc) + return rc; + + /* + * Skip interrupts other than external interrupts for + * current privilege level. + */ + if (parent.args[0] !=3D RV_IRQ_EXT) + return -EINVAL; + + return riscv_fw_parent_hartid(parent.fwnode, hartid); +} + +static int __init imsic_get_mmio_resource(struct fwnode_handle *fwnode, + u32 index, struct resource *res) +{ + /* + * Currently, only OF fwnode is support so extend this function + * for other types of fwnode for ACPI support. + */ + if (!is_of_node(fwnode)) + return -EINVAL; + return of_address_to_resource(to_of_node(fwnode), index, res); +} + +static int __init imsic_init(struct fwnode_handle *fwnode) +{ + int rc, cpu; + phys_addr_t base_addr; + struct irq_domain *domain; + void __iomem **mmios_va =3D NULL; + struct resource res, *mmios =3D NULL; + struct imsic_local_config *local; + struct imsic_global_config *global; + unsigned long reloff, hartid; + u32 i, j, index, nr_parent_irqs, nr_handlers =3D 0, num_mmios =3D 0; + + /* + * Only one IMSIC instance allowed in a platform for clean + * implementation of SMP IRQ affinity and per-CPU IPIs. + * + * This means on a multi-socket (or multi-die) platform we + * will have multiple MMIO regions for one IMSIC instance. + */ + if (imsic) { + pr_err("%pfwP: already initialized hence ignoring\n", + fwnode); + return -ENODEV; + } + + if (!riscv_isa_extension_available(NULL, SxAIA)) { + pr_err("%pfwP: AIA support not available\n", fwnode); + return -ENODEV; + } + + imsic =3D kzalloc(sizeof(*imsic), GFP_KERNEL); + if (!imsic) + return -ENOMEM; + global =3D &imsic->global; + + global->local =3D alloc_percpu(typeof(*(global->local))); + if (!global->local) { + rc =3D -ENOMEM; + goto out_free_priv; + } + + /* Find number of parent interrupts */ + nr_parent_irqs =3D 0; + while (!imsic_get_parent_hartid(fwnode, nr_parent_irqs, &hartid)) + nr_parent_irqs++; + if (!nr_parent_irqs) { + pr_err("%pfwP: no parent irqs available\n", fwnode); + rc =3D -EINVAL; + goto out_free_local; + } + + /* Find number of guest index bits in MSI address */ + rc =3D fwnode_property_read_u32_array(fwnode, "riscv,guest-index-bits", + &global->guest_index_bits, 1); + if (rc) + global->guest_index_bits =3D 0; + i =3D BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT; + if (i < global->guest_index_bits) { + pr_err("%pfwP: guest index bits too big\n", fwnode); + rc =3D -EINVAL; + goto out_free_local; + } + + /* Find number of HART index bits */ + rc =3D fwnode_property_read_u32_array(fwnode, "riscv,hart-index-bits", + &global->hart_index_bits, 1); + if (rc) { + /* Assume default value */ + global->hart_index_bits =3D __fls(nr_parent_irqs); + if (BIT(global->hart_index_bits) < nr_parent_irqs) + global->hart_index_bits++; + } + i =3D BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT - global->guest_index_bits; + if (i < global->hart_index_bits) { + pr_err("%pfwP: HART index bits too big\n", fwnode); + rc =3D -EINVAL; + goto out_free_local; + } + + /* Find number of group index bits */ + rc =3D fwnode_property_read_u32_array(fwnode, "riscv,group-index-bits", + &global->group_index_bits, 1); + if (rc) + global->group_index_bits =3D 0; + i =3D BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT - + global->guest_index_bits - global->hart_index_bits; + if (i < global->group_index_bits) { + pr_err("%pfwP: group index bits too big\n", fwnode); + rc =3D -EINVAL; + goto out_free_local; + } + + /* + * Find first bit position of group index. + * If not specified assumed the default APLIC-IMSIC configuration. + */ + rc =3D fwnode_property_read_u32_array(fwnode, "riscv,group-index-shift", + &global->group_index_shift, 1); + if (rc) + global->group_index_shift =3D IMSIC_MMIO_PAGE_SHIFT * 2; + i =3D global->group_index_bits + global->group_index_shift - 1; + if (i >=3D BITS_PER_LONG) { + pr_err("%pfwP: group index shift too big\n", fwnode); + rc =3D -EINVAL; + goto out_free_local; + } + + /* Find number of interrupt identities */ + rc =3D fwnode_property_read_u32_array(fwnode, "riscv,num-ids", + &global->nr_ids, 1); + if (rc) { + pr_err("%pfwP: number of interrupt identities not found\n", + fwnode); + goto out_free_local; + } + if ((global->nr_ids < IMSIC_MIN_ID) || + (global->nr_ids >=3D IMSIC_MAX_ID) || + ((global->nr_ids & IMSIC_MIN_ID) !=3D IMSIC_MIN_ID)) { + pr_err("%pfwP: invalid number of interrupt identities\n", + fwnode); + rc =3D -EINVAL; + goto out_free_local; + } + + /* Find number of guest interrupt identities */ + if (fwnode_property_read_u32_array(fwnode, "riscv,num-guest-ids", + &global->nr_guest_ids, 1)) + global->nr_guest_ids =3D global->nr_ids; + if ((global->nr_guest_ids < IMSIC_MIN_ID) || + (global->nr_guest_ids >=3D IMSIC_MAX_ID) || + ((global->nr_guest_ids & IMSIC_MIN_ID) !=3D IMSIC_MIN_ID)) { + pr_err("%pfwP: invalid number of guest interrupt identities\n", + fwnode); + rc =3D -EINVAL; + goto out_free_local; + } + + /* Compute base address */ + rc =3D imsic_get_mmio_resource(fwnode, 0, &res); + if (rc) { + pr_err("%pfwP: first MMIO resource not found\n", fwnode); + rc =3D -EINVAL; + goto out_free_local; + } + global->base_addr =3D res.start; + global->base_addr &=3D ~(BIT(global->guest_index_bits + + global->hart_index_bits + + IMSIC_MMIO_PAGE_SHIFT) - 1); + global->base_addr &=3D ~((BIT(global->group_index_bits) - 1) << + global->group_index_shift); + + /* Find number of MMIO register sets */ + while (!imsic_get_mmio_resource(fwnode, num_mmios, &res)) + num_mmios++; + + /* Allocate MMIO resource array */ + mmios =3D kcalloc(num_mmios, sizeof(*mmios), GFP_KERNEL); + if (!mmios) { + rc =3D -ENOMEM; + goto out_free_local; + } + + /* Allocate MMIO virtual address array */ + mmios_va =3D kcalloc(num_mmios, sizeof(*mmios_va), GFP_KERNEL); + if (!mmios_va) { + rc =3D -ENOMEM; + goto out_iounmap; + } + + /* Parse and map MMIO register sets */ + for (i =3D 0; i < num_mmios; i++) { + rc =3D imsic_get_mmio_resource(fwnode, i, &mmios[i]); + if (rc) { + pr_err("%pfwP: unable to parse MMIO regset %d\n", + fwnode, i); + goto out_iounmap; + } + + base_addr =3D mmios[i].start; + base_addr &=3D ~(BIT(global->guest_index_bits + + global->hart_index_bits + + IMSIC_MMIO_PAGE_SHIFT) - 1); + base_addr &=3D ~((BIT(global->group_index_bits) - 1) << + global->group_index_shift); + if (base_addr !=3D global->base_addr) { + rc =3D -EINVAL; + pr_err("%pfwP: address mismatch for regset %d\n", + fwnode, i); + goto out_iounmap; + } + + mmios_va[i] =3D ioremap(mmios[i].start, resource_size(&mmios[i])); + if (!mmios_va[i]) { + rc =3D -EIO; + pr_err("%pfwP: unable to map MMIO regset %d\n", + fwnode, i); + goto out_iounmap; + } + } + + /* Initialize interrupt identity management */ + rc =3D imsic_ids_init(); + if (rc) { + pr_err("%pfwP: failed to initialize interrupt management\n", + fwnode); + goto out_iounmap; + } + + /* Configure handlers for target CPUs */ + for (i =3D 0; i < nr_parent_irqs; i++) { + rc =3D imsic_get_parent_hartid(fwnode, i, &hartid); + if (rc) { + pr_warn("%pfwP: hart ID for parent irq%d not found\n", + fwnode, i); + continue; + } + + cpu =3D riscv_hartid_to_cpuid(hartid); + if (cpu < 0) { + pr_warn("%pfwP: invalid cpuid for parent irq%d\n", + fwnode, i); + continue; + } + + /* Find MMIO location of MSI page */ + index =3D num_mmios; + reloff =3D i * BIT(global->guest_index_bits) * + IMSIC_MMIO_PAGE_SZ; + for (j =3D 0; num_mmios; j++) { + if (reloff < resource_size(&mmios[j])) { + index =3D j; + break; + } + + /* + * MMIO region size may not be aligned to + * BIT(global->guest_index_bits) * IMSIC_MMIO_PAGE_SZ + * if holes are present. + */ + reloff -=3D ALIGN(resource_size(&mmios[j]), + BIT(global->guest_index_bits) * IMSIC_MMIO_PAGE_SZ); + } + if (index >=3D num_mmios) { + pr_warn("%pfwP: MMIO not found for parent irq%d\n", + fwnode, i); + continue; + } + + cpumask_set_cpu(cpu, &imsic->lmask); + + local =3D per_cpu_ptr(global->local, cpu); + local->msi_pa =3D mmios[index].start + reloff; + local->msi_va =3D mmios_va[index] + reloff; + + nr_handlers++; + } + + /* If no CPU handlers found then can't take interrupts */ + if (!nr_handlers) { + pr_err("%pfwP: No CPU handlers found\n", fwnode); + rc =3D -ENODEV; + goto out_ids_cleanup; + } + + /* Find parent domain and register chained handler */ + domain =3D irq_find_matching_fwnode(riscv_get_intc_hwnode(), + DOMAIN_BUS_ANY); + if (!domain) { + pr_err("%pfwP: Failed to find INTC domain\n", fwnode); + rc =3D -ENOENT; + goto out_ids_cleanup; + } + imsic_parent_irq =3D irq_create_mapping(domain, RV_IRQ_EXT); + if (!imsic_parent_irq) { + pr_err("%pfwP: Failed to create INTC mapping\n", fwnode); + rc =3D -ENOENT; + goto out_ids_cleanup; + } + irq_set_chained_handler(imsic_parent_irq, imsic_handle_irq); + + /* Initialize IPI domain */ + rc =3D imsic_ipi_domain_init(); + if (rc) { + pr_err("%pfwP: Failed to initialize IPI domain\n", fwnode); + goto out_ids_cleanup; + } + + /* Initialize IRQ and MSI domains */ + rc =3D imsic_irq_domains_init(fwnode); + if (rc) { + pr_err("%pfwP: Failed to initialize IRQ and MSI domains\n", + fwnode); + goto out_ipi_domain_cleanup; + } + + /* + * Setup cpuhp state (must be done after setting imsic_parent_irq) + * + * Don't disable per-CPU IMSIC file when CPU goes offline + * because this affects IPI and the masking/unmasking of + * virtual IPIs is done via generic IPI-Mux + */ + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, + "irqchip/riscv/imsic:starting", + imsic_starting_cpu, imsic_dying_cpu); + + /* We don't need MMIO arrays anymore so let's free-up */ + kfree(mmios_va); + kfree(mmios); + + pr_info("%pfwP: hart-index-bits: %d, guest-index-bits: %d\n", + fwnode, global->hart_index_bits, global->guest_index_bits); + pr_info("%pfwP: group-index-bits: %d, group-index-shift: %d\n", + fwnode, global->group_index_bits, global->group_index_shift); + pr_info("%pfwP: mapped %d interrupts for %d CPUs at %pa\n", + fwnode, global->nr_ids, nr_handlers, &global->base_addr); + if (imsic->ipi_id) + pr_info("%pfwP: providing IPIs using interrupt %d\n", + fwnode, imsic->ipi_id); + + return 0; + +out_ipi_domain_cleanup: + imsic_ipi_domain_cleanup(); +out_ids_cleanup: + imsic_ids_cleanup(); +out_iounmap: + for (i =3D 0; i < num_mmios; i++) { + if (mmios_va[i]) + iounmap(mmios_va[i]); + } + kfree(mmios_va); + kfree(mmios); +out_free_local: + free_percpu(imsic->global.local); +out_free_priv: + kfree(imsic); + imsic =3D NULL; + return rc; +} + +static int __init imsic_dt_init(struct device_node *node, + struct device_node *parent) +{ + return imsic_init(&node->fwnode); +} +IRQCHIP_DECLARE(riscv_imsic, "riscv,imsics", imsic_dt_init); diff --git a/include/linux/irqchip/riscv-imsic.h b/include/linux/irqchip/ri= scv-imsic.h new file mode 100644 index 000000000000..1f6fc9a57218 --- /dev/null +++ b/include/linux/irqchip/riscv-imsic.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ +#ifndef __LINUX_IRQCHIP_RISCV_IMSIC_H +#define __LINUX_IRQCHIP_RISCV_IMSIC_H + +#include +#include + +#define IMSIC_MMIO_PAGE_SHIFT 12 +#define IMSIC_MMIO_PAGE_SZ (1UL << IMSIC_MMIO_PAGE_SHIFT) +#define IMSIC_MMIO_PAGE_LE 0x00 +#define IMSIC_MMIO_PAGE_BE 0x04 + +#define IMSIC_MIN_ID 63 +#define IMSIC_MAX_ID 2048 + +#define IMSIC_EIDELIVERY 0x70 + +#define IMSIC_EITHRESHOLD 0x72 + +#define IMSIC_EIP0 0x80 +#define IMSIC_EIP63 0xbf +#define IMSIC_EIPx_BITS 32 + +#define IMSIC_EIE0 0xc0 +#define IMSIC_EIE63 0xff +#define IMSIC_EIEx_BITS 32 + +#define IMSIC_FIRST IMSIC_EIDELIVERY +#define IMSIC_LAST IMSIC_EIE63 + +#define IMSIC_MMIO_SETIPNUM_LE 0x00 +#define IMSIC_MMIO_SETIPNUM_BE 0x04 + +struct imsic_local_config { + phys_addr_t msi_pa; + void __iomem *msi_va; +}; + +struct imsic_global_config { + /* + * MSI Target Address Scheme + * + * XLEN-1 12 0 + * | | | + * ------------------------------------------------------------- + * |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 | + * ------------------------------------------------------------- + */ + + /* Bits representing Guest index, HART index, and Group index */ + u32 guest_index_bits; + u32 hart_index_bits; + u32 group_index_bits; + u32 group_index_shift; + + /* Global base address matching all target MSI addresses */ + phys_addr_t base_addr; + + /* Number of interrupt identities */ + u32 nr_ids; + + /* Number of guest interrupt identities */ + u32 nr_guest_ids; + + /* Per-CPU IMSIC addresses */ + struct imsic_local_config __percpu *local; +}; + +#ifdef CONFIG_RISCV_IMSIC + +extern const struct imsic_global_config *imsic_get_global_config(void); + +#else + +static inline const struct imsic_global_config *imsic_get_global_config(vo= id) +{ + return NULL; +} + +#endif + +#endif --=20 2.34.1 From nobody Sat Feb 7 11:30:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41562EB64D9 for ; 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Mon, 10 Jul 2023 02:44:12 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id k1-20020a6b7a41000000b007870c56387dsm936938iop.49.2023.07.10.02.44.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jul 2023 02:44:12 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski Cc: Atish Patra , Andrew Jones , Sunil V L , Conor Dooley , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v5 5/9] irqchip/riscv-imsic: Add support for PCI MSI irqdomain Date: Mon, 10 Jul 2023 15:13:17 +0530 Message-Id: <20230710094321.1378351-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230710094321.1378351-1-apatel@ventanamicro.com> References: <20230710094321.1378351-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Linux PCI framework requires it's own dedicated MSI irqdomain so let us create PCI MSI irqdomain as child of the IMSIC base irqdomain. Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 7 +++++ drivers/irqchip/irq-riscv-imsic.c | 49 +++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 8ef18be5f37b..d700980372ef 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -550,6 +550,13 @@ config RISCV_IMSIC select IRQ_DOMAIN_HIERARCHY select GENERIC_MSI_IRQ =20 +config RISCV_IMSIC_PCI + bool + depends on RISCV_IMSIC + depends on PCI + depends on PCI_MSI + default RISCV_IMSIC + config EXYNOS_IRQ_COMBINER bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST diff --git a/drivers/irqchip/irq-riscv-imsic.c b/drivers/irqchip/irq-riscv-= imsic.c index ceb5e0fc883c..061bba1b69a2 100644 --- a/drivers/irqchip/irq-riscv-imsic.c +++ b/drivers/irqchip/irq-riscv-imsic.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -80,6 +81,7 @@ struct imsic_priv { =20 /* IRQ domains */ struct irq_domain *base_domain; + struct irq_domain *pci_domain; struct irq_domain *plat_domain; }; =20 @@ -530,6 +532,39 @@ static const struct irq_domain_ops imsic_base_domain_o= ps =3D { .free =3D imsic_irq_domain_free, }; =20 +#ifdef CONFIG_RISCV_IMSIC_PCI + +static void imsic_pci_mask_irq(struct irq_data *d) +{ + pci_msi_mask_irq(d); + irq_chip_mask_parent(d); +} + +static void imsic_pci_unmask_irq(struct irq_data *d) +{ + pci_msi_unmask_irq(d); + irq_chip_unmask_parent(d); +} + +static struct irq_chip imsic_pci_irq_chip =3D { + .name =3D "RISC-V IMSIC-PCI", + .irq_mask =3D imsic_pci_mask_irq, + .irq_unmask =3D imsic_pci_unmask_irq, + .irq_eoi =3D irq_chip_eoi_parent, +}; + +static struct msi_domain_ops imsic_pci_domain_ops =3D { +}; + +static struct msi_domain_info imsic_pci_domain_info =3D { + .flags =3D (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), + .ops =3D &imsic_pci_domain_ops, + .chip =3D &imsic_pci_irq_chip, +}; + +#endif + static struct irq_chip imsic_plat_irq_chip =3D { .name =3D "RISC-V IMSIC-PLAT", }; @@ -554,12 +589,26 @@ static int __init imsic_irq_domains_init(struct fwnod= e_handle *fwnode) } irq_domain_update_bus_token(imsic->base_domain, DOMAIN_BUS_NEXUS); =20 +#ifdef CONFIG_RISCV_IMSIC_PCI + /* Create PCI MSI domain */ + imsic->pci_domain =3D pci_msi_create_irq_domain(fwnode, + &imsic_pci_domain_info, + imsic->base_domain); + if (!imsic->pci_domain) { + pr_err("Failed to create IMSIC PCI domain\n"); + irq_domain_remove(imsic->base_domain); + return -ENOMEM; + } +#endif + /* Create Platform MSI domain */ imsic->plat_domain =3D platform_msi_create_irq_domain(fwnode, &imsic_plat_domain_info, imsic->base_domain); if (!imsic->plat_domain) { pr_err("Failed to create IMSIC platform domain\n"); + if (imsic->pci_domain) + irq_domain_remove(imsic->pci_domain); irq_domain_remove(imsic->base_domain); return -ENOMEM; } --=20 2.34.1 From nobody Sat Feb 7 11:30:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 560C7EB64DC for ; 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charset="utf-8" We add DT bindings document for RISC-V advanced platform level interrupt controller (APLIC) defined by the RISC-V advanced interrupt architecture (AIA) specification. Signed-off-by: Anup Patel Reviewed-by: Conor Dooley --- .../interrupt-controller/riscv,aplic.yaml | 172 ++++++++++++++++++ 1 file changed, 172 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= riscv,aplic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,a= plic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,ap= lic.yaml new file mode 100644 index 000000000000..190a6499c932 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.ya= ml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Advanced Platform Level Interrupt Controller (APLIC) + +maintainers: + - Anup Patel + +description: + The RISC-V advanced interrupt architecture (AIA) defines an advanced + platform level interrupt controller (APLIC) for handling wired interrupts + in a RISC-V platform. The RISC-V AIA specification can be found at + https://github.com/riscv/riscv-aia. + + The RISC-V APLIC is implemented as hierarchical APLIC domains where all + interrupt sources connect to the root APLIC domain and a parent APLIC + domain can delegate interrupt sources to it's child APLIC domains. There + is one device tree node for each APLIC domain. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + items: + - enum: + - qemu,aplic + - const: riscv,aplic + + reg: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts-extended: + minItems: 1 + maxItems: 16384 + description: + Given APLIC domain directly injects external interrupts to a set of + RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-i= ntc + node, which has a CPU node (i.e. RISC-V HART) as parent. + + msi-parent: + description: + Given APLIC domain forwards wired interrupts as MSIs to a AIA incomi= ng + message signaled interrupt controller (IMSIC). If both "msi-parent" = and + "interrupts-extended" properties are present then it means the APLIC + domain supports both MSI mode and Direct mode in HW. In this case, t= he + APLIC driver has to choose between MSI mode or Direct mode. + + riscv,num-sources: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 1023 + description: + Specifies the number of wired interrupt sources supported by this + APLIC domain. + + riscv,children: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 1024 + items: + maxItems: 1 + description: + A list of child APLIC domains for the given APLIC domain. Each child + APLIC domain is assigned a child index in increasing order, with the + first child APLIC domain assigned child index 0. The APLIC domain ch= ild + index is used by firmware to delegate interrupts from the given APLIC + domain to a particular child APLIC domain. + + riscv,delegation: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 1024 + items: + items: + - description: child APLIC domain phandle + - description: first interrupt number of the parent APLIC domain (= inclusive) + - description: last interrupt number of the parent APLIC domain (i= nclusive) + description: + A interrupt delegation list where each entry is a triple consisting + of child APLIC domain phandle, first interrupt number of the parent + APLIC domain, and last interrupt number of the parent APLIC domain. + Firmware must configure interrupt delegation registers based on + interrupt delegation list. + +dependencies: + riscv,delegation: [ "riscv,children" ] + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + - riscv,num-sources + +anyOf: + - required: + - interrupts-extended + - required: + - msi-parent + +unevaluatedProperties: false + +examples: + - | + // Example 1 (APLIC domains directly injecting interrupt to HARTs): + + interrupt-controller@c000000 { + compatible =3D "qemu,aplic", "riscv,aplic"; + interrupts-extended =3D <&cpu1_intc 11>, + <&cpu2_intc 11>, + <&cpu3_intc 11>, + <&cpu4_intc 11>; + reg =3D <0xc000000 0x4080>; + interrupt-controller; + #interrupt-cells =3D <2>; + riscv,num-sources =3D <63>; + riscv,children =3D <&aplic1>, <&aplic2>; + riscv,delegation =3D <&aplic1 1 63>; + }; + + aplic1: interrupt-controller@d000000 { + compatible =3D "qemu,aplic", "riscv,aplic"; + interrupts-extended =3D <&cpu1_intc 9>, + <&cpu2_intc 9>; + reg =3D <0xd000000 0x4080>; + interrupt-controller; + #interrupt-cells =3D <2>; + riscv,num-sources =3D <63>; + }; + + aplic2: interrupt-controller@e000000 { + compatible =3D "qemu,aplic", "riscv,aplic"; + interrupts-extended =3D <&cpu3_intc 9>, + <&cpu4_intc 9>; + reg =3D <0xe000000 0x4080>; + interrupt-controller; + #interrupt-cells =3D <2>; + riscv,num-sources =3D <63>; + }; + + - | + // Example 2 (APLIC domains forwarding interrupts as MSIs): + + interrupt-controller@c000000 { + compatible =3D "qemu,aplic", "riscv,aplic"; + msi-parent =3D <&imsic_mlevel>; + reg =3D <0xc000000 0x4000>; + interrupt-controller; + #interrupt-cells =3D <2>; + riscv,num-sources =3D <63>; + riscv,children =3D <&aplic3>; + riscv,delegation =3D <&aplic3 1 63>; + }; + + aplic3: interrupt-controller@d000000 { + compatible =3D "qemu,aplic", "riscv,aplic"; + msi-parent =3D <&imsic_slevel>; + reg =3D <0xd000000 0x4000>; + interrupt-controller; + #interrupt-cells =3D <2>; + riscv,num-sources =3D <63>; + }; +... --=20 2.34.1 From nobody Sat Feb 7 11:30:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DA86EB64D9 for ; Mon, 10 Jul 2023 09:50:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231493AbjGJJuY (ORCPT ); Mon, 10 Jul 2023 05:50:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232986AbjGJJtQ (ORCPT ); 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Mon, 10 Jul 2023 02:44:26 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski Cc: Atish Patra , Andrew Jones , Sunil V L , Conor Dooley , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v5 7/9] irqchip: Add RISC-V advanced PLIC driver Date: Mon, 10 Jul 2023 15:13:19 +0530 Message-Id: <20230710094321.1378351-8-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230710094321.1378351-1-apatel@ventanamicro.com> References: <20230710094321.1378351-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The RISC-V advanced interrupt architecture (AIA) specification defines a new interrupt controller for managing wired interrupts on a RISC-V platform. This new interrupt controller is referred to as advanced platform-level interrupt controller (APLIC) which can forward wired interrupts to CPUs (or HARTs) as local interrupts OR as message signaled interrupts. (For more details refer https://github.com/riscv/riscv-aia) This patch adds an irqchip driver for RISC-V APLIC found on RISC-V platforms. Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 6 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-riscv-aplic.c | 774 ++++++++++++++++++++++++++++ include/linux/irqchip/riscv-aplic.h | 119 +++++ 4 files changed, 900 insertions(+) create mode 100644 drivers/irqchip/irq-riscv-aplic.c create mode 100644 include/linux/irqchip/riscv-aplic.h diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index d700980372ef..834c0329f583 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -544,6 +544,12 @@ config SIFIVE_PLIC select IRQ_DOMAIN_HIERARCHY select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP =20 +config RISCV_APLIC + bool + depends on RISCV + select IRQ_DOMAIN_HIERARCHY + select GENERIC_MSI_IRQ + config RISCV_IMSIC bool depends on RISCV diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 577bde3e986b..438b8e1a152c 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -95,6 +95,7 @@ obj-$(CONFIG_QCOM_MPM) +=3D irq-qcom-mpm.o obj-$(CONFIG_CSKY_MPINTC) +=3D irq-csky-mpintc.o obj-$(CONFIG_CSKY_APB_INTC) +=3D irq-csky-apb-intc.o obj-$(CONFIG_RISCV_INTC) +=3D irq-riscv-intc.o +obj-$(CONFIG_RISCV_APLIC) +=3D irq-riscv-aplic.o obj-$(CONFIG_RISCV_IMSIC) +=3D irq-riscv-imsic.o obj-$(CONFIG_SIFIVE_PLIC) +=3D irq-sifive-plic.o obj-$(CONFIG_IMX_IRQSTEER) +=3D irq-imx-irqsteer.o diff --git a/drivers/irqchip/irq-riscv-aplic.c b/drivers/irqchip/irq-riscv-= aplic.c new file mode 100644 index 000000000000..b4db29d4179b --- /dev/null +++ b/drivers/irqchip/irq-riscv-aplic.c @@ -0,0 +1,774 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#define pr_fmt(fmt) "riscv-aplic: " fmt +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define APLIC_DEFAULT_PRIORITY 1 +#define APLIC_DISABLE_IDELIVERY 0 +#define APLIC_ENABLE_IDELIVERY 1 +#define APLIC_DISABLE_ITHRESHOLD 1 +#define APLIC_ENABLE_ITHRESHOLD 0 + +struct aplic_msicfg { + phys_addr_t base_ppn; + u32 hhxs; + u32 hhxw; + u32 lhxs; + u32 lhxw; +}; + +struct aplic_idc { + unsigned int hart_index; + void __iomem *regs; + struct aplic_priv *priv; +}; + +struct aplic_priv { + struct fwnode_handle *fwnode; + u32 gsi_base; + u32 nr_irqs; + u32 nr_idcs; + void __iomem *regs; + struct irq_domain *irqdomain; + struct aplic_msicfg msicfg; + struct cpumask lmask; +}; + +static unsigned int aplic_idc_parent_irq; +static DEFINE_PER_CPU(struct aplic_idc, aplic_idcs); + +static void aplic_irq_unmask(struct irq_data *d) +{ + struct aplic_priv *priv =3D irq_data_get_irq_chip_data(d); + + writel(d->hwirq, priv->regs + APLIC_SETIENUM); + + if (!priv->nr_idcs) + irq_chip_unmask_parent(d); +} + +static void aplic_irq_mask(struct irq_data *d) +{ + struct aplic_priv *priv =3D irq_data_get_irq_chip_data(d); + + writel(d->hwirq, priv->regs + APLIC_CLRIENUM); + + if (!priv->nr_idcs) + irq_chip_mask_parent(d); +} + +static int aplic_set_type(struct irq_data *d, unsigned int type) +{ + u32 val =3D 0; + void __iomem *sourcecfg; + struct aplic_priv *priv =3D irq_data_get_irq_chip_data(d); + + switch (type) { + case IRQ_TYPE_NONE: + val =3D APLIC_SOURCECFG_SM_INACTIVE; + break; + case IRQ_TYPE_LEVEL_LOW: + val =3D APLIC_SOURCECFG_SM_LEVEL_LOW; + break; + case IRQ_TYPE_LEVEL_HIGH: + val =3D APLIC_SOURCECFG_SM_LEVEL_HIGH; + break; + case IRQ_TYPE_EDGE_FALLING: + val =3D APLIC_SOURCECFG_SM_EDGE_FALL; + break; + case IRQ_TYPE_EDGE_RISING: + val =3D APLIC_SOURCECFG_SM_EDGE_RISE; + break; + default: + return -EINVAL; + } + + sourcecfg =3D priv->regs + APLIC_SOURCECFG_BASE; + sourcecfg +=3D (d->hwirq - 1) * sizeof(u32); + writel(val, sourcecfg); + + return 0; +} + +static void aplic_irq_eoi(struct irq_data *d) +{ + struct aplic_priv *priv =3D irq_data_get_irq_chip_data(d); + u32 reg_off, reg_mask; + + /* + * EOI handling only required only for level-triggered + * interrupts in APLIC MSI mode. + */ + + if (priv->nr_idcs) + return; + + reg_off =3D APLIC_CLRIP_BASE + ((d->hwirq / APLIC_IRQBITS_PER_REG) * 4); + reg_mask =3D BIT(d->hwirq % APLIC_IRQBITS_PER_REG); + switch (irqd_get_trigger_type(d)) { + case IRQ_TYPE_LEVEL_LOW: + if (!(readl(priv->regs + reg_off) & reg_mask)) + writel(d->hwirq, priv->regs + APLIC_SETIPNUM_LE); + break; + case IRQ_TYPE_LEVEL_HIGH: + if (readl(priv->regs + reg_off) & reg_mask) + writel(d->hwirq, priv->regs + APLIC_SETIPNUM_LE); + break; + } +} + +#ifdef CONFIG_SMP +static int aplic_set_affinity(struct irq_data *d, + const struct cpumask *mask_val, bool force) +{ + struct aplic_priv *priv =3D irq_data_get_irq_chip_data(d); + struct aplic_idc *idc; + unsigned int cpu, val; + struct cpumask amask; + void __iomem *target; + + if (!priv->nr_idcs) + return irq_chip_set_affinity_parent(d, mask_val, force); + + cpumask_and(&amask, &priv->lmask, mask_val); + + if (force) + cpu =3D cpumask_first(&amask); + else + cpu =3D cpumask_any_and(&amask, cpu_online_mask); + + if (cpu >=3D nr_cpu_ids) + return -EINVAL; + + idc =3D per_cpu_ptr(&aplic_idcs, cpu); + target =3D priv->regs + APLIC_TARGET_BASE; + target +=3D (d->hwirq - 1) * sizeof(u32); + val =3D idc->hart_index & APLIC_TARGET_HART_IDX_MASK; + val <<=3D APLIC_TARGET_HART_IDX_SHIFT; + val |=3D APLIC_DEFAULT_PRIORITY; + writel(val, target); + + irq_data_update_effective_affinity(d, cpumask_of(cpu)); + + return IRQ_SET_MASK_OK_DONE; +} +#endif + +static struct irq_chip aplic_chip =3D { + .name =3D "RISC-V APLIC", + .irq_mask =3D aplic_irq_mask, + .irq_unmask =3D aplic_irq_unmask, + .irq_set_type =3D aplic_set_type, + .irq_eoi =3D aplic_irq_eoi, +#ifdef CONFIG_SMP + .irq_set_affinity =3D aplic_set_affinity, +#endif + .flags =3D IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND, +}; + +static int aplic_irqdomain_translate(struct irq_fwspec *fwspec, + u32 gsi_base, + unsigned long *hwirq, + unsigned int *type) +{ + if (WARN_ON(fwspec->param_count < 2)) + return -EINVAL; + if (WARN_ON(!fwspec->param[0])) + return -EINVAL; + + /* For DT, gsi_base is always zero. */ + *hwirq =3D fwspec->param[0] - gsi_base; + *type =3D fwspec->param[1] & IRQ_TYPE_SENSE_MASK; + + WARN_ON(*type =3D=3D IRQ_TYPE_NONE); + + return 0; +} + +static int aplic_irqdomain_msi_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + struct aplic_priv *priv =3D platform_msi_get_host_data(d); + + return aplic_irqdomain_translate(fwspec, priv->gsi_base, hwirq, type); +} + +static int aplic_irqdomain_msi_alloc(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs, + void *arg) +{ + int i, ret; + unsigned int type; + irq_hw_number_t hwirq; + struct irq_fwspec *fwspec =3D arg; + struct aplic_priv *priv =3D platform_msi_get_host_data(domain); + + ret =3D aplic_irqdomain_translate(fwspec, priv->gsi_base, &hwirq, &type); + if (ret) + return ret; + + ret =3D platform_msi_device_domain_alloc(domain, virq, nr_irqs); + if (ret) + return ret; + + for (i =3D 0; i < nr_irqs; i++) { + irq_domain_set_info(domain, virq + i, hwirq + i, + &aplic_chip, priv, handle_fasteoi_irq, + NULL, NULL); + /* + * APLIC does not implement irq_disable() so Linux interrupt + * subsystem will take a lazy approach for disabling an APLIC + * interrupt. This means APLIC interrupts are left unmasked + * upon system suspend and interrupts are not processed + * immediately upon system wake up. To tackle this, we disable + * the lazy approach for all APLIC interrupts. + */ + irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY); + } + + return 0; +} + +static const struct irq_domain_ops aplic_irqdomain_msi_ops =3D { + .translate =3D aplic_irqdomain_msi_translate, + .alloc =3D aplic_irqdomain_msi_alloc, + .free =3D platform_msi_device_domain_free, +}; + +static int aplic_irqdomain_idc_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + struct aplic_priv *priv =3D d->host_data; + + return aplic_irqdomain_translate(fwspec, priv->gsi_base, hwirq, type); +} + +static int aplic_irqdomain_idc_alloc(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs, + void *arg) +{ + int i, ret; + unsigned int type; + irq_hw_number_t hwirq; + struct irq_fwspec *fwspec =3D arg; + struct aplic_priv *priv =3D domain->host_data; + + ret =3D aplic_irqdomain_translate(fwspec, priv->gsi_base, &hwirq, &type); + if (ret) + return ret; + + for (i =3D 0; i < nr_irqs; i++) { + irq_domain_set_info(domain, virq + i, hwirq + i, + &aplic_chip, priv, handle_fasteoi_irq, + NULL, NULL); + irq_set_affinity(virq + i, &priv->lmask); + /* See the reason described in aplic_irqdomain_msi_alloc() */ + irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY); + } + + return 0; +} + +static const struct irq_domain_ops aplic_irqdomain_idc_ops =3D { + .translate =3D aplic_irqdomain_idc_translate, + .alloc =3D aplic_irqdomain_idc_alloc, + .free =3D irq_domain_free_irqs_top, +}; + +static void aplic_init_hw_irqs(struct aplic_priv *priv) +{ + int i; + + /* Disable all interrupts */ + for (i =3D 0; i <=3D priv->nr_irqs; i +=3D 32) + writel(-1U, priv->regs + APLIC_CLRIE_BASE + + (i / 32) * sizeof(u32)); + + /* Set interrupt type and default priority for all interrupts */ + for (i =3D 1; i <=3D priv->nr_irqs; i++) { + writel(0, priv->regs + APLIC_SOURCECFG_BASE + + (i - 1) * sizeof(u32)); + writel(APLIC_DEFAULT_PRIORITY, + priv->regs + APLIC_TARGET_BASE + + (i - 1) * sizeof(u32)); + } + + /* Clear APLIC domaincfg */ + writel(0, priv->regs + APLIC_DOMAINCFG); +} + +static void aplic_init_hw_global(struct aplic_priv *priv) +{ + u32 val; +#ifdef CONFIG_RISCV_M_MODE + u32 valH; + + if (!priv->nr_idcs) { + val =3D priv->msicfg.base_ppn; + valH =3D (priv->msicfg.base_ppn >> 32) & + APLIC_xMSICFGADDRH_BAPPN_MASK; + valH |=3D (priv->msicfg.lhxw & APLIC_xMSICFGADDRH_LHXW_MASK) + << APLIC_xMSICFGADDRH_LHXW_SHIFT; + valH |=3D (priv->msicfg.hhxw & APLIC_xMSICFGADDRH_HHXW_MASK) + << APLIC_xMSICFGADDRH_HHXW_SHIFT; + valH |=3D (priv->msicfg.lhxs & APLIC_xMSICFGADDRH_LHXS_MASK) + << APLIC_xMSICFGADDRH_LHXS_SHIFT; + valH |=3D (priv->msicfg.hhxs & APLIC_xMSICFGADDRH_HHXS_MASK) + << APLIC_xMSICFGADDRH_HHXS_SHIFT; + writel(val, priv->regs + APLIC_xMSICFGADDR); + writel(valH, priv->regs + APLIC_xMSICFGADDRH); + } +#endif + + /* Setup APLIC domaincfg register */ + val =3D readl(priv->regs + APLIC_DOMAINCFG); + val |=3D APLIC_DOMAINCFG_IE; + if (!priv->nr_idcs) + val |=3D APLIC_DOMAINCFG_DM; + writel(val, priv->regs + APLIC_DOMAINCFG); + if (readl(priv->regs + APLIC_DOMAINCFG) !=3D val) + pr_warn("%pfwP: unable to write 0x%x in domaincfg\n", + priv->fwnode, val); +} + +static void aplic_msi_write_msg(struct msi_desc *desc, struct msi_msg *msg) +{ + unsigned int group_index, hart_index, guest_index, val; + struct irq_data *d =3D irq_get_irq_data(desc->irq); + struct aplic_priv *priv =3D irq_data_get_irq_chip_data(d); + struct aplic_msicfg *mc =3D &priv->msicfg; + phys_addr_t tppn, tbppn, msg_addr; + void __iomem *target; + + /* For zeroed MSI, simply write zero into the target register */ + if (!msg->address_hi && !msg->address_lo && !msg->data) { + target =3D priv->regs + APLIC_TARGET_BASE; + target +=3D (d->hwirq - 1) * sizeof(u32); + writel(0, target); + return; + } + + /* Sanity check on message data */ + WARN_ON(msg->data > APLIC_TARGET_EIID_MASK); + + /* Compute target MSI address */ + msg_addr =3D (((u64)msg->address_hi) << 32) | msg->address_lo; + tppn =3D msg_addr >> APLIC_xMSICFGADDR_PPN_SHIFT; + + /* Compute target HART Base PPN */ + tbppn =3D tppn; + tbppn &=3D ~APLIC_xMSICFGADDR_PPN_HART(mc->lhxs); + tbppn &=3D ~APLIC_xMSICFGADDR_PPN_LHX(mc->lhxw, mc->lhxs); + tbppn &=3D ~APLIC_xMSICFGADDR_PPN_HHX(mc->hhxw, mc->hhxs); + WARN_ON(tbppn !=3D mc->base_ppn); + + /* Compute target group and hart indexes */ + group_index =3D (tppn >> APLIC_xMSICFGADDR_PPN_HHX_SHIFT(mc->hhxs)) & + APLIC_xMSICFGADDR_PPN_HHX_MASK(mc->hhxw); + hart_index =3D (tppn >> APLIC_xMSICFGADDR_PPN_LHX_SHIFT(mc->lhxs)) & + APLIC_xMSICFGADDR_PPN_LHX_MASK(mc->lhxw); + hart_index |=3D (group_index << mc->lhxw); + WARN_ON(hart_index > APLIC_TARGET_HART_IDX_MASK); + + /* Compute target guest index */ + guest_index =3D tppn & APLIC_xMSICFGADDR_PPN_HART(mc->lhxs); + WARN_ON(guest_index > APLIC_TARGET_GUEST_IDX_MASK); + + /* Update IRQ TARGET register */ + target =3D priv->regs + APLIC_TARGET_BASE; + target +=3D (d->hwirq - 1) * sizeof(u32); + val =3D (hart_index & APLIC_TARGET_HART_IDX_MASK) + << APLIC_TARGET_HART_IDX_SHIFT; + val |=3D (guest_index & APLIC_TARGET_GUEST_IDX_MASK) + << APLIC_TARGET_GUEST_IDX_SHIFT; + val |=3D (msg->data & APLIC_TARGET_EIID_MASK); + writel(val, target); +} + +static int aplic_setup_msi(struct aplic_priv *priv) +{ + struct aplic_msicfg *mc =3D &priv->msicfg; + const struct imsic_global_config *imsic_global; + + /* + * The APLIC outgoing MSI config registers assume target MSI + * controller to be RISC-V AIA IMSIC controller. + */ + imsic_global =3D imsic_get_global_config(); + if (!imsic_global) { + pr_err("%pfwP: IMSIC global config not found\n", + priv->fwnode); + return -ENODEV; + } + + /* Find number of guest index bits (LHXS) */ + mc->lhxs =3D imsic_global->guest_index_bits; + if (APLIC_xMSICFGADDRH_LHXS_MASK < mc->lhxs) { + pr_err("%pfwP: IMSIC guest index bits big for APLIC LHXS\n", + priv->fwnode); + return -EINVAL; + } + + /* Find number of HART index bits (LHXW) */ + mc->lhxw =3D imsic_global->hart_index_bits; + if (APLIC_xMSICFGADDRH_LHXW_MASK < mc->lhxw) { + pr_err("%pfwP: IMSIC hart index bits big for APLIC LHXW\n", + priv->fwnode); + return -EINVAL; + } + + /* Find number of group index bits (HHXW) */ + mc->hhxw =3D imsic_global->group_index_bits; + if (APLIC_xMSICFGADDRH_HHXW_MASK < mc->hhxw) { + pr_err("%pfwP: IMSIC group index bits big for APLIC HHXW\n", + priv->fwnode); + return -EINVAL; + } + + /* Find first bit position of group index (HHXS) */ + mc->hhxs =3D imsic_global->group_index_shift; + if (mc->hhxs < (2 * APLIC_xMSICFGADDR_PPN_SHIFT)) { + pr_err("%pfwP: IMSIC group index shift should be >=3D %d\n", + priv->fwnode, (2 * APLIC_xMSICFGADDR_PPN_SHIFT)); + return -EINVAL; + } + mc->hhxs -=3D (2 * APLIC_xMSICFGADDR_PPN_SHIFT); + if (APLIC_xMSICFGADDRH_HHXS_MASK < mc->hhxs) { + pr_err("%pfwP: IMSIC group index shift big for APLIC HHXS\n", + priv->fwnode); + return -EINVAL; + } + + /* Compute PPN base */ + mc->base_ppn =3D imsic_global->base_addr >> APLIC_xMSICFGADDR_PPN_SHIFT; + mc->base_ppn &=3D ~APLIC_xMSICFGADDR_PPN_HART(mc->lhxs); + mc->base_ppn &=3D ~APLIC_xMSICFGADDR_PPN_LHX(mc->lhxw, mc->lhxs); + mc->base_ppn &=3D ~APLIC_xMSICFGADDR_PPN_HHX(mc->hhxw, mc->hhxs); + + /* Use all possible CPUs as lmask */ + cpumask_copy(&priv->lmask, cpu_possible_mask); + + return 0; +} + +/* + * To handle an APLIC IDC interrupts, we just read the CLAIMI register + * which will return highest priority pending interrupt and clear the + * pending bit of the interrupt. This process is repeated until CLAIMI + * register return zero value. + */ +static void aplic_idc_handle_irq(struct irq_desc *desc) +{ + struct aplic_idc *idc =3D this_cpu_ptr(&aplic_idcs); + struct irq_chip *chip =3D irq_desc_get_chip(desc); + irq_hw_number_t hw_irq; + int irq; + + chained_irq_enter(chip, desc); + + while ((hw_irq =3D readl(idc->regs + APLIC_IDC_CLAIMI))) { + hw_irq =3D hw_irq >> APLIC_IDC_TOPI_ID_SHIFT; + irq =3D irq_find_mapping(idc->priv->irqdomain, hw_irq); + + if (unlikely(irq <=3D 0)) + pr_warn_ratelimited("hw_irq %lu mapping not found\n", + hw_irq); + else + generic_handle_irq(irq); + } + + chained_irq_exit(chip, desc); +} + +static void aplic_idc_set_delivery(struct aplic_idc *idc, bool en) +{ + u32 de =3D (en) ? APLIC_ENABLE_IDELIVERY : APLIC_DISABLE_IDELIVERY; + u32 th =3D (en) ? APLIC_ENABLE_ITHRESHOLD : APLIC_DISABLE_ITHRESHOLD; + + /* Priority must be less than threshold for interrupt triggering */ + writel(th, idc->regs + APLIC_IDC_ITHRESHOLD); + + /* Delivery must be set to 1 for interrupt triggering */ + writel(de, idc->regs + APLIC_IDC_IDELIVERY); +} + +static int aplic_idc_dying_cpu(unsigned int cpu) +{ + if (aplic_idc_parent_irq) + disable_percpu_irq(aplic_idc_parent_irq); + + return 0; +} + +static int aplic_idc_starting_cpu(unsigned int cpu) +{ + if (aplic_idc_parent_irq) + enable_percpu_irq(aplic_idc_parent_irq, + irq_get_trigger_type(aplic_idc_parent_irq)); + + return 0; +} + +static int aplic_setup_idc(struct aplic_priv *priv) +{ + int i, j, rc, cpu, setup_count =3D 0; + struct fwnode_reference_args parent; + struct irq_domain *domain; + unsigned long hartid; + struct aplic_idc *idc; + u32 val; + + /* Setup per-CPU IDC and target CPU mask */ + for (i =3D 0; i < priv->nr_idcs; i++) { + rc =3D fwnode_property_get_reference_args(priv->fwnode, + "interrupts-extended", "#interrupt-cells", + 0, i, &parent); + if (rc) { + pr_warn("%pfwP: parent irq for IDC%d not found\n", + priv->fwnode, i); + continue; + } + + /* + * Skip interrupts other than external interrupts for + * current privilege level. + */ + if (parent.args[0] !=3D RV_IRQ_EXT) + continue; + + rc =3D riscv_fw_parent_hartid(parent.fwnode, &hartid); + if (rc) { + pr_warn("%pfwP: invalid hartid for IDC%d\n", + priv->fwnode, i); + continue; + } + + cpu =3D riscv_hartid_to_cpuid(hartid); + if (cpu < 0) { + pr_warn("%pfwP: invalid cpuid for IDC%d\n", + priv->fwnode, i); + continue; + } + + cpumask_set_cpu(cpu, &priv->lmask); + + idc =3D per_cpu_ptr(&aplic_idcs, cpu); + idc->hart_index =3D i; + idc->regs =3D priv->regs + APLIC_IDC_BASE + i * APLIC_IDC_SIZE; + idc->priv =3D priv; + + aplic_idc_set_delivery(idc, true); + + /* + * Boot cpu might not have APLIC hart_index =3D 0 so check + * and update target registers of all interrupts. + */ + if (cpu =3D=3D smp_processor_id() && idc->hart_index) { + val =3D idc->hart_index & APLIC_TARGET_HART_IDX_MASK; + val <<=3D APLIC_TARGET_HART_IDX_SHIFT; + val |=3D APLIC_DEFAULT_PRIORITY; + for (j =3D 1; j <=3D priv->nr_irqs; j++) + writel(val, priv->regs + APLIC_TARGET_BASE + + (j - 1) * sizeof(u32)); + } + + setup_count++; + } + + /* Find parent domain and register chained handler */ + domain =3D irq_find_matching_fwnode(riscv_get_intc_hwnode(), + DOMAIN_BUS_ANY); + if (!aplic_idc_parent_irq && domain) { + aplic_idc_parent_irq =3D irq_create_mapping(domain, RV_IRQ_EXT); + if (aplic_idc_parent_irq) { + irq_set_chained_handler(aplic_idc_parent_irq, + aplic_idc_handle_irq); + + /* + * Setup CPUHP notifier to enable IDC parent + * interrupt on all CPUs + */ + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, + "irqchip/riscv/aplic:starting", + aplic_idc_starting_cpu, + aplic_idc_dying_cpu); + } + } + + /* Fail if we were not able to setup IDC for any CPU */ + return (setup_count) ? 0 : -ENODEV; +} + +static int aplic_probe(struct platform_device *pdev) +{ + struct fwnode_handle *fwnode =3D pdev->dev.fwnode; + struct fwnode_reference_args parent; + struct aplic_priv *priv; + struct resource *res; + phys_addr_t pa; + int rc; + + priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + priv->fwnode =3D fwnode; + + /* Map the MMIO registers */ + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + pr_err("%pfwP: failed to get MMIO resource\n", fwnode); + return -EINVAL; + } + priv->regs =3D devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (!priv->regs) { + pr_err("%pfwP: failed map MMIO registers\n", fwnode); + return -ENOMEM; + } + + /* + * Find out GSI base number + * + * Note: DT does not define "riscv,gsi-base" property so GSI + * base is always zero for DT. + */ + rc =3D fwnode_property_read_u32_array(fwnode, "riscv,gsi-base", + &priv->gsi_base, 1); + if (rc) + priv->gsi_base =3D 0; + + /* Find out number of interrupt sources */ + rc =3D fwnode_property_read_u32_array(fwnode, "riscv,num-sources", + &priv->nr_irqs, 1); + if (rc) { + pr_err("%pfwP: failed to get number of interrupt sources\n", + fwnode); + return rc; + } + + /* Setup initial state APLIC interrupts */ + aplic_init_hw_irqs(priv); + + /* + * Find out number of IDCs based on parent interrupts + * + * If "msi-parent" property is present then we ignore the + * APLIC IDCs which forces the APLIC driver to use MSI mode. + */ + if (!fwnode_property_present(fwnode, "msi-parent")) { + while (!fwnode_property_get_reference_args(fwnode, + "interrupts-extended", "#interrupt-cells", + 0, priv->nr_idcs, &parent)) + priv->nr_idcs++; + } + + /* Setup IDCs or MSIs based on number of IDCs */ + if (priv->nr_idcs) + rc =3D aplic_setup_idc(priv); + else + rc =3D aplic_setup_msi(priv); + if (rc) { + pr_err("%pfwP: failed setup %s\n", + fwnode, priv->nr_idcs ? "IDCs" : "MSIs"); + return rc; + } + + /* Setup global config and interrupt delivery */ + aplic_init_hw_global(priv); + + /* Create irq domain instance for the APLIC */ + if (priv->nr_idcs) + priv->irqdomain =3D irq_domain_create_linear( + priv->fwnode, + priv->nr_irqs + 1, + &aplic_irqdomain_idc_ops, + priv); + else + priv->irqdomain =3D platform_msi_create_device_domain( + &pdev->dev, + priv->nr_irqs + 1, + aplic_msi_write_msg, + &aplic_irqdomain_msi_ops, + priv); + if (!priv->irqdomain) { + pr_err("%pfwP: failed to add irq domain\n", priv->fwnode); + return -ENOMEM; + } + + /* Advertise the interrupt controller */ + if (priv->nr_idcs) { + pr_info("%pfwP: %d interrupts directly connected to %d CPUs\n", + priv->fwnode, priv->nr_irqs, priv->nr_idcs); + } else { + pa =3D priv->msicfg.base_ppn << APLIC_xMSICFGADDR_PPN_SHIFT; + pr_info("%pfwP: %d interrupts forwared to MSI base %pa\n", + priv->fwnode, priv->nr_irqs, &pa); + } + + return 0; +} + +static const struct of_device_id aplic_match[] =3D { + { .compatible =3D "riscv,aplic" }, + {} +}; + +static struct platform_driver aplic_driver =3D { + .driver =3D { + .name =3D "riscv-aplic", + .of_match_table =3D aplic_match, + }, + .probe =3D aplic_probe, +}; + +static int __init aplic_init(void) +{ + /* + * Register APLIC driver as early as possible so that APLIC + * platform device is probed as soon as it is created. + */ + return platform_driver_register(&aplic_driver); +} +core_initcall(aplic_init); + +static int __init aplic_dt_init(struct device_node *node, + struct device_node *parent) +{ + /* + * The APLIC platform driver needs to be probed early + * so for device tree: + * + * 1) Set the FWNODE_FLAG_BEST_EFFORT flag in fwnode which + * provides a hint to the device driver core to probe the + * platform driver early. + * 2) Clear the OF_POPULATED flag in device_node because + * of_irq_init() sets it which prevents creation of + * platform device. + */ + node->fwnode.flags |=3D FWNODE_FLAG_BEST_EFFORT; + of_node_clear_flag(node, OF_POPULATED); + return 0; +} +IRQCHIP_DECLARE(riscv_aplic, "riscv,aplic", aplic_dt_init); diff --git a/include/linux/irqchip/riscv-aplic.h b/include/linux/irqchip/ri= scv-aplic.h new file mode 100644 index 000000000000..97e198ea0109 --- /dev/null +++ b/include/linux/irqchip/riscv-aplic.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ +#ifndef __LINUX_IRQCHIP_RISCV_APLIC_H +#define __LINUX_IRQCHIP_RISCV_APLIC_H + +#include + +#define APLIC_MAX_IDC BIT(14) +#define APLIC_MAX_SOURCE 1024 + +#define APLIC_DOMAINCFG 0x0000 +#define APLIC_DOMAINCFG_RDONLY 0x80000000 +#define APLIC_DOMAINCFG_IE BIT(8) +#define APLIC_DOMAINCFG_DM BIT(2) +#define APLIC_DOMAINCFG_BE BIT(0) + +#define APLIC_SOURCECFG_BASE 0x0004 +#define APLIC_SOURCECFG_D BIT(10) +#define APLIC_SOURCECFG_CHILDIDX_MASK 0x000003ff +#define APLIC_SOURCECFG_SM_MASK 0x00000007 +#define APLIC_SOURCECFG_SM_INACTIVE 0x0 +#define APLIC_SOURCECFG_SM_DETACH 0x1 +#define APLIC_SOURCECFG_SM_EDGE_RISE 0x4 +#define APLIC_SOURCECFG_SM_EDGE_FALL 0x5 +#define APLIC_SOURCECFG_SM_LEVEL_HIGH 0x6 +#define APLIC_SOURCECFG_SM_LEVEL_LOW 0x7 + +#define APLIC_MMSICFGADDR 0x1bc0 +#define APLIC_MMSICFGADDRH 0x1bc4 +#define APLIC_SMSICFGADDR 0x1bc8 +#define APLIC_SMSICFGADDRH 0x1bcc + +#ifdef CONFIG_RISCV_M_MODE +#define APLIC_xMSICFGADDR APLIC_MMSICFGADDR +#define APLIC_xMSICFGADDRH APLIC_MMSICFGADDRH +#else +#define APLIC_xMSICFGADDR APLIC_SMSICFGADDR +#define APLIC_xMSICFGADDRH APLIC_SMSICFGADDRH +#endif + +#define APLIC_xMSICFGADDRH_L BIT(31) +#define APLIC_xMSICFGADDRH_HHXS_MASK 0x1f +#define APLIC_xMSICFGADDRH_HHXS_SHIFT 24 +#define APLIC_xMSICFGADDRH_LHXS_MASK 0x7 +#define APLIC_xMSICFGADDRH_LHXS_SHIFT 20 +#define APLIC_xMSICFGADDRH_HHXW_MASK 0x7 +#define APLIC_xMSICFGADDRH_HHXW_SHIFT 16 +#define APLIC_xMSICFGADDRH_LHXW_MASK 0xf +#define APLIC_xMSICFGADDRH_LHXW_SHIFT 12 +#define APLIC_xMSICFGADDRH_BAPPN_MASK 0xfff + +#define APLIC_xMSICFGADDR_PPN_SHIFT 12 + +#define APLIC_xMSICFGADDR_PPN_HART(__lhxs) \ + (BIT(__lhxs) - 1) + +#define APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) \ + (BIT(__lhxw) - 1) +#define APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs) \ + ((__lhxs)) +#define APLIC_xMSICFGADDR_PPN_LHX(__lhxw, __lhxs) \ + (APLIC_xMSICFGADDR_PPN_LHX_MASK(__lhxw) << \ + APLIC_xMSICFGADDR_PPN_LHX_SHIFT(__lhxs)) + +#define APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) \ + (BIT(__hhxw) - 1) +#define APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs) \ + ((__hhxs) + APLIC_xMSICFGADDR_PPN_SHIFT) +#define APLIC_xMSICFGADDR_PPN_HHX(__hhxw, __hhxs) \ + (APLIC_xMSICFGADDR_PPN_HHX_MASK(__hhxw) << \ + APLIC_xMSICFGADDR_PPN_HHX_SHIFT(__hhxs)) + +#define APLIC_IRQBITS_PER_REG 32 + +#define APLIC_SETIP_BASE 0x1c00 +#define APLIC_SETIPNUM 0x1cdc + +#define APLIC_CLRIP_BASE 0x1d00 +#define APLIC_CLRIPNUM 0x1ddc + +#define APLIC_SETIE_BASE 0x1e00 +#define APLIC_SETIENUM 0x1edc + +#define APLIC_CLRIE_BASE 0x1f00 +#define APLIC_CLRIENUM 0x1fdc + +#define APLIC_SETIPNUM_LE 0x2000 +#define APLIC_SETIPNUM_BE 0x2004 + +#define APLIC_GENMSI 0x3000 + +#define APLIC_TARGET_BASE 0x3004 +#define APLIC_TARGET_HART_IDX_SHIFT 18 +#define APLIC_TARGET_HART_IDX_MASK 0x3fff +#define APLIC_TARGET_GUEST_IDX_SHIFT 12 +#define APLIC_TARGET_GUEST_IDX_MASK 0x3f +#define APLIC_TARGET_IPRIO_MASK 0xff +#define APLIC_TARGET_EIID_MASK 0x7ff + +#define APLIC_IDC_BASE 0x4000 +#define APLIC_IDC_SIZE 32 + +#define APLIC_IDC_IDELIVERY 0x00 + +#define APLIC_IDC_IFORCE 0x04 + +#define APLIC_IDC_ITHRESHOLD 0x08 + +#define APLIC_IDC_TOPI 0x18 +#define APLIC_IDC_TOPI_ID_SHIFT 16 +#define APLIC_IDC_TOPI_ID_MASK 0x3ff +#define APLIC_IDC_TOPI_PRIO_MASK 0xff + +#define APLIC_IDC_CLAIMI 0x1c + +#endif --=20 2.34.1 From nobody Sat Feb 7 11:30:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 813AAEB64DA for ; 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Mon, 10 Jul 2023 02:44:34 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id k1-20020a6b7a41000000b007870c56387dsm936938iop.49.2023.07.10.02.44.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jul 2023 02:44:33 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski Cc: Atish Patra , Andrew Jones , Sunil V L , Conor Dooley , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel , Conor Dooley Subject: [PATCH v5 8/9] RISC-V: Select APLIC and IMSIC drivers Date: Mon, 10 Jul 2023 15:13:20 +0530 Message-Id: <20230710094321.1378351-9-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230710094321.1378351-1-apatel@ventanamicro.com> References: <20230710094321.1378351-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The QEMU virt machine supports AIA emulation and we also have quite a few RISC-V platforms with AIA support under development so let us select APLIC and IMSIC drivers for all RISC-V platforms. Signed-off-by: Anup Patel Reviewed-by: Conor Dooley --- arch/riscv/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 4c07b9189c86..318f62a0a187 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -148,6 +148,8 @@ config RISCV select PCI_DOMAINS_GENERIC if PCI select PCI_MSI if PCI select RISCV_ALTERNATIVE if !XIP_KERNEL + select RISCV_APLIC + select RISCV_IMSIC select RISCV_INTC select RISCV_TIMER if RISCV_SBI select SIFIVE_PLIC --=20 2.34.1 From nobody Sat Feb 7 11:30:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32BE9EB64D9 for ; Mon, 10 Jul 2023 09:50:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231195AbjGJJu4 (ORCPT ); Mon, 10 Jul 2023 05:50:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231336AbjGJJt5 (ORCPT ); Mon, 10 Jul 2023 05:49:57 -0400 Received: from mail-io1-xd30.google.com (mail-io1-xd30.google.com [IPv6:2607:f8b0:4864:20::d30]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3327C3AA2 for ; Mon, 10 Jul 2023 02:44:41 -0700 (PDT) Received: by mail-io1-xd30.google.com with SMTP id ca18e2360f4ac-78666f06691so132367539f.0 for ; Mon, 10 Jul 2023 02:44:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1688982280; x=1691574280; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ofm6ZZqXNuqTlD7ApqCkKz5DMt6TsGfpSNKkfwssKPg=; b=HcWz9mfkvs5FdQY6JwaYRUd1x8Cydw6tK0ZbXGUcKgU982e37q4E7DEL8SMpbHVCek M18eeY26JQfb8yLWtVGnb/mbiBhz7bDi6Jt7gUOzTDJk1z0MaOriGxYSWXQG4bzGYKev v4bOEb0eVuyxFcLta/fAS25xXCPi0L59bz+N3v4Xk5kGQEv+evkmjnbtfi7htPVyWmTO 0zojqgco6pcgUMwp8ayE+uk7yZs4xUExX2EKBkM9YIAHTQrSGx+FPvH+ExJXkvVYV+be +5z4fAaaipT4bwaa+qmU6zBhN2PB7VC8HwD0qBM5R1QC4D/yN7BgfG3DalcrQEWjquqp sKIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688982280; x=1691574280; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ofm6ZZqXNuqTlD7ApqCkKz5DMt6TsGfpSNKkfwssKPg=; b=kMNpDIidZ0YBPyC01/wsxq9bzGCh7d/NSTp2hkuf2vI5w0oWoQf0LgIURW+/Msx303 E1iFT5m2yyw4u6cPVklQFkF2leN+y25kbSxtkleKwZcIbro4QpNWVXmjSp6cATTAZXwu O0jSNO6GJIszc7QTFs2MfQY2KYtU4W9bCcRfOJPvVa+q8pi+zuBMMEJLptqPL2/K3p83 P4JuIO3b/ni9o28UW1/Y5B+lm4rCcG6xK+i5BJZRSoX9FBWSXYYI6pkQGKM4Wd6xpXU0 +J4l529LIjtBmcgjT546nJHJw0qCnj+MAoxFIuH5zsXEE3TgPfKhH14lvBtt1LYzqJD3 d6MA== X-Gm-Message-State: ABy/qLblSdCft6Il470243bcwupN/ZRJ7MLbKC24adyaEhg6aPAAEZ3e veWKdRAyDZVA7F2mHTDkWGTyTw== X-Google-Smtp-Source: APBJJlEvN/kXRYuvvzZyagkj3gVCiXxnv/KMPVlBOAwwPNxqHe9Zm6PU9NkVs/vOaNFxbKR3Q+kpMg== X-Received: by 2002:a5e:c910:0:b0:77e:3d2f:d1f4 with SMTP id z16-20020a5ec910000000b0077e3d2fd1f4mr11945598iol.15.1688982280420; Mon, 10 Jul 2023 02:44:40 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id k1-20020a6b7a41000000b007870c56387dsm936938iop.49.2023.07.10.02.44.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jul 2023 02:44:40 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski Cc: Atish Patra , Andrew Jones , Sunil V L , Conor Dooley , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v5 9/9] MAINTAINERS: Add entry for RISC-V AIA drivers Date: Mon, 10 Jul 2023 15:13:21 +0530 Message-Id: <20230710094321.1378351-10-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230710094321.1378351-1-apatel@ventanamicro.com> References: <20230710094321.1378351-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add myself as maintainer for RISC-V AIA drivers including the RISC-V INTC driver which supports both AIA and non-AIA platforms. Signed-off-by: Anup Patel --- MAINTAINERS | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 3be1bdfe8ecc..a85fc0102179 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18245,6 +18245,18 @@ S: Maintained F: drivers/mtd/nand/raw/r852.c F: drivers/mtd/nand/raw/r852.h =20 +RISC-V AIA DRIVERS +M: Anup Patel +L: linux-riscv@lists.infradead.org +S: Maintained +F: Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml +F: Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml +F: drivers/irqchip/irq-riscv-aplic.c +F: drivers/irqchip/irq-riscv-imsic.c +F: drivers/irqchip/irq-riscv-intc.c +F: include/linux/irqchip/riscv-aplic.h +F: include/linux/irqchip/riscv-imsic.h + RISC-V ARCHITECTURE M: Paul Walmsley M: Palmer Dabbelt --=20 2.34.1