From nobody Tue Feb 10 20:09:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EA07EB64DC for ; Tue, 11 Jul 2023 12:19:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231976AbjGKMTq (ORCPT ); Tue, 11 Jul 2023 08:19:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231819AbjGKMTZ (ORCPT ); Tue, 11 Jul 2023 08:19:25 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AB96198D for ; Tue, 11 Jul 2023 05:18:46 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2b6fbf0c0e2so87196071fa.2 for ; Tue, 11 Jul 2023 05:18:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689077924; x=1691669924; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=PMFlc3/13k/HcaPPKzdAkzi+wUJB+UhJRzkF3UPPZqA=; b=T7rFlgw7hYsncA9ByJZRwvEcG7O794ypsxDgaOhBLAcY0ldQHEysxFChKK0AqjI719 a8kgjMDtml38GrKuwQ3VBKe5YvVmtKNRnmrG46YUZ6ND4vAvJmW+dl7ENIIhBHUIT+xC 0x8zfyv33h1Lv1f38z5qEvABAZBSQ3Xg+yMMuM8Q9qRG6ItVCNS1BhxczrQc5OXXRecL bUq9SnGpIN2fEHogSk/cBmolRm5vkqBmGY5X9BsSiooemDFLqKB49i4Anc6rFP1zir/t QBn5CDNHw7smdtGq4FOnKzwjNp4pJgY5PfZ8WJoDgM6MlBxX6XOGfCquF4BZ4ligjmoQ CioQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689077924; x=1691669924; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PMFlc3/13k/HcaPPKzdAkzi+wUJB+UhJRzkF3UPPZqA=; b=I4KWuKlv0yzguvY/EX7xp+uX+z06kUEpPrr/SXInYqSpa/0NxL3YL7lQIp3nQ9D8eZ AgjDiBrS/OVZgcRBDx0TI5sOP8i1qHMfe9KV1SI/v/Gcd9YQe4b8t3f/MPq/VAqKr0JZ pR53cj37BJViraPFSGec5/OQKP/owR67qn8M56yHSr5lMPvDTqWo/5HexXWxLb/j/w+0 mv2bFhrWcJzH6Uf/MwRXCznCuaiLLTZzMHgPirmj5OEeWbC9mDbcNCsm0aZWc+gW+dcO TN+ge3uJjQz6hYlXEMX7Wmss28PHhllIP2ui+8zrKRpN7T0yBh95mslsRxc3slTM0N3e Gkhw== X-Gm-Message-State: ABy/qLbdOFM+l9GxQOwh7xvAFNBCL6uIwRKiP138EqC1kg4sjrjaXAsr 2PVKxZgrUQmXuu4qt2pFQDk3DQ== X-Google-Smtp-Source: APBJJlHoVEh50SZpWduD62/N/a5ZUmbU4962uGUX7ZK4yVhchIoJ/ZZ+9QDomMwdd8jvCnp6tJEC8g== X-Received: by 2002:a2e:b44f:0:b0:2b6:f1ad:d535 with SMTP id o15-20020a2eb44f000000b002b6f1add535mr11832275ljm.14.1689077924190; Tue, 11 Jul 2023 05:18:44 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:43 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:12 +0200 Subject: [PATCH 13/53] interconnect: qcom: sm8250: Retire DEFINE_QNODE MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-13-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=45391; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=hGYe0N70rDnwja5IvQO5Zqf0PStSfBajeNCnSM/xFtE=; b=RZw7sBl2WvUUvAH8S24zwPS3RmO8L4FVLPaEZqvEbSsDrREvWN0KTwXs54wHBbGHaXFc1/ZX6 rMGuTbnII1cAkfn8XXAOTfUZK2Z1vZr6/OuM0XXdoMUycC2DDGKRVGe X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8250.c | 1478 ++++++++++++++++++++++++++++++++= ---- 1 file changed, 1330 insertions(+), 148 deletions(-) diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom= /sm8250.c index d3d0196902cd..d4123799c2c6 100644 --- a/drivers/interconnect/qcom/sm8250.c +++ b/drivers/interconnect/qcom/sm8250.c @@ -15,154 +15,1336 @@ #include "icc-rpmh.h" #include "sm8250.h" =20 -DEFINE_QNODE(qhm_a1noc_cfg, SM8250_MASTER_A1NOC_CFG, 1, 4, SM8250_SLAVE_SE= RVICE_A1NOC); -DEFINE_QNODE(qhm_qspi, SM8250_MASTER_QSPI_0, 1, 4, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qup1, SM8250_MASTER_QUP_1, 1, 4, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qup2, SM8250_MASTER_QUP_2, 1, 4, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_tsif, SM8250_MASTER_TSIF, 1, 4, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_pcie3_modem, SM8250_MASTER_PCIE_2, 1, 8, SM8250_SLAVE_ANOC= _PCIE_GEM_NOC_1); -DEFINE_QNODE(xm_sdc4, SM8250_MASTER_SDCC_4, 1, 8, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_ufs_mem, SM8250_MASTER_UFS_MEM, 1, 8, SM8250_A1NOC_SNOC_SL= V); -DEFINE_QNODE(xm_usb3_0, SM8250_MASTER_USB3, 1, 8, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_usb3_1, SM8250_MASTER_USB3_1, 1, 8, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_a2noc_cfg, SM8250_MASTER_A2NOC_CFG, 1, 4, SM8250_SLAVE_SE= RVICE_A2NOC); -DEFINE_QNODE(qhm_qdss_bam, SM8250_MASTER_QDSS_BAM, 1, 4, SM8250_A2NOC_SNOC= _SLV); -DEFINE_QNODE(qhm_qup0, SM8250_MASTER_QUP_0, 1, 4, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(qnm_cnoc, SM8250_MASTER_CNOC_A2NOC, 1, 8, SM8250_A2NOC_SNOC_S= LV); -DEFINE_QNODE(qxm_crypto, SM8250_MASTER_CRYPTO_CORE_0, 1, 8, SM8250_A2NOC_S= NOC_SLV); -DEFINE_QNODE(qxm_ipa, SM8250_MASTER_IPA, 1, 8, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_pcie3_0, SM8250_MASTER_PCIE, 1, 8, SM8250_SLAVE_ANOC_PCIE_= GEM_NOC); -DEFINE_QNODE(xm_pcie3_1, SM8250_MASTER_PCIE_1, 1, 8, SM8250_SLAVE_ANOC_PCI= E_GEM_NOC); -DEFINE_QNODE(xm_qdss_etr, SM8250_MASTER_QDSS_ETR, 1, 8, SM8250_A2NOC_SNOC_= SLV); -DEFINE_QNODE(xm_sdc2, SM8250_MASTER_SDCC_2, 1, 8, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_ufs_card, SM8250_MASTER_UFS_CARD, 1, 8, SM8250_A2NOC_SNOC_= SLV); -DEFINE_QNODE(qnm_npu, SM8250_MASTER_NPU, 2, 32, SM8250_SLAVE_CDSP_MEM_NOC); -DEFINE_QNODE(qnm_snoc, SM8250_SNOC_CNOC_MAS, 1, 8, SM8250_SLAVE_CDSP_CFG, = SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, = SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SL= AVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_= SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NO= C_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2= _CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8= 250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_= CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY= _NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_= TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM825= 0_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM825= 0_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM8250_SL= AVE_AOSS, SM8250_SLAVE_ PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYP= TO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_Q= UP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL); -DEFINE_QNODE(xm_qdss_dap, SM8250_MASTER_QDSS_DAP, 1, 8, SM8250_SLAVE_CDSP_= CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NO= RTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM82= 50_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM= 8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE= _A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_P= CIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS= , SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_CNOC_A2NOC, SM8250_SLAVE_PCIE_0= _CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2P= HY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_= SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM= _CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_C= FG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8= 250_SLAVE_A1NOC_CFG, SM 8250_SLAVE_AOSS, SM8250_SLAVE_PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_S= LAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAV= E_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2,= SM8250_SLAVE_CLK_CTL); -DEFINE_QNODE(qhm_cnoc_dc_noc, SM8250_MASTER_CNOC_DC_NOC, 1, 4, SM8250_SLAV= E_GEM_NOC_CFG, SM8250_SLAVE_LLCC_CFG); -DEFINE_QNODE(alm_gpu_tcu, SM8250_MASTER_GPU_TCU, 1, 8, SM8250_SLAVE_LLCC, = SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(alm_sys_tcu, SM8250_MASTER_SYS_TCU, 1, 8, SM8250_SLAVE_LLCC, = SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(chm_apps, SM8250_MASTER_AMPSS_M0, 2, 32, SM8250_SLAVE_LLCC, S= M8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qhm_gemnoc_cfg, SM8250_MASTER_GEM_NOC_CFG, 1, 4, SM8250_SLAVE= _SERVICE_GEM_NOC_2, SM8250_SLAVE_SERVICE_GEM_NOC_1, SM8250_SLAVE_SERVICE_GE= M_NOC); -DEFINE_QNODE(qnm_cmpnoc, SM8250_MASTER_COMPUTE_NOC, 2, 32, SM8250_SLAVE_LL= CC, SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_gpu, SM8250_MASTER_GRAPHICS_3D, 2, 32, SM8250_SLAVE_LLCC,= SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_mnoc_hf, SM8250_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8250_SLA= VE_LLCC); -DEFINE_QNODE(qnm_mnoc_sf, SM8250_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8250_SLA= VE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_pcie, SM8250_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_SLAV= E_LLCC, SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SM8250_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8250_SLAV= E_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SM8250_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8250_SLA= VE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(llcc_mc, SM8250_MASTER_LLCC, 4, 4, SM8250_SLAVE_EBI_CH0); -DEFINE_QNODE(qhm_mnoc_cfg, SM8250_MASTER_CNOC_MNOC_CFG, 1, 4, SM8250_SLAVE= _SERVICE_MNOC); -DEFINE_QNODE(qnm_camnoc_hf, SM8250_MASTER_CAMNOC_HF, 2, 32, SM8250_SLAVE_M= NOC_HF_MEM_NOC); -DEFINE_QNODE(qnm_camnoc_icp, SM8250_MASTER_CAMNOC_ICP, 1, 8, SM8250_SLAVE_= MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_camnoc_sf, SM8250_MASTER_CAMNOC_SF, 2, 32, SM8250_SLAVE_M= NOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_video0, SM8250_MASTER_VIDEO_P0, 1, 32, SM8250_SLAVE_MNOC_= SF_MEM_NOC); -DEFINE_QNODE(qnm_video1, SM8250_MASTER_VIDEO_P1, 1, 32, SM8250_SLAVE_MNOC_= SF_MEM_NOC); -DEFINE_QNODE(qnm_video_cvp, SM8250_MASTER_VIDEO_PROC, 1, 32, SM8250_SLAVE_= MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SM8250_MASTER_MDP_PORT0, 1, 32, SM8250_SLAVE_MNOC_H= F_MEM_NOC); -DEFINE_QNODE(qxm_mdp1, SM8250_MASTER_MDP_PORT1, 1, 32, SM8250_SLAVE_MNOC_H= F_MEM_NOC); -DEFINE_QNODE(qxm_rot, SM8250_MASTER_ROTATOR, 1, 32, SM8250_SLAVE_MNOC_SF_M= EM_NOC); -DEFINE_QNODE(amm_npu_sys, SM8250_MASTER_NPU_SYS, 4, 32, SM8250_SLAVE_NPU_C= OMPUTE_NOC); -DEFINE_QNODE(amm_npu_sys_cdp_w, SM8250_MASTER_NPU_CDP, 2, 16, SM8250_SLAVE= _NPU_COMPUTE_NOC); -DEFINE_QNODE(qhm_cfg, SM8250_MASTER_NPU_NOC_CFG, 1, 4, SM8250_SLAVE_SERVIC= E_NPU_NOC, SM8250_SLAVE_ISENSE_CFG, SM8250_SLAVE_NPU_LLM_CFG, SM8250_SLAVE_= NPU_INT_DMA_BWMON_CFG, SM8250_SLAVE_NPU_CP, SM8250_SLAVE_NPU_TCM, SM8250_SL= AVE_NPU_CAL_DP0, SM8250_SLAVE_NPU_CAL_DP1, SM8250_SLAVE_NPU_DPM); -DEFINE_QNODE(qhm_snoc_cfg, SM8250_MASTER_SNOC_CFG, 1, 4, SM8250_SLAVE_SERV= ICE_SNOC); -DEFINE_QNODE(qnm_aggre1_noc, SM8250_A1NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SN= OC_GEM_NOC_SF); -DEFINE_QNODE(qnm_aggre2_noc, SM8250_A2NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SN= OC_GEM_NOC_SF); -DEFINE_QNODE(qnm_gemnoc, SM8250_MASTER_GEM_NOC_SNOC, 1, 16, SM8250_SLAVE_P= IMEM, SM8250_SLAVE_OCIMEM, SM8250_SLAVE_APPSS, SM8250_SNOC_CNOC_SLV, SM8250= _SLAVE_TCU, SM8250_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_gemnoc_pcie, SM8250_MASTER_GEM_NOC_PCIE_SNOC, 1, 8, SM825= 0_SLAVE_PCIE_2, SM8250_SLAVE_PCIE_0, SM8250_SLAVE_PCIE_1); -DEFINE_QNODE(qxm_pimem, SM8250_MASTER_PIMEM, 1, 8, SM8250_SLAVE_SNOC_GEM_N= OC_GC); -DEFINE_QNODE(xm_gic, SM8250_MASTER_GIC, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC= ); -DEFINE_QNODE(qns_a1noc_snoc, SM8250_A1NOC_SNOC_SLV, 1, 16, SM8250_A1NOC_SN= OC_MAS); -DEFINE_QNODE(qns_pcie_modem_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1, 1, = 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(srvc_aggre1_noc, SM8250_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(qns_a2noc_snoc, SM8250_A2NOC_SNOC_SLV, 1, 16, SM8250_A2NOC_SN= OC_MAS); -DEFINE_QNODE(qns_pcie_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM82= 50_MASTER_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(srvc_aggre2_noc, SM8250_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qns_cdsp_mem_noc, SM8250_SLAVE_CDSP_MEM_NOC, 2, 32, SM8250_MA= STER_COMPUTE_NOC); -DEFINE_QNODE(qhs_a1_noc_cfg, SM8250_SLAVE_A1NOC_CFG, 1, 4, SM8250_MASTER_A= 1NOC_CFG); -DEFINE_QNODE(qhs_a2_noc_cfg, SM8250_SLAVE_A2NOC_CFG, 1, 4, SM8250_MASTER_A= 2NOC_CFG); -DEFINE_QNODE(qhs_ahb2phy0, SM8250_SLAVE_AHB2PHY_SOUTH, 1, 4); -DEFINE_QNODE(qhs_ahb2phy1, SM8250_SLAVE_AHB2PHY_NORTH, 1, 4); -DEFINE_QNODE(qhs_aoss, SM8250_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_camera_cfg, SM8250_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SM8250_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_compute_dsp, SM8250_SLAVE_CDSP_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SM8250_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mmcx, SM8250_SLAVE_RBCPR_MMCX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mx, SM8250_SLAVE_RBCPR_MX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SM8250_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_cx_rdpm, SM8250_SLAVE_CX_RDPM, 1, 4); -DEFINE_QNODE(qhs_dcc_cfg, SM8250_SLAVE_DCC_CFG, 1, 4); -DEFINE_QNODE(qhs_ddrss_cfg, SM8250_SLAVE_CNOC_DDRSS, 1, 4, SM8250_MASTER_C= NOC_DC_NOC); -DEFINE_QNODE(qhs_display_cfg, SM8250_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SM8250_SLAVE_GRAPHICS_3D_CFG, 1, 8); -DEFINE_QNODE(qhs_imem_cfg, SM8250_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SM8250_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_ipc_router, SM8250_SLAVE_IPC_ROUTER_CFG, 1, 4); -DEFINE_QNODE(qhs_lpass_cfg, SM8250_SLAVE_LPASS, 1, 4); -DEFINE_QNODE(qhs_mnoc_cfg, SM8250_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8250_MASTER= _CNOC_MNOC_CFG); -DEFINE_QNODE(qhs_npu_cfg, SM8250_SLAVE_NPU_CFG, 1, 4, SM8250_MASTER_NPU_NO= C_CFG); -DEFINE_QNODE(qhs_pcie0_cfg, SM8250_SLAVE_PCIE_0_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie1_cfg, SM8250_SLAVE_PCIE_1_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie_modem_cfg, SM8250_SLAVE_PCIE_2_CFG, 1, 4); -DEFINE_QNODE(qhs_pdm, SM8250_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SM8250_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_prng, SM8250_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SM8250_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qspi, SM8250_SLAVE_QSPI_0, 1, 4); -DEFINE_QNODE(qhs_qup0, SM8250_SLAVE_QUP_0, 1, 4); -DEFINE_QNODE(qhs_qup1, SM8250_SLAVE_QUP_1, 1, 4); -DEFINE_QNODE(qhs_qup2, SM8250_SLAVE_QUP_2, 1, 4); -DEFINE_QNODE(qhs_sdc2, SM8250_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_sdc4, SM8250_SLAVE_SDCC_4, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SM8250_SLAVE_SNOC_CFG, 1, 4, SM8250_MASTER_SNOC= _CFG); -DEFINE_QNODE(qhs_tcsr, SM8250_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm0, SM8250_SLAVE_TLMM_NORTH, 1, 4); -DEFINE_QNODE(qhs_tlmm1, SM8250_SLAVE_TLMM_SOUTH, 1, 4); -DEFINE_QNODE(qhs_tlmm2, SM8250_SLAVE_TLMM_WEST, 1, 4); -DEFINE_QNODE(qhs_tsif, SM8250_SLAVE_TSIF, 1, 4); -DEFINE_QNODE(qhs_ufs_card_cfg, SM8250_SLAVE_UFS_CARD_CFG, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SM8250_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3_0, SM8250_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_usb3_1, SM8250_SLAVE_USB3_1, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SM8250_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8250_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(qns_cnoc_a2noc, SM8250_SLAVE_CNOC_A2NOC, 1, 8, SM8250_MASTER_= CNOC_A2NOC); -DEFINE_QNODE(srvc_cnoc, SM8250_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(qhs_llcc, SM8250_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qhs_memnoc, SM8250_SLAVE_GEM_NOC_CFG, 1, 4, SM8250_MASTER_GEM= _NOC_CFG); -DEFINE_QNODE(qns_gem_noc_snoc, SM8250_SLAVE_GEM_NOC_SNOC, 1, 16, SM8250_MA= STER_GEM_NOC_SNOC); -DEFINE_QNODE(qns_llcc, SM8250_SLAVE_LLCC, 4, 16, SM8250_MASTER_LLCC); -DEFINE_QNODE(qns_sys_pcie, SM8250_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SM8250_MA= STER_GEM_NOC_PCIE_SNOC); -DEFINE_QNODE(srvc_even_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_1, 1, 4); -DEFINE_QNODE(srvc_odd_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_2, 1, 4); -DEFINE_QNODE(srvc_sys_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(ebi, SM8250_SLAVE_EBI_CH0, 4, 4); -DEFINE_QNODE(qns_mem_noc_hf, SM8250_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8250_M= ASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_sf, SM8250_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8250_M= ASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SM8250_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qhs_cal_dp0, SM8250_SLAVE_NPU_CAL_DP0, 1, 4); -DEFINE_QNODE(qhs_cal_dp1, SM8250_SLAVE_NPU_CAL_DP1, 1, 4); -DEFINE_QNODE(qhs_cp, SM8250_SLAVE_NPU_CP, 1, 4); -DEFINE_QNODE(qhs_dma_bwmon, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4); -DEFINE_QNODE(qhs_dpm, SM8250_SLAVE_NPU_DPM, 1, 4); -DEFINE_QNODE(qhs_isense, SM8250_SLAVE_ISENSE_CFG, 1, 4); -DEFINE_QNODE(qhs_llm, SM8250_SLAVE_NPU_LLM_CFG, 1, 4); -DEFINE_QNODE(qhs_tcm, SM8250_SLAVE_NPU_TCM, 1, 4); -DEFINE_QNODE(qns_npu_sys, SM8250_SLAVE_NPU_COMPUTE_NOC, 2, 32); -DEFINE_QNODE(srvc_noc, SM8250_SLAVE_SERVICE_NPU_NOC, 1, 4); -DEFINE_QNODE(qhs_apss, SM8250_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qns_cnoc, SM8250_SNOC_CNOC_SLV, 1, 8, SM8250_SNOC_CNOC_MAS); -DEFINE_QNODE(qns_gemnoc_gc, SM8250_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8250_MAS= TER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_gemnoc_sf, SM8250_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8250_MA= STER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(qxs_imem, SM8250_SLAVE_OCIMEM, 1, 8); -DEFINE_QNODE(qxs_pimem, SM8250_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SM8250_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_pcie_0, SM8250_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(xs_pcie_1, SM8250_SLAVE_PCIE_1, 1, 8); -DEFINE_QNODE(xs_pcie_modem, SM8250_SLAVE_PCIE_2, 1, 8); -DEFINE_QNODE(xs_qdss_stm, SM8250_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SM8250_SLAVE_TCU, 1, 8); +static struct qcom_icc_node qhm_a1noc_cfg =3D { + .name =3D "qhm_a1noc_cfg", + .id =3D SM8250_MASTER_A1NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qhm_qspi =3D { + .name =3D "qhm_qspi", + .id =3D SM8250_MASTER_QSPI_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup1 =3D { + .name =3D "qhm_qup1", + .id =3D SM8250_MASTER_QUP_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup2 =3D { + .name =3D "qhm_qup2", + .id =3D SM8250_MASTER_QUP_2, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_tsif =3D { + .name =3D "qhm_tsif", + .id =3D SM8250_MASTER_TSIF, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_pcie3_modem =3D { + .name =3D "xm_pcie3_modem", + .id =3D SM8250_MASTER_PCIE_2, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 }, +}; + +static struct qcom_icc_node xm_sdc4 =3D { + .name =3D "xm_sdc4", + .id =3D SM8250_MASTER_SDCC_4, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_ufs_mem =3D { + .name =3D "xm_ufs_mem", + .id =3D SM8250_MASTER_UFS_MEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_usb3_0 =3D { + .name =3D "xm_usb3_0", + .id =3D SM8250_MASTER_USB3, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_usb3_1 =3D { + .name =3D "xm_usb3_1", + .id =3D SM8250_MASTER_USB3_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_a2noc_cfg =3D { + .name =3D "qhm_a2noc_cfg", + .id =3D SM8250_MASTER_A2NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam =3D { + .name =3D "qhm_qdss_bam", + .id =3D SM8250_MASTER_QDSS_BAM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup0 =3D { + .name =3D "qhm_qup0", + .id =3D SM8250_MASTER_QUP_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qnm_cnoc =3D { + .name =3D "qnm_cnoc", + .id =3D SM8250_MASTER_CNOC_A2NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_crypto =3D { + .name =3D "qxm_crypto", + .id =3D SM8250_MASTER_CRYPTO_CORE_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_ipa =3D { + .name =3D "qxm_ipa", + .id =3D SM8250_MASTER_IPA, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_pcie3_0 =3D { + .name =3D "xm_pcie3_0", + .id =3D SM8250_MASTER_PCIE, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_1 =3D { + .name =3D "xm_pcie3_1", + .id =3D SM8250_MASTER_PCIE_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_qdss_etr =3D { + .name =3D "xm_qdss_etr", + .id =3D SM8250_MASTER_QDSS_ETR, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_sdc2 =3D { + .name =3D "xm_sdc2", + .id =3D SM8250_MASTER_SDCC_2, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_ufs_card =3D { + .name =3D "xm_ufs_card", + .id =3D SM8250_MASTER_UFS_CARD, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qnm_npu =3D { + .name =3D "qnm_npu", + .id =3D SM8250_MASTER_NPU, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_CDSP_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_snoc =3D { + .name =3D "qnm_snoc", + .id =3D SM8250_SNOC_CNOC_MAS, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 49, + .links =3D { SM8250_SLAVE_CDSP_CFG, + SM8250_SLAVE_CAMERA_CFG, + SM8250_SLAVE_TLMM_SOUTH, + SM8250_SLAVE_TLMM_NORTH, + SM8250_SLAVE_SDCC_4, + SM8250_SLAVE_TLMM_WEST, + SM8250_SLAVE_SDCC_2, + SM8250_SLAVE_CNOC_MNOC_CFG, + SM8250_SLAVE_UFS_MEM_CFG, + SM8250_SLAVE_SNOC_CFG, + SM8250_SLAVE_PDM, + SM8250_SLAVE_CX_RDPM, + SM8250_SLAVE_PCIE_1_CFG, + SM8250_SLAVE_A2NOC_CFG, + SM8250_SLAVE_QDSS_CFG, + SM8250_SLAVE_DISPLAY_CFG, + SM8250_SLAVE_PCIE_2_CFG, + SM8250_SLAVE_TCSR, + SM8250_SLAVE_DCC_CFG, + SM8250_SLAVE_CNOC_DDRSS, + SM8250_SLAVE_IPC_ROUTER_CFG, + SM8250_SLAVE_PCIE_0_CFG, + SM8250_SLAVE_RBCPR_MMCX_CFG, + SM8250_SLAVE_NPU_CFG, + SM8250_SLAVE_AHB2PHY_SOUTH, + SM8250_SLAVE_AHB2PHY_NORTH, + SM8250_SLAVE_GRAPHICS_3D_CFG, + SM8250_SLAVE_VENUS_CFG, + SM8250_SLAVE_TSIF, + SM8250_SLAVE_IPA_CFG, + SM8250_SLAVE_IMEM_CFG, + SM8250_SLAVE_USB3, + SM8250_SLAVE_SERVICE_CNOC, + SM8250_SLAVE_UFS_CARD_CFG, + SM8250_SLAVE_USB3_1, + SM8250_SLAVE_LPASS, + SM8250_SLAVE_RBCPR_CX_CFG, + SM8250_SLAVE_A1NOC_CFG, + SM8250_SLAVE_AOSS, + SM8250_SLAVE_PRNG, + SM8250_SLAVE_VSENSE_CTRL_CFG, + SM8250_SLAVE_QSPI_0, + SM8250_SLAVE_CRYPTO_0_CFG, + SM8250_SLAVE_PIMEM_CFG, + SM8250_SLAVE_RBCPR_MX_CFG, + SM8250_SLAVE_QUP_0, + SM8250_SLAVE_QUP_1, + SM8250_SLAVE_QUP_2, + SM8250_SLAVE_CLK_CTL + }, +}; + +static struct qcom_icc_node xm_qdss_dap =3D { + .name =3D "xm_qdss_dap", + .id =3D SM8250_MASTER_QDSS_DAP, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 50, + .links =3D { SM8250_SLAVE_CDSP_CFG, + SM8250_SLAVE_CAMERA_CFG, + SM8250_SLAVE_TLMM_SOUTH, + SM8250_SLAVE_TLMM_NORTH, + SM8250_SLAVE_SDCC_4, + SM8250_SLAVE_TLMM_WEST, + SM8250_SLAVE_SDCC_2, + SM8250_SLAVE_CNOC_MNOC_CFG, + SM8250_SLAVE_UFS_MEM_CFG, + SM8250_SLAVE_SNOC_CFG, + SM8250_SLAVE_PDM, + SM8250_SLAVE_CX_RDPM, + SM8250_SLAVE_PCIE_1_CFG, + SM8250_SLAVE_A2NOC_CFG, + SM8250_SLAVE_QDSS_CFG, + SM8250_SLAVE_DISPLAY_CFG, + SM8250_SLAVE_PCIE_2_CFG, + SM8250_SLAVE_TCSR, + SM8250_SLAVE_DCC_CFG, + SM8250_SLAVE_CNOC_DDRSS, + SM8250_SLAVE_IPC_ROUTER_CFG, + SM8250_SLAVE_CNOC_A2NOC, + SM8250_SLAVE_PCIE_0_CFG, + SM8250_SLAVE_RBCPR_MMCX_CFG, + SM8250_SLAVE_NPU_CFG, + SM8250_SLAVE_AHB2PHY_SOUTH, + SM8250_SLAVE_AHB2PHY_NORTH, + SM8250_SLAVE_GRAPHICS_3D_CFG, + SM8250_SLAVE_VENUS_CFG, + SM8250_SLAVE_TSIF, + SM8250_SLAVE_IPA_CFG, + SM8250_SLAVE_IMEM_CFG, + SM8250_SLAVE_USB3, + SM8250_SLAVE_SERVICE_CNOC, + SM8250_SLAVE_UFS_CARD_CFG, + SM8250_SLAVE_USB3_1, + SM8250_SLAVE_LPASS, + SM8250_SLAVE_RBCPR_CX_CFG, + SM8250_SLAVE_A1NOC_CFG, + SM8250_SLAVE_AOSS, + SM8250_SLAVE_PRNG, + SM8250_SLAVE_VSENSE_CTRL_CFG, + SM8250_SLAVE_QSPI_0, + SM8250_SLAVE_CRYPTO_0_CFG, + SM8250_SLAVE_PIMEM_CFG, + SM8250_SLAVE_RBCPR_MX_CFG, + SM8250_SLAVE_QUP_0, + SM8250_SLAVE_QUP_1, + SM8250_SLAVE_QUP_2, + SM8250_SLAVE_CLK_CTL + }, +}; + +static struct qcom_icc_node qhm_cnoc_dc_noc =3D { + .name =3D "qhm_cnoc_dc_noc", + .id =3D SM8250_MASTER_CNOC_DC_NOC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .links =3D { SM8250_SLAVE_GEM_NOC_CFG, + SM8250_SLAVE_LLCC_CFG + }, +}; + +static struct qcom_icc_node alm_gpu_tcu =3D { + .name =3D "alm_gpu_tcu", + .id =3D SM8250_MASTER_GPU_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node alm_sys_tcu =3D { + .name =3D "alm_sys_tcu", + .id =3D SM8250_MASTER_SYS_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node chm_apps =3D { + .name =3D "chm_apps", + .id =3D SM8250_MASTER_AMPSS_M0, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 3, + .links =3D { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC, + SM8250_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qhm_gemnoc_cfg =3D { + .name =3D "qhm_gemnoc_cfg", + .id =3D SM8250_MASTER_GEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 3, + .links =3D { SM8250_SLAVE_SERVICE_GEM_NOC_2, + SM8250_SLAVE_SERVICE_GEM_NOC_1, + SM8250_SLAVE_SERVICE_GEM_NOC + }, +}; + +static struct qcom_icc_node qnm_cmpnoc =3D { + .name =3D "qnm_cmpnoc", + .id =3D SM8250_MASTER_COMPUTE_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_gpu =3D { + .name =3D "qnm_gpu", + .id =3D SM8250_MASTER_GRAPHICS_3D, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_mnoc_hf =3D { + .name =3D "qnm_mnoc_hf", + .id =3D SM8250_MASTER_MNOC_HF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_sf =3D { + .name =3D "qnm_mnoc_sf", + .id =3D SM8250_MASTER_MNOC_SF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_pcie =3D { + .name =3D "qnm_pcie", + .id =3D SM8250_MASTER_ANOC_PCIE_GEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 2, + .links =3D { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc =3D { + .name =3D "qnm_snoc_gc", + .id =3D SM8250_MASTER_SNOC_GC_MEM_NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf =3D { + .name =3D "qnm_snoc_sf", + .id =3D SM8250_MASTER_SNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 3, + .links =3D { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC, + SM8250_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .id =3D SM8250_MASTER_LLCC, + .channels =3D 4, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_EBI_CH0 }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg =3D { + .name =3D "qhm_mnoc_cfg", + .id =3D SM8250_MASTER_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qnm_camnoc_hf =3D { + .name =3D "qnm_camnoc_hf", + .id =3D SM8250_MASTER_CAMNOC_HF, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_icp =3D { + .name =3D "qnm_camnoc_icp", + .id =3D SM8250_MASTER_CAMNOC_ICP, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_sf =3D { + .name =3D "qnm_camnoc_sf", + .id =3D SM8250_MASTER_CAMNOC_SF, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video0 =3D { + .name =3D "qnm_video0", + .id =3D SM8250_MASTER_VIDEO_P0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video1 =3D { + .name =3D "qnm_video1", + .id =3D SM8250_MASTER_VIDEO_P1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video_cvp =3D { + .name =3D "qnm_video_cvp", + .id =3D SM8250_MASTER_VIDEO_PROC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 =3D { + .name =3D "qxm_mdp0", + .id =3D SM8250_MASTER_MDP_PORT0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp1 =3D { + .name =3D "qxm_mdp1", + .id =3D SM8250_MASTER_MDP_PORT1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_rot =3D { + .name =3D "qxm_rot", + .id =3D SM8250_MASTER_ROTATOR, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node amm_npu_sys =3D { + .name =3D "amm_npu_sys", + .id =3D SM8250_MASTER_NPU_SYS, + .channels =3D 4, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_NPU_COMPUTE_NOC }, +}; + +static struct qcom_icc_node amm_npu_sys_cdp_w =3D { + .name =3D "amm_npu_sys_cdp_w", + .id =3D SM8250_MASTER_NPU_CDP, + .channels =3D 2, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_NPU_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhm_cfg =3D { + .name =3D "qhm_cfg", + .id =3D SM8250_MASTER_NPU_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 9, + .links =3D { SM8250_SLAVE_SERVICE_NPU_NOC, + SM8250_SLAVE_ISENSE_CFG, + SM8250_SLAVE_NPU_LLM_CFG, + SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, + SM8250_SLAVE_NPU_CP, + SM8250_SLAVE_NPU_TCM, + SM8250_SLAVE_NPU_CAL_DP0, + SM8250_SLAVE_NPU_CAL_DP1, + SM8250_SLAVE_NPU_DPM + }, +}; + +static struct qcom_icc_node qhm_snoc_cfg =3D { + .name =3D "qhm_snoc_cfg", + .id =3D SM8250_MASTER_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc =3D { + .name =3D "qnm_aggre1_noc", + .id =3D SM8250_A1NOC_SNOC_MAS, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_aggre2_noc =3D { + .name =3D "qnm_aggre2_noc", + .id =3D SM8250_A2NOC_SNOC_MAS, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_gemnoc =3D { + .name =3D "qnm_gemnoc", + .id =3D SM8250_MASTER_GEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 6, + .links =3D { SM8250_SLAVE_PIMEM, + SM8250_SLAVE_OCIMEM, + SM8250_SLAVE_APPSS, + SM8250_SNOC_CNOC_SLV, + SM8250_SLAVE_TCU, + SM8250_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie =3D { + .name =3D "qnm_gemnoc_pcie", + .id =3D SM8250_MASTER_GEM_NOC_PCIE_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 3, + .links =3D { SM8250_SLAVE_PCIE_2, + SM8250_SLAVE_PCIE_0, + SM8250_SLAVE_PCIE_1 + }, +}; + +static struct qcom_icc_node qxm_pimem =3D { + .name =3D "qxm_pimem", + .id =3D SM8250_MASTER_PIMEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node xm_gic =3D { + .name =3D "xm_gic", + .id =3D SM8250_MASTER_GIC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node qns_a1noc_snoc =3D { + .name =3D "qns_a1noc_snoc", + .id =3D SM8250_A1NOC_SNOC_SLV, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8250_A1NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node qns_pcie_modem_mem_noc =3D { + .name =3D "qns_pcie_modem_mem_noc", + .id =3D SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8250_MASTER_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node srvc_aggre1_noc =3D { + .name =3D "srvc_aggre1_noc", + .id =3D SM8250_SLAVE_SERVICE_A1NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc =3D { + .name =3D "qns_a2noc_snoc", + .id =3D SM8250_A2NOC_SNOC_SLV, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8250_A2NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node qns_pcie_mem_noc =3D { + .name =3D "qns_pcie_mem_noc", + .id =3D SM8250_SLAVE_ANOC_PCIE_GEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8250_MASTER_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc =3D { + .name =3D "srvc_aggre2_noc", + .id =3D SM8250_SLAVE_SERVICE_A2NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_cdsp_mem_noc =3D { + .name =3D "qns_cdsp_mem_noc", + .id =3D SM8250_SLAVE_CDSP_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg =3D { + .name =3D "qhs_a1_noc_cfg", + .id =3D SM8250_SLAVE_A1NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhs_a2_noc_cfg =3D { + .name =3D "qhs_a2_noc_cfg", + .id =3D SM8250_SLAVE_A2NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qhs_ahb2phy0 =3D { + .name =3D "qhs_ahb2phy0", + .id =3D SM8250_SLAVE_AHB2PHY_SOUTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy1 =3D { + .name =3D "qhs_ahb2phy1", + .id =3D SM8250_SLAVE_AHB2PHY_NORTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .id =3D SM8250_SLAVE_AOSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_cfg =3D { + .name =3D "qhs_camera_cfg", + .id =3D SM8250_SLAVE_CAMERA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .id =3D SM8250_SLAVE_CLK_CTL, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_compute_dsp =3D { + .name =3D "qhs_compute_dsp", + .id =3D SM8250_SLAVE_CDSP_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_cx =3D { + .name =3D "qhs_cpr_cx", + .id =3D SM8250_SLAVE_RBCPR_CX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_mmcx =3D { + .name =3D "qhs_cpr_mmcx", + .id =3D SM8250_SLAVE_RBCPR_MMCX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_mx =3D { + .name =3D "qhs_cpr_mx", + .id =3D SM8250_SLAVE_RBCPR_MX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg =3D { + .name =3D "qhs_crypto0_cfg", + .id =3D SM8250_SLAVE_CRYPTO_0_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cx_rdpm =3D { + .name =3D "qhs_cx_rdpm", + .id =3D SM8250_SLAVE_CX_RDPM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_dcc_cfg =3D { + .name =3D "qhs_dcc_cfg", + .id =3D SM8250_SLAVE_DCC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg =3D { + .name =3D "qhs_ddrss_cfg", + .id =3D SM8250_SLAVE_CNOC_DDRSS, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qhs_display_cfg =3D { + .name =3D "qhs_display_cfg", + .id =3D SM8250_SLAVE_DISPLAY_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg =3D { + .name =3D "qhs_gpuss_cfg", + .id =3D SM8250_SLAVE_GRAPHICS_3D_CFG, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .id =3D SM8250_SLAVE_IMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipa =3D { + .name =3D "qhs_ipa", + .id =3D SM8250_SLAVE_IPA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipc_router =3D { + .name =3D "qhs_ipc_router", + .id =3D SM8250_SLAVE_IPC_ROUTER_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_lpass_cfg =3D { + .name =3D "qhs_lpass_cfg", + .id =3D SM8250_SLAVE_LPASS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg =3D { + .name =3D "qhs_mnoc_cfg", + .id =3D SM8250_SLAVE_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qhs_npu_cfg =3D { + .name =3D "qhs_npu_cfg", + .id =3D SM8250_SLAVE_NPU_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_MASTER_NPU_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_pcie0_cfg =3D { + .name =3D "qhs_pcie0_cfg", + .id =3D SM8250_SLAVE_PCIE_0_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie1_cfg =3D { + .name =3D "qhs_pcie1_cfg", + .id =3D SM8250_SLAVE_PCIE_1_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie_modem_cfg =3D { + .name =3D "qhs_pcie_modem_cfg", + .id =3D SM8250_SLAVE_PCIE_2_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pdm =3D { + .name =3D "qhs_pdm", + .id =3D SM8250_SLAVE_PDM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg =3D { + .name =3D "qhs_pimem_cfg", + .id =3D SM8250_SLAVE_PIMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_prng =3D { + .name =3D "qhs_prng", + .id =3D SM8250_SLAVE_PRNG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .id =3D SM8250_SLAVE_QDSS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qspi =3D { + .name =3D "qhs_qspi", + .id =3D SM8250_SLAVE_QSPI_0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup0 =3D { + .name =3D "qhs_qup0", + .id =3D SM8250_SLAVE_QUP_0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup1 =3D { + .name =3D "qhs_qup1", + .id =3D SM8250_SLAVE_QUP_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup2 =3D { + .name =3D "qhs_qup2", + .id =3D SM8250_SLAVE_QUP_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc2 =3D { + .name =3D "qhs_sdc2", + .id =3D SM8250_SLAVE_SDCC_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc4 =3D { + .name =3D "qhs_sdc4", + .id =3D SM8250_SLAVE_SDCC_4, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg =3D { + .name =3D "qhs_snoc_cfg", + .id =3D SM8250_SLAVE_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .id =3D SM8250_SLAVE_TCSR, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm0 =3D { + .name =3D "qhs_tlmm0", + .id =3D SM8250_SLAVE_TLMM_NORTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm1 =3D { + .name =3D "qhs_tlmm1", + .id =3D SM8250_SLAVE_TLMM_SOUTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm2 =3D { + .name =3D "qhs_tlmm2", + .id =3D SM8250_SLAVE_TLMM_WEST, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tsif =3D { + .name =3D "qhs_tsif", + .id =3D SM8250_SLAVE_TSIF, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_card_cfg =3D { + .name =3D "qhs_ufs_card_cfg", + .id =3D SM8250_SLAVE_UFS_CARD_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg =3D { + .name =3D "qhs_ufs_mem_cfg", + .id =3D SM8250_SLAVE_UFS_MEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_0 =3D { + .name =3D "qhs_usb3_0", + .id =3D SM8250_SLAVE_USB3, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_1 =3D { + .name =3D "qhs_usb3_1", + .id =3D SM8250_SLAVE_USB3_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_venus_cfg =3D { + .name =3D "qhs_venus_cfg", + .id =3D SM8250_SLAVE_VENUS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { + .name =3D "qhs_vsense_ctrl_cfg", + .id =3D SM8250_SLAVE_VSENSE_CTRL_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_cnoc_a2noc =3D { + .name =3D "qns_cnoc_a2noc", + .id =3D SM8250_SLAVE_CNOC_A2NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_MASTER_CNOC_A2NOC }, +}; + +static struct qcom_icc_node srvc_cnoc =3D { + .name =3D "srvc_cnoc", + .id =3D SM8250_SLAVE_SERVICE_CNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_llcc =3D { + .name =3D "qhs_llcc", + .id =3D SM8250_SLAVE_LLCC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_memnoc =3D { + .name =3D "qhs_memnoc", + .id =3D SM8250_SLAVE_GEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_MASTER_GEM_NOC_CFG }, +}; + +static struct qcom_icc_node qns_gem_noc_snoc =3D { + .name =3D "qns_gem_noc_snoc", + .id =3D SM8250_SLAVE_GEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8250_MASTER_GEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .id =3D SM8250_SLAVE_LLCC, + .channels =3D 4, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8250_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_sys_pcie =3D { + .name =3D "qns_sys_pcie", + .id =3D SM8250_SLAVE_MEM_NOC_PCIE_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_MASTER_GEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node srvc_even_gemnoc =3D { + .name =3D "srvc_even_gemnoc", + .id =3D SM8250_SLAVE_SERVICE_GEM_NOC_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_odd_gemnoc =3D { + .name =3D "srvc_odd_gemnoc", + .id =3D SM8250_SLAVE_SERVICE_GEM_NOC_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_sys_gemnoc =3D { + .name =3D "srvc_sys_gemnoc", + .id =3D SM8250_SLAVE_SERVICE_GEM_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .id =3D SM8250_SLAVE_EBI_CH0, + .channels =3D 4, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf =3D { + .name =3D "qns_mem_noc_hf", + .id =3D SM8250_SLAVE_MNOC_HF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_sf =3D { + .name =3D "qns_mem_noc_sf", + .id =3D SM8250_SLAVE_MNOC_SF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc =3D { + .name =3D "srvc_mnoc", + .id =3D SM8250_SLAVE_SERVICE_MNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cal_dp0 =3D { + .name =3D "qhs_cal_dp0", + .id =3D SM8250_SLAVE_NPU_CAL_DP0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cal_dp1 =3D { + .name =3D "qhs_cal_dp1", + .id =3D SM8250_SLAVE_NPU_CAL_DP1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cp =3D { + .name =3D "qhs_cp", + .id =3D SM8250_SLAVE_NPU_CP, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_dma_bwmon =3D { + .name =3D "qhs_dma_bwmon", + .id =3D SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_dpm =3D { + .name =3D "qhs_dpm", + .id =3D SM8250_SLAVE_NPU_DPM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_isense =3D { + .name =3D "qhs_isense", + .id =3D SM8250_SLAVE_ISENSE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_llm =3D { + .name =3D "qhs_llm", + .id =3D SM8250_SLAVE_NPU_LLM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tcm =3D { + .name =3D "qhs_tcm", + .id =3D SM8250_SLAVE_NPU_TCM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_npu_sys =3D { + .name =3D "qns_npu_sys", + .id =3D SM8250_SLAVE_NPU_COMPUTE_NOC, + .channels =3D 2, + .buswidth =3D 32, +}; + +static struct qcom_icc_node srvc_noc =3D { + .name =3D "srvc_noc", + .id =3D SM8250_SLAVE_SERVICE_NPU_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_apss =3D { + .name =3D "qhs_apss", + .id =3D SM8250_SLAVE_APPSS, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qns_cnoc =3D { + .name =3D "qns_cnoc", + .id =3D SM8250_SNOC_CNOC_SLV, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_SNOC_CNOC_MAS }, +}; + +static struct qcom_icc_node qns_gemnoc_gc =3D { + .name =3D "qns_gemnoc_gc", + .id =3D SM8250_SLAVE_SNOC_GEM_NOC_GC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf =3D { + .name =3D "qns_gemnoc_sf", + .id =3D SM8250_SLAVE_SNOC_GEM_NOC_SF, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8250_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .id =3D SM8250_SLAVE_OCIMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qxs_pimem =3D { + .name =3D "qxs_pimem", + .id =3D SM8250_SLAVE_PIMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node srvc_snoc =3D { + .name =3D "srvc_snoc", + .id =3D SM8250_SLAVE_SERVICE_SNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_pcie_0 =3D { + .name =3D "xs_pcie_0", + .id =3D SM8250_SLAVE_PCIE_0, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node xs_pcie_1 =3D { + .name =3D "xs_pcie_1", + .id =3D SM8250_SLAVE_PCIE_1, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node xs_pcie_modem =3D { + .name =3D "xs_pcie_modem", + .id =3D SM8250_SLAVE_PCIE_2, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .id =3D SM8250_SLAVE_QDSS_STM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .id =3D SM8250_SLAVE_TCU, + .channels =3D 1, + .buswidth =3D 8, +}; =20 static struct qcom_icc_node qup0_core_master =3D { .name =3D "qup0_core_master", --=20 2.41.0