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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:42 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:11 +0200 Subject: [PATCH 12/53] interconnect: qcom: sm8150: Retire DEFINE_QNODE MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-12-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=43197; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=KfeJu81yzM9UtZk6tkFn5rt1KeKxy7YZJdapT6RtiNw=; b=T8eC75GAZGawcHThG7JAbyPR4AmdmaoW8EFm/joEvmxnDDGfl888D7MR5q96nD7rk7l8HkAu1 ciO7wLacAWOB6/b+0WKlSa2N3GcscOr0fn9I/hrc1p+Cydc2QUslnxb X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8150.c | 1401 ++++++++++++++++++++++++++++++++= ---- 1 file changed, 1263 insertions(+), 138 deletions(-) diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom= /sm8150.c index c5ab29322164..29f16899cf5d 100644 --- a/drivers/interconnect/qcom/sm8150.c +++ b/drivers/interconnect/qcom/sm8150.c @@ -15,144 +15,1269 @@ #include "icc-rpmh.h" #include "sm8150.h" =20 -DEFINE_QNODE(qhm_a1noc_cfg, SM8150_MASTER_A1NOC_CFG, 1, 4, SM8150_SLAVE_SE= RVICE_A1NOC); -DEFINE_QNODE(qhm_qup0, SM8150_MASTER_QUP_0, 1, 4, SM8150_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_emac, SM8150_MASTER_EMAC, 1, 8, SM8150_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_ufs_mem, SM8150_MASTER_UFS_MEM, 1, 8, SM8150_A1NOC_SNOC_SL= V); -DEFINE_QNODE(xm_usb3_0, SM8150_MASTER_USB3, 1, 8, SM8150_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_usb3_1, SM8150_MASTER_USB3_1, 1, 8, SM8150_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_a2noc_cfg, SM8150_MASTER_A2NOC_CFG, 1, 4, SM8150_SLAVE_SE= RVICE_A2NOC); -DEFINE_QNODE(qhm_qdss_bam, SM8150_MASTER_QDSS_BAM, 1, 4, SM8150_A2NOC_SNOC= _SLV); -DEFINE_QNODE(qhm_qspi, SM8150_MASTER_QSPI, 1, 4, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qup1, SM8150_MASTER_QUP_1, 1, 4, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qup2, SM8150_MASTER_QUP_2, 1, 4, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qhm_sensorss_ahb, SM8150_MASTER_SENSORS_AHB, 1, 4, SM8150_A2N= OC_SNOC_SLV); -DEFINE_QNODE(qhm_tsif, SM8150_MASTER_TSIF, 1, 4, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qnm_cnoc, SM8150_MASTER_CNOC_A2NOC, 1, 8, SM8150_A2NOC_SNOC_S= LV); -DEFINE_QNODE(qxm_crypto, SM8150_MASTER_CRYPTO_CORE_0, 1, 8, SM8150_A2NOC_S= NOC_SLV); -DEFINE_QNODE(qxm_ipa, SM8150_MASTER_IPA, 1, 8, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_pcie3_0, SM8150_MASTER_PCIE, 1, 8, SM8150_SLAVE_ANOC_PCIE_= GEM_NOC); -DEFINE_QNODE(xm_pcie3_1, SM8150_MASTER_PCIE_1, 1, 8, SM8150_SLAVE_ANOC_PCI= E_GEM_NOC); -DEFINE_QNODE(xm_qdss_etr, SM8150_MASTER_QDSS_ETR, 1, 8, SM8150_A2NOC_SNOC_= SLV); -DEFINE_QNODE(xm_sdc2, SM8150_MASTER_SDCC_2, 1, 8, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_sdc4, SM8150_MASTER_SDCC_4, 1, 8, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SM8150_MASTER_CAMNOC_HF0_UNCOMP, 1, 32= , SM8150_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SM8150_MASTER_CAMNOC_HF1_UNCOMP, 1, 32= , SM8150_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_sf_uncomp, SM8150_MASTER_CAMNOC_SF_UNCOMP, 1, 32, = SM8150_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qnm_npu, SM8150_MASTER_NPU, 1, 32, SM8150_SLAVE_CDSP_MEM_NOC); -DEFINE_QNODE(qhm_spdm, SM8150_MASTER_SPDM, 1, 4, SM8150_SLAVE_CNOC_A2NOC); -DEFINE_QNODE(qnm_snoc, SM8150_SNOC_CNOC_MAS, 1, 8, SM8150_SLAVE_TLMM_SOUTH= , SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM= 8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_= SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SL= AVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAV= E_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG,= SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150= _SLAVE_CNOC_DDRSS, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM815= 0_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, S= M8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_= AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, S= M8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM= 8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_CFG, SM= 8150_SLAVE_AOSS, SM8150 _SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE= _USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_P= IMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_= IMEM_CFG); -DEFINE_QNODE(xm_qdss_dap, SM8150_MASTER_QDSS_DAP, 1, 8, SM8150_SLAVE_TLMM_= SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CF= G, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM= 8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM81= 50_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150= _SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC= _CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, S= M8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_CNOC_A2NOC, SM8150_SLAVE_RBCPR_MMCX_CF= G, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_= CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM815= 0_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY= _SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CA= RD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WE= ST, SM8150_SLAVE_A1NOC_ CFG, SM8150_SLAVE_AOSS, SM8150_SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, S= M8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAV= E_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLA= VE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG); -DEFINE_QNODE(qhm_cnoc_dc_noc, SM8150_MASTER_CNOC_DC_NOC, 1, 4, SM8150_SLAV= E_GEM_NOC_CFG, SM8150_SLAVE_LLCC_CFG); -DEFINE_QNODE(acm_apps, SM8150_MASTER_AMPSS_M0, 2, 32, SM8150_SLAVE_ECC, SM= 8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(acm_gpu_tcu, SM8150_MASTER_GPU_TCU, 1, 8, SM8150_SLAVE_LLCC, = SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(acm_sys_tcu, SM8150_MASTER_SYS_TCU, 1, 8, SM8150_SLAVE_LLCC, = SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qhm_gemnoc_cfg, SM8150_MASTER_GEM_NOC_CFG, 1, 4, SM8150_SLAVE= _SERVICE_GEM_NOC, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG); -DEFINE_QNODE(qnm_cmpnoc, SM8150_MASTER_COMPUTE_NOC, 2, 32, SM8150_SLAVE_EC= C, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_gpu, SM8150_MASTER_GRAPHICS_3D, 2, 32, SM8150_SLAVE_LLCC,= SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_mnoc_hf, SM8150_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8150_SLA= VE_LLCC); -DEFINE_QNODE(qnm_mnoc_sf, SM8150_MASTER_MNOC_SF_MEM_NOC, 1, 32, SM8150_SLA= VE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_pcie, SM8150_MASTER_GEM_NOC_PCIE_SNOC, 1, 16, SM8150_SLAV= E_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SM8150_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8150_SLAV= E_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SM8150_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8150_SLA= VE_LLCC); -DEFINE_QNODE(qxm_ecc, SM8150_MASTER_ECC, 2, 32, SM8150_SLAVE_LLCC); -DEFINE_QNODE(llcc_mc, SM8150_MASTER_LLCC, 4, 4, SM8150_SLAVE_EBI_CH0); -DEFINE_QNODE(qhm_mnoc_cfg, SM8150_MASTER_CNOC_MNOC_CFG, 1, 4, SM8150_SLAVE= _SERVICE_MNOC); -DEFINE_QNODE(qxm_camnoc_hf0, SM8150_MASTER_CAMNOC_HF0, 1, 32, SM8150_SLAVE= _MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_hf1, SM8150_MASTER_CAMNOC_HF1, 1, 32, SM8150_SLAVE= _MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_sf, SM8150_MASTER_CAMNOC_SF, 1, 32, SM8150_SLAVE_M= NOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SM8150_MASTER_MDP_PORT0, 1, 32, SM8150_SLAVE_MNOC_H= F_MEM_NOC); -DEFINE_QNODE(qxm_mdp1, SM8150_MASTER_MDP_PORT1, 1, 32, SM8150_SLAVE_MNOC_H= F_MEM_NOC); -DEFINE_QNODE(qxm_rot, SM8150_MASTER_ROTATOR, 1, 32, SM8150_SLAVE_MNOC_SF_M= EM_NOC); -DEFINE_QNODE(qxm_venus0, SM8150_MASTER_VIDEO_P0, 1, 32, SM8150_SLAVE_MNOC_= SF_MEM_NOC); -DEFINE_QNODE(qxm_venus1, SM8150_MASTER_VIDEO_P1, 1, 32, SM8150_SLAVE_MNOC_= SF_MEM_NOC); -DEFINE_QNODE(qxm_venus_arm9, SM8150_MASTER_VIDEO_PROC, 1, 8, SM8150_SLAVE_= MNOC_SF_MEM_NOC); -DEFINE_QNODE(qhm_snoc_cfg, SM8150_MASTER_SNOC_CFG, 1, 4, SM8150_SLAVE_SERV= ICE_SNOC); -DEFINE_QNODE(qnm_aggre1_noc, SM8150_A1NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SN= OC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS,= SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_aggre2_noc, SM8150_A2NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SN= OC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS,= SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_PCIE_0, SM8150_SLAVE_PCIE_1, SM8150_SLA= VE_TCU, SM8150_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_gemnoc, SM8150_MASTER_GEM_NOC_SNOC, 1, 8, SM8150_SLAVE_PI= MEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_= SLAVE_TCU, SM8150_SLAVE_QDSS_STM); -DEFINE_QNODE(qxm_pimem, SM8150_MASTER_PIMEM, 1, 8, SM8150_SLAVE_SNOC_GEM_N= OC_GC, SM8150_SLAVE_OCIMEM); -DEFINE_QNODE(xm_gic, SM8150_MASTER_GIC, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC= , SM8150_SLAVE_OCIMEM); -DEFINE_QNODE(qns_a1noc_snoc, SM8150_A1NOC_SNOC_SLV, 1, 16, SM8150_A1NOC_SN= OC_MAS); -DEFINE_QNODE(srvc_aggre1_noc, SM8150_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(qns_a2noc_snoc, SM8150_A2NOC_SNOC_SLV, 1, 16, SM8150_A2NOC_SN= OC_MAS); -DEFINE_QNODE(qns_pcie_mem_noc, SM8150_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM81= 50_MASTER_GEM_NOC_PCIE_SNOC); -DEFINE_QNODE(srvc_aggre2_noc, SM8150_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qns_camnoc_uncomp, SM8150_SLAVE_CAMNOC_UNCOMP, 1, 32); -DEFINE_QNODE(qns_cdsp_mem_noc, SM8150_SLAVE_CDSP_MEM_NOC, 2, 32, SM8150_MA= STER_COMPUTE_NOC); -DEFINE_QNODE(qhs_a1_noc_cfg, SM8150_SLAVE_A1NOC_CFG, 1, 4, SM8150_MASTER_A= 1NOC_CFG); -DEFINE_QNODE(qhs_a2_noc_cfg, SM8150_SLAVE_A2NOC_CFG, 1, 4, SM8150_MASTER_A= 2NOC_CFG); -DEFINE_QNODE(qhs_ahb2phy_south, SM8150_SLAVE_AHB2PHY_SOUTH, 1, 4); -DEFINE_QNODE(qhs_aop, SM8150_SLAVE_AOP, 1, 4); -DEFINE_QNODE(qhs_aoss, SM8150_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_camera_cfg, SM8150_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SM8150_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_compute_dsp, SM8150_SLAVE_CDSP_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SM8150_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mmcx, SM8150_SLAVE_RBCPR_MMCX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mx, SM8150_SLAVE_RBCPR_MX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SM8150_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_ddrss_cfg, SM8150_SLAVE_CNOC_DDRSS, 1, 4, SM8150_MASTER_C= NOC_DC_NOC); -DEFINE_QNODE(qhs_display_cfg, SM8150_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_emac_cfg, SM8150_SLAVE_EMAC_CFG, 1, 4); -DEFINE_QNODE(qhs_glm, SM8150_SLAVE_GLM, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SM8150_SLAVE_GRAPHICS_3D_CFG, 1, 8); -DEFINE_QNODE(qhs_imem_cfg, SM8150_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SM8150_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mnoc_cfg, SM8150_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8150_MASTER= _CNOC_MNOC_CFG); -DEFINE_QNODE(qhs_npu_cfg, SM8150_SLAVE_NPU_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie0_cfg, SM8150_SLAVE_PCIE_0_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie1_cfg, SM8150_SLAVE_PCIE_1_CFG, 1, 4); -DEFINE_QNODE(qhs_phy_refgen_north, SM8150_SLAVE_NORTH_PHY_CFG, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SM8150_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_prng, SM8150_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SM8150_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qspi, SM8150_SLAVE_QSPI, 1, 4); -DEFINE_QNODE(qhs_qupv3_east, SM8150_SLAVE_QUP_2, 1, 4); -DEFINE_QNODE(qhs_qupv3_north, SM8150_SLAVE_QUP_1, 1, 4); -DEFINE_QNODE(qhs_qupv3_south, SM8150_SLAVE_QUP_0, 1, 4); -DEFINE_QNODE(qhs_sdc2, SM8150_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_sdc4, SM8150_SLAVE_SDCC_4, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SM8150_SLAVE_SNOC_CFG, 1, 4, SM8150_MASTER_SNOC= _CFG); -DEFINE_QNODE(qhs_spdm, SM8150_SLAVE_SPDM_WRAPPER, 1, 4); -DEFINE_QNODE(qhs_spss_cfg, SM8150_SLAVE_SPSS_CFG, 1, 4); -DEFINE_QNODE(qhs_ssc_cfg, SM8150_SLAVE_SSC_CFG, 1, 4); -DEFINE_QNODE(qhs_tcsr, SM8150_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm_east, SM8150_SLAVE_TLMM_EAST, 1, 4); -DEFINE_QNODE(qhs_tlmm_north, SM8150_SLAVE_TLMM_NORTH, 1, 4); -DEFINE_QNODE(qhs_tlmm_south, SM8150_SLAVE_TLMM_SOUTH, 1, 4); -DEFINE_QNODE(qhs_tlmm_west, SM8150_SLAVE_TLMM_WEST, 1, 4); -DEFINE_QNODE(qhs_tsif, SM8150_SLAVE_TSIF, 1, 4); -DEFINE_QNODE(qhs_ufs_card_cfg, SM8150_SLAVE_UFS_CARD_CFG, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SM8150_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3_0, SM8150_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_usb3_1, SM8150_SLAVE_USB3_1, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SM8150_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8150_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(qns_cnoc_a2noc, SM8150_SLAVE_CNOC_A2NOC, 1, 8, SM8150_MASTER_= CNOC_A2NOC); -DEFINE_QNODE(srvc_cnoc, SM8150_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(qhs_llcc, SM8150_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qhs_memnoc, SM8150_SLAVE_GEM_NOC_CFG, 1, 4, SM8150_MASTER_GEM= _NOC_CFG); -DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qns_ecc, SM8150_SLAVE_ECC, 1, 32); -DEFINE_QNODE(qns_gem_noc_snoc, SM8150_SLAVE_GEM_NOC_SNOC, 1, 8, SM8150_MAS= TER_GEM_NOC_SNOC); -DEFINE_QNODE(qns_llcc, SM8150_SLAVE_LLCC, 4, 16, SM8150_MASTER_LLCC); -DEFINE_QNODE(srvc_gemnoc, SM8150_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(ebi, SM8150_SLAVE_EBI_CH0, 4, 4); -DEFINE_QNODE(qns2_mem_noc, SM8150_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM8150_MAS= TER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_hf, SM8150_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8150_M= ASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SM8150_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qhs_apss, SM8150_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qns_cnoc, SM8150_SNOC_CNOC_SLV, 1, 8, SM8150_SNOC_CNOC_MAS); -DEFINE_QNODE(qns_gemnoc_gc, SM8150_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8150_MAS= TER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_gemnoc_sf, SM8150_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8150_MA= STER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(qxs_imem, SM8150_SLAVE_OCIMEM, 1, 8); -DEFINE_QNODE(qxs_pimem, SM8150_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SM8150_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_pcie_0, SM8150_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(xs_pcie_1, SM8150_SLAVE_PCIE_1, 1, 8); -DEFINE_QNODE(xs_qdss_stm, SM8150_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SM8150_SLAVE_TCU, 1, 8); +static struct qcom_icc_node qhm_a1noc_cfg =3D { + .name =3D "qhm_a1noc_cfg", + .id =3D SM8150_MASTER_A1NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qhm_qup0 =3D { + .name =3D "qhm_qup0", + .id =3D SM8150_MASTER_QUP_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_emac =3D { + .name =3D "xm_emac", + .id =3D SM8150_MASTER_EMAC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_ufs_mem =3D { + .name =3D "xm_ufs_mem", + .id =3D SM8150_MASTER_UFS_MEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_usb3_0 =3D { + .name =3D "xm_usb3_0", + .id =3D SM8150_MASTER_USB3, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_usb3_1 =3D { + .name =3D "xm_usb3_1", + .id =3D SM8150_MASTER_USB3_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_a2noc_cfg =3D { + .name =3D "qhm_a2noc_cfg", + .id =3D SM8150_MASTER_A2NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam =3D { + .name =3D "qhm_qdss_bam", + .id =3D SM8150_MASTER_QDSS_BAM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qspi =3D { + .name =3D "qhm_qspi", + .id =3D SM8150_MASTER_QSPI, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup1 =3D { + .name =3D "qhm_qup1", + .id =3D SM8150_MASTER_QUP_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup2 =3D { + .name =3D "qhm_qup2", + .id =3D SM8150_MASTER_QUP_2, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_sensorss_ahb =3D { + .name =3D "qhm_sensorss_ahb", + .id =3D SM8150_MASTER_SENSORS_AHB, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_tsif =3D { + .name =3D "qhm_tsif", + .id =3D SM8150_MASTER_TSIF, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qnm_cnoc =3D { + .name =3D "qnm_cnoc", + .id =3D SM8150_MASTER_CNOC_A2NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_crypto =3D { + .name =3D "qxm_crypto", + .id =3D SM8150_MASTER_CRYPTO_CORE_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_ipa =3D { + .name =3D "qxm_ipa", + .id =3D SM8150_MASTER_IPA, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_pcie3_0 =3D { + .name =3D "xm_pcie3_0", + .id =3D SM8150_MASTER_PCIE, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_1 =3D { + .name =3D "xm_pcie3_1", + .id =3D SM8150_MASTER_PCIE_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_qdss_etr =3D { + .name =3D "xm_qdss_etr", + .id =3D SM8150_MASTER_QDSS_ETR, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_sdc2 =3D { + .name =3D "xm_sdc2", + .id =3D SM8150_MASTER_SDCC_2, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_sdc4 =3D { + .name =3D "xm_sdc4", + .id =3D SM8150_MASTER_SDCC_4, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0_uncomp =3D { + .name =3D "qxm_camnoc_hf0_uncomp", + .id =3D SM8150_MASTER_CAMNOC_HF0_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1_uncomp =3D { + .name =3D "qxm_camnoc_hf1_uncomp", + .id =3D SM8150_MASTER_CAMNOC_HF1_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_sf_uncomp =3D { + .name =3D "qxm_camnoc_sf_uncomp", + .id =3D SM8150_MASTER_CAMNOC_SF_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qnm_npu =3D { + .name =3D "qnm_npu", + .id =3D SM8150_MASTER_NPU, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_CDSP_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_spdm =3D { + .name =3D "qhm_spdm", + .id =3D SM8150_MASTER_SPDM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_CNOC_A2NOC }, +}; + +static struct qcom_icc_node qnm_snoc =3D { + .name =3D "qnm_snoc", + .id =3D SM8150_SNOC_CNOC_MAS, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 50, + .links =3D { SM8150_SLAVE_TLMM_SOUTH, + SM8150_SLAVE_CDSP_CFG, + SM8150_SLAVE_SPSS_CFG, + SM8150_SLAVE_CAMERA_CFG, + SM8150_SLAVE_SDCC_4, + SM8150_SLAVE_SDCC_2, + SM8150_SLAVE_CNOC_MNOC_CFG, + SM8150_SLAVE_EMAC_CFG, + SM8150_SLAVE_UFS_MEM_CFG, + SM8150_SLAVE_TLMM_EAST, + SM8150_SLAVE_SSC_CFG, + SM8150_SLAVE_SNOC_CFG, + SM8150_SLAVE_NORTH_PHY_CFG, + SM8150_SLAVE_QUP_0, + SM8150_SLAVE_GLM, + SM8150_SLAVE_PCIE_1_CFG, + SM8150_SLAVE_A2NOC_CFG, + SM8150_SLAVE_QDSS_CFG, + SM8150_SLAVE_DISPLAY_CFG, + SM8150_SLAVE_TCSR, + SM8150_SLAVE_CNOC_DDRSS, + SM8150_SLAVE_RBCPR_MMCX_CFG, + SM8150_SLAVE_NPU_CFG, + SM8150_SLAVE_PCIE_0_CFG, + SM8150_SLAVE_GRAPHICS_3D_CFG, + SM8150_SLAVE_VENUS_CFG, + SM8150_SLAVE_TSIF, + SM8150_SLAVE_IPA_CFG, + SM8150_SLAVE_CLK_CTL, + SM8150_SLAVE_AOP, + SM8150_SLAVE_QUP_1, + SM8150_SLAVE_AHB2PHY_SOUTH, + SM8150_SLAVE_USB3_1, + SM8150_SLAVE_SERVICE_CNOC, + SM8150_SLAVE_UFS_CARD_CFG, + SM8150_SLAVE_QUP_2, + SM8150_SLAVE_RBCPR_CX_CFG, + SM8150_SLAVE_TLMM_WEST, + SM8150_SLAVE_A1NOC_CFG, + SM8150_SLAVE_AOSS, + SM8150_SLAVE_PRNG, + SM8150_SLAVE_VSENSE_CTRL_CFG, + SM8150_SLAVE_QSPI, + SM8150_SLAVE_USB3, + SM8150_SLAVE_SPDM_WRAPPER, + SM8150_SLAVE_CRYPTO_0_CFG, + SM8150_SLAVE_PIMEM_CFG, + SM8150_SLAVE_TLMM_NORTH, + SM8150_SLAVE_RBCPR_MX_CFG, + SM8150_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node xm_qdss_dap =3D { + .name =3D "xm_qdss_dap", + .id =3D SM8150_MASTER_QDSS_DAP, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 51, + .links =3D { SM8150_SLAVE_TLMM_SOUTH, + SM8150_SLAVE_CDSP_CFG, + SM8150_SLAVE_SPSS_CFG, + SM8150_SLAVE_CAMERA_CFG, + SM8150_SLAVE_SDCC_4, + SM8150_SLAVE_SDCC_2, + SM8150_SLAVE_CNOC_MNOC_CFG, + SM8150_SLAVE_EMAC_CFG, + SM8150_SLAVE_UFS_MEM_CFG, + SM8150_SLAVE_TLMM_EAST, + SM8150_SLAVE_SSC_CFG, + SM8150_SLAVE_SNOC_CFG, + SM8150_SLAVE_NORTH_PHY_CFG, + SM8150_SLAVE_QUP_0, + SM8150_SLAVE_GLM, + SM8150_SLAVE_PCIE_1_CFG, + SM8150_SLAVE_A2NOC_CFG, + SM8150_SLAVE_QDSS_CFG, + SM8150_SLAVE_DISPLAY_CFG, + SM8150_SLAVE_TCSR, + SM8150_SLAVE_CNOC_DDRSS, + SM8150_SLAVE_CNOC_A2NOC, + SM8150_SLAVE_RBCPR_MMCX_CFG, + SM8150_SLAVE_NPU_CFG, + SM8150_SLAVE_PCIE_0_CFG, + SM8150_SLAVE_GRAPHICS_3D_CFG, + SM8150_SLAVE_VENUS_CFG, + SM8150_SLAVE_TSIF, + SM8150_SLAVE_IPA_CFG, + SM8150_SLAVE_CLK_CTL, + SM8150_SLAVE_AOP, + SM8150_SLAVE_QUP_1, + SM8150_SLAVE_AHB2PHY_SOUTH, + SM8150_SLAVE_USB3_1, + SM8150_SLAVE_SERVICE_CNOC, + SM8150_SLAVE_UFS_CARD_CFG, + SM8150_SLAVE_QUP_2, + SM8150_SLAVE_RBCPR_CX_CFG, + SM8150_SLAVE_TLMM_WEST, + SM8150_SLAVE_A1NOC_CFG, + SM8150_SLAVE_AOSS, + SM8150_SLAVE_PRNG, + SM8150_SLAVE_VSENSE_CTRL_CFG, + SM8150_SLAVE_QSPI, + SM8150_SLAVE_USB3, + SM8150_SLAVE_SPDM_WRAPPER, + SM8150_SLAVE_CRYPTO_0_CFG, + SM8150_SLAVE_PIMEM_CFG, + SM8150_SLAVE_TLMM_NORTH, + SM8150_SLAVE_RBCPR_MX_CFG, + SM8150_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node qhm_cnoc_dc_noc =3D { + .name =3D "qhm_cnoc_dc_noc", + .id =3D SM8150_MASTER_CNOC_DC_NOC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .links =3D { SM8150_SLAVE_GEM_NOC_CFG, + SM8150_SLAVE_LLCC_CFG + }, +}; + +static struct qcom_icc_node acm_apps =3D { + .name =3D "acm_apps", + .id =3D SM8150_MASTER_AMPSS_M0, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 3, + .links =3D { SM8150_SLAVE_ECC, + SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node acm_gpu_tcu =3D { + .name =3D "acm_gpu_tcu", + .id =3D SM8150_MASTER_GPU_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node acm_sys_tcu =3D { + .name =3D "acm_sys_tcu", + .id =3D SM8150_MASTER_SYS_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_gemnoc_cfg =3D { + .name =3D "qhm_gemnoc_cfg", + .id =3D SM8150_MASTER_GEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .links =3D { SM8150_SLAVE_SERVICE_GEM_NOC, + SM8150_SLAVE_MSS_PROC_MS_MPU_CFG + }, +}; + +static struct qcom_icc_node qnm_cmpnoc =3D { + .name =3D "qnm_cmpnoc", + .id =3D SM8150_MASTER_COMPUTE_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 3, + .links =3D { SM8150_SLAVE_ECC, + SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_gpu =3D { + .name =3D "qnm_gpu", + .id =3D SM8150_MASTER_GRAPHICS_3D, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_mnoc_hf =3D { + .name =3D "qnm_mnoc_hf", + .id =3D SM8150_MASTER_MNOC_HF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_sf =3D { + .name =3D "qnm_mnoc_sf", + .id =3D SM8150_MASTER_MNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_pcie =3D { + .name =3D "qnm_pcie", + .id =3D SM8150_MASTER_GEM_NOC_PCIE_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 2, + .links =3D { SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc =3D { + .name =3D "qnm_snoc_gc", + .id =3D SM8150_MASTER_SNOC_GC_MEM_NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf =3D { + .name =3D "qnm_snoc_sf", + .id =3D SM8150_MASTER_SNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qxm_ecc =3D { + .name =3D "qxm_ecc", + .id =3D SM8150_MASTER_ECC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_LLCC }, +}; + +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .id =3D SM8150_MASTER_LLCC, + .channels =3D 4, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_EBI_CH0 }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg =3D { + .name =3D "qhm_mnoc_cfg", + .id =3D SM8150_MASTER_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0 =3D { + .name =3D "qxm_camnoc_hf0", + .id =3D SM8150_MASTER_CAMNOC_HF0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1 =3D { + .name =3D "qxm_camnoc_hf1", + .id =3D SM8150_MASTER_CAMNOC_HF1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_sf =3D { + .name =3D "qxm_camnoc_sf", + .id =3D SM8150_MASTER_CAMNOC_SF, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 =3D { + .name =3D "qxm_mdp0", + .id =3D SM8150_MASTER_MDP_PORT0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp1 =3D { + .name =3D "qxm_mdp1", + .id =3D SM8150_MASTER_MDP_PORT1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_rot =3D { + .name =3D "qxm_rot", + .id =3D SM8150_MASTER_ROTATOR, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus0 =3D { + .name =3D "qxm_venus0", + .id =3D SM8150_MASTER_VIDEO_P0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus1 =3D { + .name =3D "qxm_venus1", + .id =3D SM8150_MASTER_VIDEO_P1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus_arm9 =3D { + .name =3D "qxm_venus_arm9", + .id =3D SM8150_MASTER_VIDEO_PROC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_snoc_cfg =3D { + .name =3D "qhm_snoc_cfg", + .id =3D SM8150_MASTER_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc =3D { + .name =3D "qnm_aggre1_noc", + .id =3D SM8150_A1NOC_SNOC_MAS, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 6, + .links =3D { SM8150_SLAVE_SNOC_GEM_NOC_SF, + SM8150_SLAVE_PIMEM, + SM8150_SLAVE_OCIMEM, + SM8150_SLAVE_APPSS, + SM8150_SNOC_CNOC_SLV, + SM8150_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_aggre2_noc =3D { + .name =3D "qnm_aggre2_noc", + .id =3D SM8150_A2NOC_SNOC_MAS, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 9, + .links =3D { SM8150_SLAVE_SNOC_GEM_NOC_SF, + SM8150_SLAVE_PIMEM, + SM8150_SLAVE_OCIMEM, + SM8150_SLAVE_APPSS, + SM8150_SNOC_CNOC_SLV, + SM8150_SLAVE_PCIE_0, + SM8150_SLAVE_PCIE_1, + SM8150_SLAVE_TCU, + SM8150_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_gemnoc =3D { + .name =3D "qnm_gemnoc", + .id =3D SM8150_MASTER_GEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 6, + .links =3D { SM8150_SLAVE_PIMEM, + SM8150_SLAVE_OCIMEM, + SM8150_SLAVE_APPSS, + SM8150_SNOC_CNOC_SLV, + SM8150_SLAVE_TCU, + SM8150_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qxm_pimem =3D { + .name =3D "qxm_pimem", + .id =3D SM8150_MASTER_PIMEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM8150_SLAVE_SNOC_GEM_NOC_GC, + SM8150_SLAVE_OCIMEM + }, +}; + +static struct qcom_icc_node xm_gic =3D { + .name =3D "xm_gic", + .id =3D SM8150_MASTER_GIC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM8150_SLAVE_SNOC_GEM_NOC_GC, + SM8150_SLAVE_OCIMEM + }, +}; + +static struct qcom_icc_node qns_a1noc_snoc =3D { + .name =3D "qns_a1noc_snoc", + .id =3D SM8150_A1NOC_SNOC_SLV, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8150_A1NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node srvc_aggre1_noc =3D { + .name =3D "srvc_aggre1_noc", + .id =3D SM8150_SLAVE_SERVICE_A1NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc =3D { + .name =3D "qns_a2noc_snoc", + .id =3D SM8150_A2NOC_SNOC_SLV, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node qns_pcie_mem_noc =3D { + .name =3D "qns_pcie_mem_noc", + .id =3D SM8150_SLAVE_ANOC_PCIE_GEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8150_MASTER_GEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc =3D { + .name =3D "srvc_aggre2_noc", + .id =3D SM8150_SLAVE_SERVICE_A2NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_camnoc_uncomp =3D { + .name =3D "qns_camnoc_uncomp", + .id =3D SM8150_SLAVE_CAMNOC_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, +}; + +static struct qcom_icc_node qns_cdsp_mem_noc =3D { + .name =3D "qns_cdsp_mem_noc", + .id =3D SM8150_SLAVE_CDSP_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg =3D { + .name =3D "qhs_a1_noc_cfg", + .id =3D SM8150_SLAVE_A1NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhs_a2_noc_cfg =3D { + .name =3D "qhs_a2_noc_cfg", + .id =3D SM8150_SLAVE_A2NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qhs_ahb2phy_south =3D { + .name =3D "qhs_ahb2phy_south", + .id =3D SM8150_SLAVE_AHB2PHY_SOUTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_aop =3D { + .name =3D "qhs_aop", + .id =3D SM8150_SLAVE_AOP, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .id =3D SM8150_SLAVE_AOSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_cfg =3D { + .name =3D "qhs_camera_cfg", + .id =3D SM8150_SLAVE_CAMERA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .id =3D SM8150_SLAVE_CLK_CTL, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_compute_dsp =3D { + .name =3D "qhs_compute_dsp", + .id =3D SM8150_SLAVE_CDSP_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_cx =3D { + .name =3D "qhs_cpr_cx", + .id =3D SM8150_SLAVE_RBCPR_CX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_mmcx =3D { + .name =3D "qhs_cpr_mmcx", + .id =3D SM8150_SLAVE_RBCPR_MMCX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_mx =3D { + .name =3D "qhs_cpr_mx", + .id =3D SM8150_SLAVE_RBCPR_MX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg =3D { + .name =3D "qhs_crypto0_cfg", + .id =3D SM8150_SLAVE_CRYPTO_0_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg =3D { + .name =3D "qhs_ddrss_cfg", + .id =3D SM8150_SLAVE_CNOC_DDRSS, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qhs_display_cfg =3D { + .name =3D "qhs_display_cfg", + .id =3D SM8150_SLAVE_DISPLAY_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_emac_cfg =3D { + .name =3D "qhs_emac_cfg", + .id =3D SM8150_SLAVE_EMAC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_glm =3D { + .name =3D "qhs_glm", + .id =3D SM8150_SLAVE_GLM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg =3D { + .name =3D "qhs_gpuss_cfg", + .id =3D SM8150_SLAVE_GRAPHICS_3D_CFG, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .id =3D SM8150_SLAVE_IMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipa =3D { + .name =3D "qhs_ipa", + .id =3D SM8150_SLAVE_IPA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg =3D { + .name =3D "qhs_mnoc_cfg", + .id =3D SM8150_SLAVE_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qhs_npu_cfg =3D { + .name =3D "qhs_npu_cfg", + .id =3D SM8150_SLAVE_NPU_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie0_cfg =3D { + .name =3D "qhs_pcie0_cfg", + .id =3D SM8150_SLAVE_PCIE_0_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie1_cfg =3D { + .name =3D "qhs_pcie1_cfg", + .id =3D SM8150_SLAVE_PCIE_1_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_phy_refgen_north =3D { + .name =3D "qhs_phy_refgen_north", + .id =3D SM8150_SLAVE_NORTH_PHY_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg =3D { + .name =3D "qhs_pimem_cfg", + .id =3D SM8150_SLAVE_PIMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_prng =3D { + .name =3D "qhs_prng", + .id =3D SM8150_SLAVE_PRNG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .id =3D SM8150_SLAVE_QDSS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qspi =3D { + .name =3D "qhs_qspi", + .id =3D SM8150_SLAVE_QSPI, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qupv3_east =3D { + .name =3D "qhs_qupv3_east", + .id =3D SM8150_SLAVE_QUP_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qupv3_north =3D { + .name =3D "qhs_qupv3_north", + .id =3D SM8150_SLAVE_QUP_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qupv3_south =3D { + .name =3D "qhs_qupv3_south", + .id =3D SM8150_SLAVE_QUP_0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc2 =3D { + .name =3D "qhs_sdc2", + .id =3D SM8150_SLAVE_SDCC_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc4 =3D { + .name =3D "qhs_sdc4", + .id =3D SM8150_SLAVE_SDCC_4, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg =3D { + .name =3D "qhs_snoc_cfg", + .id =3D SM8150_SLAVE_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_spdm =3D { + .name =3D "qhs_spdm", + .id =3D SM8150_SLAVE_SPDM_WRAPPER, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_spss_cfg =3D { + .name =3D "qhs_spss_cfg", + .id =3D SM8150_SLAVE_SPSS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ssc_cfg =3D { + .name =3D "qhs_ssc_cfg", + .id =3D SM8150_SLAVE_SSC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .id =3D SM8150_SLAVE_TCSR, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm_east =3D { + .name =3D "qhs_tlmm_east", + .id =3D SM8150_SLAVE_TLMM_EAST, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm_north =3D { + .name =3D "qhs_tlmm_north", + .id =3D SM8150_SLAVE_TLMM_NORTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm_south =3D { + .name =3D "qhs_tlmm_south", + .id =3D SM8150_SLAVE_TLMM_SOUTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm_west =3D { + .name =3D "qhs_tlmm_west", + .id =3D SM8150_SLAVE_TLMM_WEST, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tsif =3D { + .name =3D "qhs_tsif", + .id =3D SM8150_SLAVE_TSIF, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_card_cfg =3D { + .name =3D "qhs_ufs_card_cfg", + .id =3D SM8150_SLAVE_UFS_CARD_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg =3D { + .name =3D "qhs_ufs_mem_cfg", + .id =3D SM8150_SLAVE_UFS_MEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_0 =3D { + .name =3D "qhs_usb3_0", + .id =3D SM8150_SLAVE_USB3, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_1 =3D { + .name =3D "qhs_usb3_1", + .id =3D SM8150_SLAVE_USB3_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_venus_cfg =3D { + .name =3D "qhs_venus_cfg", + .id =3D SM8150_SLAVE_VENUS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { + .name =3D "qhs_vsense_ctrl_cfg", + .id =3D SM8150_SLAVE_VSENSE_CTRL_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_cnoc_a2noc =3D { + .name =3D "qns_cnoc_a2noc", + .id =3D SM8150_SLAVE_CNOC_A2NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_MASTER_CNOC_A2NOC }, +}; + +static struct qcom_icc_node srvc_cnoc =3D { + .name =3D "srvc_cnoc", + .id =3D SM8150_SLAVE_SERVICE_CNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_llcc =3D { + .name =3D "qhs_llcc", + .id =3D SM8150_SLAVE_LLCC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_memnoc =3D { + .name =3D "qhs_memnoc", + .id =3D SM8150_SLAVE_GEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_MASTER_GEM_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg =3D { + .name =3D "qhs_mdsp_ms_mpu_cfg", + .id =3D SM8150_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_ecc =3D { + .name =3D "qns_ecc", + .id =3D SM8150_SLAVE_ECC, + .channels =3D 1, + .buswidth =3D 32, +}; + +static struct qcom_icc_node qns_gem_noc_snoc =3D { + .name =3D "qns_gem_noc_snoc", + .id =3D SM8150_SLAVE_GEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_MASTER_GEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .id =3D SM8150_SLAVE_LLCC, + .channels =3D 4, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8150_MASTER_LLCC }, +}; + +static struct qcom_icc_node srvc_gemnoc =3D { + .name =3D "srvc_gemnoc", + .id =3D SM8150_SLAVE_SERVICE_GEM_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .id =3D SM8150_SLAVE_EBI_CH0, + .channels =3D 4, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns2_mem_noc =3D { + .name =3D "qns2_mem_noc", + .id =3D SM8150_SLAVE_MNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_hf =3D { + .name =3D "qns_mem_noc_hf", + .id =3D SM8150_SLAVE_MNOC_HF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc =3D { + .name =3D "srvc_mnoc", + .id =3D SM8150_SLAVE_SERVICE_MNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_apss =3D { + .name =3D "qhs_apss", + .id =3D SM8150_SLAVE_APPSS, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qns_cnoc =3D { + .name =3D "qns_cnoc", + .id =3D SM8150_SNOC_CNOC_SLV, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_SNOC_CNOC_MAS }, +}; + +static struct qcom_icc_node qns_gemnoc_gc =3D { + .name =3D "qns_gemnoc_gc", + .id =3D SM8150_SLAVE_SNOC_GEM_NOC_GC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf =3D { + .name =3D "qns_gemnoc_sf", + .id =3D SM8150_SLAVE_SNOC_GEM_NOC_SF, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8150_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .id =3D SM8150_SLAVE_OCIMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qxs_pimem =3D { + .name =3D "qxs_pimem", + .id =3D SM8150_SLAVE_PIMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node srvc_snoc =3D { + .name =3D "srvc_snoc", + .id =3D SM8150_SLAVE_SERVICE_SNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_pcie_0 =3D { + .name =3D "xs_pcie_0", + .id =3D SM8150_SLAVE_PCIE_0, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node xs_pcie_1 =3D { + .name =3D "xs_pcie_1", + .id =3D SM8150_SLAVE_PCIE_1, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .id =3D SM8150_SLAVE_QDSS_STM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .id =3D SM8150_SLAVE_TCU, + .channels =3D 1, + .buswidth =3D 8, +}; =20 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); --=20 2.41.0