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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:40 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:10 +0200 Subject: [PATCH 11/53] interconnect: qcom: sm6350: Retire DEFINE_QNODE MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-11-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=39658; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Vn2Dl/Zh9To6jL368CWOwQ/9G+yXzmEWxN811xRUl7w=; b=jTY8FGQBDJ6+bvx3jOIgPc97Y9WS7ggW4CD1BvtS0I8w0tjtiXJhYoG02YfJRyoBasAbPSjIk wj26hmOA5EMAoSWzmGloh/1ysJN/Vn2S4McKWsOLHlLKBXf5aaL/i89 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm6350.c | 1273 ++++++++++++++++++++++++++++++++= ---- 1 file changed, 1146 insertions(+), 127 deletions(-) diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom= /sm6350.c index a3d46e59444e..7421eb4cd520 100644 --- a/drivers/interconnect/qcom/sm6350.c +++ b/drivers/interconnect/qcom/sm6350.c @@ -14,133 +14,1152 @@ #include "icc-rpmh.h" #include "sm6350.h" =20 -DEFINE_QNODE(qhm_a1noc_cfg, SM6350_MASTER_A1NOC_CFG, 1, 4, SM6350_SLAVE_SE= RVICE_A1NOC); -DEFINE_QNODE(qhm_qup_0, SM6350_MASTER_QUP_0, 1, 4, SM6350_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_emmc, SM6350_MASTER_EMMC, 1, 8, SM6350_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_ufs_mem, SM6350_MASTER_UFS_MEM, 1, 8, SM6350_A1NOC_SNOC_SL= V); -DEFINE_QNODE(qhm_a2noc_cfg, SM6350_MASTER_A2NOC_CFG, 1, 4, SM6350_SLAVE_SE= RVICE_A2NOC); -DEFINE_QNODE(qhm_qdss_bam, SM6350_MASTER_QDSS_BAM, 1, 4, SM6350_A2NOC_SNOC= _SLV); -DEFINE_QNODE(qhm_qup_1, SM6350_MASTER_QUP_1, 1, 4, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_crypto, SM6350_MASTER_CRYPTO_CORE_0, 1, 8, SM6350_A2NOC_S= NOC_SLV); -DEFINE_QNODE(qxm_ipa, SM6350_MASTER_IPA, 1, 8, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_qdss_etr, SM6350_MASTER_QDSS_ETR, 1, 8, SM6350_A2NOC_SNOC_= SLV); -DEFINE_QNODE(xm_sdc2, SM6350_MASTER_SDCC_2, 1, 8, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_usb3_0, SM6350_MASTER_USB3, 1, 8, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SM6350_MASTER_CAMNOC_HF0_UNCOMP, 2, 32= , SM6350_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_icp_uncomp, SM6350_MASTER_CAMNOC_ICP_UNCOMP, 1, 32= , SM6350_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_sf_uncomp, SM6350_MASTER_CAMNOC_SF_UNCOMP, 1, 32, = SM6350_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qup0_core_master, SM6350_MASTER_QUP_CORE_0, 1, 4, SM6350_SLAV= E_QUP_CORE_0); -DEFINE_QNODE(qup1_core_master, SM6350_MASTER_QUP_CORE_1, 1, 4, SM6350_SLAV= E_QUP_CORE_1); -DEFINE_QNODE(qnm_npu, SM6350_MASTER_NPU, 2, 32, SM6350_SLAVE_CDSP_GEM_NOC); -DEFINE_QNODE(qxm_npu_dsp, SM6350_MASTER_NPU_PROC, 1, 8, SM6350_SLAVE_CDSP_= GEM_NOC); -DEFINE_QNODE(qnm_snoc, SM6350_SNOC_CNOC_MAS, 1, 8, SM6350_SLAVE_CAMERA_CFG= , SM6350_SLAVE_SDCC_2, SM6350_SLAVE_CNOC_MNOC_CFG, SM6350_SLAVE_UFS_MEM_CFG= , SM6350_SLAVE_QM_CFG, SM6350_SLAVE_SNOC_CFG, SM6350_SLAVE_QM_MPU_CFG, SM63= 50_SLAVE_GLM, SM6350_SLAVE_PDM, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, SM635= 0_SLAVE_A2NOC_CFG, SM6350_SLAVE_QDSS_CFG, SM6350_SLAVE_VSENSE_CTRL_CFG, SM6= 350_SLAVE_CAMERA_RT_THROTTLE_CFG, SM6350_SLAVE_DISPLAY_CFG, SM6350_SLAVE_TC= SR, SM6350_SLAVE_DCC_CFG, SM6350_SLAVE_CNOC_DDRSS, SM6350_SLAVE_DISPLAY_THR= OTTLE_CFG, SM6350_SLAVE_NPU_CFG, SM6350_SLAVE_AHB2PHY, SM6350_SLAVE_GRAPHIC= S_3D_CFG, SM6350_SLAVE_BOOT_ROM, SM6350_SLAVE_VENUS_CFG, SM6350_SLAVE_IPA_C= FG, SM6350_SLAVE_SECURITY, SM6350_SLAVE_IMEM_CFG, SM6350_SLAVE_CNOC_MSS, SM= 6350_SLAVE_SERVICE_CNOC, SM6350_SLAVE_USB3, SM6350_SLAVE_VENUS_THROTTLE_CFG= , SM6350_SLAVE_RBCPR_CX_CFG, SM6350_SLAVE_A1NOC_CFG, SM6350_SLAVE_AOSS, SM6= 350_SLAVE_PRNG, SM6350_SLAVE_EMMC_CFG, SM6350_SLAVE_CRYPTO_0_CFG, SM6350_SL= AVE_PIMEM_CFG, SM6350_S LAVE_RBCPR_MX_CFG, SM6350_SLAVE_QUP_0, SM6350_SLAVE_QUP_1, SM6350_SLAVE_CL= K_CTL); -DEFINE_QNODE(xm_qdss_dap, SM6350_MASTER_QDSS_DAP, 1, 8, SM6350_SLAVE_CAMER= A_CFG, SM6350_SLAVE_SDCC_2, SM6350_SLAVE_CNOC_MNOC_CFG, SM6350_SLAVE_UFS_ME= M_CFG, SM6350_SLAVE_QM_CFG, SM6350_SLAVE_SNOC_CFG, SM6350_SLAVE_QM_MPU_CFG,= SM6350_SLAVE_GLM, SM6350_SLAVE_PDM, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, = SM6350_SLAVE_A2NOC_CFG, SM6350_SLAVE_QDSS_CFG, SM6350_SLAVE_VSENSE_CTRL_CFG= , SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, SM6350_SLAVE_DISPLAY_CFG, SM6350_SLA= VE_TCSR, SM6350_SLAVE_DCC_CFG, SM6350_SLAVE_CNOC_DDRSS, SM6350_SLAVE_DISPLA= Y_THROTTLE_CFG, SM6350_SLAVE_NPU_CFG, SM6350_SLAVE_AHB2PHY, SM6350_SLAVE_GR= APHICS_3D_CFG, SM6350_SLAVE_BOOT_ROM, SM6350_SLAVE_VENUS_CFG, SM6350_SLAVE_= IPA_CFG, SM6350_SLAVE_SECURITY, SM6350_SLAVE_IMEM_CFG, SM6350_SLAVE_CNOC_MS= S, SM6350_SLAVE_SERVICE_CNOC, SM6350_SLAVE_USB3, SM6350_SLAVE_VENUS_THROTTL= E_CFG, SM6350_SLAVE_RBCPR_CX_CFG, SM6350_SLAVE_A1NOC_CFG, SM6350_SLAVE_AOSS= , SM6350_SLAVE_PRNG, SM6350_SLAVE_EMMC_CFG, SM6350_SLAVE_CRYPTO_0_CFG, SM63= 50_SLAVE_PIMEM_CFG, SM6 350_SLAVE_RBCPR_MX_CFG, SM6350_SLAVE_QUP_0, SM6350_SLAVE_QUP_1, SM6350_SLA= VE_CLK_CTL); -DEFINE_QNODE(qhm_cnoc_dc_noc, SM6350_MASTER_CNOC_DC_NOC, 1, 4, SM6350_SLAV= E_LLCC_CFG, SM6350_SLAVE_GEM_NOC_CFG); -DEFINE_QNODE(acm_apps, SM6350_MASTER_AMPSS_M0, 1, 16, SM6350_SLAVE_LLCC, S= M6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(acm_sys_tcu, SM6350_MASTER_SYS_TCU, 1, 8, SM6350_SLAVE_LLCC, = SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qhm_gemnoc_cfg, SM6350_MASTER_GEM_NOC_CFG, 1, 4, SM6350_SLAVE= _MCDMA_MS_MPU_CFG, SM6350_SLAVE_SERVICE_GEM_NOC, SM6350_SLAVE_MSS_PROC_MS_M= PU_CFG); -DEFINE_QNODE(qnm_cmpnoc, SM6350_MASTER_COMPUTE_NOC, 1, 32, SM6350_SLAVE_LL= CC, SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_mnoc_hf, SM6350_MASTER_MNOC_HF_MEM_NOC, 1, 32, SM6350_SLA= VE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_mnoc_sf, SM6350_MASTER_MNOC_SF_MEM_NOC, 1, 32, SM6350_SLA= VE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SM6350_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM6350_SLAV= E_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SM6350_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM6350_SLA= VE_LLCC); -DEFINE_QNODE(qxm_gpu, SM6350_MASTER_GRAPHICS_3D, 2, 32, SM6350_SLAVE_LLCC,= SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(llcc_mc, SM6350_MASTER_LLCC, 2, 4, SM6350_SLAVE_EBI_CH0); -DEFINE_QNODE(qhm_mnoc_cfg, SM6350_MASTER_CNOC_MNOC_CFG, 1, 4, SM6350_SLAVE= _SERVICE_MNOC); -DEFINE_QNODE(qnm_video0, SM6350_MASTER_VIDEO_P0, 1, 32, SM6350_SLAVE_MNOC_= SF_MEM_NOC); -DEFINE_QNODE(qnm_video_cvp, SM6350_MASTER_VIDEO_PROC, 1, 8, SM6350_SLAVE_M= NOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_hf, SM6350_MASTER_CAMNOC_HF, 2, 32, SM6350_SLAVE_M= NOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_icp, SM6350_MASTER_CAMNOC_ICP, 1, 8, SM6350_SLAVE_= MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_sf, SM6350_MASTER_CAMNOC_SF, 1, 32, SM6350_SLAVE_M= NOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SM6350_MASTER_MDP_PORT0, 1, 32, SM6350_SLAVE_MNOC_H= F_MEM_NOC); -DEFINE_QNODE(amm_npu_sys, SM6350_MASTER_NPU_SYS, 2, 32, SM6350_SLAVE_NPU_C= OMPUTE_NOC); -DEFINE_QNODE(qhm_npu_cfg, SM6350_MASTER_NPU_NOC_CFG, 1, 4, SM6350_SLAVE_SE= RVICE_NPU_NOC, SM6350_SLAVE_ISENSE_CFG, SM6350_SLAVE_NPU_LLM_CFG, SM6350_SL= AVE_NPU_INT_DMA_BWMON_CFG, SM6350_SLAVE_NPU_CP, SM6350_SLAVE_NPU_TCM, SM635= 0_SLAVE_NPU_CAL_DP0, SM6350_SLAVE_NPU_DPM); -DEFINE_QNODE(qhm_snoc_cfg, SM6350_MASTER_SNOC_CFG, 1, 4, SM6350_SLAVE_SERV= ICE_SNOC); -DEFINE_QNODE(qnm_aggre1_noc, SM6350_A1NOC_SNOC_MAS, 1, 16, SM6350_SLAVE_SN= OC_GEM_NOC_SF, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS,= SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_aggre2_noc, SM6350_A2NOC_SNOC_MAS, 1, 16, SM6350_SLAVE_SN= OC_GEM_NOC_SF, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS,= SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_TCU, SM6350_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_gemnoc, SM6350_MASTER_GEM_NOC_SNOC, 1, 8, SM6350_SLAVE_PI= MEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_= SLAVE_TCU, SM6350_SLAVE_QDSS_STM); -DEFINE_QNODE(qxm_pimem, SM6350_MASTER_PIMEM, 1, 8, SM6350_SLAVE_SNOC_GEM_N= OC_GC, SM6350_SLAVE_OCIMEM); -DEFINE_QNODE(xm_gic, SM6350_MASTER_GIC, 1, 8, SM6350_SLAVE_SNOC_GEM_NOC_GC= ); -DEFINE_QNODE(qns_a1noc_snoc, SM6350_A1NOC_SNOC_SLV, 1, 16, SM6350_A1NOC_SN= OC_MAS); -DEFINE_QNODE(srvc_aggre1_noc, SM6350_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(qns_a2noc_snoc, SM6350_A2NOC_SNOC_SLV, 1, 16, SM6350_A2NOC_SN= OC_MAS); -DEFINE_QNODE(srvc_aggre2_noc, SM6350_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qns_camnoc_uncomp, SM6350_SLAVE_CAMNOC_UNCOMP, 1, 32); -DEFINE_QNODE(qup0_core_slave, SM6350_SLAVE_QUP_CORE_0, 1, 4); -DEFINE_QNODE(qup1_core_slave, SM6350_SLAVE_QUP_CORE_1, 1, 4); -DEFINE_QNODE(qns_cdsp_gemnoc, SM6350_SLAVE_CDSP_GEM_NOC, 1, 32, SM6350_MAS= TER_COMPUTE_NOC); -DEFINE_QNODE(qhs_a1_noc_cfg, SM6350_SLAVE_A1NOC_CFG, 1, 4, SM6350_MASTER_A= 1NOC_CFG); -DEFINE_QNODE(qhs_a2_noc_cfg, SM6350_SLAVE_A2NOC_CFG, 1, 4, SM6350_MASTER_A= 2NOC_CFG); -DEFINE_QNODE(qhs_ahb2phy0, SM6350_SLAVE_AHB2PHY, 1, 4); -DEFINE_QNODE(qhs_ahb2phy2, SM6350_SLAVE_AHB2PHY_2, 1, 4); -DEFINE_QNODE(qhs_aoss, SM6350_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_boot_rom, SM6350_SLAVE_BOOT_ROM, 1, 4); -DEFINE_QNODE(qhs_camera_cfg, SM6350_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_camera_nrt_thrott_cfg, SM6350_SLAVE_CAMERA_NRT_THROTTLE_C= FG, 1, 4); -DEFINE_QNODE(qhs_camera_rt_throttle_cfg, SM6350_SLAVE_CAMERA_RT_THROTTLE_C= FG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SM6350_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SM6350_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mx, SM6350_SLAVE_RBCPR_MX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SM6350_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_dcc_cfg, SM6350_SLAVE_DCC_CFG, 1, 4); -DEFINE_QNODE(qhs_ddrss_cfg, SM6350_SLAVE_CNOC_DDRSS, 1, 4, SM6350_MASTER_C= NOC_DC_NOC); -DEFINE_QNODE(qhs_display_cfg, SM6350_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_display_throttle_cfg, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, = 1, 4); -DEFINE_QNODE(qhs_emmc_cfg, SM6350_SLAVE_EMMC_CFG, 1, 4); -DEFINE_QNODE(qhs_glm, SM6350_SLAVE_GLM, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SM6350_SLAVE_GRAPHICS_3D_CFG, 1, 8); -DEFINE_QNODE(qhs_imem_cfg, SM6350_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SM6350_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mnoc_cfg, SM6350_SLAVE_CNOC_MNOC_CFG, 1, 4, SM6350_MASTER= _CNOC_MNOC_CFG); -DEFINE_QNODE(qhs_mss_cfg, SM6350_SLAVE_CNOC_MSS, 1, 4); -DEFINE_QNODE(qhs_npu_cfg, SM6350_SLAVE_NPU_CFG, 1, 4, SM6350_MASTER_NPU_NO= C_CFG); -DEFINE_QNODE(qhs_pdm, SM6350_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SM6350_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_prng, SM6350_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SM6350_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qm_cfg, SM6350_SLAVE_QM_CFG, 1, 4); -DEFINE_QNODE(qhs_qm_mpu_cfg, SM6350_SLAVE_QM_MPU_CFG, 1, 4); -DEFINE_QNODE(qhs_qup0, SM6350_SLAVE_QUP_0, 1, 4); -DEFINE_QNODE(qhs_qup1, SM6350_SLAVE_QUP_1, 1, 4); -DEFINE_QNODE(qhs_sdc2, SM6350_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_security, SM6350_SLAVE_SECURITY, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SM6350_SLAVE_SNOC_CFG, 1, 4, SM6350_MASTER_SNOC= _CFG); -DEFINE_QNODE(qhs_tcsr, SM6350_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SM6350_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3_0, SM6350_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SM6350_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_venus_throttle_cfg, SM6350_SLAVE_VENUS_THROTTLE_CFG, 1, 4= ); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM6350_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(srvc_cnoc, SM6350_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(qhs_gemnoc, SM6350_SLAVE_GEM_NOC_CFG, 1, 4, SM6350_MASTER_GEM= _NOC_CFG); -DEFINE_QNODE(qhs_llcc, SM6350_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qhs_mcdma_ms_mpu_cfg, SM6350_SLAVE_MCDMA_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM6350_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qns_gem_noc_snoc, SM6350_SLAVE_GEM_NOC_SNOC, 1, 8, SM6350_MAS= TER_GEM_NOC_SNOC); -DEFINE_QNODE(qns_llcc, SM6350_SLAVE_LLCC, 1, 16, SM6350_MASTER_LLCC); -DEFINE_QNODE(srvc_gemnoc, SM6350_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(ebi, SM6350_SLAVE_EBI_CH0, 2, 4); -DEFINE_QNODE(qns_mem_noc_hf, SM6350_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SM6350_M= ASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_sf, SM6350_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM6350_M= ASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SM6350_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qhs_cal_dp0, SM6350_SLAVE_NPU_CAL_DP0, 1, 4); -DEFINE_QNODE(qhs_cp, SM6350_SLAVE_NPU_CP, 1, 4); -DEFINE_QNODE(qhs_dma_bwmon, SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4); -DEFINE_QNODE(qhs_dpm, SM6350_SLAVE_NPU_DPM, 1, 4); -DEFINE_QNODE(qhs_isense, SM6350_SLAVE_ISENSE_CFG, 1, 4); -DEFINE_QNODE(qhs_llm, SM6350_SLAVE_NPU_LLM_CFG, 1, 4); -DEFINE_QNODE(qhs_tcm, SM6350_SLAVE_NPU_TCM, 1, 4); -DEFINE_QNODE(qns_npu_sys, SM6350_SLAVE_NPU_COMPUTE_NOC, 2, 32); -DEFINE_QNODE(srvc_noc, SM6350_SLAVE_SERVICE_NPU_NOC, 1, 4); -DEFINE_QNODE(qhs_apss, SM6350_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qns_cnoc, SM6350_SNOC_CNOC_SLV, 1, 8, SM6350_SNOC_CNOC_MAS); -DEFINE_QNODE(qns_gemnoc_gc, SM6350_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM6350_MAS= TER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_gemnoc_sf, SM6350_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM6350_MA= STER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(qxs_imem, SM6350_SLAVE_OCIMEM, 1, 8); -DEFINE_QNODE(qxs_pimem, SM6350_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SM6350_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_qdss_stm, SM6350_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SM6350_SLAVE_TCU, 1, 8); +static struct qcom_icc_node qhm_a1noc_cfg =3D { + .name =3D "qhm_a1noc_cfg", + .id =3D SM6350_MASTER_A1NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qhm_qup_0 =3D { + .name =3D "qhm_qup_0", + .id =3D SM6350_MASTER_QUP_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_emmc =3D { + .name =3D "xm_emmc", + .id =3D SM6350_MASTER_EMMC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_ufs_mem =3D { + .name =3D "xm_ufs_mem", + .id =3D SM6350_MASTER_UFS_MEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_a2noc_cfg =3D { + .name =3D "qhm_a2noc_cfg", + .id =3D SM6350_MASTER_A2NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam =3D { + .name =3D "qhm_qdss_bam", + .id =3D SM6350_MASTER_QDSS_BAM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup_1 =3D { + .name =3D "qhm_qup_1", + .id =3D SM6350_MASTER_QUP_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_crypto =3D { + .name =3D "qxm_crypto", + .id =3D SM6350_MASTER_CRYPTO_CORE_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_ipa =3D { + .name =3D "qxm_ipa", + .id =3D SM6350_MASTER_IPA, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_qdss_etr =3D { + .name =3D "xm_qdss_etr", + .id =3D SM6350_MASTER_QDSS_ETR, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_sdc2 =3D { + .name =3D "xm_sdc2", + .id =3D SM6350_MASTER_SDCC_2, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_usb3_0 =3D { + .name =3D "xm_usb3_0", + .id =3D SM6350_MASTER_USB3, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0_uncomp =3D { + .name =3D "qxm_camnoc_hf0_uncomp", + .id =3D SM6350_MASTER_CAMNOC_HF0_UNCOMP, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_icp_uncomp =3D { + .name =3D "qxm_camnoc_icp_uncomp", + .id =3D SM6350_MASTER_CAMNOC_ICP_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_sf_uncomp =3D { + .name =3D "qxm_camnoc_sf_uncomp", + .id =3D SM6350_MASTER_CAMNOC_SF_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qup0_core_master =3D { + .name =3D "qup0_core_master", + .id =3D SM6350_MASTER_QUP_CORE_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_QUP_CORE_0 }, +}; + +static struct qcom_icc_node qup1_core_master =3D { + .name =3D "qup1_core_master", + .id =3D SM6350_MASTER_QUP_CORE_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_QUP_CORE_1 }, +}; + +static struct qcom_icc_node qnm_npu =3D { + .name =3D "qnm_npu", + .id =3D SM6350_MASTER_NPU, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_CDSP_GEM_NOC }, +}; + +static struct qcom_icc_node qxm_npu_dsp =3D { + .name =3D "qxm_npu_dsp", + .id =3D SM6350_MASTER_NPU_PROC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_CDSP_GEM_NOC }, +}; + +static struct qcom_icc_node qnm_snoc =3D { + .name =3D "qnm_snoc", + .id =3D SM6350_SNOC_CNOC_MAS, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 42, + .links =3D { SM6350_SLAVE_CAMERA_CFG, + SM6350_SLAVE_SDCC_2, + SM6350_SLAVE_CNOC_MNOC_CFG, + SM6350_SLAVE_UFS_MEM_CFG, + SM6350_SLAVE_QM_CFG, + SM6350_SLAVE_SNOC_CFG, + SM6350_SLAVE_QM_MPU_CFG, + SM6350_SLAVE_GLM, + SM6350_SLAVE_PDM, + SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SM6350_SLAVE_A2NOC_CFG, + SM6350_SLAVE_QDSS_CFG, + SM6350_SLAVE_VSENSE_CTRL_CFG, + SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, + SM6350_SLAVE_DISPLAY_CFG, + SM6350_SLAVE_TCSR, + SM6350_SLAVE_DCC_CFG, + SM6350_SLAVE_CNOC_DDRSS, + SM6350_SLAVE_DISPLAY_THROTTLE_CFG, + SM6350_SLAVE_NPU_CFG, + SM6350_SLAVE_AHB2PHY, + SM6350_SLAVE_GRAPHICS_3D_CFG, + SM6350_SLAVE_BOOT_ROM, + SM6350_SLAVE_VENUS_CFG, + SM6350_SLAVE_IPA_CFG, + SM6350_SLAVE_SECURITY, + SM6350_SLAVE_IMEM_CFG, + SM6350_SLAVE_CNOC_MSS, + SM6350_SLAVE_SERVICE_CNOC, + SM6350_SLAVE_USB3, + SM6350_SLAVE_VENUS_THROTTLE_CFG, + SM6350_SLAVE_RBCPR_CX_CFG, + SM6350_SLAVE_A1NOC_CFG, + SM6350_SLAVE_AOSS, + SM6350_SLAVE_PRNG, + SM6350_SLAVE_EMMC_CFG, + SM6350_SLAVE_CRYPTO_0_CFG, + SM6350_SLAVE_PIMEM_CFG, + SM6350_SLAVE_RBCPR_MX_CFG, + SM6350_SLAVE_QUP_0, + SM6350_SLAVE_QUP_1, + SM6350_SLAVE_CLK_CTL + }, +}; + +static struct qcom_icc_node xm_qdss_dap =3D { + .name =3D "xm_qdss_dap", + .id =3D SM6350_MASTER_QDSS_DAP, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 42, + .links =3D { SM6350_SLAVE_CAMERA_CFG, + SM6350_SLAVE_SDCC_2, + SM6350_SLAVE_CNOC_MNOC_CFG, + SM6350_SLAVE_UFS_MEM_CFG, + SM6350_SLAVE_QM_CFG, + SM6350_SLAVE_SNOC_CFG, + SM6350_SLAVE_QM_MPU_CFG, + SM6350_SLAVE_GLM, + SM6350_SLAVE_PDM, + SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SM6350_SLAVE_A2NOC_CFG, + SM6350_SLAVE_QDSS_CFG, + SM6350_SLAVE_VSENSE_CTRL_CFG, + SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, + SM6350_SLAVE_DISPLAY_CFG, + SM6350_SLAVE_TCSR, + SM6350_SLAVE_DCC_CFG, + SM6350_SLAVE_CNOC_DDRSS, + SM6350_SLAVE_DISPLAY_THROTTLE_CFG, + SM6350_SLAVE_NPU_CFG, + SM6350_SLAVE_AHB2PHY, + SM6350_SLAVE_GRAPHICS_3D_CFG, + SM6350_SLAVE_BOOT_ROM, + SM6350_SLAVE_VENUS_CFG, + SM6350_SLAVE_IPA_CFG, + SM6350_SLAVE_SECURITY, + SM6350_SLAVE_IMEM_CFG, + SM6350_SLAVE_CNOC_MSS, + SM6350_SLAVE_SERVICE_CNOC, + SM6350_SLAVE_USB3, + SM6350_SLAVE_VENUS_THROTTLE_CFG, + SM6350_SLAVE_RBCPR_CX_CFG, + SM6350_SLAVE_A1NOC_CFG, + SM6350_SLAVE_AOSS, + SM6350_SLAVE_PRNG, + SM6350_SLAVE_EMMC_CFG, + SM6350_SLAVE_CRYPTO_0_CFG, + SM6350_SLAVE_PIMEM_CFG, + SM6350_SLAVE_RBCPR_MX_CFG, + SM6350_SLAVE_QUP_0, + SM6350_SLAVE_QUP_1, + SM6350_SLAVE_CLK_CTL + }, +}; + +static struct qcom_icc_node qhm_cnoc_dc_noc =3D { + .name =3D "qhm_cnoc_dc_noc", + .id =3D SM6350_MASTER_CNOC_DC_NOC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .links =3D { SM6350_SLAVE_LLCC_CFG, + SM6350_SLAVE_GEM_NOC_CFG + }, +}; + +static struct qcom_icc_node acm_apps =3D { + .name =3D "acm_apps", + .id =3D SM6350_MASTER_AMPSS_M0, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 2, + .links =3D { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node acm_sys_tcu =3D { + .name =3D "acm_sys_tcu", + .id =3D SM6350_MASTER_SYS_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_gemnoc_cfg =3D { + .name =3D "qhm_gemnoc_cfg", + .id =3D SM6350_MASTER_GEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 3, + .links =3D { SM6350_SLAVE_MCDMA_MS_MPU_CFG, + SM6350_SLAVE_SERVICE_GEM_NOC, + SM6350_SLAVE_MSS_PROC_MS_MPU_CFG + }, +}; + +static struct qcom_icc_node qnm_cmpnoc =3D { + .name =3D "qnm_cmpnoc", + .id =3D SM6350_MASTER_COMPUTE_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_mnoc_hf =3D { + .name =3D "qnm_mnoc_hf", + .id =3D SM6350_MASTER_MNOC_HF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_mnoc_sf =3D { + .name =3D "qnm_mnoc_sf", + .id =3D SM6350_MASTER_MNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc =3D { + .name =3D "qnm_snoc_gc", + .id =3D SM6350_MASTER_SNOC_GC_MEM_NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf =3D { + .name =3D "qnm_snoc_sf", + .id =3D SM6350_MASTER_SNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qxm_gpu =3D { + .name =3D "qxm_gpu", + .id =3D SM6350_MASTER_GRAPHICS_3D, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .id =3D SM6350_MASTER_LLCC, + .channels =3D 2, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_EBI_CH0 }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg =3D { + .name =3D "qhm_mnoc_cfg", + .id =3D SM6350_MASTER_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qnm_video0 =3D { + .name =3D "qnm_video0", + .id =3D SM6350_MASTER_VIDEO_P0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video_cvp =3D { + .name =3D "qnm_video_cvp", + .id =3D SM6350_MASTER_VIDEO_PROC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf =3D { + .name =3D "qxm_camnoc_hf", + .id =3D SM6350_MASTER_CAMNOC_HF, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_icp =3D { + .name =3D "qxm_camnoc_icp", + .id =3D SM6350_MASTER_CAMNOC_ICP, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_sf =3D { + .name =3D "qxm_camnoc_sf", + .id =3D SM6350_MASTER_CAMNOC_SF, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 =3D { + .name =3D "qxm_mdp0", + .id =3D SM6350_MASTER_MDP_PORT0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node amm_npu_sys =3D { + .name =3D "amm_npu_sys", + .id =3D SM6350_MASTER_NPU_SYS, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_NPU_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhm_npu_cfg =3D { + .name =3D "qhm_npu_cfg", + .id =3D SM6350_MASTER_NPU_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 8, + .links =3D { SM6350_SLAVE_SERVICE_NPU_NOC, + SM6350_SLAVE_ISENSE_CFG, + SM6350_SLAVE_NPU_LLM_CFG, + SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, + SM6350_SLAVE_NPU_CP, + SM6350_SLAVE_NPU_TCM, + SM6350_SLAVE_NPU_CAL_DP0, + SM6350_SLAVE_NPU_DPM + }, +}; + +static struct qcom_icc_node qhm_snoc_cfg =3D { + .name =3D "qhm_snoc_cfg", + .id =3D SM6350_MASTER_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc =3D { + .name =3D "qnm_aggre1_noc", + .id =3D SM6350_A1NOC_SNOC_MAS, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 6, + .links =3D { SM6350_SLAVE_SNOC_GEM_NOC_SF, + SM6350_SLAVE_PIMEM, + SM6350_SLAVE_OCIMEM, + SM6350_SLAVE_APPSS, + SM6350_SNOC_CNOC_SLV, + SM6350_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_aggre2_noc =3D { + .name =3D "qnm_aggre2_noc", + .id =3D SM6350_A2NOC_SNOC_MAS, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 7, + .links =3D { SM6350_SLAVE_SNOC_GEM_NOC_SF, + SM6350_SLAVE_PIMEM, + SM6350_SLAVE_OCIMEM, + SM6350_SLAVE_APPSS, + SM6350_SNOC_CNOC_SLV, + SM6350_SLAVE_TCU, + SM6350_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_gemnoc =3D { + .name =3D "qnm_gemnoc", + .id =3D SM6350_MASTER_GEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 6, + .links =3D { SM6350_SLAVE_PIMEM, + SM6350_SLAVE_OCIMEM, + SM6350_SLAVE_APPSS, + SM6350_SNOC_CNOC_SLV, + SM6350_SLAVE_TCU, + SM6350_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qxm_pimem =3D { + .name =3D "qxm_pimem", + .id =3D SM6350_MASTER_PIMEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM6350_SLAVE_SNOC_GEM_NOC_GC, + SM6350_SLAVE_OCIMEM + }, +}; + +static struct qcom_icc_node xm_gic =3D { + .name =3D "xm_gic", + .id =3D SM6350_MASTER_GIC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node qns_a1noc_snoc =3D { + .name =3D "qns_a1noc_snoc", + .id =3D SM6350_A1NOC_SNOC_SLV, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM6350_A1NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node srvc_aggre1_noc =3D { + .name =3D "srvc_aggre1_noc", + .id =3D SM6350_SLAVE_SERVICE_A1NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc =3D { + .name =3D "qns_a2noc_snoc", + .id =3D SM6350_A2NOC_SNOC_SLV, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM6350_A2NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node srvc_aggre2_noc =3D { + .name =3D "srvc_aggre2_noc", + .id =3D SM6350_SLAVE_SERVICE_A2NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_camnoc_uncomp =3D { + .name =3D "qns_camnoc_uncomp", + .id =3D SM6350_SLAVE_CAMNOC_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, +}; + +static struct qcom_icc_node qup0_core_slave =3D { + .name =3D "qup0_core_slave", + .id =3D SM6350_SLAVE_QUP_CORE_0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qup1_core_slave =3D { + .name =3D "qup1_core_slave", + .id =3D SM6350_SLAVE_QUP_CORE_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_cdsp_gemnoc =3D { + .name =3D "qns_cdsp_gemnoc", + .id =3D SM6350_SLAVE_CDSP_GEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg =3D { + .name =3D "qhs_a1_noc_cfg", + .id =3D SM6350_SLAVE_A1NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhs_a2_noc_cfg =3D { + .name =3D "qhs_a2_noc_cfg", + .id =3D SM6350_SLAVE_A2NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qhs_ahb2phy0 =3D { + .name =3D "qhs_ahb2phy0", + .id =3D SM6350_SLAVE_AHB2PHY, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy2 =3D { + .name =3D "qhs_ahb2phy2", + .id =3D SM6350_SLAVE_AHB2PHY_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .id =3D SM6350_SLAVE_AOSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_boot_rom =3D { + .name =3D "qhs_boot_rom", + .id =3D SM6350_SLAVE_BOOT_ROM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_cfg =3D { + .name =3D "qhs_camera_cfg", + .id =3D SM6350_SLAVE_CAMERA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_nrt_thrott_cfg =3D { + .name =3D "qhs_camera_nrt_thrott_cfg", + .id =3D SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_rt_throttle_cfg =3D { + .name =3D "qhs_camera_rt_throttle_cfg", + .id =3D SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .id =3D SM6350_SLAVE_CLK_CTL, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_cx =3D { + .name =3D "qhs_cpr_cx", + .id =3D SM6350_SLAVE_RBCPR_CX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_mx =3D { + .name =3D "qhs_cpr_mx", + .id =3D SM6350_SLAVE_RBCPR_MX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg =3D { + .name =3D "qhs_crypto0_cfg", + .id =3D SM6350_SLAVE_CRYPTO_0_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_dcc_cfg =3D { + .name =3D "qhs_dcc_cfg", + .id =3D SM6350_SLAVE_DCC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg =3D { + .name =3D "qhs_ddrss_cfg", + .id =3D SM6350_SLAVE_CNOC_DDRSS, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qhs_display_cfg =3D { + .name =3D "qhs_display_cfg", + .id =3D SM6350_SLAVE_DISPLAY_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_display_throttle_cfg =3D { + .name =3D "qhs_display_throttle_cfg", + .id =3D SM6350_SLAVE_DISPLAY_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_emmc_cfg =3D { + .name =3D "qhs_emmc_cfg", + .id =3D SM6350_SLAVE_EMMC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_glm =3D { + .name =3D "qhs_glm", + .id =3D SM6350_SLAVE_GLM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg =3D { + .name =3D "qhs_gpuss_cfg", + .id =3D SM6350_SLAVE_GRAPHICS_3D_CFG, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .id =3D SM6350_SLAVE_IMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipa =3D { + .name =3D "qhs_ipa", + .id =3D SM6350_SLAVE_IPA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg =3D { + .name =3D "qhs_mnoc_cfg", + .id =3D SM6350_SLAVE_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qhs_mss_cfg =3D { + .name =3D "qhs_mss_cfg", + .id =3D SM6350_SLAVE_CNOC_MSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_npu_cfg =3D { + .name =3D "qhs_npu_cfg", + .id =3D SM6350_SLAVE_NPU_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_MASTER_NPU_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_pdm =3D { + .name =3D "qhs_pdm", + .id =3D SM6350_SLAVE_PDM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg =3D { + .name =3D "qhs_pimem_cfg", + .id =3D SM6350_SLAVE_PIMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_prng =3D { + .name =3D "qhs_prng", + .id =3D SM6350_SLAVE_PRNG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .id =3D SM6350_SLAVE_QDSS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qm_cfg =3D { + .name =3D "qhs_qm_cfg", + .id =3D SM6350_SLAVE_QM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qm_mpu_cfg =3D { + .name =3D "qhs_qm_mpu_cfg", + .id =3D SM6350_SLAVE_QM_MPU_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup0 =3D { + .name =3D "qhs_qup0", + .id =3D SM6350_SLAVE_QUP_0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup1 =3D { + .name =3D "qhs_qup1", + .id =3D SM6350_SLAVE_QUP_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc2 =3D { + .name =3D "qhs_sdc2", + .id =3D SM6350_SLAVE_SDCC_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_security =3D { + .name =3D "qhs_security", + .id =3D SM6350_SLAVE_SECURITY, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg =3D { + .name =3D "qhs_snoc_cfg", + .id =3D SM6350_SLAVE_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .id =3D SM6350_SLAVE_TCSR, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg =3D { + .name =3D "qhs_ufs_mem_cfg", + .id =3D SM6350_SLAVE_UFS_MEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_0 =3D { + .name =3D "qhs_usb3_0", + .id =3D SM6350_SLAVE_USB3, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_venus_cfg =3D { + .name =3D "qhs_venus_cfg", + .id =3D SM6350_SLAVE_VENUS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_venus_throttle_cfg =3D { + .name =3D "qhs_venus_throttle_cfg", + .id =3D SM6350_SLAVE_VENUS_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { + .name =3D "qhs_vsense_ctrl_cfg", + .id =3D SM6350_SLAVE_VSENSE_CTRL_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_cnoc =3D { + .name =3D "srvc_cnoc", + .id =3D SM6350_SLAVE_SERVICE_CNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gemnoc =3D { + .name =3D "qhs_gemnoc", + .id =3D SM6350_SLAVE_GEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_MASTER_GEM_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_llcc =3D { + .name =3D "qhs_llcc", + .id =3D SM6350_SLAVE_LLCC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mcdma_ms_mpu_cfg =3D { + .name =3D "qhs_mcdma_ms_mpu_cfg", + .id =3D SM6350_SLAVE_MCDMA_MS_MPU_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg =3D { + .name =3D "qhs_mdsp_ms_mpu_cfg", + .id =3D SM6350_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_gem_noc_snoc =3D { + .name =3D "qns_gem_noc_snoc", + .id =3D SM6350_SLAVE_GEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_MASTER_GEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .id =3D SM6350_SLAVE_LLCC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM6350_MASTER_LLCC }, +}; + +static struct qcom_icc_node srvc_gemnoc =3D { + .name =3D "srvc_gemnoc", + .id =3D SM6350_SLAVE_SERVICE_GEM_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .id =3D SM6350_SLAVE_EBI_CH0, + .channels =3D 2, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf =3D { + .name =3D "qns_mem_noc_hf", + .id =3D SM6350_SLAVE_MNOC_HF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_sf =3D { + .name =3D "qns_mem_noc_sf", + .id =3D SM6350_SLAVE_MNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc =3D { + .name =3D "srvc_mnoc", + .id =3D SM6350_SLAVE_SERVICE_MNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cal_dp0 =3D { + .name =3D "qhs_cal_dp0", + .id =3D SM6350_SLAVE_NPU_CAL_DP0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cp =3D { + .name =3D "qhs_cp", + .id =3D SM6350_SLAVE_NPU_CP, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_dma_bwmon =3D { + .name =3D "qhs_dma_bwmon", + .id =3D SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_dpm =3D { + .name =3D "qhs_dpm", + .id =3D SM6350_SLAVE_NPU_DPM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_isense =3D { + .name =3D "qhs_isense", + .id =3D SM6350_SLAVE_ISENSE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_llm =3D { + .name =3D "qhs_llm", + .id =3D SM6350_SLAVE_NPU_LLM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tcm =3D { + .name =3D "qhs_tcm", + .id =3D SM6350_SLAVE_NPU_TCM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_npu_sys =3D { + .name =3D "qns_npu_sys", + .id =3D SM6350_SLAVE_NPU_COMPUTE_NOC, + .channels =3D 2, + .buswidth =3D 32, +}; + +static struct qcom_icc_node srvc_noc =3D { + .name =3D "srvc_noc", + .id =3D SM6350_SLAVE_SERVICE_NPU_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_apss =3D { + .name =3D "qhs_apss", + .id =3D SM6350_SLAVE_APPSS, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qns_cnoc =3D { + .name =3D "qns_cnoc", + .id =3D SM6350_SNOC_CNOC_SLV, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_SNOC_CNOC_MAS }, +}; + +static struct qcom_icc_node qns_gemnoc_gc =3D { + .name =3D "qns_gemnoc_gc", + .id =3D SM6350_SLAVE_SNOC_GEM_NOC_GC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf =3D { + .name =3D "qns_gemnoc_sf", + .id =3D SM6350_SLAVE_SNOC_GEM_NOC_SF, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM6350_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .id =3D SM6350_SLAVE_OCIMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qxs_pimem =3D { + .name =3D "qxs_pimem", + .id =3D SM6350_SLAVE_PIMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node srvc_snoc =3D { + .name =3D "srvc_snoc", + .id =3D SM6350_SLAVE_SERVICE_SNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .id =3D SM6350_SLAVE_QDSS_STM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .id =3D SM6350_SLAVE_TCU, + .channels =3D 1, + .buswidth =3D 8, +}; =20 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); --=20 2.41.0