From nobody Mon Feb 9 18:07:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB9F7C001DC for ; Tue, 11 Jul 2023 12:18:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230091AbjGKMSe (ORCPT ); Tue, 11 Jul 2023 08:18:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231589AbjGKMSa (ORCPT ); Tue, 11 Jul 2023 08:18:30 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF2F7E77 for ; Tue, 11 Jul 2023 05:18:28 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2b6f97c7115so85701751fa.2 for ; Tue, 11 Jul 2023 05:18:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689077907; x=1691669907; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=gXcfnAFG0ALqJ5wchl9zMk96ke46h0gdnZo33aXqC6o=; b=VonMOp0i5+expziTeWEBTHMUNC7qXDeGRqyBPoJ1wkAUuR3RhU2Ey3IYC+JawK9rh6 bHI9uJjJTWpyxc+pRRnma1cuAF16RAAcxjDTqfJT6s4+9D2lvb1crKrbG6E4T7E3j3JE 7MBA0ngRqYrmXBTmKhP8l+hs9rWnbXQSPVyMw7DbtLvV9/KjkIbn9stCTJCLeYJ8Siq5 7i6lnvVM71Lo1lZSupzYng3WE+l4ju3i2NfEvdXOdYzXzUSKWLTohxXt0Q13+Y0mjbSM kXXdY0gVkT+n4/u+ipmWfAu03x0bq1UG9/bal13n2vWRq52X43EVZGTNJNQro/YhG8uU ocRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689077907; x=1691669907; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gXcfnAFG0ALqJ5wchl9zMk96ke46h0gdnZo33aXqC6o=; b=T91APu3vOr/Ai4Petge2yfIB2r0WgyUu5BFZRz2KJ7rHBnR3Qj7OBysBdeo/Nsom3w nXGMejBX0yfCXg/fNy3hKfBUPMRUYVc2LW4yFwqg/1t8mT2Kl0DrHOLTa2BVVeqwTxE9 Te7oSjZpOQVJshCQnc5LIjUFWxxpKWwno37+U7VVJZPdQ42SrUPwwCBNRBgcs0BGYgwu Sm7zX9nTtibbjXJ2eimHuRVo0OTbrkZEKPMkwqVOuIkKeftBGe32CkxGUvvL29I39CsP oNTQ5Fb6HaAoWxhwEuOttJLqCqRqby2CdkER2yFj76Ltz9WwzCbEmKJMTKDKOMgoJoNd K3eg== X-Gm-Message-State: ABy/qLYY09QOfibSkeSeTvRlwB/7cTCWCQMRAK+NeCh3F9o4Xmxyovnb fQBNBTHuPGA5WHBuDsIP4ykneA== X-Google-Smtp-Source: APBJJlHATZyGrxjvNQ4UHts/OGjmEwK4EuBMFcRIRxrV1Y/bvqWGJbi81Vw/Tydk5ULRpDptO1qfDQ== X-Received: by 2002:a2e:91d7:0:b0:2b6:e0b8:946e with SMTP id u23-20020a2e91d7000000b002b6e0b8946emr13108332ljg.51.1689077907043; Tue, 11 Jul 2023 05:18:27 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:26 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:00 +0200 Subject: [PATCH 01/53] dt-bindings: interconnect: qcom,icc: Introduce fixed BCM voter indices MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-1-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1189; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=9/TmGzQ1xk3CQ8ToyRcpOQBYP1VhR10l+JU+aSmEvI0=; b=N1JxOuvEYm4h/wsNdORtSNFT8AF68EXhuMFZexG+clfwKvtG5+uxA4rn/Z4fouP9EkKmuRWz+ 7R/htFQncM5BE7iN2tU0kXbvvV7s3St2Rs+MKybBnVpLAaPzAPW+821 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It makes zero (or less) sense to consume BCM voters per interconnect provider. They are shared throughout the entire system and it's enough to keep a single reference to each of them. Storing them in a shared array at fixed indices will let us improve both the representation of the RPMh architecture (every RSC can hold a resource vote on any bus, they're not limited in that regard) and save as much as kilobytes worth of RAM. Signed-off-by: Konrad Dybcio --- include/dt-bindings/interconnect/qcom,icc.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/dt-bindings/interconnect/qcom,icc.h b/include/dt-bindi= ngs/interconnect/qcom,icc.h index cd34f36daaaa..9c13ef8a044e 100644 --- a/include/dt-bindings/interconnect/qcom,icc.h +++ b/include/dt-bindings/interconnect/qcom,icc.h @@ -23,4 +23,12 @@ #define QCOM_ICC_TAG_ALWAYS (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE |\ QCOM_ICC_TAG_SLEEP) =20 +#define ICC_BCM_VOTER_APPS 0 +#define ICC_BCM_VOTER_DISP 1 +#define ICC_BCM_VOTER_CAM0 2 +#define ICC_BCM_VOTER_CAM1 3 +#define ICC_BCM_VOTER_CAM2 4 + +#define ICC_BCM_VOTER_MAX 64 + #endif --=20 2.41.0 From nobody Mon Feb 9 18:07:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 951B7EB64DC for ; Tue, 11 Jul 2023 12:18:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231183AbjGKMSp (ORCPT ); Tue, 11 Jul 2023 08:18:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231646AbjGKMSb (ORCPT ); Tue, 11 Jul 2023 08:18:31 -0400 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 167F310C2 for ; Tue, 11 Jul 2023 05:18:30 -0700 (PDT) Received: by mail-lj1-x22c.google.com with SMTP id 38308e7fff4ca-2b701e41cd3so92144921fa.3 for ; Tue, 11 Jul 2023 05:18:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689077908; x=1691669908; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+wKqZuebC0/DNlU3YArXv0CU05fgiLNPi4ZrsgdcBCw=; b=WKIt9VI7VJ3uXfTMs1BXr+QomiovZ7rSHNtwxKGNAK3FIQdok2JfMO1I7E+ZueunP5 CkJaXnjOvT+Ln3G8eLhAghX4R+wvEBRMbfW/7al/oHjA50IrXBNdY2F0tOFX16rcRJGq KmHi9fSz1G2Ho1uPijA4gQ3wUPBoGR/vsSIif9vYrvnJ+V8rI2FpRfSkgyG0yB2JLp6y g1lwIGmDPNtyphI+qKGqbiMmP5w0qAyKBomC5K4TewkEs93laxZmkPhMLnFzHNA3r6TU ojuJ60L0sWrXaBvwoFj7n0SubltRpRjnVfONXK2Ok2uWrpd+taxvpMN5D/ixeQtiUmEZ jTIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689077908; x=1691669908; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+wKqZuebC0/DNlU3YArXv0CU05fgiLNPi4ZrsgdcBCw=; b=mF3uhx5E7pTJDxk4XBytyulOOsFRT1gPwHtKik9QUOtzJjFz79ClFi/umeQksAdHA+ pShlVtndvDX3xImx7GZo0kAyljJ7qajk5eMOQQe3GHX6PBsP+yAUxLWP7H2/wMx8JGah fnxoXj4hpUviqWX+Zbhjc+nt1wTsBIY7TRkYfB5xwLiHnk3jyjZQFyaLDvoAy+zYYsoP zt9WK0RGhmZY86arJsIZjHSCaXWpMbRXJ1UlLsaSXivL2QoMI1PZdOQ8yF7Qi/kAVvNo 11/kTxAdQ7tTaDxJA675Ae8h2uuWykD63NeavWgfiEDv2OahAII7iEv4IUgNhjedwQFX 6MhQ== X-Gm-Message-State: ABy/qLZuW2ZQmltodH/BlNHaxxLdo7Zfn/BW8Rci2/a6/gp0+xW6gf3v pH9dQu9XWBC8kBqG/+pqTjgQmw== X-Google-Smtp-Source: APBJJlGFkoNLOi418Dus0WqQX99QCX3C7IKzXbumFFa8qic1h0VzMt3LwPo6s6NWOhxVmAEzfz6uDg== X-Received: by 2002:a2e:700b:0:b0:2b6:e780:97c9 with SMTP id l11-20020a2e700b000000b002b6e78097c9mr12619568ljc.18.1689077908368; Tue, 11 Jul 2023 05:18:28 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:28 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:01 +0200 Subject: [PATCH 02/53] dt-bindings: interconnect: qcom,bcm-voter: Add qcom,bcm-voter-idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-2-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1777; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=1YdtkjCpwqfCeGyrzm5y0lnW6+XAD6b/nL964j7XiAc=; b=xos5lY2485rsc/Fk8rtrxCyUPIzjqnRyhiyLpKu+58DpQKwGajPucJDjZBVy9wi9zJJ9gfdh6 VLXTFNZnq0gAaPF4VFj/7ocVEN6NJ6MYG26wIQmS+2QDKR9YXajYKvP X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In order to (at least partially) untangle the global BCM voter lookup (as again, they are shared throughout the entire system and not bound to individual buses/providers), introduce a new required property to assign a unique identifier to each BCM voter. Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/interconnect/qcom,bcm-voter.yaml | 10 ++++++= ++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.= yaml b/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml index eec987640b37..09321c1918bf 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml @@ -38,8 +38,14 @@ properties: =20 $ref: /schemas/types.yaml#/definitions/uint32 =20 + qcom,bcm-voter-idx: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + A globally unique predefined discrimnator, identifying each BCM vote= r. + required: - compatible + - qcom,bcm-voter-idx =20 additionalProperties: false =20 @@ -48,8 +54,11 @@ examples: # as defined in Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc= .yaml - | =20 + #include + apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; + qcom,bcm-voter-idx =3D ; }; =20 # Example 2: disp bcm_voter on SDM845 should be defined inside &disp_rsc= node @@ -61,5 +70,6 @@ examples: disp_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; qcom,tcs-wait =3D ; + qcom,bcm-voter-idx =3D ; }; ... --=20 2.41.0 From nobody Mon Feb 9 18:07:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4839DC001DC for ; Tue, 11 Jul 2023 12:18:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231810AbjGKMSz (ORCPT ); Tue, 11 Jul 2023 08:18:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231593AbjGKMSc (ORCPT ); Tue, 11 Jul 2023 08:18:32 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3776FE77 for ; Tue, 11 Jul 2023 05:18:31 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id 38308e7fff4ca-2b701dee4bfso92061381fa.0 for ; Tue, 11 Jul 2023 05:18:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689077909; x=1691669909; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=mSu7bVlPwYBvi/ntXbyQWTTKyDKoXG99g+rzhXkYTYg=; b=LW9axz5hH/6bh8N+psR9V8Oy8DQwB7jeXpHwqSe8DjtDtIPYdh88QbvoX+5ic7fU+Z SqrD8HwYBnDTd7xylQQfz7M0PTypGdZuC8lP5KtLRFy3qU7Pt52unmTMQXw8qAHt8vCL 9L3yTXsSRjwFtk3x74W0i7ptTXFHS2D51PU8+FPA9sBv3k+Z9zYQ57q82NkflvcjPHGI ElRaRoy1R9cAv7AoxQwmQwtGF7jAmgbIaiKBvvBahTOrNgV4WI8Nfr37Y6r3qlP9AAVJ pRzPkPqq6JH8YjkrQamvyf02datxWUqYCK81HjWN0lVG1JurV8efPPsjtOTw7zSZqxYI K+dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689077909; x=1691669909; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mSu7bVlPwYBvi/ntXbyQWTTKyDKoXG99g+rzhXkYTYg=; b=SeY0vGX/IVEgvpQTL65SV+/fiGDiJKJTvGH1pJhNc0G31AbIqKzh1P+WKOglC4V5g4 FTCGTjEaH94/xyhrDx5tTP6OF/GlI6ksiXei74ST0cgNuvhzgfsHKJMD/c4aPraEiJUY DWcGvJXzvsBSyRXtgFQhQuLM557WqIvkp0Nl+d7pCfT0qt8lyfCwh6VessUDDB8wU9dz TxvEg4EJZqjE+sTNsare/wGjId6Atm3IItvf/doUdXq6e+qdEpk5/QwbWTjyepVGk9OB cB/QDkEscDFESl8oGw9VFnDdYXd/Z1tqonkdo6M3IvooC1cxLSWUcsM0SMk5sLD/EiPQ inXw== X-Gm-Message-State: ABy/qLYow8XQMXA1WqhWSx/FkyfbjfAEdDAvOnZoF+WFau7pJTA4XCwr sp18IbVXEZ+ju/QUWA6D4VifBA== X-Google-Smtp-Source: APBJJlFoVqC9Hyia0lxUD3pXku6F21REr7sikSpzwEQHlkY9zcN4C2DAGefdaFpk2r2ivKtXESmZAg== X-Received: by 2002:a2e:8782:0:b0:2b7:243e:a2 with SMTP id n2-20020a2e8782000000b002b7243e00a2mr3522971lji.48.1689077909599; Tue, 11 Jul 2023 05:18:29 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:29 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:02 +0200 Subject: [PATCH 03/53] interconnect: qcom: icc-rpmh: Store direct BCM voter references MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-3-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=5806; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=op0OvwRNT/rufglepzjHxJNouLHRuZ5bBbm7iZd+W3A=; b=hcbnLTk5GYW1/XfQr0MsnVa4AHorgH8tXJFov6Rx8PUHIkGm+fyj0WYFcLKB912rf5F+bG2kV HPnsL3Qld0lClgPC5l+H31c8ICbLpQz4v/6Qt2Ur+dwKu8pQbc9h0YH X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It makes zero (or less) sense to consume BCM voters per interconnect provider. They are shared throughout the entire system and it's enough to keep a single reference to each of them. Since the list of these voters is common across SoCs and across buses on them, turn to caching a pointer to each voter at a dt-bindings-defined index in a shared array to make accesses O(1) (instead of a clunky loop-based lookup) and vastly save on redefining & referencing the same set over and over again. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/bcm-voter.c | 29 ++++++++++++++++++++++++++++- drivers/interconnect/qcom/icc-rpmh.c | 16 +++++++++------- drivers/interconnect/qcom/icc-rpmh.h | 4 ++++ 3 files changed, 41 insertions(+), 8 deletions(-) diff --git a/drivers/interconnect/qcom/bcm-voter.c b/drivers/interconnect/q= com/bcm-voter.c index d5f2a6b5376b..f8fbddb87e6b 100644 --- a/drivers/interconnect/qcom/bcm-voter.c +++ b/drivers/interconnect/qcom/bcm-voter.c @@ -19,6 +19,17 @@ static LIST_HEAD(bcm_voters); static DEFINE_MUTEX(bcm_voter_lock); =20 +struct bcm_voter *qcom_icc_bcm_voters[ICC_BCM_VOTER_MAX] =3D { }; +EXPORT_SYMBOL_GPL(qcom_icc_bcm_voters); + +static const char * const bcm_voter_names[ICC_BCM_VOTER_MAX] =3D { + [ICC_BCM_VOTER_APPS] =3D "APPS", + [ICC_BCM_VOTER_DISP] =3D "DISP", + [ICC_BCM_VOTER_CAM0] =3D "CAM0", + [ICC_BCM_VOTER_CAM1] =3D "CAM1", + [ICC_BCM_VOTER_CAM2] =3D "CAM2", +}; + /** * struct bcm_voter - Bus Clock Manager voter * @dev: reference to the device that communicates with the BCM @@ -37,6 +48,7 @@ struct bcm_voter { struct list_head ws_list; struct list_head voter_node; u32 tcs_wait; + u32 voter_idx; }; =20 static int cmp_vcd(void *priv, const struct list_head *a, const struct lis= t_head *b) @@ -353,12 +365,27 @@ static int qcom_icc_bcm_voter_probe(struct platform_d= evice *pdev) if (of_property_read_u32(np, "qcom,tcs-wait", &voter->tcs_wait)) voter->tcs_wait =3D QCOM_ICC_TAG_ACTIVE_ONLY; =20 + /* + * This is the best guess we can make.. + * Not registering BCMs correctly would be gamebreaking anyway! + */ + if (of_property_read_u32(np, "qcom,bcm-voter-idx", &voter->voter_idx)) + voter->voter_idx =3D ICC_BCM_VOTER_APPS; + mutex_init(&voter->lock); INIT_LIST_HEAD(&voter->commit_list); INIT_LIST_HEAD(&voter->ws_list); =20 mutex_lock(&bcm_voter_lock); - list_add_tail(&voter->voter_node, &bcm_voters); + /* Do not attempt to register BCMs with the same ID twice! */ + if (qcom_icc_bcm_voters[voter->voter_idx]) { + mutex_unlock(&bcm_voter_lock); + dev_err(&pdev->dev, "Attempted to overwrite %s BCM voter!\n", + bcm_voter_names[voter->voter_idx]); + return -EINVAL; + } + + qcom_icc_bcm_voters[voter->voter_idx] =3D voter; mutex_unlock(&bcm_voter_lock); =20 return 0; diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qc= om/icc-rpmh.c index fdb5e58e408b..53298148f24b 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -20,9 +20,9 @@ */ void qcom_icc_pre_aggregate(struct icc_node *node) { - size_t i; - struct qcom_icc_node *qn; struct qcom_icc_provider *qp; + struct qcom_icc_node *qn; + int i; =20 qn =3D node->data; qp =3D to_qcom_provider(node->provider); @@ -33,7 +33,7 @@ void qcom_icc_pre_aggregate(struct icc_node *node) } =20 for (i =3D 0; i < qn->num_bcms; i++) - qcom_icc_bcm_voter_add(qp->voter, qn->bcms[i]); + qcom_icc_bcm_voter_add(qcom_icc_bcm_voters[ICC_BCM_VOTER_APPS], qn->bcms= [i]); } EXPORT_SYMBOL_GPL(qcom_icc_pre_aggregate); =20 @@ -95,7 +95,7 @@ int qcom_icc_set(struct icc_node *src, struct icc_node *d= st) =20 qp =3D to_qcom_provider(node->provider); =20 - qcom_icc_bcm_voter_commit(qp->voter); + qcom_icc_bcm_voter_commit(qcom_icc_bcm_voters[ICC_BCM_VOTER_APPS]); =20 return 0; } @@ -167,6 +167,7 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) struct icc_provider *provider; struct qcom_icc_node * const *qnodes, *qn; struct qcom_icc_provider *qp; + struct device_node *bcm_node; struct icc_node *node; size_t num_nodes, i, j; int ret; @@ -200,9 +201,10 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) qp->bcms =3D desc->bcms; qp->num_bcms =3D desc->num_bcms; =20 - qp->voter =3D of_bcm_voter_get(qp->dev, NULL); - if (IS_ERR(qp->voter)) - return PTR_ERR(qp->voter); + /* Ensure the BCM voter is reachable (unless we don't have any) */ + qp->voter =3D qcom_icc_bcm_voters[ICC_BCM_VOTER_APPS]; + if (qp->num_bcms && !qp->voter) + return -EPROBE_DEFER; =20 for (i =3D 0; i < qp->num_bcms; i++) qcom_icc_bcm_init(qp->bcms[i], dev); diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qc= om/icc-rpmh.h index 7843d8864d6b..5634d302963a 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -88,6 +88,7 @@ struct qcom_icc_node { * communicating with RPMh * @list: used to link to other bcms when compiling lists for commit * @ws_list: used to keep track of bcms that may transition between wake/s= leep + * @voter_idx: index of the BCM voter used to convey votes to AOSS * @num_nodes: total number of @num_nodes * @nodes: list of qcom_icc_nodes that this BCM encapsulates */ @@ -104,6 +105,7 @@ struct qcom_icc_bcm { struct bcm_db aux_data; struct list_head list; struct list_head ws_list; + u8 voter_idx; size_t num_nodes; struct qcom_icc_node *nodes[]; }; @@ -138,4 +140,6 @@ void qcom_icc_pre_aggregate(struct icc_node *node); int qcom_icc_rpmh_probe(struct platform_device *pdev); int qcom_icc_rpmh_remove(struct platform_device *pdev); =20 +extern struct bcm_voter *qcom_icc_bcm_voters[ICC_BCM_VOTER_MAX]; + #endif --=20 2.41.0 From nobody Mon Feb 9 18:07:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEFD9EB64DC for ; Tue, 11 Jul 2023 12:18:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231345AbjGKMS6 (ORCPT ); Tue, 11 Jul 2023 08:18:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231241AbjGKMSf (ORCPT ); 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:30 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:03 +0200 Subject: [PATCH 04/53] interconnect: qcom: icc-rpmh: Retire dead code MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-4-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=2754; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=6mcS5eZovBnK2nwqFQIK7RBsbNQhwBhsQk+oBWRxNK4=; b=3ESDmMghTA6TIXl1ds/z4EpMEk5yAVv8VC1Tp1dLP/zINjykK+fbVDiJIiARIDeqq+KEQrt8B nrdFX/8/EnIALZGZh9DZJCTIFG3oUiASEHts3K8O46uCivUgJ4qPqU7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org of_bcm_voter_get is no longer necessary. Remove its ugly remnants. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/bcm-voter.c | 46 -------------------------------= ---- drivers/interconnect/qcom/bcm-voter.h | 1 - 2 files changed, 47 deletions(-) diff --git a/drivers/interconnect/qcom/bcm-voter.c b/drivers/interconnect/q= com/bcm-voter.c index f8fbddb87e6b..0ce3874f60d2 100644 --- a/drivers/interconnect/qcom/bcm-voter.c +++ b/drivers/interconnect/qcom/bcm-voter.c @@ -16,7 +16,6 @@ #include "bcm-voter.h" #include "icc-rpmh.h" =20 -static LIST_HEAD(bcm_voters); static DEFINE_MUTEX(bcm_voter_lock); =20 struct bcm_voter *qcom_icc_bcm_voters[ICC_BCM_VOTER_MAX] =3D { }; @@ -182,51 +181,6 @@ static void tcs_list_gen(struct bcm_voter *voter, int = bucket, } } =20 -/** - * of_bcm_voter_get - gets a bcm voter handle from DT node - * @dev: device pointer for the consumer device - * @name: name for the bcm voter device - * - * This function will match a device_node pointer for the phandle - * specified in the device DT and return a bcm_voter handle on success. - * - * Returns bcm_voter pointer or ERR_PTR() on error. EPROBE_DEFER is return= ed - * when matching bcm voter is yet to be found. - */ -struct bcm_voter *of_bcm_voter_get(struct device *dev, const char *name) -{ - struct bcm_voter *voter =3D ERR_PTR(-EPROBE_DEFER); - struct bcm_voter *temp; - struct device_node *np, *node; - int idx =3D 0; - - if (!dev || !dev->of_node) - return ERR_PTR(-ENODEV); - - np =3D dev->of_node; - - if (name) { - idx =3D of_property_match_string(np, "qcom,bcm-voter-names", name); - if (idx < 0) - return ERR_PTR(idx); - } - - node =3D of_parse_phandle(np, "qcom,bcm-voters", idx); - - mutex_lock(&bcm_voter_lock); - list_for_each_entry(temp, &bcm_voters, voter_node) { - if (temp->np =3D=3D node) { - voter =3D temp; - break; - } - } - mutex_unlock(&bcm_voter_lock); - - of_node_put(node); - return voter; -} -EXPORT_SYMBOL_GPL(of_bcm_voter_get); - /** * qcom_icc_bcm_voter_add - queues up the bcm nodes that require updates * @voter: voter that the bcms are being added to diff --git a/drivers/interconnect/qcom/bcm-voter.h b/drivers/interconnect/q= com/bcm-voter.h index 0f64c0bab2c0..30b324fcb2ee 100644 --- a/drivers/interconnect/qcom/bcm-voter.h +++ b/drivers/interconnect/qcom/bcm-voter.h @@ -20,7 +20,6 @@ static struct qcom_icc_bcm _name =3D { \ .nodes =3D { __VA_ARGS__ }, \ } =20 -struct bcm_voter *of_bcm_voter_get(struct device *dev, const char *name); void qcom_icc_bcm_voter_add(struct bcm_voter *voter, struct qcom_icc_bcm *= bcm); int qcom_icc_bcm_voter_commit(struct bcm_voter *voter); =20 --=20 2.41.0 From nobody Mon Feb 9 18:07:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4F7AEB64DC for ; Tue, 11 Jul 2023 12:19:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231706AbjGKMTB (ORCPT ); Tue, 11 Jul 2023 08:19:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52068 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231669AbjGKMSg (ORCPT ); Tue, 11 Jul 2023 08:18:36 -0400 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C914CE7E for ; Tue, 11 Jul 2023 05:18:33 -0700 (PDT) Received: by mail-lj1-x231.google.com with SMTP id 38308e7fff4ca-2b703a0453fso88402441fa.3 for ; Tue, 11 Jul 2023 05:18:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689077912; x=1691669912; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ccaHxWEA1SHNBLA/pJ32RMxAjEs2vftCpusuOqWZkaE=; b=AAa407DAcUUBZbNB2i1waM4u2+UaESZbSIFTb8IWbolXR5HnC39wh0iKZ/nEkWNsuS /u8mLAN7PTTfYQ08LT1jOQ0uDTK3C8RVGgauvdIqRJDEMrcDAcm7fVVD6qrEe87r+bvb o/dpbyN5EfbKehUidsB2RGJQpV4LJ1muPhk/tdE/XngfxGrbONlIFMF1Bq89JNUYTWCI OkuV8QkN31TY1YHRFpXYrlbdKEM6Zxahwf5yNcErl9JVNA5t1yYr/tWH1j+sVNTVutKu sAv743aQBCXiygGfItZCTDkSx20u4sQA3IMHNS/lZw8ZWoDyoZ+1ULpKH+yVl8rIaYbv x7ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689077912; x=1691669912; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ccaHxWEA1SHNBLA/pJ32RMxAjEs2vftCpusuOqWZkaE=; b=Ijhsy1PGo+Uuu/9/eUAE/fbC8TOU6MFRdTguDSyca3pvAGIwT6IUAoikYrbD6d14sT nG0iAaI9gzRs/XrGjAHcqfDSjulOQbwDh64o0wx/TIjhEiDRmyIjLP4tPjwbI2Ma/3VE jO6RHhc2d06FVYSd2GCChZ5IRLu3etbbNLfH+oyEXlU0ZOe6E0yGRTL78nr0a88AVb5l nRXRPFtT2pZAjtibyu7nDGLcpbeXvYC157xi0Qlk/wIPw5WqNrZCYRdnk9P0LIt3rfKX z9VTsvaJ83GGt47e3/pvHb56MMigAmPhxe2z/qtUpdT/5KlIA546Yaj6nCefUq6crTw0 MBWA== X-Gm-Message-State: ABy/qLZxoGU+N9pKNlMNOouB84BzhFcWN8LzVdGYxkScjfX8UJ0tQj5H soGWYHneY5CaucKwFdk6TxE16uGeSduN7xhmPwqDVQ== X-Google-Smtp-Source: APBJJlF3TDNp52qVnWvnuIz7/SR0d+mgazonvPucboip+HYCyKqB81kRMjkq1+V2da/wMQB0zmk42g== X-Received: by 2002:a2e:7a06:0:b0:2b6:bd82:80b1 with SMTP id v6-20020a2e7a06000000b002b6bd8280b1mr13846968ljc.37.1689077912056; Tue, 11 Jul 2023 05:18:32 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:31 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:04 +0200 Subject: [PATCH 05/53] interconnect: qcom: icc-rpmh: Implement voting on non-APPS RSCs MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-5-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=3399; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=qxa5myzMVst/ng/FRMS5QwwZ8ABXjqpOGI10XxQPCBc=; b=YTn8PsYOLKHdJ4Oifs+Jok/jlVwavascvy0uIPmwXcmQnyELG4gnpyZgozP0wLWdDR7INKJYf FKpv39ljyUsDLC8wn1QDYP1tm30T7i3e8mbyhY3odnYIh4XD9fY7ZnA X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Linux can cast votes on resources through different RSCs (e.g. DISP). This can be done for many reasons, from latency to fine-grain on-SoC-power-grid management. With all the necessary bits in place, add the loops and ifs necessary to vote through different RSCs. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/icc-rpmh.c | 49 ++++++++++++++++++++++++++++++--= ---- 1 file changed, 42 insertions(+), 7 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qc= om/icc-rpmh.c index 53298148f24b..3cdd9106b0c0 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -22,6 +22,8 @@ void qcom_icc_pre_aggregate(struct icc_node *node) { struct qcom_icc_provider *qp; struct qcom_icc_node *qn; + struct qcom_icc_bcm *bcm; + int voter_idx; int i; =20 qn =3D node->data; @@ -32,8 +34,17 @@ void qcom_icc_pre_aggregate(struct icc_node *node) qn->max_peak[i] =3D 0; } =20 - for (i =3D 0; i < qn->num_bcms; i++) - qcom_icc_bcm_voter_add(qcom_icc_bcm_voters[ICC_BCM_VOTER_APPS], qn->bcms= [i]); + for (i =3D 0; i < qn->num_bcms; i++) { + bcm =3D qn->bcms[i]; + + /* Old and incomplete device trees may not specify all voters. */ + if (qcom_icc_bcm_voters[bcm->voter_idx]) + voter_idx =3D bcm->voter_idx; + else + voter_idx =3D ICC_BCM_VOTER_APPS; + + qcom_icc_bcm_voter_add(qcom_icc_bcm_voters[voter_idx], bcm); + } } EXPORT_SYMBOL_GPL(qcom_icc_pre_aggregate); =20 @@ -87,6 +98,7 @@ int qcom_icc_set(struct icc_node *src, struct icc_node *d= st) { struct qcom_icc_provider *qp; struct icc_node *node; + int i, ret; =20 if (!src) node =3D dst; @@ -95,7 +107,11 @@ int qcom_icc_set(struct icc_node *src, struct icc_node = *dst) =20 qp =3D to_qcom_provider(node->provider); =20 - qcom_icc_bcm_voter_commit(qcom_icc_bcm_voters[ICC_BCM_VOTER_APPS]); + for (i =3D 0; i < ICC_BCM_VOTER_MAX; i++) { + ret =3D qcom_icc_bcm_voter_commit(qcom_icc_bcm_voters[i]); + if (ret) + return ret; + } =20 return 0; } @@ -168,6 +184,7 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) struct qcom_icc_node * const *qnodes, *qn; struct qcom_icc_provider *qp; struct device_node *bcm_node; + u32 val, voter_count =3D 0; struct icc_node *node; size_t num_nodes, i, j; int ret; @@ -201,10 +218,28 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) qp->bcms =3D desc->bcms; qp->num_bcms =3D desc->num_bcms; =20 - /* Ensure the BCM voter is reachable (unless we don't have any) */ - qp->voter =3D qcom_icc_bcm_voters[ICC_BCM_VOTER_APPS]; - if (qp->num_bcms && !qp->voter) - return -EPROBE_DEFER; + for (i =3D 0; i < ICC_BCM_VOTER_MAX; i++) { + bcm_node =3D of_parse_phandle(dev->of_node, "qcom,bcm-voters", voter_cou= nt); + if (!bcm_node) + break; + + voter_count++; + + ret =3D of_property_read_u32(bcm_node, "qcom,bcm-voter-idx", &val); + of_node_put(bcm_node); + /* Legacy DTs only ever referenced the APPS BCM voter */ + if (ret =3D=3D -EINVAL) + val =3D ICC_BCM_VOTER_APPS; + else if (ret) + return ret; + + if (!qcom_icc_bcm_voters[val]) + return -EPROBE_DEFER; + } + + /* Let's not forget to add qcom,bcm-voters to the provider node! */ + if (qp->num_bcms && !voter_count) + return -EINVAL; =20 for (i =3D 0; i < qp->num_bcms; i++) qcom_icc_bcm_init(qp->bcms[i], dev); --=20 2.41.0 From nobody Mon Feb 9 18:07:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4814EEB64DC for ; Tue, 11 Jul 2023 12:19:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229576AbjGKMTF (ORCPT ); Tue, 11 Jul 2023 08:19:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52128 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230490AbjGKMSk (ORCPT ); Tue, 11 Jul 2023 08:18:40 -0400 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88FD910E5 for ; Tue, 11 Jul 2023 05:18:35 -0700 (PDT) Received: by mail-lj1-x231.google.com with SMTP id 38308e7fff4ca-2b6ef64342aso89520341fa.3 for ; Tue, 11 Jul 2023 05:18:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689077914; x=1691669914; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=J9H8WmeBksbeh8NfCbg2+mLM/ZRxw9tuOAbuu8Kzagk=; b=Z2l74bUhXzdlPl+KuF2hPicoPPTNcoITPbBA27phJwW4uzRDBLQUC4YEsmT1q1u+av M+Z9aPJYkLtZ8QVQ7eWPDIEmFyRYA1Yc65XBs2mX3LfjANLNrw584JrwtCdv79YnpCE4 zQfQCAP7C9dtIRQiIjWor0R6Q7fU853UwBpw274DOKTgewnbirves4AGpYTTPhHhsioF IaZeav681Soa59En+DD87aUN01bHZkJGe7TxCp2V5EPBbw5x4TTxpPeR3wuR+zlc/9Te 3nziRV4BTGpRt/sfQ17UDAzurJMHwAfjBoS+tQRhUTvnHkSv3jM4P44KiAGYFA7r2tFn g8vQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689077914; x=1691669914; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J9H8WmeBksbeh8NfCbg2+mLM/ZRxw9tuOAbuu8Kzagk=; b=HP76zNsHdLFn4semonWpumpp/qpSWA+5/v8+KEN37lFglve0/6ZYKmuu53YXvgtYGu 0QEaGRluMRwXAdCFeINqXAf1UKwshUeVcSMgb2ZV99Z1Qd+m5A/IpZy1gE7qsPIVK2Hw zjoVkJvPwtL7IE8YijCmYlaqKE6YloICK7K/9KmU3ujsR+AZ+buqroOPoqbyDux4aH0U 75flwNdukFUav8c1JppD2y+zqnBIaz6i+ezx7XtfOVRh8CtHRCvYSSYuJuTtqnVFOUNj 39luvB6YsoEJJ4zWmb+U2jORqhWnZcvxql/wqYRgA1UNJyeKPgU6vg5qnt59drf+WcB+ Ly/w== X-Gm-Message-State: ABy/qLZaR88fdXrB8SqaQSf2kWmxvG1YGx/boQyOay70yKowMF6UNvVu dfoDHo2n02a4Sg8xBil9fduNHg== X-Google-Smtp-Source: APBJJlEoyYHs0oBTCCtXUJSZM0RvKuXuNkzWhekcuCpg82QMPFhKm6N9F91FKhkePyNWBp1EWhOEIQ== X-Received: by 2002:a2e:8508:0:b0:2b6:faaa:fb53 with SMTP id j8-20020a2e8508000000b002b6faaafb53mr12383406lji.26.1689077913726; Tue, 11 Jul 2023 05:18:33 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:33 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:05 +0200 Subject: [PATCH 06/53] interconnect: qcom: sc7180: Retire DEFINE_QNODE MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-6-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=42545; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=3HncnistFIjHOWYEogNMs1JXDdztHDQYLkYhd8ihntg=; b=BM4JmAz3ZkYFn2ZflIGGgiF4W0dM+uRy8eNZIGYWc+gCdGjBH4rOA0RkzW1x4E/OTx46wF/lY y1vXXAw1vHLD/P+S9Dhe5W/6nVMIbwZ+lntKyrwNBTOIbq9nH4845FU X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sc7180.c | 1356 ++++++++++++++++++++++++++++++++= ---- 1 file changed, 1219 insertions(+), 137 deletions(-) diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom= /sc7180.c index ef4e13fb4983..d1b0427f8781 100644 --- a/drivers/interconnect/qcom/sc7180.c +++ b/drivers/interconnect/qcom/sc7180.c @@ -15,143 +15,1225 @@ #include "icc-rpmh.h" #include "sc7180.h" =20 -DEFINE_QNODE(qhm_a1noc_cfg, SC7180_MASTER_A1NOC_CFG, 1, 4, SC7180_SLAVE_SE= RVICE_A1NOC); -DEFINE_QNODE(qhm_qspi, SC7180_MASTER_QSPI, 1, 4, SC7180_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(qhm_qup_0, SC7180_MASTER_QUP_0, 1, 4, SC7180_SLAVE_A1NOC_SNOC= ); -DEFINE_QNODE(xm_sdc2, SC7180_MASTER_SDCC_2, 1, 8, SC7180_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_emmc, SC7180_MASTER_EMMC, 1, 8, SC7180_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_ufs_mem, SC7180_MASTER_UFS_MEM, 1, 8, SC7180_SLAVE_A1NOC_S= NOC); -DEFINE_QNODE(qhm_a2noc_cfg, SC7180_MASTER_A2NOC_CFG, 1, 4, SC7180_SLAVE_SE= RVICE_A2NOC); -DEFINE_QNODE(qhm_qdss_bam, SC7180_MASTER_QDSS_BAM, 1, 4, SC7180_SLAVE_A2NO= C_SNOC); -DEFINE_QNODE(qhm_qup_1, SC7180_MASTER_QUP_1, 1, 4, SC7180_SLAVE_A2NOC_SNOC= ); -DEFINE_QNODE(qxm_crypto, SC7180_MASTER_CRYPTO, 1, 8, SC7180_SLAVE_A2NOC_SN= OC); -DEFINE_QNODE(qxm_ipa, SC7180_MASTER_IPA, 1, 8, SC7180_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_qdss_etr, SC7180_MASTER_QDSS_ETR, 1, 8, SC7180_SLAVE_A2NOC= _SNOC); -DEFINE_QNODE(qhm_usb3, SC7180_MASTER_USB3, 1, 8, SC7180_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SC7180_MASTER_CAMNOC_HF0_UNCOMP, 1, 32= , SC7180_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SC7180_MASTER_CAMNOC_HF1_UNCOMP, 1, 32= , SC7180_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_sf_uncomp, SC7180_MASTER_CAMNOC_SF_UNCOMP, 1, 32, = SC7180_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qnm_npu, SC7180_MASTER_NPU, 2, 32, SC7180_SLAVE_CDSP_GEM_NOC); -DEFINE_QNODE(qxm_npu_dsp, SC7180_MASTER_NPU_PROC, 1, 8, SC7180_SLAVE_CDSP_= GEM_NOC); -DEFINE_QNODE(qnm_snoc, SC7180_MASTER_SNOC_CNOC, 1, 8, SC7180_SLAVE_A1NOC_C= FG, SC7180_SLAVE_A2NOC_CFG, SC7180_SLAVE_AHB2PHY_SOUTH, SC7180_SLAVE_AHB2PH= Y_CENTER, SC7180_SLAVE_AOP, SC7180_SLAVE_AOSS, SC7180_SLAVE_BOOT_ROM, SC718= 0_SLAVE_CAMERA_CFG, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, SC7180_SLAVE_CAME= RA_RT_THROTTLE_CFG, SC7180_SLAVE_CLK_CTL, SC7180_SLAVE_RBCPR_CX_CFG, SC7180= _SLAVE_RBCPR_MX_CFG, SC7180_SLAVE_CRYPTO_0_CFG, SC7180_SLAVE_DCC_CFG, SC718= 0_SLAVE_CNOC_DDRSS, SC7180_SLAVE_DISPLAY_CFG, SC7180_SLAVE_DISPLAY_RT_THROT= TLE_CFG, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, SC7180_SLAVE_EMMC_CFG, SC7180_S= LAVE_GLM, - SC7180_SLAVE_GFX3D_CFG, SC7180_SLAVE_IMEM_CFG, SC7180_SLAVE_IPA_CFG, SC7= 180_SLAVE_CNOC_MNOC_CFG, SC7180_SLAVE_CNOC_MSS, SC7180_SLAVE_NPU_CFG, SC718= 0_SLAVE_NPU_DMA_BWMON_CFG, SC7180_SLAVE_NPU_PROC_BWMON_CFG, SC7180_SLAVE_PD= M, SC7180_SLAVE_PIMEM_CFG, SC7180_SLAVE_PRNG, SC7180_SLAVE_QDSS_CFG, SC7180= _SLAVE_QM_CFG, SC7180_SLAVE_QM_MPU_CFG, SC7180_SLAVE_QSPI_0, SC7180_SLAVE_Q= UP_0, SC7180_SLAVE_QUP_1, SC7180_SLAVE_SDCC_2, SC7180_SLAVE_SECURITY, SC718= 0_SLAVE_SNOC_CFG, SC7180_SLAVE_TCSR, SC7180_SLAVE_TLMM_WEST, SC7180_SLAVE_T= LMM_NORTH, SC7180_SLAVE_TLMM_SOUTH, SC7180_SLAVE_UFS_MEM_CFG, SC7180_SLAVE_= USB3, SC7180_SLAVE_VENUS_CFG, SC7180_SLAVE_VENUS_THROTTLE_CFG, SC7180_SLAVE= _VSENSE_CTRL_CFG, SC7180_SLAVE_SERVICE_CNOC); -DEFINE_QNODE(xm_qdss_dap, SC7180_MASTER_QDSS_DAP, 1, 8, SC7180_SLAVE_A1NOC= _CFG, SC7180_SLAVE_A2NOC_CFG, SC7180_SLAVE_AHB2PHY_SOUTH, SC7180_SLAVE_AHB2= PHY_CENTER, SC7180_SLAVE_AOP, SC7180_SLAVE_AOSS, SC7180_SLAVE_BOOT_ROM, SC7= 180_SLAVE_CAMERA_CFG, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, SC7180_SLAVE_CA= MERA_RT_THROTTLE_CFG, SC7180_SLAVE_CLK_CTL, SC7180_SLAVE_RBCPR_CX_CFG, SC71= 80_SLAVE_RBCPR_MX_CFG, SC7180_SLAVE_CRYPTO_0_CFG, SC7180_SLAVE_DCC_CFG, SC7= 180_SLAVE_CNOC_DDRSS, SC7180_SLAVE_DISPLAY_CFG, SC7180_SLAVE_DISPLAY_RT_THR= OTTLE_CFG, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, SC7180_SLAVE_EMMC_CFG, SC7180= _SLAVE_GLM, SC7180_SLAVE_GFX3D_CFG, SC7180_SLAVE_IMEM_CFG, SC7180_SLAVE_IPA= _CFG, SC7180_SLAVE_CNOC_MNOC_CFG, SC7180_SLAVE_CNOC_MSS, SC7180_SLAVE_NPU_C= FG, SC7180_SLAVE_NPU_DMA_BWMON_CFG, -SC7180_SLAVE_NPU_PROC_BWMON_CFG, SC7180_SLAVE_PDM, SC7180_SLAVE_PIMEM_CFG,= SC7180_SLAVE_PRNG, SC7180_SLAVE_QDSS_CFG, SC7180_SLAVE_QM_CFG, SC7180_SLAV= E_QM_MPU_CFG, SC7180_SLAVE_QSPI_0, SC7180_SLAVE_QUP_0, SC7180_SLAVE_QUP_1, = SC7180_SLAVE_SDCC_2, SC7180_SLAVE_SECURITY, SC7180_SLAVE_SNOC_CFG, SC7180_S= LAVE_TCSR, SC7180_SLAVE_TLMM_WEST, SC7180_SLAVE_TLMM_NORTH, SC7180_SLAVE_TL= MM_SOUTH, SC7180_SLAVE_UFS_MEM_CFG, SC7180_SLAVE_USB3, SC7180_SLAVE_VENUS_C= FG, SC7180_SLAVE_VENUS_THROTTLE_CFG, SC7180_SLAVE_VSENSE_CTRL_CFG, SC7180_S= LAVE_SERVICE_CNOC); -DEFINE_QNODE(qhm_cnoc_dc_noc, SC7180_MASTER_CNOC_DC_NOC, 1, 4, SC7180_SLAV= E_GEM_NOC_CFG, SC7180_SLAVE_LLCC_CFG); -DEFINE_QNODE(acm_apps0, SC7180_MASTER_APPSS_PROC, 1, 16, SC7180_SLAVE_GEM_= NOC_SNOC, SC7180_SLAVE_LLCC); -DEFINE_QNODE(acm_sys_tcu, SC7180_MASTER_SYS_TCU, 1, 8, SC7180_SLAVE_GEM_NO= C_SNOC, SC7180_SLAVE_LLCC); -DEFINE_QNODE(qhm_gemnoc_cfg, SC7180_MASTER_GEM_NOC_CFG, 1, 4, SC7180_SLAVE= _MSS_PROC_MS_MPU_CFG, SC7180_SLAVE_SERVICE_GEM_NOC); -DEFINE_QNODE(qnm_cmpnoc, SC7180_MASTER_COMPUTE_NOC, 1, 32, SC7180_SLAVE_GE= M_NOC_SNOC, SC7180_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_hf, SC7180_MASTER_MNOC_HF_MEM_NOC, 1, 32, SC7180_SLA= VE_LLCC); -DEFINE_QNODE(qnm_mnoc_sf, SC7180_MASTER_MNOC_SF_MEM_NOC, 1, 32, SC7180_SLA= VE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_gc, SC7180_MASTER_SNOC_GC_MEM_NOC, 1, 8, SC7180_SLAV= E_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SC7180_MASTER_SNOC_SF_MEM_NOC, 1, 16, SC7180_SLA= VE_LLCC); -DEFINE_QNODE(qxm_gpu, SC7180_MASTER_GFX3D, 2, 32, SC7180_SLAVE_GEM_NOC_SNO= C, SC7180_SLAVE_LLCC); -DEFINE_QNODE(llcc_mc, SC7180_MASTER_LLCC, 2, 4, SC7180_SLAVE_EBI1); -DEFINE_QNODE(qhm_mnoc_cfg, SC7180_MASTER_CNOC_MNOC_CFG, 1, 4, SC7180_SLAVE= _SERVICE_MNOC); -DEFINE_QNODE(qxm_camnoc_hf0, SC7180_MASTER_CAMNOC_HF0, 2, 32, SC7180_SLAVE= _MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_hf1, SC7180_MASTER_CAMNOC_HF1, 2, 32, SC7180_SLAVE= _MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_sf, SC7180_MASTER_CAMNOC_SF, 1, 32, SC7180_SLAVE_M= NOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SC7180_MASTER_MDP0, 1, 32, SC7180_SLAVE_MNOC_HF_MEM= _NOC); -DEFINE_QNODE(qxm_rot, SC7180_MASTER_ROTATOR, 1, 16, SC7180_SLAVE_MNOC_SF_M= EM_NOC); -DEFINE_QNODE(qxm_venus0, SC7180_MASTER_VIDEO_P0, 1, 32, SC7180_SLAVE_MNOC_= SF_MEM_NOC); -DEFINE_QNODE(qxm_venus_arm9, SC7180_MASTER_VIDEO_PROC, 1, 8, SC7180_SLAVE_= MNOC_SF_MEM_NOC); -DEFINE_QNODE(amm_npu_sys, SC7180_MASTER_NPU_SYS, 2, 32, SC7180_SLAVE_NPU_C= OMPUTE_NOC); -DEFINE_QNODE(qhm_npu_cfg, SC7180_MASTER_NPU_NOC_CFG, 1, 4, SC7180_SLAVE_NP= U_CAL_DP0, SC7180_SLAVE_NPU_CP, SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, SC7180_= SLAVE_NPU_DPM, SC7180_SLAVE_ISENSE_CFG, SC7180_SLAVE_NPU_LLM_CFG, SC7180_SL= AVE_NPU_TCM, SC7180_SLAVE_SERVICE_NPU_NOC); -DEFINE_QNODE(qup_core_master_1, SC7180_MASTER_QUP_CORE_0, 1, 4, SC7180_SLA= VE_QUP_CORE_0); -DEFINE_QNODE(qup_core_master_2, SC7180_MASTER_QUP_CORE_1, 1, 4, SC7180_SLA= VE_QUP_CORE_1); -DEFINE_QNODE(qhm_snoc_cfg, SC7180_MASTER_SNOC_CFG, 1, 4, SC7180_SLAVE_SERV= ICE_SNOC); -DEFINE_QNODE(qnm_aggre1_noc, SC7180_MASTER_A1NOC_SNOC, 1, 16, SC7180_SLAVE= _APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_SNOC_GEM_NOC_SF, SC7180_SLAVE_= IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_aggre2_noc, SC7180_MASTER_A2NOC_SNOC, 1, 16, SC7180_SLAVE= _APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_SNOC_GEM_NOC_SF, SC7180_SLAVE_= IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM, SC7180_SLAVE_TCU); -DEFINE_QNODE(qnm_gemnoc, SC7180_MASTER_GEM_NOC_SNOC, 1, 8, SC7180_SLAVE_AP= PSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_= SLAVE_QDSS_STM, SC7180_SLAVE_TCU); -DEFINE_QNODE(qxm_pimem, SC7180_MASTER_PIMEM, 1, 8, SC7180_SLAVE_SNOC_GEM_N= OC_GC, SC7180_SLAVE_IMEM); -DEFINE_QNODE(qns_a1noc_snoc, SC7180_SLAVE_A1NOC_SNOC, 1, 16, SC7180_MASTER= _A1NOC_SNOC); -DEFINE_QNODE(srvc_aggre1_noc, SC7180_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(qns_a2noc_snoc, SC7180_SLAVE_A2NOC_SNOC, 1, 16, SC7180_MASTER= _A2NOC_SNOC); -DEFINE_QNODE(srvc_aggre2_noc, SC7180_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qns_camnoc_uncomp, SC7180_SLAVE_CAMNOC_UNCOMP, 1, 32); -DEFINE_QNODE(qns_cdsp_gemnoc, SC7180_SLAVE_CDSP_GEM_NOC, 1, 32, SC7180_MAS= TER_COMPUTE_NOC); -DEFINE_QNODE(qhs_a1_noc_cfg, SC7180_SLAVE_A1NOC_CFG, 1, 4, SC7180_MASTER_A= 1NOC_CFG); -DEFINE_QNODE(qhs_a2_noc_cfg, SC7180_SLAVE_A2NOC_CFG, 1, 4, SC7180_MASTER_A= 2NOC_CFG); -DEFINE_QNODE(qhs_ahb2phy0, SC7180_SLAVE_AHB2PHY_SOUTH, 1, 4); -DEFINE_QNODE(qhs_ahb2phy2, SC7180_SLAVE_AHB2PHY_CENTER, 1, 4); -DEFINE_QNODE(qhs_aop, SC7180_SLAVE_AOP, 1, 4); -DEFINE_QNODE(qhs_aoss, SC7180_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_boot_rom, SC7180_SLAVE_BOOT_ROM, 1, 4); -DEFINE_QNODE(qhs_camera_cfg, SC7180_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_camera_nrt_throttle_cfg, SC7180_SLAVE_CAMERA_NRT_THROTTLE= _CFG, 1, 4); -DEFINE_QNODE(qhs_camera_rt_throttle_cfg, SC7180_SLAVE_CAMERA_RT_THROTTLE_C= FG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SC7180_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SC7180_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mx, SC7180_SLAVE_RBCPR_MX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SC7180_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_dcc_cfg, SC7180_SLAVE_DCC_CFG, 1, 4); -DEFINE_QNODE(qhs_ddrss_cfg, SC7180_SLAVE_CNOC_DDRSS, 1, 4, SC7180_MASTER_C= NOC_DC_NOC); -DEFINE_QNODE(qhs_display_cfg, SC7180_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_display_rt_throttle_cfg, SC7180_SLAVE_DISPLAY_RT_THROTTLE= _CFG, 1, 4); -DEFINE_QNODE(qhs_display_throttle_cfg, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, = 1, 4); -DEFINE_QNODE(qhs_emmc_cfg, SC7180_SLAVE_EMMC_CFG, 1, 4); -DEFINE_QNODE(qhs_glm, SC7180_SLAVE_GLM, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SC7180_SLAVE_GFX3D_CFG, 1, 8); -DEFINE_QNODE(qhs_imem_cfg, SC7180_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SC7180_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mnoc_cfg, SC7180_SLAVE_CNOC_MNOC_CFG, 1, 4, SC7180_MASTER= _CNOC_MNOC_CFG); -DEFINE_QNODE(qhs_mss_cfg, SC7180_SLAVE_CNOC_MSS, 1, 4); -DEFINE_QNODE(qhs_npu_cfg, SC7180_SLAVE_NPU_CFG, 1, 4, SC7180_MASTER_NPU_NO= C_CFG); -DEFINE_QNODE(qhs_npu_dma_throttle_cfg, SC7180_SLAVE_NPU_DMA_BWMON_CFG, 1, = 4); -DEFINE_QNODE(qhs_npu_dsp_throttle_cfg, SC7180_SLAVE_NPU_PROC_BWMON_CFG, 1,= 4); -DEFINE_QNODE(qhs_pdm, SC7180_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SC7180_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_prng, SC7180_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SC7180_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qm_cfg, SC7180_SLAVE_QM_CFG, 1, 4); -DEFINE_QNODE(qhs_qm_mpu_cfg, SC7180_SLAVE_QM_MPU_CFG, 1, 4); -DEFINE_QNODE(qhs_qspi, SC7180_SLAVE_QSPI_0, 1, 4); -DEFINE_QNODE(qhs_qup0, SC7180_SLAVE_QUP_0, 1, 4); -DEFINE_QNODE(qhs_qup1, SC7180_SLAVE_QUP_1, 1, 4); -DEFINE_QNODE(qhs_sdc2, SC7180_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_security, SC7180_SLAVE_SECURITY, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SC7180_SLAVE_SNOC_CFG, 1, 4, SC7180_MASTER_SNOC= _CFG); -DEFINE_QNODE(qhs_tcsr, SC7180_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm_1, SC7180_SLAVE_TLMM_WEST, 1, 4); -DEFINE_QNODE(qhs_tlmm_2, SC7180_SLAVE_TLMM_NORTH, 1, 4); -DEFINE_QNODE(qhs_tlmm_3, SC7180_SLAVE_TLMM_SOUTH, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SC7180_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3, SC7180_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SC7180_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_venus_throttle_cfg, SC7180_SLAVE_VENUS_THROTTLE_CFG, 1, 4= ); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SC7180_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(srvc_cnoc, SC7180_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(qhs_gemnoc, SC7180_SLAVE_GEM_NOC_CFG, 1, 4, SC7180_MASTER_GEM= _NOC_CFG); -DEFINE_QNODE(qhs_llcc, SC7180_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qns_gem_noc_snoc, SC7180_SLAVE_GEM_NOC_SNOC, 1, 8, SC7180_MAS= TER_GEM_NOC_SNOC); -DEFINE_QNODE(qns_llcc, SC7180_SLAVE_LLCC, 1, 16, SC7180_MASTER_LLCC); -DEFINE_QNODE(srvc_gemnoc, SC7180_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(ebi, SC7180_SLAVE_EBI1, 2, 4); -DEFINE_QNODE(qns_mem_noc_hf, SC7180_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SC7180_M= ASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_sf, SC7180_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SC7180_M= ASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SC7180_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qhs_cal_dp0, SC7180_SLAVE_NPU_CAL_DP0, 1, 4); -DEFINE_QNODE(qhs_cp, SC7180_SLAVE_NPU_CP, 1, 4); -DEFINE_QNODE(qhs_dma_bwmon, SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4); -DEFINE_QNODE(qhs_dpm, SC7180_SLAVE_NPU_DPM, 1, 4); -DEFINE_QNODE(qhs_isense, SC7180_SLAVE_ISENSE_CFG, 1, 4); -DEFINE_QNODE(qhs_llm, SC7180_SLAVE_NPU_LLM_CFG, 1, 4); -DEFINE_QNODE(qhs_tcm, SC7180_SLAVE_NPU_TCM, 1, 4); -DEFINE_QNODE(qns_npu_sys, SC7180_SLAVE_NPU_COMPUTE_NOC, 2, 32); -DEFINE_QNODE(srvc_noc, SC7180_SLAVE_SERVICE_NPU_NOC, 1, 4); -DEFINE_QNODE(qup_core_slave_1, SC7180_SLAVE_QUP_CORE_0, 1, 4); -DEFINE_QNODE(qup_core_slave_2, SC7180_SLAVE_QUP_CORE_1, 1, 4); -DEFINE_QNODE(qhs_apss, SC7180_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qns_cnoc, SC7180_SLAVE_SNOC_CNOC, 1, 8, SC7180_MASTER_SNOC_CN= OC); -DEFINE_QNODE(qns_gemnoc_gc, SC7180_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SC7180_MAS= TER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_gemnoc_sf, SC7180_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SC7180_MA= STER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(qxs_imem, SC7180_SLAVE_IMEM, 1, 8); -DEFINE_QNODE(qxs_pimem, SC7180_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SC7180_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_qdss_stm, SC7180_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SC7180_SLAVE_TCU, 1, 8); +static struct qcom_icc_node qhm_a1noc_cfg =3D { + .name =3D "qhm_a1noc_cfg", + .id =3D SC7180_MASTER_A1NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qhm_qspi =3D { + .name =3D "qhm_qspi", + .id =3D SC7180_MASTER_QSPI, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup_0 =3D { + .name =3D "qhm_qup_0", + .id =3D SC7180_MASTER_QUP_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc2 =3D { + .name =3D "xm_sdc2", + .id =3D SC7180_MASTER_SDCC_2, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_emmc =3D { + .name =3D "xm_emmc", + .id =3D SC7180_MASTER_EMMC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_mem =3D { + .name =3D "xm_ufs_mem", + .id =3D SC7180_MASTER_UFS_MEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_a2noc_cfg =3D { + .name =3D "qhm_a2noc_cfg", + .id =3D SC7180_MASTER_A2NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam =3D { + .name =3D "qhm_qdss_bam", + .id =3D SC7180_MASTER_QDSS_BAM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup_1 =3D { + .name =3D "qhm_qup_1", + .id =3D SC7180_MASTER_QUP_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_crypto =3D { + .name =3D "qxm_crypto", + .id =3D SC7180_MASTER_CRYPTO, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_ipa =3D { + .name =3D "qxm_ipa", + .id =3D SC7180_MASTER_IPA, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr =3D { + .name =3D "xm_qdss_etr", + .id =3D SC7180_MASTER_QDSS_ETR, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_usb3 =3D { + .name =3D "qhm_usb3", + .id =3D SC7180_MASTER_USB3, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0_uncomp =3D { + .name =3D "qxm_camnoc_hf0_uncomp", + .id =3D SC7180_MASTER_CAMNOC_HF0_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1_uncomp =3D { + .name =3D "qxm_camnoc_hf1_uncomp", + .id =3D SC7180_MASTER_CAMNOC_HF1_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_sf_uncomp =3D { + .name =3D "qxm_camnoc_sf_uncomp", + .id =3D SC7180_MASTER_CAMNOC_SF_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qnm_npu =3D { + .name =3D "qnm_npu", + .id =3D SC7180_MASTER_NPU, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_CDSP_GEM_NOC }, +}; + +static struct qcom_icc_node qxm_npu_dsp =3D { + .name =3D "qxm_npu_dsp", + .id =3D SC7180_MASTER_NPU_PROC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_CDSP_GEM_NOC }, +}; + +static struct qcom_icc_node qnm_snoc =3D { + .name =3D "qnm_snoc", + .id =3D SC7180_MASTER_SNOC_CNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 51, + .links =3D { SC7180_SLAVE_A1NOC_CFG, + SC7180_SLAVE_A2NOC_CFG, + SC7180_SLAVE_AHB2PHY_SOUTH, + SC7180_SLAVE_AHB2PHY_CENTER, + SC7180_SLAVE_AOP, + SC7180_SLAVE_AOSS, + SC7180_SLAVE_BOOT_ROM, + SC7180_SLAVE_CAMERA_CFG, + SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, + SC7180_SLAVE_CLK_CTL, + SC7180_SLAVE_RBCPR_CX_CFG, + SC7180_SLAVE_RBCPR_MX_CFG, + SC7180_SLAVE_CRYPTO_0_CFG, + SC7180_SLAVE_DCC_CFG, + SC7180_SLAVE_CNOC_DDRSS, + SC7180_SLAVE_DISPLAY_CFG, + SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, + SC7180_SLAVE_DISPLAY_THROTTLE_CFG, + SC7180_SLAVE_EMMC_CFG, + SC7180_SLAVE_GLM, + SC7180_SLAVE_GFX3D_CFG, + SC7180_SLAVE_IMEM_CFG, + SC7180_SLAVE_IPA_CFG, + SC7180_SLAVE_CNOC_MNOC_CFG, + SC7180_SLAVE_CNOC_MSS, + SC7180_SLAVE_NPU_CFG, + SC7180_SLAVE_NPU_DMA_BWMON_CFG, + SC7180_SLAVE_NPU_PROC_BWMON_CFG, + SC7180_SLAVE_PDM, + SC7180_SLAVE_PIMEM_CFG, + SC7180_SLAVE_PRNG, + SC7180_SLAVE_QDSS_CFG, + SC7180_SLAVE_QM_CFG, + SC7180_SLAVE_QM_MPU_CFG, + SC7180_SLAVE_QSPI_0, + SC7180_SLAVE_QUP_0, + SC7180_SLAVE_QUP_1, + SC7180_SLAVE_SDCC_2, + SC7180_SLAVE_SECURITY, + SC7180_SLAVE_SNOC_CFG, + SC7180_SLAVE_TCSR, + SC7180_SLAVE_TLMM_WEST, + SC7180_SLAVE_TLMM_NORTH, + SC7180_SLAVE_TLMM_SOUTH, + SC7180_SLAVE_UFS_MEM_CFG, + SC7180_SLAVE_USB3, + SC7180_SLAVE_VENUS_CFG, + SC7180_SLAVE_VENUS_THROTTLE_CFG, + SC7180_SLAVE_VSENSE_CTRL_CFG, + SC7180_SLAVE_SERVICE_CNOC + }, +}; + +static struct qcom_icc_node xm_qdss_dap =3D { + .name =3D "xm_qdss_dap", + .id =3D SC7180_MASTER_QDSS_DAP, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 51, + .links =3D { SC7180_SLAVE_A1NOC_CFG, + SC7180_SLAVE_A2NOC_CFG, + SC7180_SLAVE_AHB2PHY_SOUTH, + SC7180_SLAVE_AHB2PHY_CENTER, + SC7180_SLAVE_AOP, + SC7180_SLAVE_AOSS, + SC7180_SLAVE_BOOT_ROM, + SC7180_SLAVE_CAMERA_CFG, + SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, + SC7180_SLAVE_CLK_CTL, + SC7180_SLAVE_RBCPR_CX_CFG, + SC7180_SLAVE_RBCPR_MX_CFG, + SC7180_SLAVE_CRYPTO_0_CFG, + SC7180_SLAVE_DCC_CFG, + SC7180_SLAVE_CNOC_DDRSS, + SC7180_SLAVE_DISPLAY_CFG, + SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, + SC7180_SLAVE_DISPLAY_THROTTLE_CFG, + SC7180_SLAVE_EMMC_CFG, + SC7180_SLAVE_GLM, + SC7180_SLAVE_GFX3D_CFG, + SC7180_SLAVE_IMEM_CFG, + SC7180_SLAVE_IPA_CFG, + SC7180_SLAVE_CNOC_MNOC_CFG, + SC7180_SLAVE_CNOC_MSS, + SC7180_SLAVE_NPU_CFG, + SC7180_SLAVE_NPU_DMA_BWMON_CFG, + SC7180_SLAVE_NPU_PROC_BWMON_CFG, + SC7180_SLAVE_PDM, + SC7180_SLAVE_PIMEM_CFG, + SC7180_SLAVE_PRNG, + SC7180_SLAVE_QDSS_CFG, + SC7180_SLAVE_QM_CFG, + SC7180_SLAVE_QM_MPU_CFG, + SC7180_SLAVE_QSPI_0, + SC7180_SLAVE_QUP_0, + SC7180_SLAVE_QUP_1, + SC7180_SLAVE_SDCC_2, + SC7180_SLAVE_SECURITY, + SC7180_SLAVE_SNOC_CFG, + SC7180_SLAVE_TCSR, + SC7180_SLAVE_TLMM_WEST, + SC7180_SLAVE_TLMM_NORTH, + SC7180_SLAVE_TLMM_SOUTH, + SC7180_SLAVE_UFS_MEM_CFG, + SC7180_SLAVE_USB3, + SC7180_SLAVE_VENUS_CFG, + SC7180_SLAVE_VENUS_THROTTLE_CFG, + SC7180_SLAVE_VSENSE_CTRL_CFG, + SC7180_SLAVE_SERVICE_CNOC + }, +}; + +static struct qcom_icc_node qhm_cnoc_dc_noc =3D { + .name =3D "qhm_cnoc_dc_noc", + .id =3D SC7180_MASTER_CNOC_DC_NOC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .links =3D { SC7180_SLAVE_GEM_NOC_CFG, + SC7180_SLAVE_LLCC_CFG + }, +}; + +static struct qcom_icc_node acm_apps0 =3D { + .name =3D "acm_apps0", + .id =3D SC7180_MASTER_APPSS_PROC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 2, + .links =3D { SC7180_SLAVE_GEM_NOC_SNOC, + SC7180_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node acm_sys_tcu =3D { + .name =3D "acm_sys_tcu", + .id =3D SC7180_MASTER_SYS_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SC7180_SLAVE_GEM_NOC_SNOC, + SC7180_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qhm_gemnoc_cfg =3D { + .name =3D "qhm_gemnoc_cfg", + .id =3D SC7180_MASTER_GEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .links =3D { SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, + SC7180_SLAVE_SERVICE_GEM_NOC + }, +}; + +static struct qcom_icc_node qnm_cmpnoc =3D { + .name =3D "qnm_cmpnoc", + .id =3D SC7180_MASTER_COMPUTE_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SC7180_SLAVE_GEM_NOC_SNOC, + SC7180_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_mnoc_hf =3D { + .name =3D "qnm_mnoc_hf", + .id =3D SC7180_MASTER_MNOC_HF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_sf =3D { + .name =3D "qnm_mnoc_sf", + .id =3D SC7180_MASTER_MNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SC7180_SLAVE_GEM_NOC_SNOC, + SC7180_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc =3D { + .name =3D "qnm_snoc_gc", + .id =3D SC7180_MASTER_SNOC_GC_MEM_NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf =3D { + .name =3D "qnm_snoc_sf", + .id =3D SC7180_MASTER_SNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qxm_gpu =3D { + .name =3D "qxm_gpu", + .id =3D SC7180_MASTER_GFX3D, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SC7180_SLAVE_GEM_NOC_SNOC, + SC7180_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .id =3D SC7180_MASTER_LLCC, + .channels =3D 2, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_EBI1 }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg =3D { + .name =3D "qhm_mnoc_cfg", + .id =3D SC7180_MASTER_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0 =3D { + .name =3D "qxm_camnoc_hf0", + .id =3D SC7180_MASTER_CAMNOC_HF0, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1 =3D { + .name =3D "qxm_camnoc_hf1", + .id =3D SC7180_MASTER_CAMNOC_HF1, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_sf =3D { + .name =3D "qxm_camnoc_sf", + .id =3D SC7180_MASTER_CAMNOC_SF, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 =3D { + .name =3D "qxm_mdp0", + .id =3D SC7180_MASTER_MDP0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_rot =3D { + .name =3D "qxm_rot", + .id =3D SC7180_MASTER_ROTATOR, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus0 =3D { + .name =3D "qxm_venus0", + .id =3D SC7180_MASTER_VIDEO_P0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus_arm9 =3D { + .name =3D "qxm_venus_arm9", + .id =3D SC7180_MASTER_VIDEO_PROC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node amm_npu_sys =3D { + .name =3D "amm_npu_sys", + .id =3D SC7180_MASTER_NPU_SYS, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_NPU_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhm_npu_cfg =3D { + .name =3D "qhm_npu_cfg", + .id =3D SC7180_MASTER_NPU_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 8, + .links =3D { SC7180_SLAVE_NPU_CAL_DP0, + SC7180_SLAVE_NPU_CP, + SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, + SC7180_SLAVE_NPU_DPM, + SC7180_SLAVE_ISENSE_CFG, + SC7180_SLAVE_NPU_LLM_CFG, + SC7180_SLAVE_NPU_TCM, + SC7180_SLAVE_SERVICE_NPU_NOC + }, +}; + +static struct qcom_icc_node qup_core_master_1 =3D { + .name =3D "qup_core_master_1", + .id =3D SC7180_MASTER_QUP_CORE_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_QUP_CORE_0 }, +}; + +static struct qcom_icc_node qup_core_master_2 =3D { + .name =3D "qup_core_master_2", + .id =3D SC7180_MASTER_QUP_CORE_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_QUP_CORE_1 }, +}; + +static struct qcom_icc_node qhm_snoc_cfg =3D { + .name =3D "qhm_snoc_cfg", + .id =3D SC7180_MASTER_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SC7180_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc =3D { + .name =3D "qnm_aggre1_noc", + .id =3D SC7180_MASTER_A1NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 6, + .links =3D { SC7180_SLAVE_APPSS, + SC7180_SLAVE_SNOC_CNOC, + SC7180_SLAVE_SNOC_GEM_NOC_SF, + SC7180_SLAVE_IMEM, + SC7180_SLAVE_PIMEM, + SC7180_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_aggre2_noc =3D { + .name =3D "qnm_aggre2_noc", + .id =3D SC7180_MASTER_A2NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 7, + .links =3D { SC7180_SLAVE_APPSS, + SC7180_SLAVE_SNOC_CNOC, + SC7180_SLAVE_SNOC_GEM_NOC_SF, + SC7180_SLAVE_IMEM, + SC7180_SLAVE_PIMEM, + SC7180_SLAVE_QDSS_STM, + SC7180_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_gemnoc =3D { + .name =3D "qnm_gemnoc", + .id =3D SC7180_MASTER_GEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 6, + .links =3D { SC7180_SLAVE_APPSS, + SC7180_SLAVE_SNOC_CNOC, + SC7180_SLAVE_IMEM, + SC7180_SLAVE_PIMEM, + SC7180_SLAVE_QDSS_STM, + SC7180_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qxm_pimem =3D { + .name =3D "qxm_pimem", + .id =3D SC7180_MASTER_PIMEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SC7180_SLAVE_SNOC_GEM_NOC_GC, + SC7180_SLAVE_IMEM + }, +}; + +static struct qcom_icc_node qns_a1noc_snoc =3D { + .name =3D "qns_a1noc_snoc", + .id =3D SC7180_SLAVE_A1NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SC7180_MASTER_A1NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre1_noc =3D { + .name =3D "srvc_aggre1_noc", + .id =3D SC7180_SLAVE_SERVICE_A1NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc =3D { + .name =3D "qns_a2noc_snoc", + .id =3D SC7180_SLAVE_A2NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SC7180_MASTER_A2NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc =3D { + .name =3D "srvc_aggre2_noc", + .id =3D SC7180_SLAVE_SERVICE_A2NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_camnoc_uncomp =3D { + .name =3D "qns_camnoc_uncomp", + .id =3D SC7180_SLAVE_CAMNOC_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, +}; + +static struct qcom_icc_node qns_cdsp_gemnoc =3D { + .name =3D "qns_cdsp_gemnoc", + .id =3D SC7180_SLAVE_CDSP_GEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SC7180_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg =3D { + .name =3D "qhs_a1_noc_cfg", + .id =3D SC7180_SLAVE_A1NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SC7180_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhs_a2_noc_cfg =3D { + .name =3D "qhs_a2_noc_cfg", + .id =3D SC7180_SLAVE_A2NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SC7180_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qhs_ahb2phy0 =3D { + .name =3D "qhs_ahb2phy0", + .id =3D SC7180_SLAVE_AHB2PHY_SOUTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy2 =3D { + .name =3D "qhs_ahb2phy2", + .id =3D SC7180_SLAVE_AHB2PHY_CENTER, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_aop =3D { + .name =3D "qhs_aop", + .id =3D SC7180_SLAVE_AOP, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .id =3D SC7180_SLAVE_AOSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_boot_rom =3D { + .name =3D "qhs_boot_rom", + .id =3D SC7180_SLAVE_BOOT_ROM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_cfg =3D { + .name =3D "qhs_camera_cfg", + .id =3D SC7180_SLAVE_CAMERA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_nrt_throttle_cfg =3D { + .name =3D "qhs_camera_nrt_throttle_cfg", + .id =3D SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_rt_throttle_cfg =3D { + .name =3D "qhs_camera_rt_throttle_cfg", + .id =3D SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .id =3D SC7180_SLAVE_CLK_CTL, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_cx =3D { + .name =3D "qhs_cpr_cx", + .id =3D SC7180_SLAVE_RBCPR_CX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_mx =3D { + .name =3D "qhs_cpr_mx", + .id =3D SC7180_SLAVE_RBCPR_MX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg =3D { + .name =3D "qhs_crypto0_cfg", + .id =3D SC7180_SLAVE_CRYPTO_0_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_dcc_cfg =3D { + .name =3D "qhs_dcc_cfg", + .id =3D SC7180_SLAVE_DCC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg =3D { + .name =3D "qhs_ddrss_cfg", + .id =3D SC7180_SLAVE_CNOC_DDRSS, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SC7180_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qhs_display_cfg =3D { + .name =3D "qhs_display_cfg", + .id =3D SC7180_SLAVE_DISPLAY_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_display_rt_throttle_cfg =3D { + .name =3D "qhs_display_rt_throttle_cfg", + .id =3D SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_display_throttle_cfg =3D { + .name =3D "qhs_display_throttle_cfg", + .id =3D SC7180_SLAVE_DISPLAY_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_emmc_cfg =3D { + .name =3D "qhs_emmc_cfg", + .id =3D SC7180_SLAVE_EMMC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_glm =3D { + .name =3D "qhs_glm", + .id =3D SC7180_SLAVE_GLM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg =3D { + .name =3D "qhs_gpuss_cfg", + .id =3D SC7180_SLAVE_GFX3D_CFG, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .id =3D SC7180_SLAVE_IMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipa =3D { + .name =3D "qhs_ipa", + .id =3D SC7180_SLAVE_IPA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg =3D { + .name =3D "qhs_mnoc_cfg", + .id =3D SC7180_SLAVE_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SC7180_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qhs_mss_cfg =3D { + .name =3D "qhs_mss_cfg", + .id =3D SC7180_SLAVE_CNOC_MSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_npu_cfg =3D { + .name =3D "qhs_npu_cfg", + .id =3D SC7180_SLAVE_NPU_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SC7180_MASTER_NPU_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_npu_dma_throttle_cfg =3D { + .name =3D "qhs_npu_dma_throttle_cfg", + .id =3D SC7180_SLAVE_NPU_DMA_BWMON_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_npu_dsp_throttle_cfg =3D { + .name =3D "qhs_npu_dsp_throttle_cfg", + .id =3D SC7180_SLAVE_NPU_PROC_BWMON_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pdm =3D { + .name =3D "qhs_pdm", + .id =3D SC7180_SLAVE_PDM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg =3D { + .name =3D "qhs_pimem_cfg", + .id =3D SC7180_SLAVE_PIMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_prng =3D { + .name =3D "qhs_prng", + .id =3D SC7180_SLAVE_PRNG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .id =3D SC7180_SLAVE_QDSS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qm_cfg =3D { + .name =3D "qhs_qm_cfg", + .id =3D SC7180_SLAVE_QM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qm_mpu_cfg =3D { + .name =3D "qhs_qm_mpu_cfg", + .id =3D SC7180_SLAVE_QM_MPU_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qspi =3D { + .name =3D "qhs_qspi", + .id =3D SC7180_SLAVE_QSPI_0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup0 =3D { + .name =3D "qhs_qup0", + .id =3D SC7180_SLAVE_QUP_0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup1 =3D { + .name =3D "qhs_qup1", + .id =3D SC7180_SLAVE_QUP_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc2 =3D { + .name =3D "qhs_sdc2", + .id =3D SC7180_SLAVE_SDCC_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_security =3D { + .name =3D "qhs_security", + .id =3D SC7180_SLAVE_SECURITY, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg =3D { + .name =3D "qhs_snoc_cfg", + .id =3D SC7180_SLAVE_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SC7180_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .id =3D SC7180_SLAVE_TCSR, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm_1 =3D { + .name =3D "qhs_tlmm_1", + .id =3D SC7180_SLAVE_TLMM_WEST, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm_2 =3D { + .name =3D "qhs_tlmm_2", + .id =3D SC7180_SLAVE_TLMM_NORTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm_3 =3D { + .name =3D "qhs_tlmm_3", + .id =3D SC7180_SLAVE_TLMM_SOUTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg =3D { + .name =3D "qhs_ufs_mem_cfg", + .id =3D SC7180_SLAVE_UFS_MEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3 =3D { + .name =3D "qhs_usb3", + .id =3D SC7180_SLAVE_USB3, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_venus_cfg =3D { + .name =3D "qhs_venus_cfg", + .id =3D SC7180_SLAVE_VENUS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_venus_throttle_cfg =3D { + .name =3D "qhs_venus_throttle_cfg", + .id =3D SC7180_SLAVE_VENUS_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { + .name =3D "qhs_vsense_ctrl_cfg", + .id =3D SC7180_SLAVE_VSENSE_CTRL_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_cnoc =3D { + .name =3D "srvc_cnoc", + .id =3D SC7180_SLAVE_SERVICE_CNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gemnoc =3D { + .name =3D "qhs_gemnoc", + .id =3D SC7180_SLAVE_GEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SC7180_MASTER_GEM_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_llcc =3D { + .name =3D "qhs_llcc", + .id =3D SC7180_SLAVE_LLCC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg =3D { + .name =3D "qhs_mdsp_ms_mpu_cfg", + .id =3D SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_gem_noc_snoc =3D { + .name =3D "qns_gem_noc_snoc", + .id =3D SC7180_SLAVE_GEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SC7180_MASTER_GEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .id =3D SC7180_SLAVE_LLCC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SC7180_MASTER_LLCC }, +}; + +static struct qcom_icc_node srvc_gemnoc =3D { + .name =3D "srvc_gemnoc", + .id =3D SC7180_SLAVE_SERVICE_GEM_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .id =3D SC7180_SLAVE_EBI1, + .channels =3D 2, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf =3D { + .name =3D "qns_mem_noc_hf", + .id =3D SC7180_SLAVE_MNOC_HF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SC7180_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_sf =3D { + .name =3D "qns_mem_noc_sf", + .id =3D SC7180_SLAVE_MNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SC7180_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc =3D { + .name =3D "srvc_mnoc", + .id =3D SC7180_SLAVE_SERVICE_MNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cal_dp0 =3D { + .name =3D "qhs_cal_dp0", + .id =3D SC7180_SLAVE_NPU_CAL_DP0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cp =3D { + .name =3D "qhs_cp", + .id =3D SC7180_SLAVE_NPU_CP, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_dma_bwmon =3D { + .name =3D "qhs_dma_bwmon", + .id =3D SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_dpm =3D { + .name =3D "qhs_dpm", + .id =3D SC7180_SLAVE_NPU_DPM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_isense =3D { + .name =3D "qhs_isense", + .id =3D SC7180_SLAVE_ISENSE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_llm =3D { + .name =3D "qhs_llm", + .id =3D SC7180_SLAVE_NPU_LLM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tcm =3D { + .name =3D "qhs_tcm", + .id =3D SC7180_SLAVE_NPU_TCM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_npu_sys =3D { + .name =3D "qns_npu_sys", + .id =3D SC7180_SLAVE_NPU_COMPUTE_NOC, + .channels =3D 2, + .buswidth =3D 32, +}; + +static struct qcom_icc_node srvc_noc =3D { + .name =3D "srvc_noc", + .id =3D SC7180_SLAVE_SERVICE_NPU_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qup_core_slave_1 =3D { + .name =3D "qup_core_slave_1", + .id =3D SC7180_SLAVE_QUP_CORE_0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qup_core_slave_2 =3D { + .name =3D "qup_core_slave_2", + .id =3D SC7180_SLAVE_QUP_CORE_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_apss =3D { + .name =3D "qhs_apss", + .id =3D SC7180_SLAVE_APPSS, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qns_cnoc =3D { + .name =3D "qns_cnoc", + .id =3D SC7180_SLAVE_SNOC_CNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SC7180_MASTER_SNOC_CNOC }, +}; + +static struct qcom_icc_node qns_gemnoc_gc =3D { + .name =3D "qns_gemnoc_gc", + .id =3D SC7180_SLAVE_SNOC_GEM_NOC_GC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SC7180_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf =3D { + .name =3D "qns_gemnoc_sf", + .id =3D SC7180_SLAVE_SNOC_GEM_NOC_SF, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SC7180_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .id =3D SC7180_SLAVE_IMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qxs_pimem =3D { + .name =3D "qxs_pimem", + .id =3D SC7180_SLAVE_PIMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node srvc_snoc =3D { + .name =3D "srvc_snoc", + .id =3D SC7180_SLAVE_SERVICE_SNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .id =3D SC7180_SLAVE_QDSS_STM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .id =3D SC7180_SLAVE_TCU, + .channels =3D 1, + .buswidth =3D 8, +}; =20 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); --=20 2.41.0 From nobody Mon Feb 9 18:07:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05362EB64DD for ; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:34 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:06 +0200 Subject: [PATCH 07/53] interconnect: qcom: sdm670: Retire DEFINE_QNODE MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-7-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=34748; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=V+MGY6LePTTXD4nJ5soCKBGeCOExkcBtc/T6Gwor5mI=; b=2xqpXi14JeM5h01URD74UzsoKGBByAcM1I9rKvXkXVQMG3GyPUsPuXSZozncT/6FLtFx0c1dY RDwPssB6d1QDAen4IUdD5vriLaMYnzT0JLY2HwxsOKYvpdvZlpf8cPH X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sdm670.c | 1145 ++++++++++++++++++++++++++++++++= ---- 1 file changed, 1029 insertions(+), 116 deletions(-) diff --git a/drivers/interconnect/qcom/sdm670.c b/drivers/interconnect/qcom= /sdm670.c index bda955035518..2c2cbe1b5197 100644 --- a/drivers/interconnect/qcom/sdm670.c +++ b/drivers/interconnect/qcom/sdm670.c @@ -14,122 +14,1035 @@ #include "icc-rpmh.h" #include "sdm670.h" =20 -DEFINE_QNODE(qhm_a1noc_cfg, SDM670_MASTER_A1NOC_CFG, 1, 4, SDM670_SLAVE_SE= RVICE_A1NOC); -DEFINE_QNODE(qhm_qup1, SDM670_MASTER_BLSP_1, 1, 4, SDM670_SLAVE_A1NOC_SNOC= ); -DEFINE_QNODE(qhm_tsif, SDM670_MASTER_TSIF, 1, 4, SDM670_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_emmc, SDM670_MASTER_EMMC, 1, 8, SDM670_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_sdc2, SDM670_MASTER_SDCC_2, 1, 8, SDM670_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_sdc4, SDM670_MASTER_SDCC_4, 1, 8, SDM670_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_ufs_mem, SDM670_MASTER_UFS_MEM, 1, 8, SDM670_SLAVE_A1NOC_S= NOC); -DEFINE_QNODE(qhm_a2noc_cfg, SDM670_MASTER_A2NOC_CFG, 1, 4, SDM670_SLAVE_SE= RVICE_A2NOC); -DEFINE_QNODE(qhm_qdss_bam, SDM670_MASTER_QDSS_BAM, 1, 4, SDM670_SLAVE_A2NO= C_SNOC); -DEFINE_QNODE(qhm_qup2, SDM670_MASTER_BLSP_2, 1, 4, SDM670_SLAVE_A2NOC_SNOC= ); -DEFINE_QNODE(qnm_cnoc, SDM670_MASTER_CNOC_A2NOC, 1, 8, SDM670_SLAVE_A2NOC_= SNOC); -DEFINE_QNODE(qxm_crypto, SDM670_MASTER_CRYPTO_CORE_0, 1, 8, SDM670_SLAVE_A= 2NOC_SNOC); -DEFINE_QNODE(qxm_ipa, SDM670_MASTER_IPA, 1, 8, SDM670_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_qdss_etr, SDM670_MASTER_QDSS_ETR, 1, 8, SDM670_SLAVE_A2NOC= _SNOC); -DEFINE_QNODE(xm_usb3_0, SDM670_MASTER_USB3, 1, 8, SDM670_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SDM670_MASTER_CAMNOC_HF0_UNCOMP, 1, 32= , SDM670_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SDM670_MASTER_CAMNOC_HF1_UNCOMP, 1, 32= , SDM670_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_sf_uncomp, SDM670_MASTER_CAMNOC_SF_UNCOMP, 1, 32, = SDM670_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qhm_spdm, SDM670_MASTER_SPDM, 1, 4, SDM670_SLAVE_CNOC_A2NOC); -DEFINE_QNODE(qnm_snoc, SDM670_MASTER_SNOC_CNOC, 1, 8, SDM670_SLAVE_TLMM_SO= UTH, SDM670_SLAVE_CAMERA_CFG, SDM670_SLAVE_SDCC_4, SDM670_SLAVE_SDCC_2, SDM= 670_SLAVE_CNOC_MNOC_CFG, SDM670_SLAVE_UFS_MEM_CFG, SDM670_SLAVE_GLM, SDM670= _SLAVE_PDM, SDM670_SLAVE_A2NOC_CFG, SDM670_SLAVE_QDSS_CFG, SDM670_SLAVE_DIS= PLAY_CFG, SDM670_SLAVE_TCSR, SDM670_SLAVE_DCC_CFG, SDM670_SLAVE_CNOC_DDRSS,= SDM670_SLAVE_SNOC_CFG, SDM670_SLAVE_SOUTH_PHY_CFG, SDM670_SLAVE_GRAPHICS_3= D_CFG, SDM670_SLAVE_VENUS_CFG, SDM670_SLAVE_TSIF, SDM670_SLAVE_CDSP_CFG, SD= M670_SLAVE_AOP, SDM670_SLAVE_BLSP_2, SDM670_SLAVE_SERVICE_CNOC, SDM670_SLAV= E_USB3, SDM670_SLAVE_IPA_CFG, SDM670_SLAVE_RBCPR_CX_CFG, SDM670_SLAVE_A1NOC= _CFG, SDM670_SLAVE_AOSS, SDM670_SLAVE_PRNG, SDM670_SLAVE_VSENSE_CTRL_CFG, S= DM670_SLAVE_EMMC_CFG, SDM670_SLAVE_BLSP_1, SDM670_SLAVE_SPDM_WRAPPER, SDM67= 0_SLAVE_CRYPTO_0_CFG, SDM670_SLAVE_PIMEM_CFG, SDM670_SLAVE_TLMM_NORTH, SDM6= 70_SLAVE_CLK_CTL, SDM670_SLAVE_IMEM_CFG); -DEFINE_QNODE(qhm_cnoc, SDM670_MASTER_CNOC_DC_NOC, 1, 4, SDM670_SLAVE_MEM_N= OC_CFG, SDM670_SLAVE_LLCC_CFG); -DEFINE_QNODE(acm_l3, SDM670_MASTER_AMPSS_M0, 1, 16, SDM670_SLAVE_SERVICE_G= NOC, SDM670_SLAVE_GNOC_SNOC, SDM670_SLAVE_GNOC_MEM_NOC); -DEFINE_QNODE(pm_gnoc_cfg, SDM670_MASTER_GNOC_CFG, 1, 4, SDM670_SLAVE_SERVI= CE_GNOC); -DEFINE_QNODE(llcc_mc, SDM670_MASTER_LLCC, 2, 4, SDM670_SLAVE_EBI_CH0); -DEFINE_QNODE(acm_tcu, SDM670_MASTER_TCU_0, 1, 8, SDM670_SLAVE_MEM_NOC_GNOC= , SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC); -DEFINE_QNODE(qhm_memnoc_cfg, SDM670_MASTER_MEM_NOC_CFG, 1, 4, SDM670_SLAVE= _SERVICE_MEM_NOC, SDM670_SLAVE_MSS_PROC_MS_MPU_CFG); -DEFINE_QNODE(qnm_apps, SDM670_MASTER_GNOC_MEM_NOC, 2, 32, SDM670_SLAVE_LLC= C); -DEFINE_QNODE(qnm_mnoc_hf, SDM670_MASTER_MNOC_HF_MEM_NOC, 2, 32, SDM670_SLA= VE_LLCC); -DEFINE_QNODE(qnm_mnoc_sf, SDM670_MASTER_MNOC_SF_MEM_NOC, 1, 32, SDM670_SLA= VE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SDM670_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDM670_SLAV= E_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SDM670_MASTER_SNOC_SF_MEM_NOC, 1, 16, SDM670_SLA= VE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC); -DEFINE_QNODE(qxm_gpu, SDM670_MASTER_GRAPHICS_3D, 2, 32, SDM670_SLAVE_MEM_N= OC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC); -DEFINE_QNODE(qhm_mnoc_cfg, SDM670_MASTER_CNOC_MNOC_CFG, 1, 4, SDM670_SLAVE= _SERVICE_MNOC); -DEFINE_QNODE(qxm_camnoc_hf0, SDM670_MASTER_CAMNOC_HF0, 1, 32, SDM670_SLAVE= _MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_hf1, SDM670_MASTER_CAMNOC_HF1, 1, 32, SDM670_SLAVE= _MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_sf, SDM670_MASTER_CAMNOC_SF, 1, 32, SDM670_SLAVE_M= NOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SDM670_MASTER_MDP_PORT0, 1, 32, SDM670_SLAVE_MNOC_H= F_MEM_NOC); -DEFINE_QNODE(qxm_mdp1, SDM670_MASTER_MDP_PORT1, 1, 32, SDM670_SLAVE_MNOC_H= F_MEM_NOC); -DEFINE_QNODE(qxm_rot, SDM670_MASTER_ROTATOR, 1, 32, SDM670_SLAVE_MNOC_SF_M= EM_NOC); -DEFINE_QNODE(qxm_venus0, SDM670_MASTER_VIDEO_P0, 1, 32, SDM670_SLAVE_MNOC_= SF_MEM_NOC); -DEFINE_QNODE(qxm_venus1, SDM670_MASTER_VIDEO_P1, 1, 32, SDM670_SLAVE_MNOC_= SF_MEM_NOC); -DEFINE_QNODE(qxm_venus_arm9, SDM670_MASTER_VIDEO_PROC, 1, 8, SDM670_SLAVE_= MNOC_SF_MEM_NOC); -DEFINE_QNODE(qhm_snoc_cfg, SDM670_MASTER_SNOC_CFG, 1, 4, SDM670_SLAVE_SERV= ICE_SNOC); -DEFINE_QNODE(qnm_aggre1_noc, SDM670_MASTER_A1NOC_SNOC, 1, 16, SDM670_SLAVE= _PIMEM, SDM670_SLAVE_SNOC_MEM_NOC_SF, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APP= SS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_aggre2_noc, SDM670_MASTER_A2NOC_SNOC, 1, 16, SDM670_SLAVE= _PIMEM, SDM670_SLAVE_SNOC_MEM_NOC_SF, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APP= SS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_TCU, SDM670_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_gladiator_sodv, SDM670_MASTER_GNOC_SNOC, 1, 8, SDM670_SLA= VE_PIMEM, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, = SDM670_SLAVE_TCU, SDM670_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_memnoc, SDM670_MASTER_MEM_NOC_SNOC, 1, 8, SDM670_SLAVE_OC= IMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_CNOC, SDM67= 0_SLAVE_QDSS_STM); -DEFINE_QNODE(qxm_pimem, SDM670_MASTER_PIMEM, 1, 8, SDM670_SLAVE_OCIMEM, SD= M670_SLAVE_SNOC_MEM_NOC_GC); -DEFINE_QNODE(xm_gic, SDM670_MASTER_GIC, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_= SLAVE_SNOC_MEM_NOC_GC); -DEFINE_QNODE(qns_a1noc_snoc, SDM670_SLAVE_A1NOC_SNOC, 1, 16, SDM670_MASTER= _A1NOC_SNOC); -DEFINE_QNODE(srvc_aggre1_noc, SDM670_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(qns_a2noc_snoc, SDM670_SLAVE_A2NOC_SNOC, 1, 16, SDM670_MASTER= _A2NOC_SNOC); -DEFINE_QNODE(srvc_aggre2_noc, SDM670_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qns_camnoc_uncomp, SDM670_SLAVE_CAMNOC_UNCOMP, 1, 32); -DEFINE_QNODE(qhs_a1_noc_cfg, SDM670_SLAVE_A1NOC_CFG, 1, 4, SDM670_MASTER_A= 1NOC_CFG); -DEFINE_QNODE(qhs_a2_noc_cfg, SDM670_SLAVE_A2NOC_CFG, 1, 4, SDM670_MASTER_A= 2NOC_CFG); -DEFINE_QNODE(qhs_aop, SDM670_SLAVE_AOP, 1, 4); -DEFINE_QNODE(qhs_aoss, SDM670_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_camera_cfg, SDM670_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SDM670_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_compute_dsp_cfg, SDM670_SLAVE_CDSP_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SDM670_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SDM670_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_dcc_cfg, SDM670_SLAVE_DCC_CFG, 1, 4, SDM670_MASTER_CNOC_D= C_NOC); -DEFINE_QNODE(qhs_ddrss_cfg, SDM670_SLAVE_CNOC_DDRSS, 1, 4); -DEFINE_QNODE(qhs_display_cfg, SDM670_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_emmc_cfg, SDM670_SLAVE_EMMC_CFG, 1, 4); -DEFINE_QNODE(qhs_glm, SDM670_SLAVE_GLM, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SDM670_SLAVE_GRAPHICS_3D_CFG, 1, 8); -DEFINE_QNODE(qhs_imem_cfg, SDM670_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SDM670_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mnoc_cfg, SDM670_SLAVE_CNOC_MNOC_CFG, 1, 4, SDM670_MASTER= _CNOC_MNOC_CFG); -DEFINE_QNODE(qhs_pdm, SDM670_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_phy_refgen_south, SDM670_SLAVE_SOUTH_PHY_CFG, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SDM670_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_prng, SDM670_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SDM670_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qupv3_north, SDM670_SLAVE_BLSP_2, 1, 4); -DEFINE_QNODE(qhs_qupv3_south, SDM670_SLAVE_BLSP_1, 1, 4); -DEFINE_QNODE(qhs_sdc2, SDM670_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_sdc4, SDM670_SLAVE_SDCC_4, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SDM670_SLAVE_SNOC_CFG, 1, 4, SDM670_MASTER_SNOC= _CFG); -DEFINE_QNODE(qhs_spdm, SDM670_SLAVE_SPDM_WRAPPER, 1, 4); -DEFINE_QNODE(qhs_tcsr, SDM670_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm_north, SDM670_SLAVE_TLMM_NORTH, 1, 4); -DEFINE_QNODE(qhs_tlmm_south, SDM670_SLAVE_TLMM_SOUTH, 1, 4); -DEFINE_QNODE(qhs_tsif, SDM670_SLAVE_TSIF, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SDM670_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3_0, SDM670_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SDM670_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SDM670_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(qns_cnoc_a2noc, SDM670_SLAVE_CNOC_A2NOC, 1, 8, SDM670_MASTER_= CNOC_A2NOC); -DEFINE_QNODE(srvc_cnoc, SDM670_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(qhs_llcc, SDM670_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qhs_memnoc, SDM670_SLAVE_MEM_NOC_CFG, 1, 4, SDM670_MASTER_MEM= _NOC_CFG); -DEFINE_QNODE(qns_gladiator_sodv, SDM670_SLAVE_GNOC_SNOC, 1, 8, SDM670_MAST= ER_GNOC_SNOC); -DEFINE_QNODE(qns_gnoc_memnoc, SDM670_SLAVE_GNOC_MEM_NOC, 2, 32, SDM670_MAS= TER_GNOC_MEM_NOC); -DEFINE_QNODE(srvc_gnoc, SDM670_SLAVE_SERVICE_GNOC, 1, 4); -DEFINE_QNODE(ebi, SDM670_SLAVE_EBI_CH0, 2, 4); -DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SDM670_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qns_apps_io, SDM670_SLAVE_MEM_NOC_GNOC, 1, 32); -DEFINE_QNODE(qns_llcc, SDM670_SLAVE_LLCC, 2, 16, SDM670_MASTER_LLCC); -DEFINE_QNODE(qns_memnoc_snoc, SDM670_SLAVE_MEM_NOC_SNOC, 1, 8, SDM670_MAST= ER_MEM_NOC_SNOC); -DEFINE_QNODE(srvc_memnoc, SDM670_SLAVE_SERVICE_MEM_NOC, 1, 4); -DEFINE_QNODE(qns2_mem_noc, SDM670_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SDM670_MAS= TER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_hf, SDM670_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SDM670_M= ASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SDM670_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qhs_apss, SDM670_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qns_cnoc, SDM670_SLAVE_SNOC_CNOC, 1, 8, SDM670_MASTER_SNOC_CN= OC); -DEFINE_QNODE(qns_memnoc_gc, SDM670_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDM670_MAS= TER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_memnoc_sf, SDM670_SLAVE_SNOC_MEM_NOC_SF, 1, 16, SDM670_MA= STER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(qxs_imem, SDM670_SLAVE_OCIMEM, 1, 8); -DEFINE_QNODE(qxs_pimem, SDM670_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SDM670_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_qdss_stm, SDM670_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SDM670_SLAVE_TCU, 1, 8); +static struct qcom_icc_node qhm_a1noc_cfg =3D { + .name =3D "qhm_a1noc_cfg", + .id =3D SDM670_MASTER_A1NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qhm_qup1 =3D { + .name =3D "qhm_qup1", + .id =3D SDM670_MASTER_BLSP_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_tsif =3D { + .name =3D "qhm_tsif", + .id =3D SDM670_MASTER_TSIF, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_emmc =3D { + .name =3D "xm_emmc", + .id =3D SDM670_MASTER_EMMC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc2 =3D { + .name =3D "xm_sdc2", + .id =3D SDM670_MASTER_SDCC_2, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc4 =3D { + .name =3D "xm_sdc4", + .id =3D SDM670_MASTER_SDCC_4, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_mem =3D { + .name =3D "xm_ufs_mem", + .id =3D SDM670_MASTER_UFS_MEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_a2noc_cfg =3D { + .name =3D "qhm_a2noc_cfg", + .id =3D SDM670_MASTER_A2NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam =3D { + .name =3D "qhm_qdss_bam", + .id =3D SDM670_MASTER_QDSS_BAM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup2 =3D { + .name =3D "qhm_qup2", + .id =3D SDM670_MASTER_BLSP_2, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_cnoc =3D { + .name =3D "qnm_cnoc", + .id =3D SDM670_MASTER_CNOC_A2NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_crypto =3D { + .name =3D "qxm_crypto", + .id =3D SDM670_MASTER_CRYPTO_CORE_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_ipa =3D { + .name =3D "qxm_ipa", + .id =3D SDM670_MASTER_IPA, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr =3D { + .name =3D "xm_qdss_etr", + .id =3D SDM670_MASTER_QDSS_ETR, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_0 =3D { + .name =3D "xm_usb3_0", + .id =3D SDM670_MASTER_USB3, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0_uncomp =3D { + .name =3D "qxm_camnoc_hf0_uncomp", + .id =3D SDM670_MASTER_CAMNOC_HF0_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1_uncomp =3D { + .name =3D "qxm_camnoc_hf1_uncomp", + .id =3D SDM670_MASTER_CAMNOC_HF1_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_sf_uncomp =3D { + .name =3D "qxm_camnoc_sf_uncomp", + .id =3D SDM670_MASTER_CAMNOC_SF_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qhm_spdm =3D { + .name =3D "qhm_spdm", + .id =3D SDM670_MASTER_SPDM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_CNOC_A2NOC }, +}; + +static struct qcom_icc_node qnm_snoc =3D { + .name =3D "qnm_snoc", + .id =3D SDM670_MASTER_SNOC_CNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 38, + .links =3D { SDM670_SLAVE_TLMM_SOUTH, + SDM670_SLAVE_CAMERA_CFG, + SDM670_SLAVE_SDCC_4, + SDM670_SLAVE_SDCC_2, + SDM670_SLAVE_CNOC_MNOC_CFG, + SDM670_SLAVE_UFS_MEM_CFG, + SDM670_SLAVE_GLM, + SDM670_SLAVE_PDM, + SDM670_SLAVE_A2NOC_CFG, + SDM670_SLAVE_QDSS_CFG, + SDM670_SLAVE_DISPLAY_CFG, + SDM670_SLAVE_TCSR, + SDM670_SLAVE_DCC_CFG, + SDM670_SLAVE_CNOC_DDRSS, + SDM670_SLAVE_SNOC_CFG, + SDM670_SLAVE_SOUTH_PHY_CFG, + SDM670_SLAVE_GRAPHICS_3D_CFG, + SDM670_SLAVE_VENUS_CFG, + SDM670_SLAVE_TSIF, + SDM670_SLAVE_CDSP_CFG, + SDM670_SLAVE_AOP, + SDM670_SLAVE_BLSP_2, + SDM670_SLAVE_SERVICE_CNOC, + SDM670_SLAVE_USB3, + SDM670_SLAVE_IPA_CFG, + SDM670_SLAVE_RBCPR_CX_CFG, + SDM670_SLAVE_A1NOC_CFG, + SDM670_SLAVE_AOSS, + SDM670_SLAVE_PRNG, + SDM670_SLAVE_VSENSE_CTRL_CFG, + SDM670_SLAVE_EMMC_CFG, + SDM670_SLAVE_BLSP_1, + SDM670_SLAVE_SPDM_WRAPPER, + SDM670_SLAVE_CRYPTO_0_CFG, + SDM670_SLAVE_PIMEM_CFG, + SDM670_SLAVE_TLMM_NORTH, + SDM670_SLAVE_CLK_CTL, + SDM670_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node qhm_cnoc =3D { + .name =3D "qhm_cnoc", + .id =3D SDM670_MASTER_CNOC_DC_NOC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .links =3D { SDM670_SLAVE_MEM_NOC_CFG, + SDM670_SLAVE_LLCC_CFG + }, +}; + +static struct qcom_icc_node acm_l3 =3D { + .name =3D "acm_l3", + .id =3D SDM670_MASTER_AMPSS_M0, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 3, + .links =3D { SDM670_SLAVE_SERVICE_GNOC, + SDM670_SLAVE_GNOC_SNOC, + SDM670_SLAVE_GNOC_MEM_NOC + }, +}; + +static struct qcom_icc_node pm_gnoc_cfg =3D { + .name =3D "pm_gnoc_cfg", + .id =3D SDM670_MASTER_GNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_SERVICE_GNOC }, +}; + +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .id =3D SDM670_MASTER_LLCC, + .channels =3D 2, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_EBI_CH0 }, +}; + +static struct qcom_icc_node acm_tcu =3D { + .name =3D "acm_tcu", + .id =3D SDM670_MASTER_TCU_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 3, + .links =3D { SDM670_SLAVE_MEM_NOC_GNOC, + SDM670_SLAVE_LLCC, + SDM670_SLAVE_MEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_memnoc_cfg =3D { + .name =3D "qhm_memnoc_cfg", + .id =3D SDM670_MASTER_MEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .links =3D { SDM670_SLAVE_SERVICE_MEM_NOC, + SDM670_SLAVE_MSS_PROC_MS_MPU_CFG + }, +}; + +static struct qcom_icc_node qnm_apps =3D { + .name =3D "qnm_apps", + .id =3D SDM670_MASTER_GNOC_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_hf =3D { + .name =3D "qnm_mnoc_hf", + .id =3D SDM670_MASTER_MNOC_HF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_sf =3D { + .name =3D "qnm_mnoc_sf", + .id =3D SDM670_MASTER_MNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 3, + .links =3D { SDM670_SLAVE_MEM_NOC_GNOC, + SDM670_SLAVE_LLCC, + SDM670_SLAVE_MEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc =3D { + .name =3D "qnm_snoc_gc", + .id =3D SDM670_MASTER_SNOC_GC_MEM_NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf =3D { + .name =3D "qnm_snoc_sf", + .id =3D SDM670_MASTER_SNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 2, + .links =3D { SDM670_SLAVE_MEM_NOC_GNOC, + SDM670_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qxm_gpu =3D { + .name =3D "qxm_gpu", + .id =3D SDM670_MASTER_GRAPHICS_3D, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 3, + .links =3D { SDM670_SLAVE_MEM_NOC_GNOC, + SDM670_SLAVE_LLCC, + SDM670_SLAVE_MEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg =3D { + .name =3D "qhm_mnoc_cfg", + .id =3D SDM670_MASTER_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0 =3D { + .name =3D "qxm_camnoc_hf0", + .id =3D SDM670_MASTER_CAMNOC_HF0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1 =3D { + .name =3D "qxm_camnoc_hf1", + .id =3D SDM670_MASTER_CAMNOC_HF1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_sf =3D { + .name =3D "qxm_camnoc_sf", + .id =3D SDM670_MASTER_CAMNOC_SF, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 =3D { + .name =3D "qxm_mdp0", + .id =3D SDM670_MASTER_MDP_PORT0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp1 =3D { + .name =3D "qxm_mdp1", + .id =3D SDM670_MASTER_MDP_PORT1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_rot =3D { + .name =3D "qxm_rot", + .id =3D SDM670_MASTER_ROTATOR, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus0 =3D { + .name =3D "qxm_venus0", + .id =3D SDM670_MASTER_VIDEO_P0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus1 =3D { + .name =3D "qxm_venus1", + .id =3D SDM670_MASTER_VIDEO_P1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus_arm9 =3D { + .name =3D "qxm_venus_arm9", + .id =3D SDM670_MASTER_VIDEO_PROC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_snoc_cfg =3D { + .name =3D "qhm_snoc_cfg", + .id =3D SDM670_MASTER_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM670_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc =3D { + .name =3D "qnm_aggre1_noc", + .id =3D SDM670_MASTER_A1NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 6, + .links =3D { SDM670_SLAVE_PIMEM, + SDM670_SLAVE_SNOC_MEM_NOC_SF, + SDM670_SLAVE_OCIMEM, + SDM670_SLAVE_APPSS, + SDM670_SLAVE_SNOC_CNOC, + SDM670_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_aggre2_noc =3D { + .name =3D "qnm_aggre2_noc", + .id =3D SDM670_MASTER_A2NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 7, + .links =3D { SDM670_SLAVE_PIMEM, + SDM670_SLAVE_SNOC_MEM_NOC_SF, + SDM670_SLAVE_OCIMEM, + SDM670_SLAVE_APPSS, + SDM670_SLAVE_SNOC_CNOC, + SDM670_SLAVE_TCU, + SDM670_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_gladiator_sodv =3D { + .name =3D "qnm_gladiator_sodv", + .id =3D SDM670_MASTER_GNOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 6, + .links =3D { SDM670_SLAVE_PIMEM, + SDM670_SLAVE_OCIMEM, + SDM670_SLAVE_APPSS, + SDM670_SLAVE_SNOC_CNOC, + SDM670_SLAVE_TCU, + SDM670_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_memnoc =3D { + .name =3D "qnm_memnoc", + .id =3D SDM670_MASTER_MEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 5, + .links =3D { SDM670_SLAVE_OCIMEM, + SDM670_SLAVE_APPSS, + SDM670_SLAVE_PIMEM, + SDM670_SLAVE_SNOC_CNOC, + SDM670_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qxm_pimem =3D { + .name =3D "qxm_pimem", + .id =3D SDM670_MASTER_PIMEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SDM670_SLAVE_OCIMEM, + SDM670_SLAVE_SNOC_MEM_NOC_GC + }, +}; + +static struct qcom_icc_node xm_gic =3D { + .name =3D "xm_gic", + .id =3D SDM670_MASTER_GIC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SDM670_SLAVE_OCIMEM, + SDM670_SLAVE_SNOC_MEM_NOC_GC + }, +}; + +static struct qcom_icc_node qns_a1noc_snoc =3D { + .name =3D "qns_a1noc_snoc", + .id =3D SDM670_SLAVE_A1NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SDM670_MASTER_A1NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre1_noc =3D { + .name =3D "srvc_aggre1_noc", + .id =3D SDM670_SLAVE_SERVICE_A1NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc =3D { + .name =3D "qns_a2noc_snoc", + .id =3D SDM670_SLAVE_A2NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SDM670_MASTER_A2NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc =3D { + .name =3D "srvc_aggre2_noc", + .id =3D SDM670_SLAVE_SERVICE_A2NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_camnoc_uncomp =3D { + .name =3D "qns_camnoc_uncomp", + .id =3D SDM670_SLAVE_CAMNOC_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg =3D { + .name =3D "qhs_a1_noc_cfg", + .id =3D SDM670_SLAVE_A1NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM670_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhs_a2_noc_cfg =3D { + .name =3D "qhs_a2_noc_cfg", + .id =3D SDM670_SLAVE_A2NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM670_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qhs_aop =3D { + .name =3D "qhs_aop", + .id =3D SDM670_SLAVE_AOP, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .id =3D SDM670_SLAVE_AOSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_cfg =3D { + .name =3D "qhs_camera_cfg", + .id =3D SDM670_SLAVE_CAMERA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .id =3D SDM670_SLAVE_CLK_CTL, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_compute_dsp_cfg =3D { + .name =3D "qhs_compute_dsp_cfg", + .id =3D SDM670_SLAVE_CDSP_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_cx =3D { + .name =3D "qhs_cpr_cx", + .id =3D SDM670_SLAVE_RBCPR_CX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg =3D { + .name =3D "qhs_crypto0_cfg", + .id =3D SDM670_SLAVE_CRYPTO_0_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_dcc_cfg =3D { + .name =3D "qhs_dcc_cfg", + .id =3D SDM670_SLAVE_DCC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM670_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qhs_ddrss_cfg =3D { + .name =3D "qhs_ddrss_cfg", + .id =3D SDM670_SLAVE_CNOC_DDRSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_display_cfg =3D { + .name =3D "qhs_display_cfg", + .id =3D SDM670_SLAVE_DISPLAY_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_emmc_cfg =3D { + .name =3D "qhs_emmc_cfg", + .id =3D SDM670_SLAVE_EMMC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_glm =3D { + .name =3D "qhs_glm", + .id =3D SDM670_SLAVE_GLM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg =3D { + .name =3D "qhs_gpuss_cfg", + .id =3D SDM670_SLAVE_GRAPHICS_3D_CFG, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .id =3D SDM670_SLAVE_IMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipa =3D { + .name =3D "qhs_ipa", + .id =3D SDM670_SLAVE_IPA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg =3D { + .name =3D "qhs_mnoc_cfg", + .id =3D SDM670_SLAVE_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM670_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qhs_pdm =3D { + .name =3D "qhs_pdm", + .id =3D SDM670_SLAVE_PDM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_phy_refgen_south =3D { + .name =3D "qhs_phy_refgen_south", + .id =3D SDM670_SLAVE_SOUTH_PHY_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg =3D { + .name =3D "qhs_pimem_cfg", + .id =3D SDM670_SLAVE_PIMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_prng =3D { + .name =3D "qhs_prng", + .id =3D SDM670_SLAVE_PRNG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .id =3D SDM670_SLAVE_QDSS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qupv3_north =3D { + .name =3D "qhs_qupv3_north", + .id =3D SDM670_SLAVE_BLSP_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qupv3_south =3D { + .name =3D "qhs_qupv3_south", + .id =3D SDM670_SLAVE_BLSP_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc2 =3D { + .name =3D "qhs_sdc2", + .id =3D SDM670_SLAVE_SDCC_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc4 =3D { + .name =3D "qhs_sdc4", + .id =3D SDM670_SLAVE_SDCC_4, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg =3D { + .name =3D "qhs_snoc_cfg", + .id =3D SDM670_SLAVE_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM670_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_spdm =3D { + .name =3D "qhs_spdm", + .id =3D SDM670_SLAVE_SPDM_WRAPPER, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .id =3D SDM670_SLAVE_TCSR, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm_north =3D { + .name =3D "qhs_tlmm_north", + .id =3D SDM670_SLAVE_TLMM_NORTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm_south =3D { + .name =3D "qhs_tlmm_south", + .id =3D SDM670_SLAVE_TLMM_SOUTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tsif =3D { + .name =3D "qhs_tsif", + .id =3D SDM670_SLAVE_TSIF, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg =3D { + .name =3D "qhs_ufs_mem_cfg", + .id =3D SDM670_SLAVE_UFS_MEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_0 =3D { + .name =3D "qhs_usb3_0", + .id =3D SDM670_SLAVE_USB3, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_venus_cfg =3D { + .name =3D "qhs_venus_cfg", + .id =3D SDM670_SLAVE_VENUS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { + .name =3D "qhs_vsense_ctrl_cfg", + .id =3D SDM670_SLAVE_VSENSE_CTRL_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_cnoc_a2noc =3D { + .name =3D "qns_cnoc_a2noc", + .id =3D SDM670_SLAVE_CNOC_A2NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM670_MASTER_CNOC_A2NOC }, +}; + +static struct qcom_icc_node srvc_cnoc =3D { + .name =3D "srvc_cnoc", + .id =3D SDM670_SLAVE_SERVICE_CNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_llcc =3D { + .name =3D "qhs_llcc", + .id =3D SDM670_SLAVE_LLCC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_memnoc =3D { + .name =3D "qhs_memnoc", + .id =3D SDM670_SLAVE_MEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM670_MASTER_MEM_NOC_CFG }, +}; + +static struct qcom_icc_node qns_gladiator_sodv =3D { + .name =3D "qns_gladiator_sodv", + .id =3D SDM670_SLAVE_GNOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM670_MASTER_GNOC_SNOC }, +}; + +static struct qcom_icc_node qns_gnoc_memnoc =3D { + .name =3D "qns_gnoc_memnoc", + .id =3D SDM670_SLAVE_GNOC_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM670_MASTER_GNOC_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_gnoc =3D { + .name =3D "srvc_gnoc", + .id =3D SDM670_SLAVE_SERVICE_GNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .id =3D SDM670_SLAVE_EBI_CH0, + .channels =3D 2, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg =3D { + .name =3D "qhs_mdsp_ms_mpu_cfg", + .id =3D SDM670_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_apps_io =3D { + .name =3D "qns_apps_io", + .id =3D SDM670_SLAVE_MEM_NOC_GNOC, + .channels =3D 1, + .buswidth =3D 32, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .id =3D SDM670_SLAVE_LLCC, + .channels =3D 2, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SDM670_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_memnoc_snoc =3D { + .name =3D "qns_memnoc_snoc", + .id =3D SDM670_SLAVE_MEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM670_MASTER_MEM_NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_memnoc =3D { + .name =3D "srvc_memnoc", + .id =3D SDM670_SLAVE_SERVICE_MEM_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns2_mem_noc =3D { + .name =3D "qns2_mem_noc", + .id =3D SDM670_SLAVE_MNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM670_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_hf =3D { + .name =3D "qns_mem_noc_hf", + .id =3D SDM670_SLAVE_MNOC_HF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM670_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc =3D { + .name =3D "srvc_mnoc", + .id =3D SDM670_SLAVE_SERVICE_MNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_apss =3D { + .name =3D "qhs_apss", + .id =3D SDM670_SLAVE_APPSS, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qns_cnoc =3D { + .name =3D "qns_cnoc", + .id =3D SDM670_SLAVE_SNOC_CNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM670_MASTER_SNOC_CNOC }, +}; + +static struct qcom_icc_node qns_memnoc_gc =3D { + .name =3D "qns_memnoc_gc", + .id =3D SDM670_SLAVE_SNOC_MEM_NOC_GC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM670_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_memnoc_sf =3D { + .name =3D "qns_memnoc_sf", + .id =3D SDM670_SLAVE_SNOC_MEM_NOC_SF, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SDM670_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .id =3D SDM670_SLAVE_OCIMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qxs_pimem =3D { + .name =3D "qxs_pimem", + .id =3D SDM670_SLAVE_PIMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node srvc_snoc =3D { + .name =3D "srvc_snoc", + .id =3D SDM670_SLAVE_SERVICE_SNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .id =3D SDM670_SLAVE_QDSS_STM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .id =3D SDM670_SLAVE_TCU, + .channels =3D 1, + .buswidth =3D 8, +}; =20 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:36 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:07 +0200 Subject: [PATCH 08/53] interconnect: qcom: sdm845: Retire DEFINE_QNODE MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-8-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=43630; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=KNfiEgG3TyzMX9xEccJ89zpUneCkvrGmifaqFWTB5ZU=; b=O8I/wugUASx/V7NKMfFLfXKCCu/uhyHiC1vZLkjvDjANzR0ZDXqW8lhpkEsHjpLEgPD4ZU8xJ L4ozSoWtzQJAYhIkizhYFUcmQbbB7n+wNFzAPH1j891XgRU0KERvgVm X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sdm845.c | 1376 ++++++++++++++++++++++++++++++++= ---- 1 file changed, 1246 insertions(+), 130 deletions(-) diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom= /sdm845.c index 954e7bd13fc4..5caf6e5aeeca 100644 --- a/drivers/interconnect/qcom/sdm845.c +++ b/drivers/interconnect/qcom/sdm845.c @@ -15,136 +15,1252 @@ #include "icc-rpmh.h" #include "sdm845.h" =20 -DEFINE_QNODE(qhm_a1noc_cfg, SDM845_MASTER_A1NOC_CFG, 1, 4, SDM845_SLAVE_SE= RVICE_A1NOC); -DEFINE_QNODE(qhm_qup1, SDM845_MASTER_BLSP_1, 1, 4, SDM845_SLAVE_A1NOC_SNOC= ); -DEFINE_QNODE(qhm_tsif, SDM845_MASTER_TSIF, 1, 4, SDM845_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_sdc2, SDM845_MASTER_SDCC_2, 1, 8, SDM845_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_sdc4, SDM845_MASTER_SDCC_4, 1, 8, SDM845_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_ufs_card, SDM845_MASTER_UFS_CARD, 1, 8, SDM845_SLAVE_A1NOC= _SNOC); -DEFINE_QNODE(xm_ufs_mem, SDM845_MASTER_UFS_MEM, 1, 8, SDM845_SLAVE_A1NOC_S= NOC); -DEFINE_QNODE(xm_pcie_0, SDM845_MASTER_PCIE_0, 1, 8, SDM845_SLAVE_ANOC_PCIE= _A1NOC_SNOC); -DEFINE_QNODE(qhm_a2noc_cfg, SDM845_MASTER_A2NOC_CFG, 1, 4, SDM845_SLAVE_SE= RVICE_A2NOC); -DEFINE_QNODE(qhm_qdss_bam, SDM845_MASTER_QDSS_BAM, 1, 4, SDM845_SLAVE_A2NO= C_SNOC); -DEFINE_QNODE(qhm_qup2, SDM845_MASTER_BLSP_2, 1, 4, SDM845_SLAVE_A2NOC_SNOC= ); -DEFINE_QNODE(qnm_cnoc, SDM845_MASTER_CNOC_A2NOC, 1, 8, SDM845_SLAVE_A2NOC_= SNOC); -DEFINE_QNODE(qxm_crypto, SDM845_MASTER_CRYPTO, 1, 8, SDM845_SLAVE_A2NOC_SN= OC); -DEFINE_QNODE(qxm_ipa, SDM845_MASTER_IPA, 1, 8, SDM845_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_pcie3_1, SDM845_MASTER_PCIE_1, 1, 8, SDM845_SLAVE_ANOC_PCI= E_SNOC); -DEFINE_QNODE(xm_qdss_etr, SDM845_MASTER_QDSS_ETR, 1, 8, SDM845_SLAVE_A2NOC= _SNOC); -DEFINE_QNODE(xm_usb3_0, SDM845_MASTER_USB3_0, 1, 8, SDM845_SLAVE_A2NOC_SNO= C); -DEFINE_QNODE(xm_usb3_1, SDM845_MASTER_USB3_1, 1, 8, SDM845_SLAVE_A2NOC_SNO= C); -DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SDM845_MASTER_CAMNOC_HF0_UNCOMP, 1, 32= , SDM845_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SDM845_MASTER_CAMNOC_HF1_UNCOMP, 1, 32= , SDM845_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_sf_uncomp, SDM845_MASTER_CAMNOC_SF_UNCOMP, 1, 32, = SDM845_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qhm_spdm, SDM845_MASTER_SPDM, 1, 4, SDM845_SLAVE_CNOC_A2NOC); -DEFINE_QNODE(qhm_tic, SDM845_MASTER_TIC, 1, 4, SDM845_SLAVE_A1NOC_CFG, SDM= 845_SLAVE_A2NOC_CFG, SDM845_SLAVE_AOP, SDM845_SLAVE_AOSS, SDM845_SLAVE_CAME= RA_CFG, SDM845_SLAVE_CLK_CTL, SDM845_SLAVE_CDSP_CFG, SDM845_SLAVE_RBCPR_CX_= CFG, SDM845_SLAVE_CRYPTO_0_CFG, SDM845_SLAVE_DCC_CFG, SDM845_SLAVE_CNOC_DDR= SS, SDM845_SLAVE_DISPLAY_CFG, SDM845_SLAVE_GLM, SDM845_SLAVE_GFX3D_CFG, SDM= 845_SLAVE_IMEM_CFG, SDM845_SLAVE_IPA_CFG, SDM845_SLAVE_CNOC_MNOC_CFG, SDM84= 5_SLAVE_PCIE_0_CFG, SDM845_SLAVE_PCIE_1_CFG, SDM845_SLAVE_PDM, SDM845_SLAVE= _SOUTH_PHY_CFG, SDM845_SLAVE_PIMEM_CFG, SDM845_SLAVE_PRNG, SDM845_SLAVE_QDS= S_CFG, SDM845_SLAVE_BLSP_2, SDM845_SLAVE_BLSP_1, SDM845_SLAVE_SDCC_2, SDM84= 5_SLAVE_SDCC_4, SDM845_SLAVE_SNOC_CFG, SDM845_SLAVE_SPDM_WRAPPER, SDM845_SL= AVE_SPSS_CFG, SDM845_SLAVE_TCSR, SDM845_SLAVE_TLMM_NORTH, SDM845_SLAVE_TLMM= _SOUTH, SDM845_SLAVE_TSIF, SDM845_SLAVE_UFS_CARD_CFG, SDM845_SLAVE_UFS_MEM_= CFG, SDM845_SLAVE_USB3_0, SDM845_SLAVE_USB3_1, SDM845_SLAVE_VENUS_CFG, SDM8= 45_SLAVE_VSENSE_CTRL_CF G, SDM845_SLAVE_CNOC_A2NOC, SDM845_SLAVE_SERVICE_CNOC); -DEFINE_QNODE(qnm_snoc, SDM845_MASTER_SNOC_CNOC, 1, 8, SDM845_SLAVE_A1NOC_C= FG, SDM845_SLAVE_A2NOC_CFG, SDM845_SLAVE_AOP, SDM845_SLAVE_AOSS, SDM845_SLA= VE_CAMERA_CFG, SDM845_SLAVE_CLK_CTL, SDM845_SLAVE_CDSP_CFG, SDM845_SLAVE_RB= CPR_CX_CFG, SDM845_SLAVE_CRYPTO_0_CFG, SDM845_SLAVE_DCC_CFG, SDM845_SLAVE_C= NOC_DDRSS, SDM845_SLAVE_DISPLAY_CFG, SDM845_SLAVE_GLM, SDM845_SLAVE_GFX3D_C= FG, SDM845_SLAVE_IMEM_CFG, SDM845_SLAVE_IPA_CFG, SDM845_SLAVE_CNOC_MNOC_CFG= , SDM845_SLAVE_PCIE_0_CFG, SDM845_SLAVE_PCIE_1_CFG, SDM845_SLAVE_PDM, SDM84= 5_SLAVE_SOUTH_PHY_CFG, SDM845_SLAVE_PIMEM_CFG, SDM845_SLAVE_PRNG, SDM845_SL= AVE_QDSS_CFG, SDM845_SLAVE_BLSP_2, SDM845_SLAVE_BLSP_1, SDM845_SLAVE_SDCC_2= , SDM845_SLAVE_SDCC_4, SDM845_SLAVE_SNOC_CFG, SDM845_SLAVE_SPDM_WRAPPER, SD= M845_SLAVE_SPSS_CFG, SDM845_SLAVE_TCSR, SDM845_SLAVE_TLMM_NORTH, SDM845_SLA= VE_TLMM_SOUTH, SDM845_SLAVE_TSIF, SDM845_SLAVE_UFS_CARD_CFG, SDM845_SLAVE_U= FS_MEM_CFG, SDM845_SLAVE_USB3_0, SDM845_SLAVE_USB3_1, SDM845_SLAVE_VENUS_CF= G, SDM845_SLAVE_VSENSE_ CTRL_CFG, SDM845_SLAVE_SERVICE_CNOC); -DEFINE_QNODE(xm_qdss_dap, SDM845_MASTER_QDSS_DAP, 1, 8, SDM845_SLAVE_A1NOC= _CFG, SDM845_SLAVE_A2NOC_CFG, SDM845_SLAVE_AOP, SDM845_SLAVE_AOSS, SDM845_S= LAVE_CAMERA_CFG, SDM845_SLAVE_CLK_CTL, SDM845_SLAVE_CDSP_CFG, SDM845_SLAVE_= RBCPR_CX_CFG, SDM845_SLAVE_CRYPTO_0_CFG, SDM845_SLAVE_DCC_CFG, SDM845_SLAVE= _CNOC_DDRSS, SDM845_SLAVE_DISPLAY_CFG, SDM845_SLAVE_GLM, SDM845_SLAVE_GFX3D= _CFG, SDM845_SLAVE_IMEM_CFG, SDM845_SLAVE_IPA_CFG, SDM845_SLAVE_CNOC_MNOC_C= FG, SDM845_SLAVE_PCIE_0_CFG, SDM845_SLAVE_PCIE_1_CFG, SDM845_SLAVE_PDM, SDM= 845_SLAVE_SOUTH_PHY_CFG, SDM845_SLAVE_PIMEM_CFG, SDM845_SLAVE_PRNG, SDM845_= SLAVE_QDSS_CFG, SDM845_SLAVE_BLSP_2, SDM845_SLAVE_BLSP_1, SDM845_SLAVE_SDCC= _2, SDM845_SLAVE_SDCC_4, SDM845_SLAVE_SNOC_CFG, SDM845_SLAVE_SPDM_WRAPPER, = SDM845_SLAVE_SPSS_CFG, SDM845_SLAVE_TCSR, SDM845_SLAVE_TLMM_NORTH, SDM845_S= LAVE_TLMM_SOUTH, SDM845_SLAVE_TSIF, SDM845_SLAVE_UFS_CARD_CFG, SDM845_SLAVE= _UFS_MEM_CFG, SDM845_SLAVE_USB3_0, SDM845_SLAVE_USB3_1, SDM845_SLAVE_VENUS_= CFG, SDM845_SLAVE_VSENS E_CTRL_CFG, SDM845_SLAVE_CNOC_A2NOC, SDM845_SLAVE_SERVICE_CNOC); -DEFINE_QNODE(qhm_cnoc, SDM845_MASTER_CNOC_DC_NOC, 1, 4, SDM845_SLAVE_LLCC_= CFG, SDM845_SLAVE_MEM_NOC_CFG); -DEFINE_QNODE(acm_l3, SDM845_MASTER_APPSS_PROC, 1, 16, SDM845_SLAVE_GNOC_SN= OC, SDM845_SLAVE_GNOC_MEM_NOC, SDM845_SLAVE_SERVICE_GNOC); -DEFINE_QNODE(pm_gnoc_cfg, SDM845_MASTER_GNOC_CFG, 1, 4, SDM845_SLAVE_SERVI= CE_GNOC); -DEFINE_QNODE(llcc_mc, SDM845_MASTER_LLCC, 4, 4, SDM845_SLAVE_EBI1); -DEFINE_QNODE(acm_tcu, SDM845_MASTER_TCU_0, 1, 8, SDM845_SLAVE_MEM_NOC_GNOC= , SDM845_SLAVE_LLCC, SDM845_SLAVE_MEM_NOC_SNOC); -DEFINE_QNODE(qhm_memnoc_cfg, SDM845_MASTER_MEM_NOC_CFG, 1, 4, SDM845_SLAVE= _MSS_PROC_MS_MPU_CFG, SDM845_SLAVE_SERVICE_MEM_NOC); -DEFINE_QNODE(qnm_apps, SDM845_MASTER_GNOC_MEM_NOC, 2, 32, SDM845_SLAVE_LLC= C); -DEFINE_QNODE(qnm_mnoc_hf, SDM845_MASTER_MNOC_HF_MEM_NOC, 2, 32, SDM845_SLA= VE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_sf, SDM845_MASTER_MNOC_SF_MEM_NOC, 1, 32, SDM845_SLA= VE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC, SDM845_SLAVE_MEM_NOC_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SDM845_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDM845_SLAV= E_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SDM845_MASTER_SNOC_SF_MEM_NOC, 1, 16, SDM845_SLA= VE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC); -DEFINE_QNODE(qxm_gpu, SDM845_MASTER_GFX3D, 2, 32, SDM845_SLAVE_MEM_NOC_GNO= C, SDM845_SLAVE_LLCC, SDM845_SLAVE_MEM_NOC_SNOC); -DEFINE_QNODE(qhm_mnoc_cfg, SDM845_MASTER_CNOC_MNOC_CFG, 1, 4, SDM845_SLAVE= _SERVICE_MNOC); -DEFINE_QNODE(qxm_camnoc_hf0, SDM845_MASTER_CAMNOC_HF0, 1, 32, SDM845_SLAVE= _MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_hf1, SDM845_MASTER_CAMNOC_HF1, 1, 32, SDM845_SLAVE= _MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_sf, SDM845_MASTER_CAMNOC_SF, 1, 32, SDM845_SLAVE_M= NOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SDM845_MASTER_MDP0, 1, 32, SDM845_SLAVE_MNOC_HF_MEM= _NOC); -DEFINE_QNODE(qxm_mdp1, SDM845_MASTER_MDP1, 1, 32, SDM845_SLAVE_MNOC_HF_MEM= _NOC); -DEFINE_QNODE(qxm_rot, SDM845_MASTER_ROTATOR, 1, 32, SDM845_SLAVE_MNOC_SF_M= EM_NOC); -DEFINE_QNODE(qxm_venus0, SDM845_MASTER_VIDEO_P0, 1, 32, SDM845_SLAVE_MNOC_= SF_MEM_NOC); -DEFINE_QNODE(qxm_venus1, SDM845_MASTER_VIDEO_P1, 1, 32, SDM845_SLAVE_MNOC_= SF_MEM_NOC); -DEFINE_QNODE(qxm_venus_arm9, SDM845_MASTER_VIDEO_PROC, 1, 8, SDM845_SLAVE_= MNOC_SF_MEM_NOC); -DEFINE_QNODE(qhm_snoc_cfg, SDM845_MASTER_SNOC_CFG, 1, 4, SDM845_SLAVE_SERV= ICE_SNOC); -DEFINE_QNODE(qnm_aggre1_noc, SDM845_MASTER_A1NOC_SNOC, 1, 16, SDM845_SLAVE= _APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_SNOC_MEM_NOC_SF, SDM845_SLAVE_= IMEM, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_aggre2_noc, SDM845_MASTER_A2NOC_SNOC, 1, 16, SDM845_SLAVE= _APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_SNOC_MEM_NOC_SF, SDM845_SLAVE_= IMEM, SDM845_SLAVE_PCIE_0, SDM845_SLAVE_PCIE_1, SDM845_SLAVE_PIMEM, SDM845_= SLAVE_QDSS_STM, SDM845_SLAVE_TCU); -DEFINE_QNODE(qnm_gladiator_sodv, SDM845_MASTER_GNOC_SNOC, 1, 8, SDM845_SLA= VE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_IMEM, SDM845_SLAVE_PCIE_0, S= DM845_SLAVE_PCIE_1, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM, SDM845_SLAVE= _TCU); -DEFINE_QNODE(qnm_memnoc, SDM845_MASTER_MEM_NOC_SNOC, 1, 8, SDM845_SLAVE_AP= PSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_IMEM, SDM845_SLAVE_PIMEM, SDM845_= SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_pcie_anoc, SDM845_MASTER_ANOC_PCIE_SNOC, 1, 16, SDM845_SL= AVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_SNOC_MEM_NOC_SF, SDM845_SLA= VE_IMEM, SDM845_SLAVE_QDSS_STM); -DEFINE_QNODE(qxm_pimem, SDM845_MASTER_PIMEM, 1, 8, SDM845_SLAVE_SNOC_MEM_N= OC_GC, SDM845_SLAVE_IMEM); -DEFINE_QNODE(xm_gic, SDM845_MASTER_GIC, 1, 8, SDM845_SLAVE_SNOC_MEM_NOC_GC= , SDM845_SLAVE_IMEM); -DEFINE_QNODE(qns_a1noc_snoc, SDM845_SLAVE_A1NOC_SNOC, 1, 16, SDM845_MASTER= _A1NOC_SNOC); -DEFINE_QNODE(srvc_aggre1_noc, SDM845_SLAVE_SERVICE_A1NOC, 1, 4, 0); -DEFINE_QNODE(qns_pcie_a1noc_snoc, SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC, 1, 16= , SDM845_MASTER_ANOC_PCIE_SNOC); -DEFINE_QNODE(qns_a2noc_snoc, SDM845_SLAVE_A2NOC_SNOC, 1, 16, SDM845_MASTER= _A2NOC_SNOC); -DEFINE_QNODE(qns_pcie_snoc, SDM845_SLAVE_ANOC_PCIE_SNOC, 1, 16, SDM845_MAS= TER_ANOC_PCIE_SNOC); -DEFINE_QNODE(srvc_aggre2_noc, SDM845_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qns_camnoc_uncomp, SDM845_SLAVE_CAMNOC_UNCOMP, 1, 32); -DEFINE_QNODE(qhs_a1_noc_cfg, SDM845_SLAVE_A1NOC_CFG, 1, 4, SDM845_MASTER_A= 1NOC_CFG); -DEFINE_QNODE(qhs_a2_noc_cfg, SDM845_SLAVE_A2NOC_CFG, 1, 4, SDM845_MASTER_A= 2NOC_CFG); -DEFINE_QNODE(qhs_aop, SDM845_SLAVE_AOP, 1, 4); -DEFINE_QNODE(qhs_aoss, SDM845_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_camera_cfg, SDM845_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SDM845_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_compute_dsp_cfg, SDM845_SLAVE_CDSP_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SDM845_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SDM845_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_dcc_cfg, SDM845_SLAVE_DCC_CFG, 1, 4, SDM845_MASTER_CNOC_D= C_NOC); -DEFINE_QNODE(qhs_ddrss_cfg, SDM845_SLAVE_CNOC_DDRSS, 1, 4); -DEFINE_QNODE(qhs_display_cfg, SDM845_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_glm, SDM845_SLAVE_GLM, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SDM845_SLAVE_GFX3D_CFG, 1, 8); -DEFINE_QNODE(qhs_imem_cfg, SDM845_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SDM845_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mnoc_cfg, SDM845_SLAVE_CNOC_MNOC_CFG, 1, 4, SDM845_MASTER= _CNOC_MNOC_CFG); -DEFINE_QNODE(qhs_pcie0_cfg, SDM845_SLAVE_PCIE_0_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie_gen3_cfg, SDM845_SLAVE_PCIE_1_CFG, 1, 4); -DEFINE_QNODE(qhs_pdm, SDM845_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_phy_refgen_south, SDM845_SLAVE_SOUTH_PHY_CFG, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SDM845_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_prng, SDM845_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SDM845_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qupv3_north, SDM845_SLAVE_BLSP_2, 1, 4); -DEFINE_QNODE(qhs_qupv3_south, SDM845_SLAVE_BLSP_1, 1, 4); -DEFINE_QNODE(qhs_sdc2, SDM845_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_sdc4, SDM845_SLAVE_SDCC_4, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SDM845_SLAVE_SNOC_CFG, 1, 4, SDM845_MASTER_SNOC= _CFG); -DEFINE_QNODE(qhs_spdm, SDM845_SLAVE_SPDM_WRAPPER, 1, 4); -DEFINE_QNODE(qhs_spss_cfg, SDM845_SLAVE_SPSS_CFG, 1, 4); -DEFINE_QNODE(qhs_tcsr, SDM845_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm_north, SDM845_SLAVE_TLMM_NORTH, 1, 4); -DEFINE_QNODE(qhs_tlmm_south, SDM845_SLAVE_TLMM_SOUTH, 1, 4); -DEFINE_QNODE(qhs_tsif, SDM845_SLAVE_TSIF, 1, 4); -DEFINE_QNODE(qhs_ufs_card_cfg, SDM845_SLAVE_UFS_CARD_CFG, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SDM845_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3_0, SDM845_SLAVE_USB3_0, 1, 4); -DEFINE_QNODE(qhs_usb3_1, SDM845_SLAVE_USB3_1, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SDM845_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SDM845_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(qns_cnoc_a2noc, SDM845_SLAVE_CNOC_A2NOC, 1, 8, SDM845_MASTER_= CNOC_A2NOC); -DEFINE_QNODE(srvc_cnoc, SDM845_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(qhs_llcc, SDM845_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qhs_memnoc, SDM845_SLAVE_MEM_NOC_CFG, 1, 4, SDM845_MASTER_MEM= _NOC_CFG); -DEFINE_QNODE(qns_gladiator_sodv, SDM845_SLAVE_GNOC_SNOC, 1, 8, SDM845_MAST= ER_GNOC_SNOC); -DEFINE_QNODE(qns_gnoc_memnoc, SDM845_SLAVE_GNOC_MEM_NOC, 2, 32, SDM845_MAS= TER_GNOC_MEM_NOC); -DEFINE_QNODE(srvc_gnoc, SDM845_SLAVE_SERVICE_GNOC, 1, 4); -DEFINE_QNODE(ebi, SDM845_SLAVE_EBI1, 4, 4); -DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qns_apps_io, SDM845_SLAVE_MEM_NOC_GNOC, 1, 32); -DEFINE_QNODE(qns_llcc, SDM845_SLAVE_LLCC, 4, 16, SDM845_MASTER_LLCC); -DEFINE_QNODE(qns_memnoc_snoc, SDM845_SLAVE_MEM_NOC_SNOC, 1, 8, SDM845_MAST= ER_MEM_NOC_SNOC); -DEFINE_QNODE(srvc_memnoc, SDM845_SLAVE_SERVICE_MEM_NOC, 1, 4); -DEFINE_QNODE(qns2_mem_noc, SDM845_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SDM845_MAS= TER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_hf, SDM845_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SDM845_M= ASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SDM845_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qhs_apss, SDM845_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qns_cnoc, SDM845_SLAVE_SNOC_CNOC, 1, 8, SDM845_MASTER_SNOC_CN= OC); -DEFINE_QNODE(qns_memnoc_gc, SDM845_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDM845_MAS= TER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_memnoc_sf, SDM845_SLAVE_SNOC_MEM_NOC_SF, 1, 16, SDM845_MA= STER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(qxs_imem, SDM845_SLAVE_IMEM, 1, 8); -DEFINE_QNODE(qxs_pcie, SDM845_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(qxs_pcie_gen3, SDM845_SLAVE_PCIE_1, 1, 8); -DEFINE_QNODE(qxs_pimem, SDM845_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SDM845_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_qdss_stm, SDM845_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SDM845_SLAVE_TCU, 1, 8); +static struct qcom_icc_node qhm_a1noc_cfg =3D { + .name =3D "qhm_a1noc_cfg", + .id =3D SDM845_MASTER_A1NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qhm_qup1 =3D { + .name =3D "qhm_qup1", + .id =3D SDM845_MASTER_BLSP_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_tsif =3D { + .name =3D "qhm_tsif", + .id =3D SDM845_MASTER_TSIF, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc2 =3D { + .name =3D "xm_sdc2", + .id =3D SDM845_MASTER_SDCC_2, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc4 =3D { + .name =3D "xm_sdc4", + .id =3D SDM845_MASTER_SDCC_4, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_card =3D { + .name =3D "xm_ufs_card", + .id =3D SDM845_MASTER_UFS_CARD, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_mem =3D { + .name =3D "xm_ufs_mem", + .id =3D SDM845_MASTER_UFS_MEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_pcie_0 =3D { + .name =3D "xm_pcie_0", + .id =3D SDM845_MASTER_PCIE_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_a2noc_cfg =3D { + .name =3D "qhm_a2noc_cfg", + .id =3D SDM845_MASTER_A2NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam =3D { + .name =3D "qhm_qdss_bam", + .id =3D SDM845_MASTER_QDSS_BAM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup2 =3D { + .name =3D "qhm_qup2", + .id =3D SDM845_MASTER_BLSP_2, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_cnoc =3D { + .name =3D "qnm_cnoc", + .id =3D SDM845_MASTER_CNOC_A2NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_crypto =3D { + .name =3D "qxm_crypto", + .id =3D SDM845_MASTER_CRYPTO, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_ipa =3D { + .name =3D "qxm_ipa", + .id =3D SDM845_MASTER_IPA, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_pcie3_1 =3D { + .name =3D "xm_pcie3_1", + .id =3D SDM845_MASTER_PCIE_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_ANOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr =3D { + .name =3D "xm_qdss_etr", + .id =3D SDM845_MASTER_QDSS_ETR, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_0 =3D { + .name =3D "xm_usb3_0", + .id =3D SDM845_MASTER_USB3_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_1 =3D { + .name =3D "xm_usb3_1", + .id =3D SDM845_MASTER_USB3_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0_uncomp =3D { + .name =3D "qxm_camnoc_hf0_uncomp", + .id =3D SDM845_MASTER_CAMNOC_HF0_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1_uncomp =3D { + .name =3D "qxm_camnoc_hf1_uncomp", + .id =3D SDM845_MASTER_CAMNOC_HF1_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_sf_uncomp =3D { + .name =3D "qxm_camnoc_sf_uncomp", + .id =3D SDM845_MASTER_CAMNOC_SF_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qhm_spdm =3D { + .name =3D "qhm_spdm", + .id =3D SDM845_MASTER_SPDM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_CNOC_A2NOC }, +}; + +static struct qcom_icc_node qhm_tic =3D { + .name =3D "qhm_tic", + .id =3D SDM845_MASTER_TIC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 43, + .links =3D { SDM845_SLAVE_A1NOC_CFG, + SDM845_SLAVE_A2NOC_CFG, + SDM845_SLAVE_AOP, + SDM845_SLAVE_AOSS, + SDM845_SLAVE_CAMERA_CFG, + SDM845_SLAVE_CLK_CTL, + SDM845_SLAVE_CDSP_CFG, + SDM845_SLAVE_RBCPR_CX_CFG, + SDM845_SLAVE_CRYPTO_0_CFG, + SDM845_SLAVE_DCC_CFG, + SDM845_SLAVE_CNOC_DDRSS, + SDM845_SLAVE_DISPLAY_CFG, + SDM845_SLAVE_GLM, + SDM845_SLAVE_GFX3D_CFG, + SDM845_SLAVE_IMEM_CFG, + SDM845_SLAVE_IPA_CFG, + SDM845_SLAVE_CNOC_MNOC_CFG, + SDM845_SLAVE_PCIE_0_CFG, + SDM845_SLAVE_PCIE_1_CFG, + SDM845_SLAVE_PDM, + SDM845_SLAVE_SOUTH_PHY_CFG, + SDM845_SLAVE_PIMEM_CFG, + SDM845_SLAVE_PRNG, + SDM845_SLAVE_QDSS_CFG, + SDM845_SLAVE_BLSP_2, + SDM845_SLAVE_BLSP_1, + SDM845_SLAVE_SDCC_2, + SDM845_SLAVE_SDCC_4, + SDM845_SLAVE_SNOC_CFG, + SDM845_SLAVE_SPDM_WRAPPER, + SDM845_SLAVE_SPSS_CFG, + SDM845_SLAVE_TCSR, + SDM845_SLAVE_TLMM_NORTH, + SDM845_SLAVE_TLMM_SOUTH, + SDM845_SLAVE_TSIF, + SDM845_SLAVE_UFS_CARD_CFG, + SDM845_SLAVE_UFS_MEM_CFG, + SDM845_SLAVE_USB3_0, + SDM845_SLAVE_USB3_1, + SDM845_SLAVE_VENUS_CFG, + SDM845_SLAVE_VSENSE_CTRL_CFG, + SDM845_SLAVE_CNOC_A2NOC, + SDM845_SLAVE_SERVICE_CNOC + }, +}; + +static struct qcom_icc_node qnm_snoc =3D { + .name =3D "qnm_snoc", + .id =3D SDM845_MASTER_SNOC_CNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 42, + .links =3D { SDM845_SLAVE_A1NOC_CFG, + SDM845_SLAVE_A2NOC_CFG, + SDM845_SLAVE_AOP, + SDM845_SLAVE_AOSS, + SDM845_SLAVE_CAMERA_CFG, + SDM845_SLAVE_CLK_CTL, + SDM845_SLAVE_CDSP_CFG, + SDM845_SLAVE_RBCPR_CX_CFG, + SDM845_SLAVE_CRYPTO_0_CFG, + SDM845_SLAVE_DCC_CFG, + SDM845_SLAVE_CNOC_DDRSS, + SDM845_SLAVE_DISPLAY_CFG, + SDM845_SLAVE_GLM, + SDM845_SLAVE_GFX3D_CFG, + SDM845_SLAVE_IMEM_CFG, + SDM845_SLAVE_IPA_CFG, + SDM845_SLAVE_CNOC_MNOC_CFG, + SDM845_SLAVE_PCIE_0_CFG, + SDM845_SLAVE_PCIE_1_CFG, + SDM845_SLAVE_PDM, + SDM845_SLAVE_SOUTH_PHY_CFG, + SDM845_SLAVE_PIMEM_CFG, + SDM845_SLAVE_PRNG, + SDM845_SLAVE_QDSS_CFG, + SDM845_SLAVE_BLSP_2, + SDM845_SLAVE_BLSP_1, + SDM845_SLAVE_SDCC_2, + SDM845_SLAVE_SDCC_4, + SDM845_SLAVE_SNOC_CFG, + SDM845_SLAVE_SPDM_WRAPPER, + SDM845_SLAVE_SPSS_CFG, + SDM845_SLAVE_TCSR, + SDM845_SLAVE_TLMM_NORTH, + SDM845_SLAVE_TLMM_SOUTH, + SDM845_SLAVE_TSIF, + SDM845_SLAVE_UFS_CARD_CFG, + SDM845_SLAVE_UFS_MEM_CFG, + SDM845_SLAVE_USB3_0, + SDM845_SLAVE_USB3_1, + SDM845_SLAVE_VENUS_CFG, + SDM845_SLAVE_VSENSE_CTRL_CFG, + SDM845_SLAVE_SERVICE_CNOC + }, +}; + +static struct qcom_icc_node xm_qdss_dap =3D { + .name =3D "xm_qdss_dap", + .id =3D SDM845_MASTER_QDSS_DAP, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 43, + .links =3D { SDM845_SLAVE_A1NOC_CFG, + SDM845_SLAVE_A2NOC_CFG, + SDM845_SLAVE_AOP, + SDM845_SLAVE_AOSS, + SDM845_SLAVE_CAMERA_CFG, + SDM845_SLAVE_CLK_CTL, + SDM845_SLAVE_CDSP_CFG, + SDM845_SLAVE_RBCPR_CX_CFG, + SDM845_SLAVE_CRYPTO_0_CFG, + SDM845_SLAVE_DCC_CFG, + SDM845_SLAVE_CNOC_DDRSS, + SDM845_SLAVE_DISPLAY_CFG, + SDM845_SLAVE_GLM, + SDM845_SLAVE_GFX3D_CFG, + SDM845_SLAVE_IMEM_CFG, + SDM845_SLAVE_IPA_CFG, + SDM845_SLAVE_CNOC_MNOC_CFG, + SDM845_SLAVE_PCIE_0_CFG, + SDM845_SLAVE_PCIE_1_CFG, + SDM845_SLAVE_PDM, + SDM845_SLAVE_SOUTH_PHY_CFG, + SDM845_SLAVE_PIMEM_CFG, + SDM845_SLAVE_PRNG, + SDM845_SLAVE_QDSS_CFG, + SDM845_SLAVE_BLSP_2, + SDM845_SLAVE_BLSP_1, + SDM845_SLAVE_SDCC_2, + SDM845_SLAVE_SDCC_4, + SDM845_SLAVE_SNOC_CFG, + SDM845_SLAVE_SPDM_WRAPPER, + SDM845_SLAVE_SPSS_CFG, + SDM845_SLAVE_TCSR, + SDM845_SLAVE_TLMM_NORTH, + SDM845_SLAVE_TLMM_SOUTH, + SDM845_SLAVE_TSIF, + SDM845_SLAVE_UFS_CARD_CFG, + SDM845_SLAVE_UFS_MEM_CFG, + SDM845_SLAVE_USB3_0, + SDM845_SLAVE_USB3_1, + SDM845_SLAVE_VENUS_CFG, + SDM845_SLAVE_VSENSE_CTRL_CFG, + SDM845_SLAVE_CNOC_A2NOC, + SDM845_SLAVE_SERVICE_CNOC + }, +}; + +static struct qcom_icc_node qhm_cnoc =3D { + .name =3D "qhm_cnoc", + .id =3D SDM845_MASTER_CNOC_DC_NOC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .links =3D { SDM845_SLAVE_LLCC_CFG, + SDM845_SLAVE_MEM_NOC_CFG + }, +}; + +static struct qcom_icc_node acm_l3 =3D { + .name =3D "acm_l3", + .id =3D SDM845_MASTER_APPSS_PROC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 3, + .links =3D { SDM845_SLAVE_GNOC_SNOC, + SDM845_SLAVE_GNOC_MEM_NOC, + SDM845_SLAVE_SERVICE_GNOC + }, +}; + +static struct qcom_icc_node pm_gnoc_cfg =3D { + .name =3D "pm_gnoc_cfg", + .id =3D SDM845_MASTER_GNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_SERVICE_GNOC }, +}; + +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .id =3D SDM845_MASTER_LLCC, + .channels =3D 4, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_EBI1 }, +}; + +static struct qcom_icc_node acm_tcu =3D { + .name =3D "acm_tcu", + .id =3D SDM845_MASTER_TCU_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 3, + .links =3D { SDM845_SLAVE_MEM_NOC_GNOC, + SDM845_SLAVE_LLCC, + SDM845_SLAVE_MEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_memnoc_cfg =3D { + .name =3D "qhm_memnoc_cfg", + .id =3D SDM845_MASTER_MEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .links =3D { SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, + SDM845_SLAVE_SERVICE_MEM_NOC + }, +}; + +static struct qcom_icc_node qnm_apps =3D { + .name =3D "qnm_apps", + .id =3D SDM845_MASTER_GNOC_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_hf =3D { + .name =3D "qnm_mnoc_hf", + .id =3D SDM845_MASTER_MNOC_HF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SDM845_SLAVE_MEM_NOC_GNOC, + SDM845_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_mnoc_sf =3D { + .name =3D "qnm_mnoc_sf", + .id =3D SDM845_MASTER_MNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 3, + .links =3D { SDM845_SLAVE_MEM_NOC_GNOC, + SDM845_SLAVE_LLCC, + SDM845_SLAVE_MEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc =3D { + .name =3D "qnm_snoc_gc", + .id =3D SDM845_MASTER_SNOC_GC_MEM_NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf =3D { + .name =3D "qnm_snoc_sf", + .id =3D SDM845_MASTER_SNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 2, + .links =3D { SDM845_SLAVE_MEM_NOC_GNOC, + SDM845_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qxm_gpu =3D { + .name =3D "qxm_gpu", + .id =3D SDM845_MASTER_GFX3D, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 3, + .links =3D { SDM845_SLAVE_MEM_NOC_GNOC, + SDM845_SLAVE_LLCC, + SDM845_SLAVE_MEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg =3D { + .name =3D "qhm_mnoc_cfg", + .id =3D SDM845_MASTER_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0 =3D { + .name =3D "qxm_camnoc_hf0", + .id =3D SDM845_MASTER_CAMNOC_HF0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1 =3D { + .name =3D "qxm_camnoc_hf1", + .id =3D SDM845_MASTER_CAMNOC_HF1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_sf =3D { + .name =3D "qxm_camnoc_sf", + .id =3D SDM845_MASTER_CAMNOC_SF, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 =3D { + .name =3D "qxm_mdp0", + .id =3D SDM845_MASTER_MDP0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp1 =3D { + .name =3D "qxm_mdp1", + .id =3D SDM845_MASTER_MDP1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_rot =3D { + .name =3D "qxm_rot", + .id =3D SDM845_MASTER_ROTATOR, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus0 =3D { + .name =3D "qxm_venus0", + .id =3D SDM845_MASTER_VIDEO_P0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus1 =3D { + .name =3D "qxm_venus1", + .id =3D SDM845_MASTER_VIDEO_P1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus_arm9 =3D { + .name =3D "qxm_venus_arm9", + .id =3D SDM845_MASTER_VIDEO_PROC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_snoc_cfg =3D { + .name =3D "qhm_snoc_cfg", + .id =3D SDM845_MASTER_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM845_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc =3D { + .name =3D "qnm_aggre1_noc", + .id =3D SDM845_MASTER_A1NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 6, + .links =3D { SDM845_SLAVE_APPSS, + SDM845_SLAVE_SNOC_CNOC, + SDM845_SLAVE_SNOC_MEM_NOC_SF, + SDM845_SLAVE_IMEM, + SDM845_SLAVE_PIMEM, + SDM845_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_aggre2_noc =3D { + .name =3D "qnm_aggre2_noc", + .id =3D SDM845_MASTER_A2NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 9, + .links =3D { SDM845_SLAVE_APPSS, + SDM845_SLAVE_SNOC_CNOC, + SDM845_SLAVE_SNOC_MEM_NOC_SF, + SDM845_SLAVE_IMEM, + SDM845_SLAVE_PCIE_0, + SDM845_SLAVE_PCIE_1, + SDM845_SLAVE_PIMEM, + SDM845_SLAVE_QDSS_STM, + SDM845_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_gladiator_sodv =3D { + .name =3D "qnm_gladiator_sodv", + .id =3D SDM845_MASTER_GNOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 8, + .links =3D { SDM845_SLAVE_APPSS, + SDM845_SLAVE_SNOC_CNOC, + SDM845_SLAVE_IMEM, + SDM845_SLAVE_PCIE_0, + SDM845_SLAVE_PCIE_1, + SDM845_SLAVE_PIMEM, + SDM845_SLAVE_QDSS_STM, + SDM845_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_memnoc =3D { + .name =3D "qnm_memnoc", + .id =3D SDM845_MASTER_MEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 5, + .links =3D { SDM845_SLAVE_APPSS, + SDM845_SLAVE_SNOC_CNOC, + SDM845_SLAVE_IMEM, + SDM845_SLAVE_PIMEM, + SDM845_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_pcie_anoc =3D { + .name =3D "qnm_pcie_anoc", + .id =3D SDM845_MASTER_ANOC_PCIE_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 5, + .links =3D { SDM845_SLAVE_APPSS, + SDM845_SLAVE_SNOC_CNOC, + SDM845_SLAVE_SNOC_MEM_NOC_SF, + SDM845_SLAVE_IMEM, + SDM845_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qxm_pimem =3D { + .name =3D "qxm_pimem", + .id =3D SDM845_MASTER_PIMEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SDM845_SLAVE_SNOC_MEM_NOC_GC, + SDM845_SLAVE_IMEM + }, +}; + +static struct qcom_icc_node xm_gic =3D { + .name =3D "xm_gic", + .id =3D SDM845_MASTER_GIC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SDM845_SLAVE_SNOC_MEM_NOC_GC, + SDM845_SLAVE_IMEM + }, +}; + +static struct qcom_icc_node qns_a1noc_snoc =3D { + .name =3D "qns_a1noc_snoc", + .id =3D SDM845_SLAVE_A1NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SDM845_MASTER_A1NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre1_noc =3D { + .name =3D "srvc_aggre1_noc", + .id =3D SDM845_SLAVE_SERVICE_A1NOC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { 0 }, +}; + +static struct qcom_icc_node qns_pcie_a1noc_snoc =3D { + .name =3D "qns_pcie_a1noc_snoc", + .id =3D SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SDM845_MASTER_ANOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qns_a2noc_snoc =3D { + .name =3D "qns_a2noc_snoc", + .id =3D SDM845_SLAVE_A2NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SDM845_MASTER_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qns_pcie_snoc =3D { + .name =3D "qns_pcie_snoc", + .id =3D SDM845_SLAVE_ANOC_PCIE_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SDM845_MASTER_ANOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc =3D { + .name =3D "srvc_aggre2_noc", + .id =3D SDM845_SLAVE_SERVICE_A2NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_camnoc_uncomp =3D { + .name =3D "qns_camnoc_uncomp", + .id =3D SDM845_SLAVE_CAMNOC_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg =3D { + .name =3D "qhs_a1_noc_cfg", + .id =3D SDM845_SLAVE_A1NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM845_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhs_a2_noc_cfg =3D { + .name =3D "qhs_a2_noc_cfg", + .id =3D SDM845_SLAVE_A2NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM845_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qhs_aop =3D { + .name =3D "qhs_aop", + .id =3D SDM845_SLAVE_AOP, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .id =3D SDM845_SLAVE_AOSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_cfg =3D { + .name =3D "qhs_camera_cfg", + .id =3D SDM845_SLAVE_CAMERA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .id =3D SDM845_SLAVE_CLK_CTL, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_compute_dsp_cfg =3D { + .name =3D "qhs_compute_dsp_cfg", + .id =3D SDM845_SLAVE_CDSP_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_cx =3D { + .name =3D "qhs_cpr_cx", + .id =3D SDM845_SLAVE_RBCPR_CX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg =3D { + .name =3D "qhs_crypto0_cfg", + .id =3D SDM845_SLAVE_CRYPTO_0_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_dcc_cfg =3D { + .name =3D "qhs_dcc_cfg", + .id =3D SDM845_SLAVE_DCC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM845_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qhs_ddrss_cfg =3D { + .name =3D "qhs_ddrss_cfg", + .id =3D SDM845_SLAVE_CNOC_DDRSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_display_cfg =3D { + .name =3D "qhs_display_cfg", + .id =3D SDM845_SLAVE_DISPLAY_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_glm =3D { + .name =3D "qhs_glm", + .id =3D SDM845_SLAVE_GLM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg =3D { + .name =3D "qhs_gpuss_cfg", + .id =3D SDM845_SLAVE_GFX3D_CFG, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .id =3D SDM845_SLAVE_IMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipa =3D { + .name =3D "qhs_ipa", + .id =3D SDM845_SLAVE_IPA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg =3D { + .name =3D "qhs_mnoc_cfg", + .id =3D SDM845_SLAVE_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM845_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qhs_pcie0_cfg =3D { + .name =3D "qhs_pcie0_cfg", + .id =3D SDM845_SLAVE_PCIE_0_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie_gen3_cfg =3D { + .name =3D "qhs_pcie_gen3_cfg", + .id =3D SDM845_SLAVE_PCIE_1_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pdm =3D { + .name =3D "qhs_pdm", + .id =3D SDM845_SLAVE_PDM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_phy_refgen_south =3D { + .name =3D "qhs_phy_refgen_south", + .id =3D SDM845_SLAVE_SOUTH_PHY_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg =3D { + .name =3D "qhs_pimem_cfg", + .id =3D SDM845_SLAVE_PIMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_prng =3D { + .name =3D "qhs_prng", + .id =3D SDM845_SLAVE_PRNG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .id =3D SDM845_SLAVE_QDSS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qupv3_north =3D { + .name =3D "qhs_qupv3_north", + .id =3D SDM845_SLAVE_BLSP_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qupv3_south =3D { + .name =3D "qhs_qupv3_south", + .id =3D SDM845_SLAVE_BLSP_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc2 =3D { + .name =3D "qhs_sdc2", + .id =3D SDM845_SLAVE_SDCC_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc4 =3D { + .name =3D "qhs_sdc4", + .id =3D SDM845_SLAVE_SDCC_4, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg =3D { + .name =3D "qhs_snoc_cfg", + .id =3D SDM845_SLAVE_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM845_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_spdm =3D { + .name =3D "qhs_spdm", + .id =3D SDM845_SLAVE_SPDM_WRAPPER, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_spss_cfg =3D { + .name =3D "qhs_spss_cfg", + .id =3D SDM845_SLAVE_SPSS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .id =3D SDM845_SLAVE_TCSR, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm_north =3D { + .name =3D "qhs_tlmm_north", + .id =3D SDM845_SLAVE_TLMM_NORTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm_south =3D { + .name =3D "qhs_tlmm_south", + .id =3D SDM845_SLAVE_TLMM_SOUTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tsif =3D { + .name =3D "qhs_tsif", + .id =3D SDM845_SLAVE_TSIF, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_card_cfg =3D { + .name =3D "qhs_ufs_card_cfg", + .id =3D SDM845_SLAVE_UFS_CARD_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg =3D { + .name =3D "qhs_ufs_mem_cfg", + .id =3D SDM845_SLAVE_UFS_MEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_0 =3D { + .name =3D "qhs_usb3_0", + .id =3D SDM845_SLAVE_USB3_0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_1 =3D { + .name =3D "qhs_usb3_1", + .id =3D SDM845_SLAVE_USB3_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_venus_cfg =3D { + .name =3D "qhs_venus_cfg", + .id =3D SDM845_SLAVE_VENUS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { + .name =3D "qhs_vsense_ctrl_cfg", + .id =3D SDM845_SLAVE_VSENSE_CTRL_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_cnoc_a2noc =3D { + .name =3D "qns_cnoc_a2noc", + .id =3D SDM845_SLAVE_CNOC_A2NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM845_MASTER_CNOC_A2NOC }, +}; + +static struct qcom_icc_node srvc_cnoc =3D { + .name =3D "srvc_cnoc", + .id =3D SDM845_SLAVE_SERVICE_CNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_llcc =3D { + .name =3D "qhs_llcc", + .id =3D SDM845_SLAVE_LLCC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_memnoc =3D { + .name =3D "qhs_memnoc", + .id =3D SDM845_SLAVE_MEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDM845_MASTER_MEM_NOC_CFG }, +}; + +static struct qcom_icc_node qns_gladiator_sodv =3D { + .name =3D "qns_gladiator_sodv", + .id =3D SDM845_SLAVE_GNOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM845_MASTER_GNOC_SNOC }, +}; + +static struct qcom_icc_node qns_gnoc_memnoc =3D { + .name =3D "qns_gnoc_memnoc", + .id =3D SDM845_SLAVE_GNOC_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM845_MASTER_GNOC_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_gnoc =3D { + .name =3D "srvc_gnoc", + .id =3D SDM845_SLAVE_SERVICE_GNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .id =3D SDM845_SLAVE_EBI1, + .channels =3D 4, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg =3D { + .name =3D "qhs_mdsp_ms_mpu_cfg", + .id =3D SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_apps_io =3D { + .name =3D "qns_apps_io", + .id =3D SDM845_SLAVE_MEM_NOC_GNOC, + .channels =3D 1, + .buswidth =3D 32, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .id =3D SDM845_SLAVE_LLCC, + .channels =3D 4, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SDM845_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_memnoc_snoc =3D { + .name =3D "qns_memnoc_snoc", + .id =3D SDM845_SLAVE_MEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM845_MASTER_MEM_NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_memnoc =3D { + .name =3D "srvc_memnoc", + .id =3D SDM845_SLAVE_SERVICE_MEM_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns2_mem_noc =3D { + .name =3D "qns2_mem_noc", + .id =3D SDM845_SLAVE_MNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM845_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_hf =3D { + .name =3D "qns_mem_noc_hf", + .id =3D SDM845_SLAVE_MNOC_HF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SDM845_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc =3D { + .name =3D "srvc_mnoc", + .id =3D SDM845_SLAVE_SERVICE_MNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_apss =3D { + .name =3D "qhs_apss", + .id =3D SDM845_SLAVE_APPSS, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qns_cnoc =3D { + .name =3D "qns_cnoc", + .id =3D SDM845_SLAVE_SNOC_CNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM845_MASTER_SNOC_CNOC }, +}; + +static struct qcom_icc_node qns_memnoc_gc =3D { + .name =3D "qns_memnoc_gc", + .id =3D SDM845_SLAVE_SNOC_MEM_NOC_GC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDM845_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_memnoc_sf =3D { + .name =3D "qns_memnoc_sf", + .id =3D SDM845_SLAVE_SNOC_MEM_NOC_SF, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SDM845_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .id =3D SDM845_SLAVE_IMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qxs_pcie =3D { + .name =3D "qxs_pcie", + .id =3D SDM845_SLAVE_PCIE_0, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qxs_pcie_gen3 =3D { + .name =3D "qxs_pcie_gen3", + .id =3D SDM845_SLAVE_PCIE_1, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qxs_pimem =3D { + .name =3D "qxs_pimem", + .id =3D SDM845_SLAVE_PIMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node srvc_snoc =3D { + .name =3D "srvc_snoc", + .id =3D SDM845_SLAVE_SERVICE_SNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .id =3D SDM845_SLAVE_QDSS_STM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .id =3D SDM845_SLAVE_TCU, + .channels =3D 1, + .buswidth =3D 8, +}; =20 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADD74C001E0 for ; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:37 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:08 +0200 Subject: [PATCH 09/53] interconnect: qcom: sdx55: Retire DEFINE_QNODE MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-9-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=22083; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=DfvVOVIJtBrOMDPH5uxDCesHNBsdiS2Js6MQ8bXhn3w=; b=eT0LvUJhmLKsKNSJml7cLtTJ25fwA5ZUjjQXGVbYrJ9bR2dWLhT4vlK4FMuFijkpTq2D50mOh hv2kBcQRx9QCjUMYaVQBlkk/HC4/kOEGkW10lPE0xHV+5LMWnLS4WY1 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sdx55.c | 681 ++++++++++++++++++++++++++++++++++= ---- 1 file changed, 623 insertions(+), 58 deletions(-) diff --git a/drivers/interconnect/qcom/sdx55.c b/drivers/interconnect/qcom/= sdx55.c index 130a828c3873..2b5e8873eaa5 100644 --- a/drivers/interconnect/qcom/sdx55.c +++ b/drivers/interconnect/qcom/sdx55.c @@ -18,64 +18,629 @@ #include "icc-rpmh.h" #include "sdx55.h" =20 -DEFINE_QNODE(llcc_mc, SDX55_MASTER_LLCC, 4, 4, SDX55_SLAVE_EBI_CH0); -DEFINE_QNODE(acm_tcu, SDX55_MASTER_TCU_0, 1, 8, SDX55_SLAVE_LLCC, SDX55_SL= AVE_MEM_NOC_SNOC, SDX55_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SDX55_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDX55_SLAVE_= LLCC); -DEFINE_QNODE(xm_apps_rdwr, SDX55_MASTER_AMPSS_M0, 1, 16, SDX55_SLAVE_LLCC,= SDX55_SLAVE_MEM_NOC_SNOC, SDX55_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qhm_audio, SDX55_MASTER_AUDIO, 1, 4, SDX55_SLAVE_ANOC_SNOC); -DEFINE_QNODE(qhm_blsp1, SDX55_MASTER_BLSP_1, 1, 4, SDX55_SLAVE_ANOC_SNOC); -DEFINE_QNODE(qhm_qdss_bam, SDX55_MASTER_QDSS_BAM, 1, 4, SDX55_SLAVE_SNOC_C= FG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_TLMM, SDX55_SLAVE_S= PMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NO= C_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, = SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3= _PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SL= AVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO= , SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE= _TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG); -DEFINE_QNODE(qhm_qpic, SDX55_MASTER_QPIC, 1, 4, SDX55_SLAVE_AOSS, SDX55_SL= AVE_IPA_CFG, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP, SDX55_SLAVE_AUDIO); -DEFINE_QNODE(qhm_snoc_cfg, SDX55_MASTER_SNOC_CFG, 1, 4, SDX55_SLAVE_SERVIC= E_SNOC); -DEFINE_QNODE(qhm_spmi_fetcher1, SDX55_MASTER_SPMI_FETCHER, 1, 4, SDX55_SLA= VE_AOSS, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP); -DEFINE_QNODE(qnm_aggre_noc, SDX55_MASTER_ANOC_SNOC, 1, 8, SDX55_SLAVE_PCIE= _0, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_TLMM, SDX55_SLAVE= _SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_= NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX= , SDX55_SLAVE_QDSS_STM, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_I= PA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX5= 5_SLAVE_USB3, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_= CFG, SDX55_SLAVE_APPSS, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PR= NG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_S= LAVE_IMEM_CFG); -DEFINE_QNODE(qnm_ipa, SDX55_MASTER_IPA, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_= SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_AOSS, SDX55_SLAVE_SPMI_FETCHE= R, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX5= 5_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_QDSS_STM, SDX55_SLAVE_QPI= C, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55= _SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, S= DX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_T= LMM, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_CLK_CTL, SDX55= _SLAVE_IMEM_CFG); -DEFINE_QNODE(qnm_memnoc, SDX55_MASTER_MEM_NOC_SNOC, 1, 8, SDX55_SLAVE_SNOC= _CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_TLMM, SDX55_SLAVE= _SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_TCSR, SDX= 55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QDSS_STM, SDX55= _SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_= CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_C= NOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_APPSS, SD= X55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_C= FG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG); -DEFINE_QNODE(qnm_memnoc_pcie, SDX55_MASTER_MEM_NOC_PCIE_SNOC, 1, 8, SDX55_= SLAVE_PCIE_0); -DEFINE_QNODE(qxm_crypto, SDX55_MASTER_CRYPTO_CORE_0, 1, 8, SDX55_SLAVE_AOS= S, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP); -DEFINE_QNODE(xm_emac, SDX55_MASTER_EMAC, 1, 8, SDX55_SLAVE_ANOC_SNOC); -DEFINE_QNODE(xm_ipa2pcie_slv, SDX55_MASTER_IPA_PCIE, 1, 8, SDX55_SLAVE_PCI= E_0); -DEFINE_QNODE(xm_pcie, SDX55_MASTER_PCIE, 1, 8, SDX55_SLAVE_ANOC_SNOC); -DEFINE_QNODE(xm_qdss_etr, SDX55_MASTER_QDSS_ETR, 1, 8, SDX55_SLAVE_SNOC_CF= G, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_AOSS, SDX55_SLAVE_SP= MI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC= _GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, S= DX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_= PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLA= VE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO,= SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_= TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG); -DEFINE_QNODE(xm_sdc1, SDX55_MASTER_SDCC_1, 1, 8, SDX55_SLAVE_AOSS, SDX55_S= LAVE_IPA_CFG, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP, SDX55_SLAVE_AUDIO); -DEFINE_QNODE(xm_usb3, SDX55_MASTER_USB3, 1, 8, SDX55_SLAVE_ANOC_SNOC); -DEFINE_QNODE(ebi, SDX55_SLAVE_EBI_CH0, 1, 4); -DEFINE_QNODE(qns_llcc, SDX55_SLAVE_LLCC, 1, 16, SDX55_SLAVE_EBI_CH0); -DEFINE_QNODE(qns_memnoc_snoc, SDX55_SLAVE_MEM_NOC_SNOC, 1, 8, SDX55_MASTER= _MEM_NOC_SNOC); -DEFINE_QNODE(qns_sys_pcie, SDX55_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SDX55_MAST= ER_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qhs_aop, SDX55_SLAVE_AOP, 1, 4); -DEFINE_QNODE(qhs_aoss, SDX55_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_apss, SDX55_SLAVE_APPSS, 1, 4); -DEFINE_QNODE(qhs_audio, SDX55_SLAVE_AUDIO, 1, 4); -DEFINE_QNODE(qhs_blsp1, SDX55_SLAVE_BLSP_1, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SDX55_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SDX55_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_ddrss_cfg, SDX55_SLAVE_CNOC_DDRSS, 1, 4); -DEFINE_QNODE(qhs_ecc_cfg, SDX55_SLAVE_ECC_CFG, 1, 4); -DEFINE_QNODE(qhs_emac_cfg, SDX55_SLAVE_EMAC_CFG, 1, 4); -DEFINE_QNODE(qhs_imem_cfg, SDX55_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SDX55_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mss_cfg, SDX55_SLAVE_CNOC_MSS, 1, 4); -DEFINE_QNODE(qhs_pcie_parf, SDX55_SLAVE_PCIE_PARF, 1, 4); -DEFINE_QNODE(qhs_pdm, SDX55_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_prng, SDX55_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SDX55_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qpic, SDX55_SLAVE_QPIC, 1, 4); -DEFINE_QNODE(qhs_sdc1, SDX55_SLAVE_SDCC_1, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SDX55_SLAVE_SNOC_CFG, 1, 4, SDX55_MASTER_SNOC_C= FG); -DEFINE_QNODE(qhs_spmi_fetcher, SDX55_SLAVE_SPMI_FETCHER, 1, 4); -DEFINE_QNODE(qhs_spmi_vgi_coex, SDX55_SLAVE_SPMI_VGI_COEX, 1, 4); -DEFINE_QNODE(qhs_tcsr, SDX55_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm, SDX55_SLAVE_TLMM, 1, 4); -DEFINE_QNODE(qhs_usb3, SDX55_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_usb3_phy, SDX55_SLAVE_USB3_PHY_CFG, 1, 4); -DEFINE_QNODE(qns_aggre_noc, SDX55_SLAVE_ANOC_SNOC, 1, 8, SDX55_MASTER_ANOC= _SNOC); -DEFINE_QNODE(qns_snoc_memnoc, SDX55_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDX55_MAS= TER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qxs_imem, SDX55_SLAVE_OCIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SDX55_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_pcie, SDX55_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(xs_qdss_stm, SDX55_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SDX55_SLAVE_TCU, 1, 8); +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .id =3D SDX55_MASTER_LLCC, + .channels =3D 4, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDX55_SLAVE_EBI_CH0 }, +}; + +static struct qcom_icc_node acm_tcu =3D { + .name =3D "acm_tcu", + .id =3D SDX55_MASTER_TCU_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 3, + .links =3D { SDX55_SLAVE_LLCC, + SDX55_SLAVE_MEM_NOC_SNOC, + SDX55_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc =3D { + .name =3D "qnm_snoc_gc", + .id =3D SDX55_MASTER_SNOC_GC_MEM_NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDX55_SLAVE_LLCC }, +}; + +static struct qcom_icc_node xm_apps_rdwr =3D { + .name =3D "xm_apps_rdwr", + .id =3D SDX55_MASTER_AMPSS_M0, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 3, + .links =3D { SDX55_SLAVE_LLCC, + SDX55_SLAVE_MEM_NOC_SNOC, + SDX55_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qhm_audio =3D { + .name =3D "qhm_audio", + .id =3D SDX55_MASTER_AUDIO, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDX55_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node qhm_blsp1 =3D { + .name =3D "qhm_blsp1", + .id =3D SDX55_MASTER_BLSP_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDX55_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam =3D { + .name =3D "qhm_qdss_bam", + .id =3D SDX55_MASTER_QDSS_BAM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 28, + .links =3D { SDX55_SLAVE_SNOC_CFG, + SDX55_SLAVE_EMAC_CFG, + SDX55_SLAVE_USB3, + SDX55_SLAVE_TLMM, + SDX55_SLAVE_SPMI_FETCHER, + SDX55_SLAVE_QDSS_CFG, + SDX55_SLAVE_PDM, + SDX55_SLAVE_SNOC_MEM_NOC_GC, + SDX55_SLAVE_TCSR, + SDX55_SLAVE_CNOC_DDRSS, + SDX55_SLAVE_SPMI_VGI_COEX, + SDX55_SLAVE_QPIC, + SDX55_SLAVE_OCIMEM, + SDX55_SLAVE_IPA_CFG, + SDX55_SLAVE_USB3_PHY_CFG, + SDX55_SLAVE_AOP, + SDX55_SLAVE_BLSP_1, + SDX55_SLAVE_SDCC_1, + SDX55_SLAVE_CNOC_MSS, + SDX55_SLAVE_PCIE_PARF, + SDX55_SLAVE_ECC_CFG, + SDX55_SLAVE_AUDIO, + SDX55_SLAVE_AOSS, + SDX55_SLAVE_PRNG, + SDX55_SLAVE_CRYPTO_0_CFG, + SDX55_SLAVE_TCU, + SDX55_SLAVE_CLK_CTL, + SDX55_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node qhm_qpic =3D { + .name =3D "qhm_qpic", + .id =3D SDX55_MASTER_QPIC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 5, + .links =3D { SDX55_SLAVE_AOSS, + SDX55_SLAVE_IPA_CFG, + SDX55_SLAVE_ANOC_SNOC, + SDX55_SLAVE_AOP, + SDX55_SLAVE_AUDIO + }, +}; + +static struct qcom_icc_node qhm_snoc_cfg =3D { + .name =3D "qhm_snoc_cfg", + .id =3D SDX55_MASTER_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDX55_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qhm_spmi_fetcher1 =3D { + .name =3D "qhm_spmi_fetcher1", + .id =3D SDX55_MASTER_SPMI_FETCHER, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 3, + .links =3D { SDX55_SLAVE_AOSS, + SDX55_SLAVE_ANOC_SNOC, + SDX55_SLAVE_AOP + }, +}; + +static struct qcom_icc_node qnm_aggre_noc =3D { + .name =3D "qnm_aggre_noc", + .id =3D SDX55_MASTER_ANOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 30, + .links =3D { SDX55_SLAVE_PCIE_0, + SDX55_SLAVE_SNOC_CFG, + SDX55_SLAVE_SDCC_1, + SDX55_SLAVE_TLMM, + SDX55_SLAVE_SPMI_FETCHER, + SDX55_SLAVE_QDSS_CFG, + SDX55_SLAVE_PDM, + SDX55_SLAVE_SNOC_MEM_NOC_GC, + SDX55_SLAVE_TCSR, + SDX55_SLAVE_CNOC_DDRSS, + SDX55_SLAVE_SPMI_VGI_COEX, + SDX55_SLAVE_QDSS_STM, + SDX55_SLAVE_QPIC, + SDX55_SLAVE_OCIMEM, + SDX55_SLAVE_IPA_CFG, + SDX55_SLAVE_USB3_PHY_CFG, + SDX55_SLAVE_AOP, + SDX55_SLAVE_BLSP_1, + SDX55_SLAVE_USB3, + SDX55_SLAVE_CNOC_MSS, + SDX55_SLAVE_PCIE_PARF, + SDX55_SLAVE_ECC_CFG, + SDX55_SLAVE_APPSS, + SDX55_SLAVE_AUDIO, + SDX55_SLAVE_AOSS, + SDX55_SLAVE_PRNG, + SDX55_SLAVE_CRYPTO_0_CFG, + SDX55_SLAVE_TCU, + SDX55_SLAVE_CLK_CTL, + SDX55_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node qnm_ipa =3D { + .name =3D "qnm_ipa", + .id =3D SDX55_MASTER_IPA, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 27, + .links =3D { SDX55_SLAVE_SNOC_CFG, + SDX55_SLAVE_EMAC_CFG, + SDX55_SLAVE_USB3, + SDX55_SLAVE_AOSS, + SDX55_SLAVE_SPMI_FETCHER, + SDX55_SLAVE_QDSS_CFG, + SDX55_SLAVE_PDM, + SDX55_SLAVE_SNOC_MEM_NOC_GC, + SDX55_SLAVE_TCSR, + SDX55_SLAVE_CNOC_DDRSS, + SDX55_SLAVE_QDSS_STM, + SDX55_SLAVE_QPIC, + SDX55_SLAVE_OCIMEM, + SDX55_SLAVE_IPA_CFG, + SDX55_SLAVE_USB3_PHY_CFG, + SDX55_SLAVE_AOP, + SDX55_SLAVE_BLSP_1, + SDX55_SLAVE_SDCC_1, + SDX55_SLAVE_CNOC_MSS, + SDX55_SLAVE_PCIE_PARF, + SDX55_SLAVE_ECC_CFG, + SDX55_SLAVE_AUDIO, + SDX55_SLAVE_TLMM, + SDX55_SLAVE_PRNG, + SDX55_SLAVE_CRYPTO_0_CFG, + SDX55_SLAVE_CLK_CTL, + SDX55_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node qnm_memnoc =3D { + .name =3D "qnm_memnoc", + .id =3D SDX55_MASTER_MEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 29, + .links =3D { SDX55_SLAVE_SNOC_CFG, + SDX55_SLAVE_EMAC_CFG, + SDX55_SLAVE_USB3, + SDX55_SLAVE_TLMM, + SDX55_SLAVE_SPMI_FETCHER, + SDX55_SLAVE_QDSS_CFG, + SDX55_SLAVE_PDM, + SDX55_SLAVE_TCSR, + SDX55_SLAVE_CNOC_DDRSS, + SDX55_SLAVE_SPMI_VGI_COEX, + SDX55_SLAVE_QDSS_STM, + SDX55_SLAVE_QPIC, + SDX55_SLAVE_OCIMEM, + SDX55_SLAVE_IPA_CFG, + SDX55_SLAVE_USB3_PHY_CFG, + SDX55_SLAVE_AOP, + SDX55_SLAVE_BLSP_1, + SDX55_SLAVE_SDCC_1, + SDX55_SLAVE_CNOC_MSS, + SDX55_SLAVE_PCIE_PARF, + SDX55_SLAVE_ECC_CFG, + SDX55_SLAVE_APPSS, + SDX55_SLAVE_AUDIO, + SDX55_SLAVE_AOSS, + SDX55_SLAVE_PRNG, + SDX55_SLAVE_CRYPTO_0_CFG, + SDX55_SLAVE_TCU, + SDX55_SLAVE_CLK_CTL, + SDX55_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node qnm_memnoc_pcie =3D { + .name =3D "qnm_memnoc_pcie", + .id =3D SDX55_MASTER_MEM_NOC_PCIE_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDX55_SLAVE_PCIE_0 }, +}; + +static struct qcom_icc_node qxm_crypto =3D { + .name =3D "qxm_crypto", + .id =3D SDX55_MASTER_CRYPTO_CORE_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 3, + .links =3D { SDX55_SLAVE_AOSS, + SDX55_SLAVE_ANOC_SNOC, + SDX55_SLAVE_AOP + }, +}; + +static struct qcom_icc_node xm_emac =3D { + .name =3D "xm_emac", + .id =3D SDX55_MASTER_EMAC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDX55_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node xm_ipa2pcie_slv =3D { + .name =3D "xm_ipa2pcie_slv", + .id =3D SDX55_MASTER_IPA_PCIE, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDX55_SLAVE_PCIE_0 }, +}; + +static struct qcom_icc_node xm_pcie =3D { + .name =3D "xm_pcie", + .id =3D SDX55_MASTER_PCIE, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDX55_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr =3D { + .name =3D "xm_qdss_etr", + .id =3D SDX55_MASTER_QDSS_ETR, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 28, + .links =3D { SDX55_SLAVE_SNOC_CFG, + SDX55_SLAVE_EMAC_CFG, + SDX55_SLAVE_USB3, + SDX55_SLAVE_AOSS, + SDX55_SLAVE_SPMI_FETCHER, + SDX55_SLAVE_QDSS_CFG, + SDX55_SLAVE_PDM, + SDX55_SLAVE_SNOC_MEM_NOC_GC, + SDX55_SLAVE_TCSR, + SDX55_SLAVE_CNOC_DDRSS, + SDX55_SLAVE_SPMI_VGI_COEX, + SDX55_SLAVE_QPIC, + SDX55_SLAVE_OCIMEM, + SDX55_SLAVE_IPA_CFG, + SDX55_SLAVE_USB3_PHY_CFG, + SDX55_SLAVE_AOP, + SDX55_SLAVE_BLSP_1, + SDX55_SLAVE_SDCC_1, + SDX55_SLAVE_CNOC_MSS, + SDX55_SLAVE_PCIE_PARF, + SDX55_SLAVE_ECC_CFG, + SDX55_SLAVE_AUDIO, + SDX55_SLAVE_AOSS, + SDX55_SLAVE_PRNG, + SDX55_SLAVE_CRYPTO_0_CFG, + SDX55_SLAVE_TCU, + SDX55_SLAVE_CLK_CTL, + SDX55_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node xm_sdc1 =3D { + .name =3D "xm_sdc1", + .id =3D SDX55_MASTER_SDCC_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 5, + .links =3D { SDX55_SLAVE_AOSS, + SDX55_SLAVE_IPA_CFG, + SDX55_SLAVE_ANOC_SNOC, + SDX55_SLAVE_AOP, + SDX55_SLAVE_AUDIO + }, +}; + +static struct qcom_icc_node xm_usb3 =3D { + .name =3D "xm_usb3", + .id =3D SDX55_MASTER_USB3, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDX55_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .id =3D SDX55_SLAVE_EBI_CH0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .id =3D SDX55_SLAVE_LLCC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SDX55_SLAVE_EBI_CH0 }, +}; + +static struct qcom_icc_node qns_memnoc_snoc =3D { + .name =3D "qns_memnoc_snoc", + .id =3D SDX55_SLAVE_MEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDX55_MASTER_MEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qns_sys_pcie =3D { + .name =3D "qns_sys_pcie", + .id =3D SDX55_SLAVE_MEM_NOC_PCIE_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDX55_MASTER_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qhs_aop =3D { + .name =3D "qhs_aop", + .id =3D SDX55_SLAVE_AOP, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .id =3D SDX55_SLAVE_AOSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_apss =3D { + .name =3D "qhs_apss", + .id =3D SDX55_SLAVE_APPSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_audio =3D { + .name =3D "qhs_audio", + .id =3D SDX55_SLAVE_AUDIO, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_blsp1 =3D { + .name =3D "qhs_blsp1", + .id =3D SDX55_SLAVE_BLSP_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .id =3D SDX55_SLAVE_CLK_CTL, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg =3D { + .name =3D "qhs_crypto0_cfg", + .id =3D SDX55_SLAVE_CRYPTO_0_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg =3D { + .name =3D "qhs_ddrss_cfg", + .id =3D SDX55_SLAVE_CNOC_DDRSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ecc_cfg =3D { + .name =3D "qhs_ecc_cfg", + .id =3D SDX55_SLAVE_ECC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_emac_cfg =3D { + .name =3D "qhs_emac_cfg", + .id =3D SDX55_SLAVE_EMAC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .id =3D SDX55_SLAVE_IMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipa =3D { + .name =3D "qhs_ipa", + .id =3D SDX55_SLAVE_IPA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mss_cfg =3D { + .name =3D "qhs_mss_cfg", + .id =3D SDX55_SLAVE_CNOC_MSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie_parf =3D { + .name =3D "qhs_pcie_parf", + .id =3D SDX55_SLAVE_PCIE_PARF, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pdm =3D { + .name =3D "qhs_pdm", + .id =3D SDX55_SLAVE_PDM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_prng =3D { + .name =3D "qhs_prng", + .id =3D SDX55_SLAVE_PRNG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .id =3D SDX55_SLAVE_QDSS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qpic =3D { + .name =3D "qhs_qpic", + .id =3D SDX55_SLAVE_QPIC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc1 =3D { + .name =3D "qhs_sdc1", + .id =3D SDX55_SLAVE_SDCC_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg =3D { + .name =3D "qhs_snoc_cfg", + .id =3D SDX55_SLAVE_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDX55_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_spmi_fetcher =3D { + .name =3D "qhs_spmi_fetcher", + .id =3D SDX55_SLAVE_SPMI_FETCHER, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_spmi_vgi_coex =3D { + .name =3D "qhs_spmi_vgi_coex", + .id =3D SDX55_SLAVE_SPMI_VGI_COEX, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .id =3D SDX55_SLAVE_TCSR, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm =3D { + .name =3D "qhs_tlmm", + .id =3D SDX55_SLAVE_TLMM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3 =3D { + .name =3D "qhs_usb3", + .id =3D SDX55_SLAVE_USB3, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_phy =3D { + .name =3D "qhs_usb3_phy", + .id =3D SDX55_SLAVE_USB3_PHY_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_aggre_noc =3D { + .name =3D "qns_aggre_noc", + .id =3D SDX55_SLAVE_ANOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDX55_MASTER_ANOC_SNOC }, +}; + +static struct qcom_icc_node qns_snoc_memnoc =3D { + .name =3D "qns_snoc_memnoc", + .id =3D SDX55_SLAVE_SNOC_MEM_NOC_GC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDX55_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .id =3D SDX55_SLAVE_OCIMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node srvc_snoc =3D { + .name =3D "srvc_snoc", + .id =3D SDX55_SLAVE_SERVICE_SNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_pcie =3D { + .name =3D "xs_pcie", + .id =3D SDX55_SLAVE_PCIE_0, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .id =3D SDX55_SLAVE_QDSS_STM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .id =3D SDX55_SLAVE_TCU, + .channels =3D 1, + .buswidth =3D 8, +}; =20 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F420C001DC for ; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:39 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:09 +0200 Subject: [PATCH 10/53] interconnect: qcom: sdx65: Retire DEFINE_QNODE MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-10-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=20861; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Atb806ycN2p4ZV3kQEetNQMYYysNjcCZbT7AH3nl6w0=; b=h3fQTqSs52o/JOpIqVi3C5ad1i5Fhw2YHzPt9XKqy0iG4IfGtHdU4Bt3LSr8CtD4Uka0SKTn5 GYMw65afihsCsW9mJSeiqEPKxu3TN8C2hBy4r2sMh/6r5fK+5RAL8Ui X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sdx65.c | 643 ++++++++++++++++++++++++++++++++++= ---- 1 file changed, 588 insertions(+), 55 deletions(-) diff --git a/drivers/interconnect/qcom/sdx65.c b/drivers/interconnect/qcom/= sdx65.c index b16d31d53e9b..bebed036fe7a 100644 --- a/drivers/interconnect/qcom/sdx65.c +++ b/drivers/interconnect/qcom/sdx65.c @@ -14,61 +14,594 @@ #include "icc-rpmh.h" #include "sdx65.h" =20 -DEFINE_QNODE(llcc_mc, SDX65_MASTER_LLCC, 1, 4, SDX65_SLAVE_EBI1); -DEFINE_QNODE(acm_tcu, SDX65_MASTER_TCU_0, 1, 8, SDX65_SLAVE_LLCC, SDX65_SL= AVE_MEM_NOC_SNOC, SDX65_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SDX65_MASTER_SNOC_GC_MEM_NOC, 1, 16, SDX65_SLAVE= _LLCC); -DEFINE_QNODE(xm_apps_rdwr, SDX65_MASTER_APPSS_PROC, 1, 16, SDX65_SLAVE_LLC= C, SDX65_SLAVE_MEM_NOC_SNOC, SDX65_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qhm_audio, SDX65_MASTER_AUDIO, 1, 4, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(qhm_blsp1, SDX65_MASTER_BLSP_1, 1, 4, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(qhm_qdss_bam, SDX65_MASTER_QDSS_BAM, 1, 4, SDX65_SLAVE_AOSS, = SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRY= PTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CF= G, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_= SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_= SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_S= PMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_S= LAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLA= VE_TCU); -DEFINE_QNODE(qhm_qpic, SDX65_MASTER_QPIC, 1, 4, SDX65_SLAVE_AOSS, SDX65_SL= AVE_AUDIO, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(qhm_snoc_cfg, SDX65_MASTER_SNOC_CFG, 1, 4, SDX65_SLAVE_SERVIC= E_SNOC); -DEFINE_QNODE(qhm_spmi_fetcher1, SDX65_MASTER_SPMI_FETCHER, 1, 4, SDX65_SLA= VE_AOSS, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(qnm_aggre_noc, SDX65_MASTER_ANOC_SNOC, 1, 8, SDX65_SLAVE_AOSS= , SDX65_SLAVE_APPSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK= _CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG= , SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SL= AVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX= 65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_F= ETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX6= 5_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_= SLAVE_IMEM, SDX65_SLAVE_PCIE_0, SDX65_SLAVE_QDSS_STM, SDX65_SLAVE_TCU); -DEFINE_QNODE(qnm_ipa, SDX65_MASTER_IPA, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAV= E_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG,= SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_S= LAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM,= SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC= _1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_TCSR, SDX65= _SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_M= EM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_PCIE_0, SDX65_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_memnoc, SDX65_MASTER_MEM_NOC_SNOC, 1, 8, SDX65_SLAVE_AOSS= , SDX65_SLAVE_APPSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK= _CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG= , SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SL= AVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX= 65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_F= ETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX6= 5_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_IMEM, SDX65_SLAVE_QDSS_= STM, SDX65_SLAVE_TCU); -DEFINE_QNODE(qnm_memnoc_pcie, SDX65_MASTER_MEM_NOC_PCIE_SNOC, 1, 8, SDX65_= SLAVE_PCIE_0); -DEFINE_QNODE(qxm_crypto, SDX65_MASTER_CRYPTO, 1, 8, SDX65_SLAVE_AOSS, SDX6= 5_SLAVE_ANOC_SNOC); -DEFINE_QNODE(xm_ipa2pcie_slv, SDX65_MASTER_IPA_PCIE, 1, 8, SDX65_SLAVE_PCI= E_0); -DEFINE_QNODE(xm_pcie, SDX65_MASTER_PCIE_0, 1, 8, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(xm_qdss_etr, SDX65_MASTER_QDSS_ETR, 1, 8, SDX65_SLAVE_AOSS, S= DX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYP= TO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG= , SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_S= LAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_S= LAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SP= MI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SL= AVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAV= E_TCU); -DEFINE_QNODE(xm_sdc1, SDX65_MASTER_SDCC_1, 1, 8, SDX65_SLAVE_AOSS, SDX65_S= LAVE_AUDIO, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(xm_usb3, SDX65_MASTER_USB3, 1, 8, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(ebi, SDX65_SLAVE_EBI1, 1, 4); -DEFINE_QNODE(qns_llcc, SDX65_SLAVE_LLCC, 1, 16, SDX65_MASTER_LLCC); -DEFINE_QNODE(qns_memnoc_snoc, SDX65_SLAVE_MEM_NOC_SNOC, 1, 8, SDX65_MASTER= _MEM_NOC_SNOC); -DEFINE_QNODE(qns_sys_pcie, SDX65_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SDX65_MAST= ER_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qhs_aoss, SDX65_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_apss, SDX65_SLAVE_APPSS, 1, 4); -DEFINE_QNODE(qhs_audio, SDX65_SLAVE_AUDIO, 1, 4); -DEFINE_QNODE(qhs_blsp1, SDX65_SLAVE_BLSP_1, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SDX65_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SDX65_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_ddrss_cfg, SDX65_SLAVE_CNOC_DDRSS, 1, 4); -DEFINE_QNODE(qhs_ecc_cfg, SDX65_SLAVE_ECC_CFG, 1, 4); -DEFINE_QNODE(qhs_imem_cfg, SDX65_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SDX65_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mss_cfg, SDX65_SLAVE_CNOC_MSS, 1, 4); -DEFINE_QNODE(qhs_pcie_parf, SDX65_SLAVE_PCIE_PARF, 1, 4); -DEFINE_QNODE(qhs_pdm, SDX65_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_prng, SDX65_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SDX65_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qpic, SDX65_SLAVE_QPIC, 1, 4); -DEFINE_QNODE(qhs_sdc1, SDX65_SLAVE_SDCC_1, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SDX65_SLAVE_SNOC_CFG, 1, 4, SDX65_MASTER_SNOC_C= FG); -DEFINE_QNODE(qhs_spmi_fetcher, SDX65_SLAVE_SPMI_FETCHER, 1, 4); -DEFINE_QNODE(qhs_spmi_vgi_coex, SDX65_SLAVE_SPMI_VGI_COEX, 1, 4); -DEFINE_QNODE(qhs_tcsr, SDX65_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm, SDX65_SLAVE_TLMM, 1, 4); -DEFINE_QNODE(qhs_usb3, SDX65_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_usb3_phy, SDX65_SLAVE_USB3_PHY_CFG, 1, 4); -DEFINE_QNODE(qns_aggre_noc, SDX65_SLAVE_ANOC_SNOC, 1, 8, SDX65_MASTER_ANOC= _SNOC); -DEFINE_QNODE(qns_snoc_memnoc, SDX65_SLAVE_SNOC_MEM_NOC_GC, 1, 16, SDX65_MA= STER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qxs_imem, SDX65_SLAVE_IMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SDX65_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_pcie, SDX65_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(xs_qdss_stm, SDX65_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SDX65_SLAVE_TCU, 1, 8); +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .id =3D SDX65_MASTER_LLCC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDX65_SLAVE_EBI1 }, +}; + +static struct qcom_icc_node acm_tcu =3D { + .name =3D "acm_tcu", + .id =3D SDX65_MASTER_TCU_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 3, + .links =3D { SDX65_SLAVE_LLCC, + SDX65_SLAVE_MEM_NOC_SNOC, + SDX65_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc =3D { + .name =3D "qnm_snoc_gc", + .id =3D SDX65_MASTER_SNOC_GC_MEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SDX65_SLAVE_LLCC }, +}; + +static struct qcom_icc_node xm_apps_rdwr =3D { + .name =3D "xm_apps_rdwr", + .id =3D SDX65_MASTER_APPSS_PROC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 3, + .links =3D { SDX65_SLAVE_LLCC, + SDX65_SLAVE_MEM_NOC_SNOC, + SDX65_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qhm_audio =3D { + .name =3D "qhm_audio", + .id =3D SDX65_MASTER_AUDIO, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDX65_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node qhm_blsp1 =3D { + .name =3D "qhm_blsp1", + .id =3D SDX65_MASTER_BLSP_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDX65_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam =3D { + .name =3D "qhm_qdss_bam", + .id =3D SDX65_MASTER_QDSS_BAM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 26, + .links =3D { SDX65_SLAVE_AOSS, + SDX65_SLAVE_AUDIO, + SDX65_SLAVE_BLSP_1, + SDX65_SLAVE_CLK_CTL, + SDX65_SLAVE_CRYPTO_0_CFG, + SDX65_SLAVE_CNOC_DDRSS, + SDX65_SLAVE_ECC_CFG, + SDX65_SLAVE_IMEM_CFG, + SDX65_SLAVE_IPA_CFG, + SDX65_SLAVE_CNOC_MSS, + SDX65_SLAVE_PCIE_PARF, + SDX65_SLAVE_PDM, + SDX65_SLAVE_PRNG, + SDX65_SLAVE_QDSS_CFG, + SDX65_SLAVE_QPIC, + SDX65_SLAVE_SDCC_1, + SDX65_SLAVE_SNOC_CFG, + SDX65_SLAVE_SPMI_FETCHER, + SDX65_SLAVE_SPMI_VGI_COEX, + SDX65_SLAVE_TCSR, + SDX65_SLAVE_TLMM, + SDX65_SLAVE_USB3, + SDX65_SLAVE_USB3_PHY_CFG, + SDX65_SLAVE_SNOC_MEM_NOC_GC, + SDX65_SLAVE_IMEM, + SDX65_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qhm_qpic =3D { + .name =3D "qhm_qpic", + .id =3D SDX65_MASTER_QPIC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 4, + .links =3D { SDX65_SLAVE_AOSS, + SDX65_SLAVE_AUDIO, + SDX65_SLAVE_IPA_CFG, + SDX65_SLAVE_ANOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_snoc_cfg =3D { + .name =3D "qhm_snoc_cfg", + .id =3D SDX65_MASTER_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDX65_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qhm_spmi_fetcher1 =3D { + .name =3D "qhm_spmi_fetcher1", + .id =3D SDX65_MASTER_SPMI_FETCHER, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .links =3D { SDX65_SLAVE_AOSS, + SDX65_SLAVE_ANOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_aggre_noc =3D { + .name =3D "qnm_aggre_noc", + .id =3D SDX65_MASTER_ANOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 29, + .links =3D { SDX65_SLAVE_AOSS, + SDX65_SLAVE_APPSS, + SDX65_SLAVE_AUDIO, + SDX65_SLAVE_BLSP_1, + SDX65_SLAVE_CLK_CTL, + SDX65_SLAVE_CRYPTO_0_CFG, + SDX65_SLAVE_CNOC_DDRSS, + SDX65_SLAVE_ECC_CFG, + SDX65_SLAVE_IMEM_CFG, + SDX65_SLAVE_IPA_CFG, + SDX65_SLAVE_CNOC_MSS, + SDX65_SLAVE_PCIE_PARF, + SDX65_SLAVE_PDM, + SDX65_SLAVE_PRNG, + SDX65_SLAVE_QDSS_CFG, + SDX65_SLAVE_QPIC, + SDX65_SLAVE_SDCC_1, + SDX65_SLAVE_SNOC_CFG, + SDX65_SLAVE_SPMI_FETCHER, + SDX65_SLAVE_SPMI_VGI_COEX, + SDX65_SLAVE_TCSR, + SDX65_SLAVE_TLMM, + SDX65_SLAVE_USB3, + SDX65_SLAVE_USB3_PHY_CFG, + SDX65_SLAVE_SNOC_MEM_NOC_GC, + SDX65_SLAVE_IMEM, + SDX65_SLAVE_PCIE_0, + SDX65_SLAVE_QDSS_STM, + SDX65_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_ipa =3D { + .name =3D "qnm_ipa", + .id =3D SDX65_MASTER_IPA, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 26, + .links =3D { SDX65_SLAVE_AOSS, + SDX65_SLAVE_AUDIO, + SDX65_SLAVE_BLSP_1, + SDX65_SLAVE_CLK_CTL, + SDX65_SLAVE_CRYPTO_0_CFG, + SDX65_SLAVE_CNOC_DDRSS, + SDX65_SLAVE_ECC_CFG, + SDX65_SLAVE_IMEM_CFG, + SDX65_SLAVE_IPA_CFG, + SDX65_SLAVE_CNOC_MSS, + SDX65_SLAVE_PCIE_PARF, + SDX65_SLAVE_PDM, + SDX65_SLAVE_PRNG, + SDX65_SLAVE_QDSS_CFG, + SDX65_SLAVE_QPIC, + SDX65_SLAVE_SDCC_1, + SDX65_SLAVE_SNOC_CFG, + SDX65_SLAVE_SPMI_FETCHER, + SDX65_SLAVE_TCSR, + SDX65_SLAVE_TLMM, + SDX65_SLAVE_USB3, + SDX65_SLAVE_USB3_PHY_CFG, + SDX65_SLAVE_SNOC_MEM_NOC_GC, + SDX65_SLAVE_IMEM, + SDX65_SLAVE_PCIE_0, + SDX65_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_memnoc =3D { + .name =3D "qnm_memnoc", + .id =3D SDX65_MASTER_MEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 27, + .links =3D { SDX65_SLAVE_AOSS, + SDX65_SLAVE_APPSS, + SDX65_SLAVE_AUDIO, + SDX65_SLAVE_BLSP_1, + SDX65_SLAVE_CLK_CTL, + SDX65_SLAVE_CRYPTO_0_CFG, + SDX65_SLAVE_CNOC_DDRSS, + SDX65_SLAVE_ECC_CFG, + SDX65_SLAVE_IMEM_CFG, + SDX65_SLAVE_IPA_CFG, + SDX65_SLAVE_CNOC_MSS, + SDX65_SLAVE_PCIE_PARF, + SDX65_SLAVE_PDM, + SDX65_SLAVE_PRNG, + SDX65_SLAVE_QDSS_CFG, + SDX65_SLAVE_QPIC, + SDX65_SLAVE_SDCC_1, + SDX65_SLAVE_SNOC_CFG, + SDX65_SLAVE_SPMI_FETCHER, + SDX65_SLAVE_SPMI_VGI_COEX, + SDX65_SLAVE_TCSR, + SDX65_SLAVE_TLMM, + SDX65_SLAVE_USB3, + SDX65_SLAVE_USB3_PHY_CFG, + SDX65_SLAVE_IMEM, + SDX65_SLAVE_QDSS_STM, + SDX65_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_memnoc_pcie =3D { + .name =3D "qnm_memnoc_pcie", + .id =3D SDX65_MASTER_MEM_NOC_PCIE_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDX65_SLAVE_PCIE_0 }, +}; + +static struct qcom_icc_node qxm_crypto =3D { + .name =3D "qxm_crypto", + .id =3D SDX65_MASTER_CRYPTO, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SDX65_SLAVE_AOSS, + SDX65_SLAVE_ANOC_SNOC + }, +}; + +static struct qcom_icc_node xm_ipa2pcie_slv =3D { + .name =3D "xm_ipa2pcie_slv", + .id =3D SDX65_MASTER_IPA_PCIE, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDX65_SLAVE_PCIE_0 }, +}; + +static struct qcom_icc_node xm_pcie =3D { + .name =3D "xm_pcie", + .id =3D SDX65_MASTER_PCIE_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDX65_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr =3D { + .name =3D "xm_qdss_etr", + .id =3D SDX65_MASTER_QDSS_ETR, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 26, + .links =3D { SDX65_SLAVE_AOSS, + SDX65_SLAVE_AUDIO, + SDX65_SLAVE_BLSP_1, + SDX65_SLAVE_CLK_CTL, + SDX65_SLAVE_CRYPTO_0_CFG, + SDX65_SLAVE_CNOC_DDRSS, + SDX65_SLAVE_ECC_CFG, + SDX65_SLAVE_IMEM_CFG, + SDX65_SLAVE_IPA_CFG, + SDX65_SLAVE_CNOC_MSS, + SDX65_SLAVE_PCIE_PARF, + SDX65_SLAVE_PDM, + SDX65_SLAVE_PRNG, + SDX65_SLAVE_QDSS_CFG, + SDX65_SLAVE_QPIC, + SDX65_SLAVE_SDCC_1, + SDX65_SLAVE_SNOC_CFG, + SDX65_SLAVE_SPMI_FETCHER, + SDX65_SLAVE_SPMI_VGI_COEX, + SDX65_SLAVE_TCSR, + SDX65_SLAVE_TLMM, + SDX65_SLAVE_USB3, + SDX65_SLAVE_USB3_PHY_CFG, + SDX65_SLAVE_SNOC_MEM_NOC_GC, + SDX65_SLAVE_IMEM, + SDX65_SLAVE_TCU + }, +}; + +static struct qcom_icc_node xm_sdc1 =3D { + .name =3D "xm_sdc1", + .id =3D SDX65_MASTER_SDCC_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 4, + .links =3D { SDX65_SLAVE_AOSS, + SDX65_SLAVE_AUDIO, + SDX65_SLAVE_IPA_CFG, + SDX65_SLAVE_ANOC_SNOC + }, +}; + +static struct qcom_icc_node xm_usb3 =3D { + .name =3D "xm_usb3", + .id =3D SDX65_MASTER_USB3, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDX65_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .id =3D SDX65_SLAVE_EBI1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .id =3D SDX65_SLAVE_LLCC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SDX65_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_memnoc_snoc =3D { + .name =3D "qns_memnoc_snoc", + .id =3D SDX65_SLAVE_MEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDX65_MASTER_MEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qns_sys_pcie =3D { + .name =3D "qns_sys_pcie", + .id =3D SDX65_SLAVE_MEM_NOC_PCIE_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDX65_MASTER_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .id =3D SDX65_SLAVE_AOSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_apss =3D { + .name =3D "qhs_apss", + .id =3D SDX65_SLAVE_APPSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_audio =3D { + .name =3D "qhs_audio", + .id =3D SDX65_SLAVE_AUDIO, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_blsp1 =3D { + .name =3D "qhs_blsp1", + .id =3D SDX65_SLAVE_BLSP_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .id =3D SDX65_SLAVE_CLK_CTL, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg =3D { + .name =3D "qhs_crypto0_cfg", + .id =3D SDX65_SLAVE_CRYPTO_0_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg =3D { + .name =3D "qhs_ddrss_cfg", + .id =3D SDX65_SLAVE_CNOC_DDRSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ecc_cfg =3D { + .name =3D "qhs_ecc_cfg", + .id =3D SDX65_SLAVE_ECC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .id =3D SDX65_SLAVE_IMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipa =3D { + .name =3D "qhs_ipa", + .id =3D SDX65_SLAVE_IPA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mss_cfg =3D { + .name =3D "qhs_mss_cfg", + .id =3D SDX65_SLAVE_CNOC_MSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie_parf =3D { + .name =3D "qhs_pcie_parf", + .id =3D SDX65_SLAVE_PCIE_PARF, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pdm =3D { + .name =3D "qhs_pdm", + .id =3D SDX65_SLAVE_PDM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_prng =3D { + .name =3D "qhs_prng", + .id =3D SDX65_SLAVE_PRNG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .id =3D SDX65_SLAVE_QDSS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qpic =3D { + .name =3D "qhs_qpic", + .id =3D SDX65_SLAVE_QPIC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc1 =3D { + .name =3D "qhs_sdc1", + .id =3D SDX65_SLAVE_SDCC_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg =3D { + .name =3D "qhs_snoc_cfg", + .id =3D SDX65_SLAVE_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SDX65_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_spmi_fetcher =3D { + .name =3D "qhs_spmi_fetcher", + .id =3D SDX65_SLAVE_SPMI_FETCHER, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_spmi_vgi_coex =3D { + .name =3D "qhs_spmi_vgi_coex", + .id =3D SDX65_SLAVE_SPMI_VGI_COEX, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .id =3D SDX65_SLAVE_TCSR, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm =3D { + .name =3D "qhs_tlmm", + .id =3D SDX65_SLAVE_TLMM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3 =3D { + .name =3D "qhs_usb3", + .id =3D SDX65_SLAVE_USB3, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_phy =3D { + .name =3D "qhs_usb3_phy", + .id =3D SDX65_SLAVE_USB3_PHY_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_aggre_noc =3D { + .name =3D "qns_aggre_noc", + .id =3D SDX65_SLAVE_ANOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SDX65_MASTER_ANOC_SNOC }, +}; + +static struct qcom_icc_node qns_snoc_memnoc =3D { + .name =3D "qns_snoc_memnoc", + .id =3D SDX65_SLAVE_SNOC_MEM_NOC_GC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SDX65_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .id =3D SDX65_SLAVE_IMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node srvc_snoc =3D { + .name =3D "srvc_snoc", + .id =3D SDX65_SLAVE_SERVICE_SNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_pcie =3D { + .name =3D "xs_pcie", + .id =3D SDX65_SLAVE_PCIE_0, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .id =3D SDX65_SLAVE_QDSS_STM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .id =3D SDX65_SLAVE_TCU, + .channels =3D 1, + .buswidth =3D 8, +}; =20 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BA0AEB64DC for ; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:40 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:10 +0200 Subject: [PATCH 11/53] interconnect: qcom: sm6350: Retire DEFINE_QNODE MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-11-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=39658; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Vn2Dl/Zh9To6jL368CWOwQ/9G+yXzmEWxN811xRUl7w=; b=jTY8FGQBDJ6+bvx3jOIgPc97Y9WS7ggW4CD1BvtS0I8w0tjtiXJhYoG02YfJRyoBasAbPSjIk wj26hmOA5EMAoSWzmGloh/1ysJN/Vn2S4McKWsOLHlLKBXf5aaL/i89 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm6350.c | 1273 ++++++++++++++++++++++++++++++++= ---- 1 file changed, 1146 insertions(+), 127 deletions(-) diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom= /sm6350.c index a3d46e59444e..7421eb4cd520 100644 --- a/drivers/interconnect/qcom/sm6350.c +++ b/drivers/interconnect/qcom/sm6350.c @@ -14,133 +14,1152 @@ #include "icc-rpmh.h" #include "sm6350.h" =20 -DEFINE_QNODE(qhm_a1noc_cfg, SM6350_MASTER_A1NOC_CFG, 1, 4, SM6350_SLAVE_SE= RVICE_A1NOC); -DEFINE_QNODE(qhm_qup_0, SM6350_MASTER_QUP_0, 1, 4, SM6350_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_emmc, SM6350_MASTER_EMMC, 1, 8, SM6350_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_ufs_mem, SM6350_MASTER_UFS_MEM, 1, 8, SM6350_A1NOC_SNOC_SL= V); -DEFINE_QNODE(qhm_a2noc_cfg, SM6350_MASTER_A2NOC_CFG, 1, 4, SM6350_SLAVE_SE= RVICE_A2NOC); -DEFINE_QNODE(qhm_qdss_bam, SM6350_MASTER_QDSS_BAM, 1, 4, SM6350_A2NOC_SNOC= _SLV); -DEFINE_QNODE(qhm_qup_1, SM6350_MASTER_QUP_1, 1, 4, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_crypto, SM6350_MASTER_CRYPTO_CORE_0, 1, 8, SM6350_A2NOC_S= NOC_SLV); -DEFINE_QNODE(qxm_ipa, SM6350_MASTER_IPA, 1, 8, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_qdss_etr, SM6350_MASTER_QDSS_ETR, 1, 8, SM6350_A2NOC_SNOC_= SLV); -DEFINE_QNODE(xm_sdc2, SM6350_MASTER_SDCC_2, 1, 8, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_usb3_0, SM6350_MASTER_USB3, 1, 8, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SM6350_MASTER_CAMNOC_HF0_UNCOMP, 2, 32= , SM6350_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_icp_uncomp, SM6350_MASTER_CAMNOC_ICP_UNCOMP, 1, 32= , SM6350_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_sf_uncomp, SM6350_MASTER_CAMNOC_SF_UNCOMP, 1, 32, = SM6350_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qup0_core_master, SM6350_MASTER_QUP_CORE_0, 1, 4, SM6350_SLAV= E_QUP_CORE_0); -DEFINE_QNODE(qup1_core_master, SM6350_MASTER_QUP_CORE_1, 1, 4, SM6350_SLAV= E_QUP_CORE_1); -DEFINE_QNODE(qnm_npu, SM6350_MASTER_NPU, 2, 32, SM6350_SLAVE_CDSP_GEM_NOC); -DEFINE_QNODE(qxm_npu_dsp, SM6350_MASTER_NPU_PROC, 1, 8, SM6350_SLAVE_CDSP_= GEM_NOC); -DEFINE_QNODE(qnm_snoc, SM6350_SNOC_CNOC_MAS, 1, 8, SM6350_SLAVE_CAMERA_CFG= , SM6350_SLAVE_SDCC_2, SM6350_SLAVE_CNOC_MNOC_CFG, SM6350_SLAVE_UFS_MEM_CFG= , SM6350_SLAVE_QM_CFG, SM6350_SLAVE_SNOC_CFG, SM6350_SLAVE_QM_MPU_CFG, SM63= 50_SLAVE_GLM, SM6350_SLAVE_PDM, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, SM635= 0_SLAVE_A2NOC_CFG, SM6350_SLAVE_QDSS_CFG, SM6350_SLAVE_VSENSE_CTRL_CFG, SM6= 350_SLAVE_CAMERA_RT_THROTTLE_CFG, SM6350_SLAVE_DISPLAY_CFG, SM6350_SLAVE_TC= SR, SM6350_SLAVE_DCC_CFG, SM6350_SLAVE_CNOC_DDRSS, SM6350_SLAVE_DISPLAY_THR= OTTLE_CFG, SM6350_SLAVE_NPU_CFG, SM6350_SLAVE_AHB2PHY, SM6350_SLAVE_GRAPHIC= S_3D_CFG, SM6350_SLAVE_BOOT_ROM, SM6350_SLAVE_VENUS_CFG, SM6350_SLAVE_IPA_C= FG, SM6350_SLAVE_SECURITY, SM6350_SLAVE_IMEM_CFG, SM6350_SLAVE_CNOC_MSS, SM= 6350_SLAVE_SERVICE_CNOC, SM6350_SLAVE_USB3, SM6350_SLAVE_VENUS_THROTTLE_CFG= , SM6350_SLAVE_RBCPR_CX_CFG, SM6350_SLAVE_A1NOC_CFG, SM6350_SLAVE_AOSS, SM6= 350_SLAVE_PRNG, SM6350_SLAVE_EMMC_CFG, SM6350_SLAVE_CRYPTO_0_CFG, SM6350_SL= AVE_PIMEM_CFG, SM6350_S LAVE_RBCPR_MX_CFG, SM6350_SLAVE_QUP_0, SM6350_SLAVE_QUP_1, SM6350_SLAVE_CL= K_CTL); -DEFINE_QNODE(xm_qdss_dap, SM6350_MASTER_QDSS_DAP, 1, 8, SM6350_SLAVE_CAMER= A_CFG, SM6350_SLAVE_SDCC_2, SM6350_SLAVE_CNOC_MNOC_CFG, SM6350_SLAVE_UFS_ME= M_CFG, SM6350_SLAVE_QM_CFG, SM6350_SLAVE_SNOC_CFG, SM6350_SLAVE_QM_MPU_CFG,= SM6350_SLAVE_GLM, SM6350_SLAVE_PDM, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, = SM6350_SLAVE_A2NOC_CFG, SM6350_SLAVE_QDSS_CFG, SM6350_SLAVE_VSENSE_CTRL_CFG= , SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, SM6350_SLAVE_DISPLAY_CFG, SM6350_SLA= VE_TCSR, SM6350_SLAVE_DCC_CFG, SM6350_SLAVE_CNOC_DDRSS, SM6350_SLAVE_DISPLA= Y_THROTTLE_CFG, SM6350_SLAVE_NPU_CFG, SM6350_SLAVE_AHB2PHY, SM6350_SLAVE_GR= APHICS_3D_CFG, SM6350_SLAVE_BOOT_ROM, SM6350_SLAVE_VENUS_CFG, SM6350_SLAVE_= IPA_CFG, SM6350_SLAVE_SECURITY, SM6350_SLAVE_IMEM_CFG, SM6350_SLAVE_CNOC_MS= S, SM6350_SLAVE_SERVICE_CNOC, SM6350_SLAVE_USB3, SM6350_SLAVE_VENUS_THROTTL= E_CFG, SM6350_SLAVE_RBCPR_CX_CFG, SM6350_SLAVE_A1NOC_CFG, SM6350_SLAVE_AOSS= , SM6350_SLAVE_PRNG, SM6350_SLAVE_EMMC_CFG, SM6350_SLAVE_CRYPTO_0_CFG, SM63= 50_SLAVE_PIMEM_CFG, SM6 350_SLAVE_RBCPR_MX_CFG, SM6350_SLAVE_QUP_0, SM6350_SLAVE_QUP_1, SM6350_SLA= VE_CLK_CTL); -DEFINE_QNODE(qhm_cnoc_dc_noc, SM6350_MASTER_CNOC_DC_NOC, 1, 4, SM6350_SLAV= E_LLCC_CFG, SM6350_SLAVE_GEM_NOC_CFG); -DEFINE_QNODE(acm_apps, SM6350_MASTER_AMPSS_M0, 1, 16, SM6350_SLAVE_LLCC, S= M6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(acm_sys_tcu, SM6350_MASTER_SYS_TCU, 1, 8, SM6350_SLAVE_LLCC, = SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qhm_gemnoc_cfg, SM6350_MASTER_GEM_NOC_CFG, 1, 4, SM6350_SLAVE= _MCDMA_MS_MPU_CFG, SM6350_SLAVE_SERVICE_GEM_NOC, SM6350_SLAVE_MSS_PROC_MS_M= PU_CFG); -DEFINE_QNODE(qnm_cmpnoc, SM6350_MASTER_COMPUTE_NOC, 1, 32, SM6350_SLAVE_LL= CC, SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_mnoc_hf, SM6350_MASTER_MNOC_HF_MEM_NOC, 1, 32, SM6350_SLA= VE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_mnoc_sf, SM6350_MASTER_MNOC_SF_MEM_NOC, 1, 32, SM6350_SLA= VE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SM6350_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM6350_SLAV= E_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SM6350_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM6350_SLA= VE_LLCC); -DEFINE_QNODE(qxm_gpu, SM6350_MASTER_GRAPHICS_3D, 2, 32, SM6350_SLAVE_LLCC,= SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(llcc_mc, SM6350_MASTER_LLCC, 2, 4, SM6350_SLAVE_EBI_CH0); -DEFINE_QNODE(qhm_mnoc_cfg, SM6350_MASTER_CNOC_MNOC_CFG, 1, 4, SM6350_SLAVE= _SERVICE_MNOC); -DEFINE_QNODE(qnm_video0, SM6350_MASTER_VIDEO_P0, 1, 32, SM6350_SLAVE_MNOC_= SF_MEM_NOC); -DEFINE_QNODE(qnm_video_cvp, SM6350_MASTER_VIDEO_PROC, 1, 8, SM6350_SLAVE_M= NOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_hf, SM6350_MASTER_CAMNOC_HF, 2, 32, SM6350_SLAVE_M= NOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_icp, SM6350_MASTER_CAMNOC_ICP, 1, 8, SM6350_SLAVE_= MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_sf, SM6350_MASTER_CAMNOC_SF, 1, 32, SM6350_SLAVE_M= NOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SM6350_MASTER_MDP_PORT0, 1, 32, SM6350_SLAVE_MNOC_H= F_MEM_NOC); -DEFINE_QNODE(amm_npu_sys, SM6350_MASTER_NPU_SYS, 2, 32, SM6350_SLAVE_NPU_C= OMPUTE_NOC); -DEFINE_QNODE(qhm_npu_cfg, SM6350_MASTER_NPU_NOC_CFG, 1, 4, SM6350_SLAVE_SE= RVICE_NPU_NOC, SM6350_SLAVE_ISENSE_CFG, SM6350_SLAVE_NPU_LLM_CFG, SM6350_SL= AVE_NPU_INT_DMA_BWMON_CFG, SM6350_SLAVE_NPU_CP, SM6350_SLAVE_NPU_TCM, SM635= 0_SLAVE_NPU_CAL_DP0, SM6350_SLAVE_NPU_DPM); -DEFINE_QNODE(qhm_snoc_cfg, SM6350_MASTER_SNOC_CFG, 1, 4, SM6350_SLAVE_SERV= ICE_SNOC); -DEFINE_QNODE(qnm_aggre1_noc, SM6350_A1NOC_SNOC_MAS, 1, 16, SM6350_SLAVE_SN= OC_GEM_NOC_SF, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS,= SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_aggre2_noc, SM6350_A2NOC_SNOC_MAS, 1, 16, SM6350_SLAVE_SN= OC_GEM_NOC_SF, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS,= SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_TCU, SM6350_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_gemnoc, SM6350_MASTER_GEM_NOC_SNOC, 1, 8, SM6350_SLAVE_PI= MEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_= SLAVE_TCU, SM6350_SLAVE_QDSS_STM); -DEFINE_QNODE(qxm_pimem, SM6350_MASTER_PIMEM, 1, 8, SM6350_SLAVE_SNOC_GEM_N= OC_GC, SM6350_SLAVE_OCIMEM); -DEFINE_QNODE(xm_gic, SM6350_MASTER_GIC, 1, 8, SM6350_SLAVE_SNOC_GEM_NOC_GC= ); -DEFINE_QNODE(qns_a1noc_snoc, SM6350_A1NOC_SNOC_SLV, 1, 16, SM6350_A1NOC_SN= OC_MAS); -DEFINE_QNODE(srvc_aggre1_noc, SM6350_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(qns_a2noc_snoc, SM6350_A2NOC_SNOC_SLV, 1, 16, SM6350_A2NOC_SN= OC_MAS); -DEFINE_QNODE(srvc_aggre2_noc, SM6350_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qns_camnoc_uncomp, SM6350_SLAVE_CAMNOC_UNCOMP, 1, 32); -DEFINE_QNODE(qup0_core_slave, SM6350_SLAVE_QUP_CORE_0, 1, 4); -DEFINE_QNODE(qup1_core_slave, SM6350_SLAVE_QUP_CORE_1, 1, 4); -DEFINE_QNODE(qns_cdsp_gemnoc, SM6350_SLAVE_CDSP_GEM_NOC, 1, 32, SM6350_MAS= TER_COMPUTE_NOC); -DEFINE_QNODE(qhs_a1_noc_cfg, SM6350_SLAVE_A1NOC_CFG, 1, 4, SM6350_MASTER_A= 1NOC_CFG); -DEFINE_QNODE(qhs_a2_noc_cfg, SM6350_SLAVE_A2NOC_CFG, 1, 4, SM6350_MASTER_A= 2NOC_CFG); -DEFINE_QNODE(qhs_ahb2phy0, SM6350_SLAVE_AHB2PHY, 1, 4); -DEFINE_QNODE(qhs_ahb2phy2, SM6350_SLAVE_AHB2PHY_2, 1, 4); -DEFINE_QNODE(qhs_aoss, SM6350_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_boot_rom, SM6350_SLAVE_BOOT_ROM, 1, 4); -DEFINE_QNODE(qhs_camera_cfg, SM6350_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_camera_nrt_thrott_cfg, SM6350_SLAVE_CAMERA_NRT_THROTTLE_C= FG, 1, 4); -DEFINE_QNODE(qhs_camera_rt_throttle_cfg, SM6350_SLAVE_CAMERA_RT_THROTTLE_C= FG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SM6350_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SM6350_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mx, SM6350_SLAVE_RBCPR_MX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SM6350_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_dcc_cfg, SM6350_SLAVE_DCC_CFG, 1, 4); -DEFINE_QNODE(qhs_ddrss_cfg, SM6350_SLAVE_CNOC_DDRSS, 1, 4, SM6350_MASTER_C= NOC_DC_NOC); -DEFINE_QNODE(qhs_display_cfg, SM6350_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_display_throttle_cfg, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, = 1, 4); -DEFINE_QNODE(qhs_emmc_cfg, SM6350_SLAVE_EMMC_CFG, 1, 4); -DEFINE_QNODE(qhs_glm, SM6350_SLAVE_GLM, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SM6350_SLAVE_GRAPHICS_3D_CFG, 1, 8); -DEFINE_QNODE(qhs_imem_cfg, SM6350_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SM6350_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mnoc_cfg, SM6350_SLAVE_CNOC_MNOC_CFG, 1, 4, SM6350_MASTER= _CNOC_MNOC_CFG); -DEFINE_QNODE(qhs_mss_cfg, SM6350_SLAVE_CNOC_MSS, 1, 4); -DEFINE_QNODE(qhs_npu_cfg, SM6350_SLAVE_NPU_CFG, 1, 4, SM6350_MASTER_NPU_NO= C_CFG); -DEFINE_QNODE(qhs_pdm, SM6350_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SM6350_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_prng, SM6350_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SM6350_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qm_cfg, SM6350_SLAVE_QM_CFG, 1, 4); -DEFINE_QNODE(qhs_qm_mpu_cfg, SM6350_SLAVE_QM_MPU_CFG, 1, 4); -DEFINE_QNODE(qhs_qup0, SM6350_SLAVE_QUP_0, 1, 4); -DEFINE_QNODE(qhs_qup1, SM6350_SLAVE_QUP_1, 1, 4); -DEFINE_QNODE(qhs_sdc2, SM6350_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_security, SM6350_SLAVE_SECURITY, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SM6350_SLAVE_SNOC_CFG, 1, 4, SM6350_MASTER_SNOC= _CFG); -DEFINE_QNODE(qhs_tcsr, SM6350_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SM6350_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3_0, SM6350_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SM6350_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_venus_throttle_cfg, SM6350_SLAVE_VENUS_THROTTLE_CFG, 1, 4= ); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM6350_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(srvc_cnoc, SM6350_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(qhs_gemnoc, SM6350_SLAVE_GEM_NOC_CFG, 1, 4, SM6350_MASTER_GEM= _NOC_CFG); -DEFINE_QNODE(qhs_llcc, SM6350_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qhs_mcdma_ms_mpu_cfg, SM6350_SLAVE_MCDMA_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM6350_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qns_gem_noc_snoc, SM6350_SLAVE_GEM_NOC_SNOC, 1, 8, SM6350_MAS= TER_GEM_NOC_SNOC); -DEFINE_QNODE(qns_llcc, SM6350_SLAVE_LLCC, 1, 16, SM6350_MASTER_LLCC); -DEFINE_QNODE(srvc_gemnoc, SM6350_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(ebi, SM6350_SLAVE_EBI_CH0, 2, 4); -DEFINE_QNODE(qns_mem_noc_hf, SM6350_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SM6350_M= ASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_sf, SM6350_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM6350_M= ASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SM6350_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qhs_cal_dp0, SM6350_SLAVE_NPU_CAL_DP0, 1, 4); -DEFINE_QNODE(qhs_cp, SM6350_SLAVE_NPU_CP, 1, 4); -DEFINE_QNODE(qhs_dma_bwmon, SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4); -DEFINE_QNODE(qhs_dpm, SM6350_SLAVE_NPU_DPM, 1, 4); -DEFINE_QNODE(qhs_isense, SM6350_SLAVE_ISENSE_CFG, 1, 4); -DEFINE_QNODE(qhs_llm, SM6350_SLAVE_NPU_LLM_CFG, 1, 4); -DEFINE_QNODE(qhs_tcm, SM6350_SLAVE_NPU_TCM, 1, 4); -DEFINE_QNODE(qns_npu_sys, SM6350_SLAVE_NPU_COMPUTE_NOC, 2, 32); -DEFINE_QNODE(srvc_noc, SM6350_SLAVE_SERVICE_NPU_NOC, 1, 4); -DEFINE_QNODE(qhs_apss, SM6350_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qns_cnoc, SM6350_SNOC_CNOC_SLV, 1, 8, SM6350_SNOC_CNOC_MAS); -DEFINE_QNODE(qns_gemnoc_gc, SM6350_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM6350_MAS= TER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_gemnoc_sf, SM6350_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM6350_MA= STER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(qxs_imem, SM6350_SLAVE_OCIMEM, 1, 8); -DEFINE_QNODE(qxs_pimem, SM6350_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SM6350_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_qdss_stm, SM6350_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SM6350_SLAVE_TCU, 1, 8); +static struct qcom_icc_node qhm_a1noc_cfg =3D { + .name =3D "qhm_a1noc_cfg", + .id =3D SM6350_MASTER_A1NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qhm_qup_0 =3D { + .name =3D "qhm_qup_0", + .id =3D SM6350_MASTER_QUP_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_emmc =3D { + .name =3D "xm_emmc", + .id =3D SM6350_MASTER_EMMC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_ufs_mem =3D { + .name =3D "xm_ufs_mem", + .id =3D SM6350_MASTER_UFS_MEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_a2noc_cfg =3D { + .name =3D "qhm_a2noc_cfg", + .id =3D SM6350_MASTER_A2NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam =3D { + .name =3D "qhm_qdss_bam", + .id =3D SM6350_MASTER_QDSS_BAM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup_1 =3D { + .name =3D "qhm_qup_1", + .id =3D SM6350_MASTER_QUP_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_crypto =3D { + .name =3D "qxm_crypto", + .id =3D SM6350_MASTER_CRYPTO_CORE_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_ipa =3D { + .name =3D "qxm_ipa", + .id =3D SM6350_MASTER_IPA, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_qdss_etr =3D { + .name =3D "xm_qdss_etr", + .id =3D SM6350_MASTER_QDSS_ETR, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_sdc2 =3D { + .name =3D "xm_sdc2", + .id =3D SM6350_MASTER_SDCC_2, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_usb3_0 =3D { + .name =3D "xm_usb3_0", + .id =3D SM6350_MASTER_USB3, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0_uncomp =3D { + .name =3D "qxm_camnoc_hf0_uncomp", + .id =3D SM6350_MASTER_CAMNOC_HF0_UNCOMP, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_icp_uncomp =3D { + .name =3D "qxm_camnoc_icp_uncomp", + .id =3D SM6350_MASTER_CAMNOC_ICP_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_sf_uncomp =3D { + .name =3D "qxm_camnoc_sf_uncomp", + .id =3D SM6350_MASTER_CAMNOC_SF_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qup0_core_master =3D { + .name =3D "qup0_core_master", + .id =3D SM6350_MASTER_QUP_CORE_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_QUP_CORE_0 }, +}; + +static struct qcom_icc_node qup1_core_master =3D { + .name =3D "qup1_core_master", + .id =3D SM6350_MASTER_QUP_CORE_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_QUP_CORE_1 }, +}; + +static struct qcom_icc_node qnm_npu =3D { + .name =3D "qnm_npu", + .id =3D SM6350_MASTER_NPU, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_CDSP_GEM_NOC }, +}; + +static struct qcom_icc_node qxm_npu_dsp =3D { + .name =3D "qxm_npu_dsp", + .id =3D SM6350_MASTER_NPU_PROC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_CDSP_GEM_NOC }, +}; + +static struct qcom_icc_node qnm_snoc =3D { + .name =3D "qnm_snoc", + .id =3D SM6350_SNOC_CNOC_MAS, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 42, + .links =3D { SM6350_SLAVE_CAMERA_CFG, + SM6350_SLAVE_SDCC_2, + SM6350_SLAVE_CNOC_MNOC_CFG, + SM6350_SLAVE_UFS_MEM_CFG, + SM6350_SLAVE_QM_CFG, + SM6350_SLAVE_SNOC_CFG, + SM6350_SLAVE_QM_MPU_CFG, + SM6350_SLAVE_GLM, + SM6350_SLAVE_PDM, + SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SM6350_SLAVE_A2NOC_CFG, + SM6350_SLAVE_QDSS_CFG, + SM6350_SLAVE_VSENSE_CTRL_CFG, + SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, + SM6350_SLAVE_DISPLAY_CFG, + SM6350_SLAVE_TCSR, + SM6350_SLAVE_DCC_CFG, + SM6350_SLAVE_CNOC_DDRSS, + SM6350_SLAVE_DISPLAY_THROTTLE_CFG, + SM6350_SLAVE_NPU_CFG, + SM6350_SLAVE_AHB2PHY, + SM6350_SLAVE_GRAPHICS_3D_CFG, + SM6350_SLAVE_BOOT_ROM, + SM6350_SLAVE_VENUS_CFG, + SM6350_SLAVE_IPA_CFG, + SM6350_SLAVE_SECURITY, + SM6350_SLAVE_IMEM_CFG, + SM6350_SLAVE_CNOC_MSS, + SM6350_SLAVE_SERVICE_CNOC, + SM6350_SLAVE_USB3, + SM6350_SLAVE_VENUS_THROTTLE_CFG, + SM6350_SLAVE_RBCPR_CX_CFG, + SM6350_SLAVE_A1NOC_CFG, + SM6350_SLAVE_AOSS, + SM6350_SLAVE_PRNG, + SM6350_SLAVE_EMMC_CFG, + SM6350_SLAVE_CRYPTO_0_CFG, + SM6350_SLAVE_PIMEM_CFG, + SM6350_SLAVE_RBCPR_MX_CFG, + SM6350_SLAVE_QUP_0, + SM6350_SLAVE_QUP_1, + SM6350_SLAVE_CLK_CTL + }, +}; + +static struct qcom_icc_node xm_qdss_dap =3D { + .name =3D "xm_qdss_dap", + .id =3D SM6350_MASTER_QDSS_DAP, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 42, + .links =3D { SM6350_SLAVE_CAMERA_CFG, + SM6350_SLAVE_SDCC_2, + SM6350_SLAVE_CNOC_MNOC_CFG, + SM6350_SLAVE_UFS_MEM_CFG, + SM6350_SLAVE_QM_CFG, + SM6350_SLAVE_SNOC_CFG, + SM6350_SLAVE_QM_MPU_CFG, + SM6350_SLAVE_GLM, + SM6350_SLAVE_PDM, + SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SM6350_SLAVE_A2NOC_CFG, + SM6350_SLAVE_QDSS_CFG, + SM6350_SLAVE_VSENSE_CTRL_CFG, + SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, + SM6350_SLAVE_DISPLAY_CFG, + SM6350_SLAVE_TCSR, + SM6350_SLAVE_DCC_CFG, + SM6350_SLAVE_CNOC_DDRSS, + SM6350_SLAVE_DISPLAY_THROTTLE_CFG, + SM6350_SLAVE_NPU_CFG, + SM6350_SLAVE_AHB2PHY, + SM6350_SLAVE_GRAPHICS_3D_CFG, + SM6350_SLAVE_BOOT_ROM, + SM6350_SLAVE_VENUS_CFG, + SM6350_SLAVE_IPA_CFG, + SM6350_SLAVE_SECURITY, + SM6350_SLAVE_IMEM_CFG, + SM6350_SLAVE_CNOC_MSS, + SM6350_SLAVE_SERVICE_CNOC, + SM6350_SLAVE_USB3, + SM6350_SLAVE_VENUS_THROTTLE_CFG, + SM6350_SLAVE_RBCPR_CX_CFG, + SM6350_SLAVE_A1NOC_CFG, + SM6350_SLAVE_AOSS, + SM6350_SLAVE_PRNG, + SM6350_SLAVE_EMMC_CFG, + SM6350_SLAVE_CRYPTO_0_CFG, + SM6350_SLAVE_PIMEM_CFG, + SM6350_SLAVE_RBCPR_MX_CFG, + SM6350_SLAVE_QUP_0, + SM6350_SLAVE_QUP_1, + SM6350_SLAVE_CLK_CTL + }, +}; + +static struct qcom_icc_node qhm_cnoc_dc_noc =3D { + .name =3D "qhm_cnoc_dc_noc", + .id =3D SM6350_MASTER_CNOC_DC_NOC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .links =3D { SM6350_SLAVE_LLCC_CFG, + SM6350_SLAVE_GEM_NOC_CFG + }, +}; + +static struct qcom_icc_node acm_apps =3D { + .name =3D "acm_apps", + .id =3D SM6350_MASTER_AMPSS_M0, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 2, + .links =3D { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node acm_sys_tcu =3D { + .name =3D "acm_sys_tcu", + .id =3D SM6350_MASTER_SYS_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_gemnoc_cfg =3D { + .name =3D "qhm_gemnoc_cfg", + .id =3D SM6350_MASTER_GEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 3, + .links =3D { SM6350_SLAVE_MCDMA_MS_MPU_CFG, + SM6350_SLAVE_SERVICE_GEM_NOC, + SM6350_SLAVE_MSS_PROC_MS_MPU_CFG + }, +}; + +static struct qcom_icc_node qnm_cmpnoc =3D { + .name =3D "qnm_cmpnoc", + .id =3D SM6350_MASTER_COMPUTE_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_mnoc_hf =3D { + .name =3D "qnm_mnoc_hf", + .id =3D SM6350_MASTER_MNOC_HF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_mnoc_sf =3D { + .name =3D "qnm_mnoc_sf", + .id =3D SM6350_MASTER_MNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc =3D { + .name =3D "qnm_snoc_gc", + .id =3D SM6350_MASTER_SNOC_GC_MEM_NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf =3D { + .name =3D "qnm_snoc_sf", + .id =3D SM6350_MASTER_SNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qxm_gpu =3D { + .name =3D "qxm_gpu", + .id =3D SM6350_MASTER_GRAPHICS_3D, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .id =3D SM6350_MASTER_LLCC, + .channels =3D 2, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_EBI_CH0 }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg =3D { + .name =3D "qhm_mnoc_cfg", + .id =3D SM6350_MASTER_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qnm_video0 =3D { + .name =3D "qnm_video0", + .id =3D SM6350_MASTER_VIDEO_P0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video_cvp =3D { + .name =3D "qnm_video_cvp", + .id =3D SM6350_MASTER_VIDEO_PROC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf =3D { + .name =3D "qxm_camnoc_hf", + .id =3D SM6350_MASTER_CAMNOC_HF, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_icp =3D { + .name =3D "qxm_camnoc_icp", + .id =3D SM6350_MASTER_CAMNOC_ICP, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_sf =3D { + .name =3D "qxm_camnoc_sf", + .id =3D SM6350_MASTER_CAMNOC_SF, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 =3D { + .name =3D "qxm_mdp0", + .id =3D SM6350_MASTER_MDP_PORT0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node amm_npu_sys =3D { + .name =3D "amm_npu_sys", + .id =3D SM6350_MASTER_NPU_SYS, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_NPU_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhm_npu_cfg =3D { + .name =3D "qhm_npu_cfg", + .id =3D SM6350_MASTER_NPU_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 8, + .links =3D { SM6350_SLAVE_SERVICE_NPU_NOC, + SM6350_SLAVE_ISENSE_CFG, + SM6350_SLAVE_NPU_LLM_CFG, + SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, + SM6350_SLAVE_NPU_CP, + SM6350_SLAVE_NPU_TCM, + SM6350_SLAVE_NPU_CAL_DP0, + SM6350_SLAVE_NPU_DPM + }, +}; + +static struct qcom_icc_node qhm_snoc_cfg =3D { + .name =3D "qhm_snoc_cfg", + .id =3D SM6350_MASTER_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc =3D { + .name =3D "qnm_aggre1_noc", + .id =3D SM6350_A1NOC_SNOC_MAS, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 6, + .links =3D { SM6350_SLAVE_SNOC_GEM_NOC_SF, + SM6350_SLAVE_PIMEM, + SM6350_SLAVE_OCIMEM, + SM6350_SLAVE_APPSS, + SM6350_SNOC_CNOC_SLV, + SM6350_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_aggre2_noc =3D { + .name =3D "qnm_aggre2_noc", + .id =3D SM6350_A2NOC_SNOC_MAS, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 7, + .links =3D { SM6350_SLAVE_SNOC_GEM_NOC_SF, + SM6350_SLAVE_PIMEM, + SM6350_SLAVE_OCIMEM, + SM6350_SLAVE_APPSS, + SM6350_SNOC_CNOC_SLV, + SM6350_SLAVE_TCU, + SM6350_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_gemnoc =3D { + .name =3D "qnm_gemnoc", + .id =3D SM6350_MASTER_GEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 6, + .links =3D { SM6350_SLAVE_PIMEM, + SM6350_SLAVE_OCIMEM, + SM6350_SLAVE_APPSS, + SM6350_SNOC_CNOC_SLV, + SM6350_SLAVE_TCU, + SM6350_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qxm_pimem =3D { + .name =3D "qxm_pimem", + .id =3D SM6350_MASTER_PIMEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM6350_SLAVE_SNOC_GEM_NOC_GC, + SM6350_SLAVE_OCIMEM + }, +}; + +static struct qcom_icc_node xm_gic =3D { + .name =3D "xm_gic", + .id =3D SM6350_MASTER_GIC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node qns_a1noc_snoc =3D { + .name =3D "qns_a1noc_snoc", + .id =3D SM6350_A1NOC_SNOC_SLV, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM6350_A1NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node srvc_aggre1_noc =3D { + .name =3D "srvc_aggre1_noc", + .id =3D SM6350_SLAVE_SERVICE_A1NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc =3D { + .name =3D "qns_a2noc_snoc", + .id =3D SM6350_A2NOC_SNOC_SLV, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM6350_A2NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node srvc_aggre2_noc =3D { + .name =3D "srvc_aggre2_noc", + .id =3D SM6350_SLAVE_SERVICE_A2NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_camnoc_uncomp =3D { + .name =3D "qns_camnoc_uncomp", + .id =3D SM6350_SLAVE_CAMNOC_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, +}; + +static struct qcom_icc_node qup0_core_slave =3D { + .name =3D "qup0_core_slave", + .id =3D SM6350_SLAVE_QUP_CORE_0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qup1_core_slave =3D { + .name =3D "qup1_core_slave", + .id =3D SM6350_SLAVE_QUP_CORE_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_cdsp_gemnoc =3D { + .name =3D "qns_cdsp_gemnoc", + .id =3D SM6350_SLAVE_CDSP_GEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg =3D { + .name =3D "qhs_a1_noc_cfg", + .id =3D SM6350_SLAVE_A1NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhs_a2_noc_cfg =3D { + .name =3D "qhs_a2_noc_cfg", + .id =3D SM6350_SLAVE_A2NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qhs_ahb2phy0 =3D { + .name =3D "qhs_ahb2phy0", + .id =3D SM6350_SLAVE_AHB2PHY, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy2 =3D { + .name =3D "qhs_ahb2phy2", + .id =3D SM6350_SLAVE_AHB2PHY_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .id =3D SM6350_SLAVE_AOSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_boot_rom =3D { + .name =3D "qhs_boot_rom", + .id =3D SM6350_SLAVE_BOOT_ROM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_cfg =3D { + .name =3D "qhs_camera_cfg", + .id =3D SM6350_SLAVE_CAMERA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_nrt_thrott_cfg =3D { + .name =3D "qhs_camera_nrt_thrott_cfg", + .id =3D SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_rt_throttle_cfg =3D { + .name =3D "qhs_camera_rt_throttle_cfg", + .id =3D SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .id =3D SM6350_SLAVE_CLK_CTL, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_cx =3D { + .name =3D "qhs_cpr_cx", + .id =3D SM6350_SLAVE_RBCPR_CX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_mx =3D { + .name =3D "qhs_cpr_mx", + .id =3D SM6350_SLAVE_RBCPR_MX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg =3D { + .name =3D "qhs_crypto0_cfg", + .id =3D SM6350_SLAVE_CRYPTO_0_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_dcc_cfg =3D { + .name =3D "qhs_dcc_cfg", + .id =3D SM6350_SLAVE_DCC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg =3D { + .name =3D "qhs_ddrss_cfg", + .id =3D SM6350_SLAVE_CNOC_DDRSS, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qhs_display_cfg =3D { + .name =3D "qhs_display_cfg", + .id =3D SM6350_SLAVE_DISPLAY_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_display_throttle_cfg =3D { + .name =3D "qhs_display_throttle_cfg", + .id =3D SM6350_SLAVE_DISPLAY_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_emmc_cfg =3D { + .name =3D "qhs_emmc_cfg", + .id =3D SM6350_SLAVE_EMMC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_glm =3D { + .name =3D "qhs_glm", + .id =3D SM6350_SLAVE_GLM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg =3D { + .name =3D "qhs_gpuss_cfg", + .id =3D SM6350_SLAVE_GRAPHICS_3D_CFG, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .id =3D SM6350_SLAVE_IMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipa =3D { + .name =3D "qhs_ipa", + .id =3D SM6350_SLAVE_IPA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg =3D { + .name =3D "qhs_mnoc_cfg", + .id =3D SM6350_SLAVE_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qhs_mss_cfg =3D { + .name =3D "qhs_mss_cfg", + .id =3D SM6350_SLAVE_CNOC_MSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_npu_cfg =3D { + .name =3D "qhs_npu_cfg", + .id =3D SM6350_SLAVE_NPU_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_MASTER_NPU_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_pdm =3D { + .name =3D "qhs_pdm", + .id =3D SM6350_SLAVE_PDM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg =3D { + .name =3D "qhs_pimem_cfg", + .id =3D SM6350_SLAVE_PIMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_prng =3D { + .name =3D "qhs_prng", + .id =3D SM6350_SLAVE_PRNG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .id =3D SM6350_SLAVE_QDSS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qm_cfg =3D { + .name =3D "qhs_qm_cfg", + .id =3D SM6350_SLAVE_QM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qm_mpu_cfg =3D { + .name =3D "qhs_qm_mpu_cfg", + .id =3D SM6350_SLAVE_QM_MPU_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup0 =3D { + .name =3D "qhs_qup0", + .id =3D SM6350_SLAVE_QUP_0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup1 =3D { + .name =3D "qhs_qup1", + .id =3D SM6350_SLAVE_QUP_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc2 =3D { + .name =3D "qhs_sdc2", + .id =3D SM6350_SLAVE_SDCC_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_security =3D { + .name =3D "qhs_security", + .id =3D SM6350_SLAVE_SECURITY, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg =3D { + .name =3D "qhs_snoc_cfg", + .id =3D SM6350_SLAVE_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .id =3D SM6350_SLAVE_TCSR, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg =3D { + .name =3D "qhs_ufs_mem_cfg", + .id =3D SM6350_SLAVE_UFS_MEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_0 =3D { + .name =3D "qhs_usb3_0", + .id =3D SM6350_SLAVE_USB3, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_venus_cfg =3D { + .name =3D "qhs_venus_cfg", + .id =3D SM6350_SLAVE_VENUS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_venus_throttle_cfg =3D { + .name =3D "qhs_venus_throttle_cfg", + .id =3D SM6350_SLAVE_VENUS_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { + .name =3D "qhs_vsense_ctrl_cfg", + .id =3D SM6350_SLAVE_VSENSE_CTRL_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_cnoc =3D { + .name =3D "srvc_cnoc", + .id =3D SM6350_SLAVE_SERVICE_CNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gemnoc =3D { + .name =3D "qhs_gemnoc", + .id =3D SM6350_SLAVE_GEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM6350_MASTER_GEM_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_llcc =3D { + .name =3D "qhs_llcc", + .id =3D SM6350_SLAVE_LLCC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mcdma_ms_mpu_cfg =3D { + .name =3D "qhs_mcdma_ms_mpu_cfg", + .id =3D SM6350_SLAVE_MCDMA_MS_MPU_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg =3D { + .name =3D "qhs_mdsp_ms_mpu_cfg", + .id =3D SM6350_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_gem_noc_snoc =3D { + .name =3D "qns_gem_noc_snoc", + .id =3D SM6350_SLAVE_GEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_MASTER_GEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .id =3D SM6350_SLAVE_LLCC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM6350_MASTER_LLCC }, +}; + +static struct qcom_icc_node srvc_gemnoc =3D { + .name =3D "srvc_gemnoc", + .id =3D SM6350_SLAVE_SERVICE_GEM_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .id =3D SM6350_SLAVE_EBI_CH0, + .channels =3D 2, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf =3D { + .name =3D "qns_mem_noc_hf", + .id =3D SM6350_SLAVE_MNOC_HF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_sf =3D { + .name =3D "qns_mem_noc_sf", + .id =3D SM6350_SLAVE_MNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM6350_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc =3D { + .name =3D "srvc_mnoc", + .id =3D SM6350_SLAVE_SERVICE_MNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cal_dp0 =3D { + .name =3D "qhs_cal_dp0", + .id =3D SM6350_SLAVE_NPU_CAL_DP0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cp =3D { + .name =3D "qhs_cp", + .id =3D SM6350_SLAVE_NPU_CP, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_dma_bwmon =3D { + .name =3D "qhs_dma_bwmon", + .id =3D SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_dpm =3D { + .name =3D "qhs_dpm", + .id =3D SM6350_SLAVE_NPU_DPM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_isense =3D { + .name =3D "qhs_isense", + .id =3D SM6350_SLAVE_ISENSE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_llm =3D { + .name =3D "qhs_llm", + .id =3D SM6350_SLAVE_NPU_LLM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tcm =3D { + .name =3D "qhs_tcm", + .id =3D SM6350_SLAVE_NPU_TCM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_npu_sys =3D { + .name =3D "qns_npu_sys", + .id =3D SM6350_SLAVE_NPU_COMPUTE_NOC, + .channels =3D 2, + .buswidth =3D 32, +}; + +static struct qcom_icc_node srvc_noc =3D { + .name =3D "srvc_noc", + .id =3D SM6350_SLAVE_SERVICE_NPU_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_apss =3D { + .name =3D "qhs_apss", + .id =3D SM6350_SLAVE_APPSS, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qns_cnoc =3D { + .name =3D "qns_cnoc", + .id =3D SM6350_SNOC_CNOC_SLV, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_SNOC_CNOC_MAS }, +}; + +static struct qcom_icc_node qns_gemnoc_gc =3D { + .name =3D "qns_gemnoc_gc", + .id =3D SM6350_SLAVE_SNOC_GEM_NOC_GC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM6350_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf =3D { + .name =3D "qns_gemnoc_sf", + .id =3D SM6350_SLAVE_SNOC_GEM_NOC_SF, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM6350_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .id =3D SM6350_SLAVE_OCIMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qxs_pimem =3D { + .name =3D "qxs_pimem", + .id =3D SM6350_SLAVE_PIMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node srvc_snoc =3D { + .name =3D "srvc_snoc", + .id =3D SM6350_SLAVE_SERVICE_SNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .id =3D SM6350_SLAVE_QDSS_STM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .id =3D SM6350_SLAVE_TCU, + .channels =3D 1, + .buswidth =3D 8, +}; =20 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC19CC001DF for ; Tue, 11 Jul 2023 12:19:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231969AbjGKMTl (ORCPT ); Tue, 11 Jul 2023 08:19:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231764AbjGKMTY (ORCPT ); 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:42 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:11 +0200 Subject: [PATCH 12/53] interconnect: qcom: sm8150: Retire DEFINE_QNODE MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-12-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=43197; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=KfeJu81yzM9UtZk6tkFn5rt1KeKxy7YZJdapT6RtiNw=; b=T8eC75GAZGawcHThG7JAbyPR4AmdmaoW8EFm/joEvmxnDDGfl888D7MR5q96nD7rk7l8HkAu1 ciO7wLacAWOB6/b+0WKlSa2N3GcscOr0fn9I/hrc1p+Cydc2QUslnxb X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8150.c | 1401 ++++++++++++++++++++++++++++++++= ---- 1 file changed, 1263 insertions(+), 138 deletions(-) diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom= /sm8150.c index c5ab29322164..29f16899cf5d 100644 --- a/drivers/interconnect/qcom/sm8150.c +++ b/drivers/interconnect/qcom/sm8150.c @@ -15,144 +15,1269 @@ #include "icc-rpmh.h" #include "sm8150.h" =20 -DEFINE_QNODE(qhm_a1noc_cfg, SM8150_MASTER_A1NOC_CFG, 1, 4, SM8150_SLAVE_SE= RVICE_A1NOC); -DEFINE_QNODE(qhm_qup0, SM8150_MASTER_QUP_0, 1, 4, SM8150_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_emac, SM8150_MASTER_EMAC, 1, 8, SM8150_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_ufs_mem, SM8150_MASTER_UFS_MEM, 1, 8, SM8150_A1NOC_SNOC_SL= V); -DEFINE_QNODE(xm_usb3_0, SM8150_MASTER_USB3, 1, 8, SM8150_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_usb3_1, SM8150_MASTER_USB3_1, 1, 8, SM8150_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_a2noc_cfg, SM8150_MASTER_A2NOC_CFG, 1, 4, SM8150_SLAVE_SE= RVICE_A2NOC); -DEFINE_QNODE(qhm_qdss_bam, SM8150_MASTER_QDSS_BAM, 1, 4, SM8150_A2NOC_SNOC= _SLV); -DEFINE_QNODE(qhm_qspi, SM8150_MASTER_QSPI, 1, 4, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qup1, SM8150_MASTER_QUP_1, 1, 4, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qup2, SM8150_MASTER_QUP_2, 1, 4, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qhm_sensorss_ahb, SM8150_MASTER_SENSORS_AHB, 1, 4, SM8150_A2N= OC_SNOC_SLV); -DEFINE_QNODE(qhm_tsif, SM8150_MASTER_TSIF, 1, 4, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qnm_cnoc, SM8150_MASTER_CNOC_A2NOC, 1, 8, SM8150_A2NOC_SNOC_S= LV); -DEFINE_QNODE(qxm_crypto, SM8150_MASTER_CRYPTO_CORE_0, 1, 8, SM8150_A2NOC_S= NOC_SLV); -DEFINE_QNODE(qxm_ipa, SM8150_MASTER_IPA, 1, 8, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_pcie3_0, SM8150_MASTER_PCIE, 1, 8, SM8150_SLAVE_ANOC_PCIE_= GEM_NOC); -DEFINE_QNODE(xm_pcie3_1, SM8150_MASTER_PCIE_1, 1, 8, SM8150_SLAVE_ANOC_PCI= E_GEM_NOC); -DEFINE_QNODE(xm_qdss_etr, SM8150_MASTER_QDSS_ETR, 1, 8, SM8150_A2NOC_SNOC_= SLV); -DEFINE_QNODE(xm_sdc2, SM8150_MASTER_SDCC_2, 1, 8, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_sdc4, SM8150_MASTER_SDCC_4, 1, 8, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SM8150_MASTER_CAMNOC_HF0_UNCOMP, 1, 32= , SM8150_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SM8150_MASTER_CAMNOC_HF1_UNCOMP, 1, 32= , SM8150_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_sf_uncomp, SM8150_MASTER_CAMNOC_SF_UNCOMP, 1, 32, = SM8150_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qnm_npu, SM8150_MASTER_NPU, 1, 32, SM8150_SLAVE_CDSP_MEM_NOC); -DEFINE_QNODE(qhm_spdm, SM8150_MASTER_SPDM, 1, 4, SM8150_SLAVE_CNOC_A2NOC); -DEFINE_QNODE(qnm_snoc, SM8150_SNOC_CNOC_MAS, 1, 8, SM8150_SLAVE_TLMM_SOUTH= , SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM= 8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_= SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SL= AVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAV= E_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG,= SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150= _SLAVE_CNOC_DDRSS, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM815= 0_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, S= M8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_= AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, S= M8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM= 8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_CFG, SM= 8150_SLAVE_AOSS, SM8150 _SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE= _USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_P= IMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_= IMEM_CFG); -DEFINE_QNODE(xm_qdss_dap, SM8150_MASTER_QDSS_DAP, 1, 8, SM8150_SLAVE_TLMM_= SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CF= G, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM= 8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM81= 50_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150= _SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC= _CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, S= M8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_CNOC_A2NOC, SM8150_SLAVE_RBCPR_MMCX_CF= G, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_= CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM815= 0_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY= _SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CA= RD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WE= ST, SM8150_SLAVE_A1NOC_ CFG, SM8150_SLAVE_AOSS, SM8150_SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, S= M8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAV= E_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLA= VE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG); -DEFINE_QNODE(qhm_cnoc_dc_noc, SM8150_MASTER_CNOC_DC_NOC, 1, 4, SM8150_SLAV= E_GEM_NOC_CFG, SM8150_SLAVE_LLCC_CFG); -DEFINE_QNODE(acm_apps, SM8150_MASTER_AMPSS_M0, 2, 32, SM8150_SLAVE_ECC, SM= 8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(acm_gpu_tcu, SM8150_MASTER_GPU_TCU, 1, 8, SM8150_SLAVE_LLCC, = SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(acm_sys_tcu, SM8150_MASTER_SYS_TCU, 1, 8, SM8150_SLAVE_LLCC, = SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qhm_gemnoc_cfg, SM8150_MASTER_GEM_NOC_CFG, 1, 4, SM8150_SLAVE= _SERVICE_GEM_NOC, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG); -DEFINE_QNODE(qnm_cmpnoc, SM8150_MASTER_COMPUTE_NOC, 2, 32, SM8150_SLAVE_EC= C, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_gpu, SM8150_MASTER_GRAPHICS_3D, 2, 32, SM8150_SLAVE_LLCC,= SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_mnoc_hf, SM8150_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8150_SLA= VE_LLCC); -DEFINE_QNODE(qnm_mnoc_sf, SM8150_MASTER_MNOC_SF_MEM_NOC, 1, 32, SM8150_SLA= VE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_pcie, SM8150_MASTER_GEM_NOC_PCIE_SNOC, 1, 16, SM8150_SLAV= E_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SM8150_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8150_SLAV= E_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SM8150_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8150_SLA= VE_LLCC); -DEFINE_QNODE(qxm_ecc, SM8150_MASTER_ECC, 2, 32, SM8150_SLAVE_LLCC); -DEFINE_QNODE(llcc_mc, SM8150_MASTER_LLCC, 4, 4, SM8150_SLAVE_EBI_CH0); -DEFINE_QNODE(qhm_mnoc_cfg, SM8150_MASTER_CNOC_MNOC_CFG, 1, 4, SM8150_SLAVE= _SERVICE_MNOC); -DEFINE_QNODE(qxm_camnoc_hf0, SM8150_MASTER_CAMNOC_HF0, 1, 32, SM8150_SLAVE= _MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_hf1, SM8150_MASTER_CAMNOC_HF1, 1, 32, SM8150_SLAVE= _MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_sf, SM8150_MASTER_CAMNOC_SF, 1, 32, SM8150_SLAVE_M= NOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SM8150_MASTER_MDP_PORT0, 1, 32, SM8150_SLAVE_MNOC_H= F_MEM_NOC); -DEFINE_QNODE(qxm_mdp1, SM8150_MASTER_MDP_PORT1, 1, 32, SM8150_SLAVE_MNOC_H= F_MEM_NOC); -DEFINE_QNODE(qxm_rot, SM8150_MASTER_ROTATOR, 1, 32, SM8150_SLAVE_MNOC_SF_M= EM_NOC); -DEFINE_QNODE(qxm_venus0, SM8150_MASTER_VIDEO_P0, 1, 32, SM8150_SLAVE_MNOC_= SF_MEM_NOC); -DEFINE_QNODE(qxm_venus1, SM8150_MASTER_VIDEO_P1, 1, 32, SM8150_SLAVE_MNOC_= SF_MEM_NOC); -DEFINE_QNODE(qxm_venus_arm9, SM8150_MASTER_VIDEO_PROC, 1, 8, SM8150_SLAVE_= MNOC_SF_MEM_NOC); -DEFINE_QNODE(qhm_snoc_cfg, SM8150_MASTER_SNOC_CFG, 1, 4, SM8150_SLAVE_SERV= ICE_SNOC); -DEFINE_QNODE(qnm_aggre1_noc, SM8150_A1NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SN= OC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS,= SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_aggre2_noc, SM8150_A2NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SN= OC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS,= SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_PCIE_0, SM8150_SLAVE_PCIE_1, SM8150_SLA= VE_TCU, SM8150_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_gemnoc, SM8150_MASTER_GEM_NOC_SNOC, 1, 8, SM8150_SLAVE_PI= MEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_= SLAVE_TCU, SM8150_SLAVE_QDSS_STM); -DEFINE_QNODE(qxm_pimem, SM8150_MASTER_PIMEM, 1, 8, SM8150_SLAVE_SNOC_GEM_N= OC_GC, SM8150_SLAVE_OCIMEM); -DEFINE_QNODE(xm_gic, SM8150_MASTER_GIC, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC= , SM8150_SLAVE_OCIMEM); -DEFINE_QNODE(qns_a1noc_snoc, SM8150_A1NOC_SNOC_SLV, 1, 16, SM8150_A1NOC_SN= OC_MAS); -DEFINE_QNODE(srvc_aggre1_noc, SM8150_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(qns_a2noc_snoc, SM8150_A2NOC_SNOC_SLV, 1, 16, SM8150_A2NOC_SN= OC_MAS); -DEFINE_QNODE(qns_pcie_mem_noc, SM8150_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM81= 50_MASTER_GEM_NOC_PCIE_SNOC); -DEFINE_QNODE(srvc_aggre2_noc, SM8150_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qns_camnoc_uncomp, SM8150_SLAVE_CAMNOC_UNCOMP, 1, 32); -DEFINE_QNODE(qns_cdsp_mem_noc, SM8150_SLAVE_CDSP_MEM_NOC, 2, 32, SM8150_MA= STER_COMPUTE_NOC); -DEFINE_QNODE(qhs_a1_noc_cfg, SM8150_SLAVE_A1NOC_CFG, 1, 4, SM8150_MASTER_A= 1NOC_CFG); -DEFINE_QNODE(qhs_a2_noc_cfg, SM8150_SLAVE_A2NOC_CFG, 1, 4, SM8150_MASTER_A= 2NOC_CFG); -DEFINE_QNODE(qhs_ahb2phy_south, SM8150_SLAVE_AHB2PHY_SOUTH, 1, 4); -DEFINE_QNODE(qhs_aop, SM8150_SLAVE_AOP, 1, 4); -DEFINE_QNODE(qhs_aoss, SM8150_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_camera_cfg, SM8150_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SM8150_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_compute_dsp, SM8150_SLAVE_CDSP_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SM8150_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mmcx, SM8150_SLAVE_RBCPR_MMCX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mx, SM8150_SLAVE_RBCPR_MX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SM8150_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_ddrss_cfg, SM8150_SLAVE_CNOC_DDRSS, 1, 4, SM8150_MASTER_C= NOC_DC_NOC); -DEFINE_QNODE(qhs_display_cfg, SM8150_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_emac_cfg, SM8150_SLAVE_EMAC_CFG, 1, 4); -DEFINE_QNODE(qhs_glm, SM8150_SLAVE_GLM, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SM8150_SLAVE_GRAPHICS_3D_CFG, 1, 8); -DEFINE_QNODE(qhs_imem_cfg, SM8150_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SM8150_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mnoc_cfg, SM8150_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8150_MASTER= _CNOC_MNOC_CFG); -DEFINE_QNODE(qhs_npu_cfg, SM8150_SLAVE_NPU_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie0_cfg, SM8150_SLAVE_PCIE_0_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie1_cfg, SM8150_SLAVE_PCIE_1_CFG, 1, 4); -DEFINE_QNODE(qhs_phy_refgen_north, SM8150_SLAVE_NORTH_PHY_CFG, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SM8150_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_prng, SM8150_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SM8150_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qspi, SM8150_SLAVE_QSPI, 1, 4); -DEFINE_QNODE(qhs_qupv3_east, SM8150_SLAVE_QUP_2, 1, 4); -DEFINE_QNODE(qhs_qupv3_north, SM8150_SLAVE_QUP_1, 1, 4); -DEFINE_QNODE(qhs_qupv3_south, SM8150_SLAVE_QUP_0, 1, 4); -DEFINE_QNODE(qhs_sdc2, SM8150_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_sdc4, SM8150_SLAVE_SDCC_4, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SM8150_SLAVE_SNOC_CFG, 1, 4, SM8150_MASTER_SNOC= _CFG); -DEFINE_QNODE(qhs_spdm, SM8150_SLAVE_SPDM_WRAPPER, 1, 4); -DEFINE_QNODE(qhs_spss_cfg, SM8150_SLAVE_SPSS_CFG, 1, 4); -DEFINE_QNODE(qhs_ssc_cfg, SM8150_SLAVE_SSC_CFG, 1, 4); -DEFINE_QNODE(qhs_tcsr, SM8150_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm_east, SM8150_SLAVE_TLMM_EAST, 1, 4); -DEFINE_QNODE(qhs_tlmm_north, SM8150_SLAVE_TLMM_NORTH, 1, 4); -DEFINE_QNODE(qhs_tlmm_south, SM8150_SLAVE_TLMM_SOUTH, 1, 4); -DEFINE_QNODE(qhs_tlmm_west, SM8150_SLAVE_TLMM_WEST, 1, 4); -DEFINE_QNODE(qhs_tsif, SM8150_SLAVE_TSIF, 1, 4); -DEFINE_QNODE(qhs_ufs_card_cfg, SM8150_SLAVE_UFS_CARD_CFG, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SM8150_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3_0, SM8150_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_usb3_1, SM8150_SLAVE_USB3_1, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SM8150_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8150_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(qns_cnoc_a2noc, SM8150_SLAVE_CNOC_A2NOC, 1, 8, SM8150_MASTER_= CNOC_A2NOC); -DEFINE_QNODE(srvc_cnoc, SM8150_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(qhs_llcc, SM8150_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qhs_memnoc, SM8150_SLAVE_GEM_NOC_CFG, 1, 4, SM8150_MASTER_GEM= _NOC_CFG); -DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qns_ecc, SM8150_SLAVE_ECC, 1, 32); -DEFINE_QNODE(qns_gem_noc_snoc, SM8150_SLAVE_GEM_NOC_SNOC, 1, 8, SM8150_MAS= TER_GEM_NOC_SNOC); -DEFINE_QNODE(qns_llcc, SM8150_SLAVE_LLCC, 4, 16, SM8150_MASTER_LLCC); -DEFINE_QNODE(srvc_gemnoc, SM8150_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(ebi, SM8150_SLAVE_EBI_CH0, 4, 4); -DEFINE_QNODE(qns2_mem_noc, SM8150_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM8150_MAS= TER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_hf, SM8150_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8150_M= ASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SM8150_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qhs_apss, SM8150_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qns_cnoc, SM8150_SNOC_CNOC_SLV, 1, 8, SM8150_SNOC_CNOC_MAS); -DEFINE_QNODE(qns_gemnoc_gc, SM8150_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8150_MAS= TER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_gemnoc_sf, SM8150_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8150_MA= STER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(qxs_imem, SM8150_SLAVE_OCIMEM, 1, 8); -DEFINE_QNODE(qxs_pimem, SM8150_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SM8150_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_pcie_0, SM8150_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(xs_pcie_1, SM8150_SLAVE_PCIE_1, 1, 8); -DEFINE_QNODE(xs_qdss_stm, SM8150_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SM8150_SLAVE_TCU, 1, 8); +static struct qcom_icc_node qhm_a1noc_cfg =3D { + .name =3D "qhm_a1noc_cfg", + .id =3D SM8150_MASTER_A1NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qhm_qup0 =3D { + .name =3D "qhm_qup0", + .id =3D SM8150_MASTER_QUP_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_emac =3D { + .name =3D "xm_emac", + .id =3D SM8150_MASTER_EMAC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_ufs_mem =3D { + .name =3D "xm_ufs_mem", + .id =3D SM8150_MASTER_UFS_MEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_usb3_0 =3D { + .name =3D "xm_usb3_0", + .id =3D SM8150_MASTER_USB3, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_usb3_1 =3D { + .name =3D "xm_usb3_1", + .id =3D SM8150_MASTER_USB3_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_a2noc_cfg =3D { + .name =3D "qhm_a2noc_cfg", + .id =3D SM8150_MASTER_A2NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam =3D { + .name =3D "qhm_qdss_bam", + .id =3D SM8150_MASTER_QDSS_BAM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qspi =3D { + .name =3D "qhm_qspi", + .id =3D SM8150_MASTER_QSPI, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup1 =3D { + .name =3D "qhm_qup1", + .id =3D SM8150_MASTER_QUP_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup2 =3D { + .name =3D "qhm_qup2", + .id =3D SM8150_MASTER_QUP_2, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_sensorss_ahb =3D { + .name =3D "qhm_sensorss_ahb", + .id =3D SM8150_MASTER_SENSORS_AHB, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_tsif =3D { + .name =3D "qhm_tsif", + .id =3D SM8150_MASTER_TSIF, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qnm_cnoc =3D { + .name =3D "qnm_cnoc", + .id =3D SM8150_MASTER_CNOC_A2NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_crypto =3D { + .name =3D "qxm_crypto", + .id =3D SM8150_MASTER_CRYPTO_CORE_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_ipa =3D { + .name =3D "qxm_ipa", + .id =3D SM8150_MASTER_IPA, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_pcie3_0 =3D { + .name =3D "xm_pcie3_0", + .id =3D SM8150_MASTER_PCIE, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_1 =3D { + .name =3D "xm_pcie3_1", + .id =3D SM8150_MASTER_PCIE_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_qdss_etr =3D { + .name =3D "xm_qdss_etr", + .id =3D SM8150_MASTER_QDSS_ETR, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_sdc2 =3D { + .name =3D "xm_sdc2", + .id =3D SM8150_MASTER_SDCC_2, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_sdc4 =3D { + .name =3D "xm_sdc4", + .id =3D SM8150_MASTER_SDCC_4, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0_uncomp =3D { + .name =3D "qxm_camnoc_hf0_uncomp", + .id =3D SM8150_MASTER_CAMNOC_HF0_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1_uncomp =3D { + .name =3D "qxm_camnoc_hf1_uncomp", + .id =3D SM8150_MASTER_CAMNOC_HF1_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_sf_uncomp =3D { + .name =3D "qxm_camnoc_sf_uncomp", + .id =3D SM8150_MASTER_CAMNOC_SF_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qnm_npu =3D { + .name =3D "qnm_npu", + .id =3D SM8150_MASTER_NPU, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_CDSP_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_spdm =3D { + .name =3D "qhm_spdm", + .id =3D SM8150_MASTER_SPDM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_CNOC_A2NOC }, +}; + +static struct qcom_icc_node qnm_snoc =3D { + .name =3D "qnm_snoc", + .id =3D SM8150_SNOC_CNOC_MAS, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 50, + .links =3D { SM8150_SLAVE_TLMM_SOUTH, + SM8150_SLAVE_CDSP_CFG, + SM8150_SLAVE_SPSS_CFG, + SM8150_SLAVE_CAMERA_CFG, + SM8150_SLAVE_SDCC_4, + SM8150_SLAVE_SDCC_2, + SM8150_SLAVE_CNOC_MNOC_CFG, + SM8150_SLAVE_EMAC_CFG, + SM8150_SLAVE_UFS_MEM_CFG, + SM8150_SLAVE_TLMM_EAST, + SM8150_SLAVE_SSC_CFG, + SM8150_SLAVE_SNOC_CFG, + SM8150_SLAVE_NORTH_PHY_CFG, + SM8150_SLAVE_QUP_0, + SM8150_SLAVE_GLM, + SM8150_SLAVE_PCIE_1_CFG, + SM8150_SLAVE_A2NOC_CFG, + SM8150_SLAVE_QDSS_CFG, + SM8150_SLAVE_DISPLAY_CFG, + SM8150_SLAVE_TCSR, + SM8150_SLAVE_CNOC_DDRSS, + SM8150_SLAVE_RBCPR_MMCX_CFG, + SM8150_SLAVE_NPU_CFG, + SM8150_SLAVE_PCIE_0_CFG, + SM8150_SLAVE_GRAPHICS_3D_CFG, + SM8150_SLAVE_VENUS_CFG, + SM8150_SLAVE_TSIF, + SM8150_SLAVE_IPA_CFG, + SM8150_SLAVE_CLK_CTL, + SM8150_SLAVE_AOP, + SM8150_SLAVE_QUP_1, + SM8150_SLAVE_AHB2PHY_SOUTH, + SM8150_SLAVE_USB3_1, + SM8150_SLAVE_SERVICE_CNOC, + SM8150_SLAVE_UFS_CARD_CFG, + SM8150_SLAVE_QUP_2, + SM8150_SLAVE_RBCPR_CX_CFG, + SM8150_SLAVE_TLMM_WEST, + SM8150_SLAVE_A1NOC_CFG, + SM8150_SLAVE_AOSS, + SM8150_SLAVE_PRNG, + SM8150_SLAVE_VSENSE_CTRL_CFG, + SM8150_SLAVE_QSPI, + SM8150_SLAVE_USB3, + SM8150_SLAVE_SPDM_WRAPPER, + SM8150_SLAVE_CRYPTO_0_CFG, + SM8150_SLAVE_PIMEM_CFG, + SM8150_SLAVE_TLMM_NORTH, + SM8150_SLAVE_RBCPR_MX_CFG, + SM8150_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node xm_qdss_dap =3D { + .name =3D "xm_qdss_dap", + .id =3D SM8150_MASTER_QDSS_DAP, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 51, + .links =3D { SM8150_SLAVE_TLMM_SOUTH, + SM8150_SLAVE_CDSP_CFG, + SM8150_SLAVE_SPSS_CFG, + SM8150_SLAVE_CAMERA_CFG, + SM8150_SLAVE_SDCC_4, + SM8150_SLAVE_SDCC_2, + SM8150_SLAVE_CNOC_MNOC_CFG, + SM8150_SLAVE_EMAC_CFG, + SM8150_SLAVE_UFS_MEM_CFG, + SM8150_SLAVE_TLMM_EAST, + SM8150_SLAVE_SSC_CFG, + SM8150_SLAVE_SNOC_CFG, + SM8150_SLAVE_NORTH_PHY_CFG, + SM8150_SLAVE_QUP_0, + SM8150_SLAVE_GLM, + SM8150_SLAVE_PCIE_1_CFG, + SM8150_SLAVE_A2NOC_CFG, + SM8150_SLAVE_QDSS_CFG, + SM8150_SLAVE_DISPLAY_CFG, + SM8150_SLAVE_TCSR, + SM8150_SLAVE_CNOC_DDRSS, + SM8150_SLAVE_CNOC_A2NOC, + SM8150_SLAVE_RBCPR_MMCX_CFG, + SM8150_SLAVE_NPU_CFG, + SM8150_SLAVE_PCIE_0_CFG, + SM8150_SLAVE_GRAPHICS_3D_CFG, + SM8150_SLAVE_VENUS_CFG, + SM8150_SLAVE_TSIF, + SM8150_SLAVE_IPA_CFG, + SM8150_SLAVE_CLK_CTL, + SM8150_SLAVE_AOP, + SM8150_SLAVE_QUP_1, + SM8150_SLAVE_AHB2PHY_SOUTH, + SM8150_SLAVE_USB3_1, + SM8150_SLAVE_SERVICE_CNOC, + SM8150_SLAVE_UFS_CARD_CFG, + SM8150_SLAVE_QUP_2, + SM8150_SLAVE_RBCPR_CX_CFG, + SM8150_SLAVE_TLMM_WEST, + SM8150_SLAVE_A1NOC_CFG, + SM8150_SLAVE_AOSS, + SM8150_SLAVE_PRNG, + SM8150_SLAVE_VSENSE_CTRL_CFG, + SM8150_SLAVE_QSPI, + SM8150_SLAVE_USB3, + SM8150_SLAVE_SPDM_WRAPPER, + SM8150_SLAVE_CRYPTO_0_CFG, + SM8150_SLAVE_PIMEM_CFG, + SM8150_SLAVE_TLMM_NORTH, + SM8150_SLAVE_RBCPR_MX_CFG, + SM8150_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node qhm_cnoc_dc_noc =3D { + .name =3D "qhm_cnoc_dc_noc", + .id =3D SM8150_MASTER_CNOC_DC_NOC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .links =3D { SM8150_SLAVE_GEM_NOC_CFG, + SM8150_SLAVE_LLCC_CFG + }, +}; + +static struct qcom_icc_node acm_apps =3D { + .name =3D "acm_apps", + .id =3D SM8150_MASTER_AMPSS_M0, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 3, + .links =3D { SM8150_SLAVE_ECC, + SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node acm_gpu_tcu =3D { + .name =3D "acm_gpu_tcu", + .id =3D SM8150_MASTER_GPU_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node acm_sys_tcu =3D { + .name =3D "acm_sys_tcu", + .id =3D SM8150_MASTER_SYS_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_gemnoc_cfg =3D { + .name =3D "qhm_gemnoc_cfg", + .id =3D SM8150_MASTER_GEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .links =3D { SM8150_SLAVE_SERVICE_GEM_NOC, + SM8150_SLAVE_MSS_PROC_MS_MPU_CFG + }, +}; + +static struct qcom_icc_node qnm_cmpnoc =3D { + .name =3D "qnm_cmpnoc", + .id =3D SM8150_MASTER_COMPUTE_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 3, + .links =3D { SM8150_SLAVE_ECC, + SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_gpu =3D { + .name =3D "qnm_gpu", + .id =3D SM8150_MASTER_GRAPHICS_3D, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_mnoc_hf =3D { + .name =3D "qnm_mnoc_hf", + .id =3D SM8150_MASTER_MNOC_HF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_sf =3D { + .name =3D "qnm_mnoc_sf", + .id =3D SM8150_MASTER_MNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_pcie =3D { + .name =3D "qnm_pcie", + .id =3D SM8150_MASTER_GEM_NOC_PCIE_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 2, + .links =3D { SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc =3D { + .name =3D "qnm_snoc_gc", + .id =3D SM8150_MASTER_SNOC_GC_MEM_NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf =3D { + .name =3D "qnm_snoc_sf", + .id =3D SM8150_MASTER_SNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qxm_ecc =3D { + .name =3D "qxm_ecc", + .id =3D SM8150_MASTER_ECC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_LLCC }, +}; + +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .id =3D SM8150_MASTER_LLCC, + .channels =3D 4, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_EBI_CH0 }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg =3D { + .name =3D "qhm_mnoc_cfg", + .id =3D SM8150_MASTER_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0 =3D { + .name =3D "qxm_camnoc_hf0", + .id =3D SM8150_MASTER_CAMNOC_HF0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1 =3D { + .name =3D "qxm_camnoc_hf1", + .id =3D SM8150_MASTER_CAMNOC_HF1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_sf =3D { + .name =3D "qxm_camnoc_sf", + .id =3D SM8150_MASTER_CAMNOC_SF, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 =3D { + .name =3D "qxm_mdp0", + .id =3D SM8150_MASTER_MDP_PORT0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp1 =3D { + .name =3D "qxm_mdp1", + .id =3D SM8150_MASTER_MDP_PORT1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_rot =3D { + .name =3D "qxm_rot", + .id =3D SM8150_MASTER_ROTATOR, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus0 =3D { + .name =3D "qxm_venus0", + .id =3D SM8150_MASTER_VIDEO_P0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus1 =3D { + .name =3D "qxm_venus1", + .id =3D SM8150_MASTER_VIDEO_P1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus_arm9 =3D { + .name =3D "qxm_venus_arm9", + .id =3D SM8150_MASTER_VIDEO_PROC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_snoc_cfg =3D { + .name =3D "qhm_snoc_cfg", + .id =3D SM8150_MASTER_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc =3D { + .name =3D "qnm_aggre1_noc", + .id =3D SM8150_A1NOC_SNOC_MAS, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 6, + .links =3D { SM8150_SLAVE_SNOC_GEM_NOC_SF, + SM8150_SLAVE_PIMEM, + SM8150_SLAVE_OCIMEM, + SM8150_SLAVE_APPSS, + SM8150_SNOC_CNOC_SLV, + SM8150_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_aggre2_noc =3D { + .name =3D "qnm_aggre2_noc", + .id =3D SM8150_A2NOC_SNOC_MAS, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 9, + .links =3D { SM8150_SLAVE_SNOC_GEM_NOC_SF, + SM8150_SLAVE_PIMEM, + SM8150_SLAVE_OCIMEM, + SM8150_SLAVE_APPSS, + SM8150_SNOC_CNOC_SLV, + SM8150_SLAVE_PCIE_0, + SM8150_SLAVE_PCIE_1, + SM8150_SLAVE_TCU, + SM8150_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_gemnoc =3D { + .name =3D "qnm_gemnoc", + .id =3D SM8150_MASTER_GEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 6, + .links =3D { SM8150_SLAVE_PIMEM, + SM8150_SLAVE_OCIMEM, + SM8150_SLAVE_APPSS, + SM8150_SNOC_CNOC_SLV, + SM8150_SLAVE_TCU, + SM8150_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qxm_pimem =3D { + .name =3D "qxm_pimem", + .id =3D SM8150_MASTER_PIMEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM8150_SLAVE_SNOC_GEM_NOC_GC, + SM8150_SLAVE_OCIMEM + }, +}; + +static struct qcom_icc_node xm_gic =3D { + .name =3D "xm_gic", + .id =3D SM8150_MASTER_GIC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM8150_SLAVE_SNOC_GEM_NOC_GC, + SM8150_SLAVE_OCIMEM + }, +}; + +static struct qcom_icc_node qns_a1noc_snoc =3D { + .name =3D "qns_a1noc_snoc", + .id =3D SM8150_A1NOC_SNOC_SLV, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8150_A1NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node srvc_aggre1_noc =3D { + .name =3D "srvc_aggre1_noc", + .id =3D SM8150_SLAVE_SERVICE_A1NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc =3D { + .name =3D "qns_a2noc_snoc", + .id =3D SM8150_A2NOC_SNOC_SLV, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8150_A2NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node qns_pcie_mem_noc =3D { + .name =3D "qns_pcie_mem_noc", + .id =3D SM8150_SLAVE_ANOC_PCIE_GEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8150_MASTER_GEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc =3D { + .name =3D "srvc_aggre2_noc", + .id =3D SM8150_SLAVE_SERVICE_A2NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_camnoc_uncomp =3D { + .name =3D "qns_camnoc_uncomp", + .id =3D SM8150_SLAVE_CAMNOC_UNCOMP, + .channels =3D 1, + .buswidth =3D 32, +}; + +static struct qcom_icc_node qns_cdsp_mem_noc =3D { + .name =3D "qns_cdsp_mem_noc", + .id =3D SM8150_SLAVE_CDSP_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg =3D { + .name =3D "qhs_a1_noc_cfg", + .id =3D SM8150_SLAVE_A1NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhs_a2_noc_cfg =3D { + .name =3D "qhs_a2_noc_cfg", + .id =3D SM8150_SLAVE_A2NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qhs_ahb2phy_south =3D { + .name =3D "qhs_ahb2phy_south", + .id =3D SM8150_SLAVE_AHB2PHY_SOUTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_aop =3D { + .name =3D "qhs_aop", + .id =3D SM8150_SLAVE_AOP, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .id =3D SM8150_SLAVE_AOSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_cfg =3D { + .name =3D "qhs_camera_cfg", + .id =3D SM8150_SLAVE_CAMERA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .id =3D SM8150_SLAVE_CLK_CTL, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_compute_dsp =3D { + .name =3D "qhs_compute_dsp", + .id =3D SM8150_SLAVE_CDSP_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_cx =3D { + .name =3D "qhs_cpr_cx", + .id =3D SM8150_SLAVE_RBCPR_CX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_mmcx =3D { + .name =3D "qhs_cpr_mmcx", + .id =3D SM8150_SLAVE_RBCPR_MMCX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_mx =3D { + .name =3D "qhs_cpr_mx", + .id =3D SM8150_SLAVE_RBCPR_MX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg =3D { + .name =3D "qhs_crypto0_cfg", + .id =3D SM8150_SLAVE_CRYPTO_0_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg =3D { + .name =3D "qhs_ddrss_cfg", + .id =3D SM8150_SLAVE_CNOC_DDRSS, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qhs_display_cfg =3D { + .name =3D "qhs_display_cfg", + .id =3D SM8150_SLAVE_DISPLAY_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_emac_cfg =3D { + .name =3D "qhs_emac_cfg", + .id =3D SM8150_SLAVE_EMAC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_glm =3D { + .name =3D "qhs_glm", + .id =3D SM8150_SLAVE_GLM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg =3D { + .name =3D "qhs_gpuss_cfg", + .id =3D SM8150_SLAVE_GRAPHICS_3D_CFG, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .id =3D SM8150_SLAVE_IMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipa =3D { + .name =3D "qhs_ipa", + .id =3D SM8150_SLAVE_IPA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg =3D { + .name =3D "qhs_mnoc_cfg", + .id =3D SM8150_SLAVE_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qhs_npu_cfg =3D { + .name =3D "qhs_npu_cfg", + .id =3D SM8150_SLAVE_NPU_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie0_cfg =3D { + .name =3D "qhs_pcie0_cfg", + .id =3D SM8150_SLAVE_PCIE_0_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie1_cfg =3D { + .name =3D "qhs_pcie1_cfg", + .id =3D SM8150_SLAVE_PCIE_1_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_phy_refgen_north =3D { + .name =3D "qhs_phy_refgen_north", + .id =3D SM8150_SLAVE_NORTH_PHY_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg =3D { + .name =3D "qhs_pimem_cfg", + .id =3D SM8150_SLAVE_PIMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_prng =3D { + .name =3D "qhs_prng", + .id =3D SM8150_SLAVE_PRNG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .id =3D SM8150_SLAVE_QDSS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qspi =3D { + .name =3D "qhs_qspi", + .id =3D SM8150_SLAVE_QSPI, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qupv3_east =3D { + .name =3D "qhs_qupv3_east", + .id =3D SM8150_SLAVE_QUP_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qupv3_north =3D { + .name =3D "qhs_qupv3_north", + .id =3D SM8150_SLAVE_QUP_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qupv3_south =3D { + .name =3D "qhs_qupv3_south", + .id =3D SM8150_SLAVE_QUP_0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc2 =3D { + .name =3D "qhs_sdc2", + .id =3D SM8150_SLAVE_SDCC_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc4 =3D { + .name =3D "qhs_sdc4", + .id =3D SM8150_SLAVE_SDCC_4, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg =3D { + .name =3D "qhs_snoc_cfg", + .id =3D SM8150_SLAVE_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_spdm =3D { + .name =3D "qhs_spdm", + .id =3D SM8150_SLAVE_SPDM_WRAPPER, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_spss_cfg =3D { + .name =3D "qhs_spss_cfg", + .id =3D SM8150_SLAVE_SPSS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ssc_cfg =3D { + .name =3D "qhs_ssc_cfg", + .id =3D SM8150_SLAVE_SSC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .id =3D SM8150_SLAVE_TCSR, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm_east =3D { + .name =3D "qhs_tlmm_east", + .id =3D SM8150_SLAVE_TLMM_EAST, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm_north =3D { + .name =3D "qhs_tlmm_north", + .id =3D SM8150_SLAVE_TLMM_NORTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm_south =3D { + .name =3D "qhs_tlmm_south", + .id =3D SM8150_SLAVE_TLMM_SOUTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm_west =3D { + .name =3D "qhs_tlmm_west", + .id =3D SM8150_SLAVE_TLMM_WEST, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tsif =3D { + .name =3D "qhs_tsif", + .id =3D SM8150_SLAVE_TSIF, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_card_cfg =3D { + .name =3D "qhs_ufs_card_cfg", + .id =3D SM8150_SLAVE_UFS_CARD_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg =3D { + .name =3D "qhs_ufs_mem_cfg", + .id =3D SM8150_SLAVE_UFS_MEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_0 =3D { + .name =3D "qhs_usb3_0", + .id =3D SM8150_SLAVE_USB3, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_1 =3D { + .name =3D "qhs_usb3_1", + .id =3D SM8150_SLAVE_USB3_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_venus_cfg =3D { + .name =3D "qhs_venus_cfg", + .id =3D SM8150_SLAVE_VENUS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { + .name =3D "qhs_vsense_ctrl_cfg", + .id =3D SM8150_SLAVE_VSENSE_CTRL_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_cnoc_a2noc =3D { + .name =3D "qns_cnoc_a2noc", + .id =3D SM8150_SLAVE_CNOC_A2NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_MASTER_CNOC_A2NOC }, +}; + +static struct qcom_icc_node srvc_cnoc =3D { + .name =3D "srvc_cnoc", + .id =3D SM8150_SLAVE_SERVICE_CNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_llcc =3D { + .name =3D "qhs_llcc", + .id =3D SM8150_SLAVE_LLCC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_memnoc =3D { + .name =3D "qhs_memnoc", + .id =3D SM8150_SLAVE_GEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8150_MASTER_GEM_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg =3D { + .name =3D "qhs_mdsp_ms_mpu_cfg", + .id =3D SM8150_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_ecc =3D { + .name =3D "qns_ecc", + .id =3D SM8150_SLAVE_ECC, + .channels =3D 1, + .buswidth =3D 32, +}; + +static struct qcom_icc_node qns_gem_noc_snoc =3D { + .name =3D "qns_gem_noc_snoc", + .id =3D SM8150_SLAVE_GEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_MASTER_GEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .id =3D SM8150_SLAVE_LLCC, + .channels =3D 4, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8150_MASTER_LLCC }, +}; + +static struct qcom_icc_node srvc_gemnoc =3D { + .name =3D "srvc_gemnoc", + .id =3D SM8150_SLAVE_SERVICE_GEM_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .id =3D SM8150_SLAVE_EBI_CH0, + .channels =3D 4, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns2_mem_noc =3D { + .name =3D "qns2_mem_noc", + .id =3D SM8150_SLAVE_MNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_hf =3D { + .name =3D "qns_mem_noc_hf", + .id =3D SM8150_SLAVE_MNOC_HF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8150_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc =3D { + .name =3D "srvc_mnoc", + .id =3D SM8150_SLAVE_SERVICE_MNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_apss =3D { + .name =3D "qhs_apss", + .id =3D SM8150_SLAVE_APPSS, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qns_cnoc =3D { + .name =3D "qns_cnoc", + .id =3D SM8150_SNOC_CNOC_SLV, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_SNOC_CNOC_MAS }, +}; + +static struct qcom_icc_node qns_gemnoc_gc =3D { + .name =3D "qns_gemnoc_gc", + .id =3D SM8150_SLAVE_SNOC_GEM_NOC_GC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8150_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf =3D { + .name =3D "qns_gemnoc_sf", + .id =3D SM8150_SLAVE_SNOC_GEM_NOC_SF, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8150_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .id =3D SM8150_SLAVE_OCIMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qxs_pimem =3D { + .name =3D "qxs_pimem", + .id =3D SM8150_SLAVE_PIMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node srvc_snoc =3D { + .name =3D "srvc_snoc", + .id =3D SM8150_SLAVE_SERVICE_SNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_pcie_0 =3D { + .name =3D "xs_pcie_0", + .id =3D SM8150_SLAVE_PCIE_0, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node xs_pcie_1 =3D { + .name =3D "xs_pcie_1", + .id =3D SM8150_SLAVE_PCIE_1, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .id =3D SM8150_SLAVE_QDSS_STM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .id =3D SM8150_SLAVE_TCU, + .channels =3D 1, + .buswidth =3D 8, +}; =20 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EA07EB64DC for ; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:43 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:12 +0200 Subject: [PATCH 13/53] interconnect: qcom: sm8250: Retire DEFINE_QNODE MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-13-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=45391; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=hGYe0N70rDnwja5IvQO5Zqf0PStSfBajeNCnSM/xFtE=; b=RZw7sBl2WvUUvAH8S24zwPS3RmO8L4FVLPaEZqvEbSsDrREvWN0KTwXs54wHBbGHaXFc1/ZX6 rMGuTbnII1cAkfn8XXAOTfUZK2Z1vZr6/OuM0XXdoMUycC2DDGKRVGe X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8250.c | 1478 ++++++++++++++++++++++++++++++++= ---- 1 file changed, 1330 insertions(+), 148 deletions(-) diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom= /sm8250.c index d3d0196902cd..d4123799c2c6 100644 --- a/drivers/interconnect/qcom/sm8250.c +++ b/drivers/interconnect/qcom/sm8250.c @@ -15,154 +15,1336 @@ #include "icc-rpmh.h" #include "sm8250.h" =20 -DEFINE_QNODE(qhm_a1noc_cfg, SM8250_MASTER_A1NOC_CFG, 1, 4, SM8250_SLAVE_SE= RVICE_A1NOC); -DEFINE_QNODE(qhm_qspi, SM8250_MASTER_QSPI_0, 1, 4, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qup1, SM8250_MASTER_QUP_1, 1, 4, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qup2, SM8250_MASTER_QUP_2, 1, 4, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_tsif, SM8250_MASTER_TSIF, 1, 4, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_pcie3_modem, SM8250_MASTER_PCIE_2, 1, 8, SM8250_SLAVE_ANOC= _PCIE_GEM_NOC_1); -DEFINE_QNODE(xm_sdc4, SM8250_MASTER_SDCC_4, 1, 8, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_ufs_mem, SM8250_MASTER_UFS_MEM, 1, 8, SM8250_A1NOC_SNOC_SL= V); -DEFINE_QNODE(xm_usb3_0, SM8250_MASTER_USB3, 1, 8, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_usb3_1, SM8250_MASTER_USB3_1, 1, 8, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_a2noc_cfg, SM8250_MASTER_A2NOC_CFG, 1, 4, SM8250_SLAVE_SE= RVICE_A2NOC); -DEFINE_QNODE(qhm_qdss_bam, SM8250_MASTER_QDSS_BAM, 1, 4, SM8250_A2NOC_SNOC= _SLV); -DEFINE_QNODE(qhm_qup0, SM8250_MASTER_QUP_0, 1, 4, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(qnm_cnoc, SM8250_MASTER_CNOC_A2NOC, 1, 8, SM8250_A2NOC_SNOC_S= LV); -DEFINE_QNODE(qxm_crypto, SM8250_MASTER_CRYPTO_CORE_0, 1, 8, SM8250_A2NOC_S= NOC_SLV); -DEFINE_QNODE(qxm_ipa, SM8250_MASTER_IPA, 1, 8, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_pcie3_0, SM8250_MASTER_PCIE, 1, 8, SM8250_SLAVE_ANOC_PCIE_= GEM_NOC); -DEFINE_QNODE(xm_pcie3_1, SM8250_MASTER_PCIE_1, 1, 8, SM8250_SLAVE_ANOC_PCI= E_GEM_NOC); -DEFINE_QNODE(xm_qdss_etr, SM8250_MASTER_QDSS_ETR, 1, 8, SM8250_A2NOC_SNOC_= SLV); -DEFINE_QNODE(xm_sdc2, SM8250_MASTER_SDCC_2, 1, 8, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_ufs_card, SM8250_MASTER_UFS_CARD, 1, 8, SM8250_A2NOC_SNOC_= SLV); -DEFINE_QNODE(qnm_npu, SM8250_MASTER_NPU, 2, 32, SM8250_SLAVE_CDSP_MEM_NOC); -DEFINE_QNODE(qnm_snoc, SM8250_SNOC_CNOC_MAS, 1, 8, SM8250_SLAVE_CDSP_CFG, = SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, = SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SL= AVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_= SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NO= C_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2= _CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8= 250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_= CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY= _NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_= TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM825= 0_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM825= 0_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM8250_SL= AVE_AOSS, SM8250_SLAVE_ PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYP= TO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_Q= UP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL); -DEFINE_QNODE(xm_qdss_dap, SM8250_MASTER_QDSS_DAP, 1, 8, SM8250_SLAVE_CDSP_= CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NO= RTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM82= 50_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM= 8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE= _A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_P= CIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS= , SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_CNOC_A2NOC, SM8250_SLAVE_PCIE_0= _CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2P= HY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_= SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM= _CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_C= FG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8= 250_SLAVE_A1NOC_CFG, SM 8250_SLAVE_AOSS, SM8250_SLAVE_PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_S= LAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAV= E_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2,= SM8250_SLAVE_CLK_CTL); -DEFINE_QNODE(qhm_cnoc_dc_noc, SM8250_MASTER_CNOC_DC_NOC, 1, 4, SM8250_SLAV= E_GEM_NOC_CFG, SM8250_SLAVE_LLCC_CFG); -DEFINE_QNODE(alm_gpu_tcu, SM8250_MASTER_GPU_TCU, 1, 8, SM8250_SLAVE_LLCC, = SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(alm_sys_tcu, SM8250_MASTER_SYS_TCU, 1, 8, SM8250_SLAVE_LLCC, = SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(chm_apps, SM8250_MASTER_AMPSS_M0, 2, 32, SM8250_SLAVE_LLCC, S= M8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qhm_gemnoc_cfg, SM8250_MASTER_GEM_NOC_CFG, 1, 4, SM8250_SLAVE= _SERVICE_GEM_NOC_2, SM8250_SLAVE_SERVICE_GEM_NOC_1, SM8250_SLAVE_SERVICE_GE= M_NOC); -DEFINE_QNODE(qnm_cmpnoc, SM8250_MASTER_COMPUTE_NOC, 2, 32, SM8250_SLAVE_LL= CC, SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_gpu, SM8250_MASTER_GRAPHICS_3D, 2, 32, SM8250_SLAVE_LLCC,= SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_mnoc_hf, SM8250_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8250_SLA= VE_LLCC); -DEFINE_QNODE(qnm_mnoc_sf, SM8250_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8250_SLA= VE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_pcie, SM8250_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_SLAV= E_LLCC, SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SM8250_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8250_SLAV= E_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SM8250_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8250_SLA= VE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(llcc_mc, SM8250_MASTER_LLCC, 4, 4, SM8250_SLAVE_EBI_CH0); -DEFINE_QNODE(qhm_mnoc_cfg, SM8250_MASTER_CNOC_MNOC_CFG, 1, 4, SM8250_SLAVE= _SERVICE_MNOC); -DEFINE_QNODE(qnm_camnoc_hf, SM8250_MASTER_CAMNOC_HF, 2, 32, SM8250_SLAVE_M= NOC_HF_MEM_NOC); -DEFINE_QNODE(qnm_camnoc_icp, SM8250_MASTER_CAMNOC_ICP, 1, 8, SM8250_SLAVE_= MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_camnoc_sf, SM8250_MASTER_CAMNOC_SF, 2, 32, SM8250_SLAVE_M= NOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_video0, SM8250_MASTER_VIDEO_P0, 1, 32, SM8250_SLAVE_MNOC_= SF_MEM_NOC); -DEFINE_QNODE(qnm_video1, SM8250_MASTER_VIDEO_P1, 1, 32, SM8250_SLAVE_MNOC_= SF_MEM_NOC); -DEFINE_QNODE(qnm_video_cvp, SM8250_MASTER_VIDEO_PROC, 1, 32, SM8250_SLAVE_= MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SM8250_MASTER_MDP_PORT0, 1, 32, SM8250_SLAVE_MNOC_H= F_MEM_NOC); -DEFINE_QNODE(qxm_mdp1, SM8250_MASTER_MDP_PORT1, 1, 32, SM8250_SLAVE_MNOC_H= F_MEM_NOC); -DEFINE_QNODE(qxm_rot, SM8250_MASTER_ROTATOR, 1, 32, SM8250_SLAVE_MNOC_SF_M= EM_NOC); -DEFINE_QNODE(amm_npu_sys, SM8250_MASTER_NPU_SYS, 4, 32, SM8250_SLAVE_NPU_C= OMPUTE_NOC); -DEFINE_QNODE(amm_npu_sys_cdp_w, SM8250_MASTER_NPU_CDP, 2, 16, SM8250_SLAVE= _NPU_COMPUTE_NOC); -DEFINE_QNODE(qhm_cfg, SM8250_MASTER_NPU_NOC_CFG, 1, 4, SM8250_SLAVE_SERVIC= E_NPU_NOC, SM8250_SLAVE_ISENSE_CFG, SM8250_SLAVE_NPU_LLM_CFG, SM8250_SLAVE_= NPU_INT_DMA_BWMON_CFG, SM8250_SLAVE_NPU_CP, SM8250_SLAVE_NPU_TCM, SM8250_SL= AVE_NPU_CAL_DP0, SM8250_SLAVE_NPU_CAL_DP1, SM8250_SLAVE_NPU_DPM); -DEFINE_QNODE(qhm_snoc_cfg, SM8250_MASTER_SNOC_CFG, 1, 4, SM8250_SLAVE_SERV= ICE_SNOC); -DEFINE_QNODE(qnm_aggre1_noc, SM8250_A1NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SN= OC_GEM_NOC_SF); -DEFINE_QNODE(qnm_aggre2_noc, SM8250_A2NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SN= OC_GEM_NOC_SF); -DEFINE_QNODE(qnm_gemnoc, SM8250_MASTER_GEM_NOC_SNOC, 1, 16, SM8250_SLAVE_P= IMEM, SM8250_SLAVE_OCIMEM, SM8250_SLAVE_APPSS, SM8250_SNOC_CNOC_SLV, SM8250= _SLAVE_TCU, SM8250_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_gemnoc_pcie, SM8250_MASTER_GEM_NOC_PCIE_SNOC, 1, 8, SM825= 0_SLAVE_PCIE_2, SM8250_SLAVE_PCIE_0, SM8250_SLAVE_PCIE_1); -DEFINE_QNODE(qxm_pimem, SM8250_MASTER_PIMEM, 1, 8, SM8250_SLAVE_SNOC_GEM_N= OC_GC); -DEFINE_QNODE(xm_gic, SM8250_MASTER_GIC, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC= ); -DEFINE_QNODE(qns_a1noc_snoc, SM8250_A1NOC_SNOC_SLV, 1, 16, SM8250_A1NOC_SN= OC_MAS); -DEFINE_QNODE(qns_pcie_modem_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1, 1, = 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(srvc_aggre1_noc, SM8250_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(qns_a2noc_snoc, SM8250_A2NOC_SNOC_SLV, 1, 16, SM8250_A2NOC_SN= OC_MAS); -DEFINE_QNODE(qns_pcie_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM82= 50_MASTER_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(srvc_aggre2_noc, SM8250_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qns_cdsp_mem_noc, SM8250_SLAVE_CDSP_MEM_NOC, 2, 32, SM8250_MA= STER_COMPUTE_NOC); -DEFINE_QNODE(qhs_a1_noc_cfg, SM8250_SLAVE_A1NOC_CFG, 1, 4, SM8250_MASTER_A= 1NOC_CFG); -DEFINE_QNODE(qhs_a2_noc_cfg, SM8250_SLAVE_A2NOC_CFG, 1, 4, SM8250_MASTER_A= 2NOC_CFG); -DEFINE_QNODE(qhs_ahb2phy0, SM8250_SLAVE_AHB2PHY_SOUTH, 1, 4); -DEFINE_QNODE(qhs_ahb2phy1, SM8250_SLAVE_AHB2PHY_NORTH, 1, 4); -DEFINE_QNODE(qhs_aoss, SM8250_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_camera_cfg, SM8250_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SM8250_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_compute_dsp, SM8250_SLAVE_CDSP_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SM8250_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mmcx, SM8250_SLAVE_RBCPR_MMCX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mx, SM8250_SLAVE_RBCPR_MX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SM8250_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_cx_rdpm, SM8250_SLAVE_CX_RDPM, 1, 4); -DEFINE_QNODE(qhs_dcc_cfg, SM8250_SLAVE_DCC_CFG, 1, 4); -DEFINE_QNODE(qhs_ddrss_cfg, SM8250_SLAVE_CNOC_DDRSS, 1, 4, SM8250_MASTER_C= NOC_DC_NOC); -DEFINE_QNODE(qhs_display_cfg, SM8250_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SM8250_SLAVE_GRAPHICS_3D_CFG, 1, 8); -DEFINE_QNODE(qhs_imem_cfg, SM8250_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SM8250_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_ipc_router, SM8250_SLAVE_IPC_ROUTER_CFG, 1, 4); -DEFINE_QNODE(qhs_lpass_cfg, SM8250_SLAVE_LPASS, 1, 4); -DEFINE_QNODE(qhs_mnoc_cfg, SM8250_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8250_MASTER= _CNOC_MNOC_CFG); -DEFINE_QNODE(qhs_npu_cfg, SM8250_SLAVE_NPU_CFG, 1, 4, SM8250_MASTER_NPU_NO= C_CFG); -DEFINE_QNODE(qhs_pcie0_cfg, SM8250_SLAVE_PCIE_0_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie1_cfg, SM8250_SLAVE_PCIE_1_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie_modem_cfg, SM8250_SLAVE_PCIE_2_CFG, 1, 4); -DEFINE_QNODE(qhs_pdm, SM8250_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SM8250_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_prng, SM8250_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SM8250_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qspi, SM8250_SLAVE_QSPI_0, 1, 4); -DEFINE_QNODE(qhs_qup0, SM8250_SLAVE_QUP_0, 1, 4); -DEFINE_QNODE(qhs_qup1, SM8250_SLAVE_QUP_1, 1, 4); -DEFINE_QNODE(qhs_qup2, SM8250_SLAVE_QUP_2, 1, 4); -DEFINE_QNODE(qhs_sdc2, SM8250_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_sdc4, SM8250_SLAVE_SDCC_4, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SM8250_SLAVE_SNOC_CFG, 1, 4, SM8250_MASTER_SNOC= _CFG); -DEFINE_QNODE(qhs_tcsr, SM8250_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm0, SM8250_SLAVE_TLMM_NORTH, 1, 4); -DEFINE_QNODE(qhs_tlmm1, SM8250_SLAVE_TLMM_SOUTH, 1, 4); -DEFINE_QNODE(qhs_tlmm2, SM8250_SLAVE_TLMM_WEST, 1, 4); -DEFINE_QNODE(qhs_tsif, SM8250_SLAVE_TSIF, 1, 4); -DEFINE_QNODE(qhs_ufs_card_cfg, SM8250_SLAVE_UFS_CARD_CFG, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SM8250_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3_0, SM8250_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_usb3_1, SM8250_SLAVE_USB3_1, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SM8250_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8250_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(qns_cnoc_a2noc, SM8250_SLAVE_CNOC_A2NOC, 1, 8, SM8250_MASTER_= CNOC_A2NOC); -DEFINE_QNODE(srvc_cnoc, SM8250_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(qhs_llcc, SM8250_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qhs_memnoc, SM8250_SLAVE_GEM_NOC_CFG, 1, 4, SM8250_MASTER_GEM= _NOC_CFG); -DEFINE_QNODE(qns_gem_noc_snoc, SM8250_SLAVE_GEM_NOC_SNOC, 1, 16, SM8250_MA= STER_GEM_NOC_SNOC); -DEFINE_QNODE(qns_llcc, SM8250_SLAVE_LLCC, 4, 16, SM8250_MASTER_LLCC); -DEFINE_QNODE(qns_sys_pcie, SM8250_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SM8250_MA= STER_GEM_NOC_PCIE_SNOC); -DEFINE_QNODE(srvc_even_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_1, 1, 4); -DEFINE_QNODE(srvc_odd_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_2, 1, 4); -DEFINE_QNODE(srvc_sys_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(ebi, SM8250_SLAVE_EBI_CH0, 4, 4); -DEFINE_QNODE(qns_mem_noc_hf, SM8250_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8250_M= ASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_sf, SM8250_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8250_M= ASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SM8250_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qhs_cal_dp0, SM8250_SLAVE_NPU_CAL_DP0, 1, 4); -DEFINE_QNODE(qhs_cal_dp1, SM8250_SLAVE_NPU_CAL_DP1, 1, 4); -DEFINE_QNODE(qhs_cp, SM8250_SLAVE_NPU_CP, 1, 4); -DEFINE_QNODE(qhs_dma_bwmon, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4); -DEFINE_QNODE(qhs_dpm, SM8250_SLAVE_NPU_DPM, 1, 4); -DEFINE_QNODE(qhs_isense, SM8250_SLAVE_ISENSE_CFG, 1, 4); -DEFINE_QNODE(qhs_llm, SM8250_SLAVE_NPU_LLM_CFG, 1, 4); -DEFINE_QNODE(qhs_tcm, SM8250_SLAVE_NPU_TCM, 1, 4); -DEFINE_QNODE(qns_npu_sys, SM8250_SLAVE_NPU_COMPUTE_NOC, 2, 32); -DEFINE_QNODE(srvc_noc, SM8250_SLAVE_SERVICE_NPU_NOC, 1, 4); -DEFINE_QNODE(qhs_apss, SM8250_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qns_cnoc, SM8250_SNOC_CNOC_SLV, 1, 8, SM8250_SNOC_CNOC_MAS); -DEFINE_QNODE(qns_gemnoc_gc, SM8250_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8250_MAS= TER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_gemnoc_sf, SM8250_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8250_MA= STER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(qxs_imem, SM8250_SLAVE_OCIMEM, 1, 8); -DEFINE_QNODE(qxs_pimem, SM8250_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SM8250_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_pcie_0, SM8250_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(xs_pcie_1, SM8250_SLAVE_PCIE_1, 1, 8); -DEFINE_QNODE(xs_pcie_modem, SM8250_SLAVE_PCIE_2, 1, 8); -DEFINE_QNODE(xs_qdss_stm, SM8250_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SM8250_SLAVE_TCU, 1, 8); +static struct qcom_icc_node qhm_a1noc_cfg =3D { + .name =3D "qhm_a1noc_cfg", + .id =3D SM8250_MASTER_A1NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qhm_qspi =3D { + .name =3D "qhm_qspi", + .id =3D SM8250_MASTER_QSPI_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup1 =3D { + .name =3D "qhm_qup1", + .id =3D SM8250_MASTER_QUP_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup2 =3D { + .name =3D "qhm_qup2", + .id =3D SM8250_MASTER_QUP_2, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_tsif =3D { + .name =3D "qhm_tsif", + .id =3D SM8250_MASTER_TSIF, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_pcie3_modem =3D { + .name =3D "xm_pcie3_modem", + .id =3D SM8250_MASTER_PCIE_2, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 }, +}; + +static struct qcom_icc_node xm_sdc4 =3D { + .name =3D "xm_sdc4", + .id =3D SM8250_MASTER_SDCC_4, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_ufs_mem =3D { + .name =3D "xm_ufs_mem", + .id =3D SM8250_MASTER_UFS_MEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_usb3_0 =3D { + .name =3D "xm_usb3_0", + .id =3D SM8250_MASTER_USB3, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_usb3_1 =3D { + .name =3D "xm_usb3_1", + .id =3D SM8250_MASTER_USB3_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_a2noc_cfg =3D { + .name =3D "qhm_a2noc_cfg", + .id =3D SM8250_MASTER_A2NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam =3D { + .name =3D "qhm_qdss_bam", + .id =3D SM8250_MASTER_QDSS_BAM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup0 =3D { + .name =3D "qhm_qup0", + .id =3D SM8250_MASTER_QUP_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qnm_cnoc =3D { + .name =3D "qnm_cnoc", + .id =3D SM8250_MASTER_CNOC_A2NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_crypto =3D { + .name =3D "qxm_crypto", + .id =3D SM8250_MASTER_CRYPTO_CORE_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_ipa =3D { + .name =3D "qxm_ipa", + .id =3D SM8250_MASTER_IPA, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_pcie3_0 =3D { + .name =3D "xm_pcie3_0", + .id =3D SM8250_MASTER_PCIE, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_1 =3D { + .name =3D "xm_pcie3_1", + .id =3D SM8250_MASTER_PCIE_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_qdss_etr =3D { + .name =3D "xm_qdss_etr", + .id =3D SM8250_MASTER_QDSS_ETR, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_sdc2 =3D { + .name =3D "xm_sdc2", + .id =3D SM8250_MASTER_SDCC_2, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_ufs_card =3D { + .name =3D "xm_ufs_card", + .id =3D SM8250_MASTER_UFS_CARD, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qnm_npu =3D { + .name =3D "qnm_npu", + .id =3D SM8250_MASTER_NPU, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_CDSP_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_snoc =3D { + .name =3D "qnm_snoc", + .id =3D SM8250_SNOC_CNOC_MAS, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 49, + .links =3D { SM8250_SLAVE_CDSP_CFG, + SM8250_SLAVE_CAMERA_CFG, + SM8250_SLAVE_TLMM_SOUTH, + SM8250_SLAVE_TLMM_NORTH, + SM8250_SLAVE_SDCC_4, + SM8250_SLAVE_TLMM_WEST, + SM8250_SLAVE_SDCC_2, + SM8250_SLAVE_CNOC_MNOC_CFG, + SM8250_SLAVE_UFS_MEM_CFG, + SM8250_SLAVE_SNOC_CFG, + SM8250_SLAVE_PDM, + SM8250_SLAVE_CX_RDPM, + SM8250_SLAVE_PCIE_1_CFG, + SM8250_SLAVE_A2NOC_CFG, + SM8250_SLAVE_QDSS_CFG, + SM8250_SLAVE_DISPLAY_CFG, + SM8250_SLAVE_PCIE_2_CFG, + SM8250_SLAVE_TCSR, + SM8250_SLAVE_DCC_CFG, + SM8250_SLAVE_CNOC_DDRSS, + SM8250_SLAVE_IPC_ROUTER_CFG, + SM8250_SLAVE_PCIE_0_CFG, + SM8250_SLAVE_RBCPR_MMCX_CFG, + SM8250_SLAVE_NPU_CFG, + SM8250_SLAVE_AHB2PHY_SOUTH, + SM8250_SLAVE_AHB2PHY_NORTH, + SM8250_SLAVE_GRAPHICS_3D_CFG, + SM8250_SLAVE_VENUS_CFG, + SM8250_SLAVE_TSIF, + SM8250_SLAVE_IPA_CFG, + SM8250_SLAVE_IMEM_CFG, + SM8250_SLAVE_USB3, + SM8250_SLAVE_SERVICE_CNOC, + SM8250_SLAVE_UFS_CARD_CFG, + SM8250_SLAVE_USB3_1, + SM8250_SLAVE_LPASS, + SM8250_SLAVE_RBCPR_CX_CFG, + SM8250_SLAVE_A1NOC_CFG, + SM8250_SLAVE_AOSS, + SM8250_SLAVE_PRNG, + SM8250_SLAVE_VSENSE_CTRL_CFG, + SM8250_SLAVE_QSPI_0, + SM8250_SLAVE_CRYPTO_0_CFG, + SM8250_SLAVE_PIMEM_CFG, + SM8250_SLAVE_RBCPR_MX_CFG, + SM8250_SLAVE_QUP_0, + SM8250_SLAVE_QUP_1, + SM8250_SLAVE_QUP_2, + SM8250_SLAVE_CLK_CTL + }, +}; + +static struct qcom_icc_node xm_qdss_dap =3D { + .name =3D "xm_qdss_dap", + .id =3D SM8250_MASTER_QDSS_DAP, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 50, + .links =3D { SM8250_SLAVE_CDSP_CFG, + SM8250_SLAVE_CAMERA_CFG, + SM8250_SLAVE_TLMM_SOUTH, + SM8250_SLAVE_TLMM_NORTH, + SM8250_SLAVE_SDCC_4, + SM8250_SLAVE_TLMM_WEST, + SM8250_SLAVE_SDCC_2, + SM8250_SLAVE_CNOC_MNOC_CFG, + SM8250_SLAVE_UFS_MEM_CFG, + SM8250_SLAVE_SNOC_CFG, + SM8250_SLAVE_PDM, + SM8250_SLAVE_CX_RDPM, + SM8250_SLAVE_PCIE_1_CFG, + SM8250_SLAVE_A2NOC_CFG, + SM8250_SLAVE_QDSS_CFG, + SM8250_SLAVE_DISPLAY_CFG, + SM8250_SLAVE_PCIE_2_CFG, + SM8250_SLAVE_TCSR, + SM8250_SLAVE_DCC_CFG, + SM8250_SLAVE_CNOC_DDRSS, + SM8250_SLAVE_IPC_ROUTER_CFG, + SM8250_SLAVE_CNOC_A2NOC, + SM8250_SLAVE_PCIE_0_CFG, + SM8250_SLAVE_RBCPR_MMCX_CFG, + SM8250_SLAVE_NPU_CFG, + SM8250_SLAVE_AHB2PHY_SOUTH, + SM8250_SLAVE_AHB2PHY_NORTH, + SM8250_SLAVE_GRAPHICS_3D_CFG, + SM8250_SLAVE_VENUS_CFG, + SM8250_SLAVE_TSIF, + SM8250_SLAVE_IPA_CFG, + SM8250_SLAVE_IMEM_CFG, + SM8250_SLAVE_USB3, + SM8250_SLAVE_SERVICE_CNOC, + SM8250_SLAVE_UFS_CARD_CFG, + SM8250_SLAVE_USB3_1, + SM8250_SLAVE_LPASS, + SM8250_SLAVE_RBCPR_CX_CFG, + SM8250_SLAVE_A1NOC_CFG, + SM8250_SLAVE_AOSS, + SM8250_SLAVE_PRNG, + SM8250_SLAVE_VSENSE_CTRL_CFG, + SM8250_SLAVE_QSPI_0, + SM8250_SLAVE_CRYPTO_0_CFG, + SM8250_SLAVE_PIMEM_CFG, + SM8250_SLAVE_RBCPR_MX_CFG, + SM8250_SLAVE_QUP_0, + SM8250_SLAVE_QUP_1, + SM8250_SLAVE_QUP_2, + SM8250_SLAVE_CLK_CTL + }, +}; + +static struct qcom_icc_node qhm_cnoc_dc_noc =3D { + .name =3D "qhm_cnoc_dc_noc", + .id =3D SM8250_MASTER_CNOC_DC_NOC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .links =3D { SM8250_SLAVE_GEM_NOC_CFG, + SM8250_SLAVE_LLCC_CFG + }, +}; + +static struct qcom_icc_node alm_gpu_tcu =3D { + .name =3D "alm_gpu_tcu", + .id =3D SM8250_MASTER_GPU_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node alm_sys_tcu =3D { + .name =3D "alm_sys_tcu", + .id =3D SM8250_MASTER_SYS_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node chm_apps =3D { + .name =3D "chm_apps", + .id =3D SM8250_MASTER_AMPSS_M0, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 3, + .links =3D { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC, + SM8250_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qhm_gemnoc_cfg =3D { + .name =3D "qhm_gemnoc_cfg", + .id =3D SM8250_MASTER_GEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 3, + .links =3D { SM8250_SLAVE_SERVICE_GEM_NOC_2, + SM8250_SLAVE_SERVICE_GEM_NOC_1, + SM8250_SLAVE_SERVICE_GEM_NOC + }, +}; + +static struct qcom_icc_node qnm_cmpnoc =3D { + .name =3D "qnm_cmpnoc", + .id =3D SM8250_MASTER_COMPUTE_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_gpu =3D { + .name =3D "qnm_gpu", + .id =3D SM8250_MASTER_GRAPHICS_3D, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_mnoc_hf =3D { + .name =3D "qnm_mnoc_hf", + .id =3D SM8250_MASTER_MNOC_HF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_sf =3D { + .name =3D "qnm_mnoc_sf", + .id =3D SM8250_MASTER_MNOC_SF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_pcie =3D { + .name =3D "qnm_pcie", + .id =3D SM8250_MASTER_ANOC_PCIE_GEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 2, + .links =3D { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc =3D { + .name =3D "qnm_snoc_gc", + .id =3D SM8250_MASTER_SNOC_GC_MEM_NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf =3D { + .name =3D "qnm_snoc_sf", + .id =3D SM8250_MASTER_SNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 3, + .links =3D { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC, + SM8250_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .id =3D SM8250_MASTER_LLCC, + .channels =3D 4, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_EBI_CH0 }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg =3D { + .name =3D "qhm_mnoc_cfg", + .id =3D SM8250_MASTER_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qnm_camnoc_hf =3D { + .name =3D "qnm_camnoc_hf", + .id =3D SM8250_MASTER_CAMNOC_HF, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_icp =3D { + .name =3D "qnm_camnoc_icp", + .id =3D SM8250_MASTER_CAMNOC_ICP, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_sf =3D { + .name =3D "qnm_camnoc_sf", + .id =3D SM8250_MASTER_CAMNOC_SF, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video0 =3D { + .name =3D "qnm_video0", + .id =3D SM8250_MASTER_VIDEO_P0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video1 =3D { + .name =3D "qnm_video1", + .id =3D SM8250_MASTER_VIDEO_P1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video_cvp =3D { + .name =3D "qnm_video_cvp", + .id =3D SM8250_MASTER_VIDEO_PROC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 =3D { + .name =3D "qxm_mdp0", + .id =3D SM8250_MASTER_MDP_PORT0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp1 =3D { + .name =3D "qxm_mdp1", + .id =3D SM8250_MASTER_MDP_PORT1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_rot =3D { + .name =3D "qxm_rot", + .id =3D SM8250_MASTER_ROTATOR, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node amm_npu_sys =3D { + .name =3D "amm_npu_sys", + .id =3D SM8250_MASTER_NPU_SYS, + .channels =3D 4, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_NPU_COMPUTE_NOC }, +}; + +static struct qcom_icc_node amm_npu_sys_cdp_w =3D { + .name =3D "amm_npu_sys_cdp_w", + .id =3D SM8250_MASTER_NPU_CDP, + .channels =3D 2, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_NPU_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhm_cfg =3D { + .name =3D "qhm_cfg", + .id =3D SM8250_MASTER_NPU_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 9, + .links =3D { SM8250_SLAVE_SERVICE_NPU_NOC, + SM8250_SLAVE_ISENSE_CFG, + SM8250_SLAVE_NPU_LLM_CFG, + SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, + SM8250_SLAVE_NPU_CP, + SM8250_SLAVE_NPU_TCM, + SM8250_SLAVE_NPU_CAL_DP0, + SM8250_SLAVE_NPU_CAL_DP1, + SM8250_SLAVE_NPU_DPM + }, +}; + +static struct qcom_icc_node qhm_snoc_cfg =3D { + .name =3D "qhm_snoc_cfg", + .id =3D SM8250_MASTER_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc =3D { + .name =3D "qnm_aggre1_noc", + .id =3D SM8250_A1NOC_SNOC_MAS, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_aggre2_noc =3D { + .name =3D "qnm_aggre2_noc", + .id =3D SM8250_A2NOC_SNOC_MAS, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_gemnoc =3D { + .name =3D "qnm_gemnoc", + .id =3D SM8250_MASTER_GEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 6, + .links =3D { SM8250_SLAVE_PIMEM, + SM8250_SLAVE_OCIMEM, + SM8250_SLAVE_APPSS, + SM8250_SNOC_CNOC_SLV, + SM8250_SLAVE_TCU, + SM8250_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie =3D { + .name =3D "qnm_gemnoc_pcie", + .id =3D SM8250_MASTER_GEM_NOC_PCIE_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 3, + .links =3D { SM8250_SLAVE_PCIE_2, + SM8250_SLAVE_PCIE_0, + SM8250_SLAVE_PCIE_1 + }, +}; + +static struct qcom_icc_node qxm_pimem =3D { + .name =3D "qxm_pimem", + .id =3D SM8250_MASTER_PIMEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node xm_gic =3D { + .name =3D "xm_gic", + .id =3D SM8250_MASTER_GIC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node qns_a1noc_snoc =3D { + .name =3D "qns_a1noc_snoc", + .id =3D SM8250_A1NOC_SNOC_SLV, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8250_A1NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node qns_pcie_modem_mem_noc =3D { + .name =3D "qns_pcie_modem_mem_noc", + .id =3D SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8250_MASTER_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node srvc_aggre1_noc =3D { + .name =3D "srvc_aggre1_noc", + .id =3D SM8250_SLAVE_SERVICE_A1NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc =3D { + .name =3D "qns_a2noc_snoc", + .id =3D SM8250_A2NOC_SNOC_SLV, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8250_A2NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node qns_pcie_mem_noc =3D { + .name =3D "qns_pcie_mem_noc", + .id =3D SM8250_SLAVE_ANOC_PCIE_GEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8250_MASTER_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc =3D { + .name =3D "srvc_aggre2_noc", + .id =3D SM8250_SLAVE_SERVICE_A2NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_cdsp_mem_noc =3D { + .name =3D "qns_cdsp_mem_noc", + .id =3D SM8250_SLAVE_CDSP_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg =3D { + .name =3D "qhs_a1_noc_cfg", + .id =3D SM8250_SLAVE_A1NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhs_a2_noc_cfg =3D { + .name =3D "qhs_a2_noc_cfg", + .id =3D SM8250_SLAVE_A2NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qhs_ahb2phy0 =3D { + .name =3D "qhs_ahb2phy0", + .id =3D SM8250_SLAVE_AHB2PHY_SOUTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy1 =3D { + .name =3D "qhs_ahb2phy1", + .id =3D SM8250_SLAVE_AHB2PHY_NORTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .id =3D SM8250_SLAVE_AOSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_cfg =3D { + .name =3D "qhs_camera_cfg", + .id =3D SM8250_SLAVE_CAMERA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .id =3D SM8250_SLAVE_CLK_CTL, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_compute_dsp =3D { + .name =3D "qhs_compute_dsp", + .id =3D SM8250_SLAVE_CDSP_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_cx =3D { + .name =3D "qhs_cpr_cx", + .id =3D SM8250_SLAVE_RBCPR_CX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_mmcx =3D { + .name =3D "qhs_cpr_mmcx", + .id =3D SM8250_SLAVE_RBCPR_MMCX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_mx =3D { + .name =3D "qhs_cpr_mx", + .id =3D SM8250_SLAVE_RBCPR_MX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg =3D { + .name =3D "qhs_crypto0_cfg", + .id =3D SM8250_SLAVE_CRYPTO_0_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cx_rdpm =3D { + .name =3D "qhs_cx_rdpm", + .id =3D SM8250_SLAVE_CX_RDPM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_dcc_cfg =3D { + .name =3D "qhs_dcc_cfg", + .id =3D SM8250_SLAVE_DCC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg =3D { + .name =3D "qhs_ddrss_cfg", + .id =3D SM8250_SLAVE_CNOC_DDRSS, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qhs_display_cfg =3D { + .name =3D "qhs_display_cfg", + .id =3D SM8250_SLAVE_DISPLAY_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg =3D { + .name =3D "qhs_gpuss_cfg", + .id =3D SM8250_SLAVE_GRAPHICS_3D_CFG, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .id =3D SM8250_SLAVE_IMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipa =3D { + .name =3D "qhs_ipa", + .id =3D SM8250_SLAVE_IPA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipc_router =3D { + .name =3D "qhs_ipc_router", + .id =3D SM8250_SLAVE_IPC_ROUTER_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_lpass_cfg =3D { + .name =3D "qhs_lpass_cfg", + .id =3D SM8250_SLAVE_LPASS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg =3D { + .name =3D "qhs_mnoc_cfg", + .id =3D SM8250_SLAVE_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qhs_npu_cfg =3D { + .name =3D "qhs_npu_cfg", + .id =3D SM8250_SLAVE_NPU_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_MASTER_NPU_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_pcie0_cfg =3D { + .name =3D "qhs_pcie0_cfg", + .id =3D SM8250_SLAVE_PCIE_0_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie1_cfg =3D { + .name =3D "qhs_pcie1_cfg", + .id =3D SM8250_SLAVE_PCIE_1_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie_modem_cfg =3D { + .name =3D "qhs_pcie_modem_cfg", + .id =3D SM8250_SLAVE_PCIE_2_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pdm =3D { + .name =3D "qhs_pdm", + .id =3D SM8250_SLAVE_PDM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg =3D { + .name =3D "qhs_pimem_cfg", + .id =3D SM8250_SLAVE_PIMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_prng =3D { + .name =3D "qhs_prng", + .id =3D SM8250_SLAVE_PRNG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .id =3D SM8250_SLAVE_QDSS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qspi =3D { + .name =3D "qhs_qspi", + .id =3D SM8250_SLAVE_QSPI_0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup0 =3D { + .name =3D "qhs_qup0", + .id =3D SM8250_SLAVE_QUP_0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup1 =3D { + .name =3D "qhs_qup1", + .id =3D SM8250_SLAVE_QUP_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup2 =3D { + .name =3D "qhs_qup2", + .id =3D SM8250_SLAVE_QUP_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc2 =3D { + .name =3D "qhs_sdc2", + .id =3D SM8250_SLAVE_SDCC_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc4 =3D { + .name =3D "qhs_sdc4", + .id =3D SM8250_SLAVE_SDCC_4, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg =3D { + .name =3D "qhs_snoc_cfg", + .id =3D SM8250_SLAVE_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .id =3D SM8250_SLAVE_TCSR, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm0 =3D { + .name =3D "qhs_tlmm0", + .id =3D SM8250_SLAVE_TLMM_NORTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm1 =3D { + .name =3D "qhs_tlmm1", + .id =3D SM8250_SLAVE_TLMM_SOUTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm2 =3D { + .name =3D "qhs_tlmm2", + .id =3D SM8250_SLAVE_TLMM_WEST, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tsif =3D { + .name =3D "qhs_tsif", + .id =3D SM8250_SLAVE_TSIF, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_card_cfg =3D { + .name =3D "qhs_ufs_card_cfg", + .id =3D SM8250_SLAVE_UFS_CARD_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg =3D { + .name =3D "qhs_ufs_mem_cfg", + .id =3D SM8250_SLAVE_UFS_MEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_0 =3D { + .name =3D "qhs_usb3_0", + .id =3D SM8250_SLAVE_USB3, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_1 =3D { + .name =3D "qhs_usb3_1", + .id =3D SM8250_SLAVE_USB3_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_venus_cfg =3D { + .name =3D "qhs_venus_cfg", + .id =3D SM8250_SLAVE_VENUS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { + .name =3D "qhs_vsense_ctrl_cfg", + .id =3D SM8250_SLAVE_VSENSE_CTRL_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_cnoc_a2noc =3D { + .name =3D "qns_cnoc_a2noc", + .id =3D SM8250_SLAVE_CNOC_A2NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_MASTER_CNOC_A2NOC }, +}; + +static struct qcom_icc_node srvc_cnoc =3D { + .name =3D "srvc_cnoc", + .id =3D SM8250_SLAVE_SERVICE_CNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_llcc =3D { + .name =3D "qhs_llcc", + .id =3D SM8250_SLAVE_LLCC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_memnoc =3D { + .name =3D "qhs_memnoc", + .id =3D SM8250_SLAVE_GEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8250_MASTER_GEM_NOC_CFG }, +}; + +static struct qcom_icc_node qns_gem_noc_snoc =3D { + .name =3D "qns_gem_noc_snoc", + .id =3D SM8250_SLAVE_GEM_NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8250_MASTER_GEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .id =3D SM8250_SLAVE_LLCC, + .channels =3D 4, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8250_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_sys_pcie =3D { + .name =3D "qns_sys_pcie", + .id =3D SM8250_SLAVE_MEM_NOC_PCIE_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_MASTER_GEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node srvc_even_gemnoc =3D { + .name =3D "srvc_even_gemnoc", + .id =3D SM8250_SLAVE_SERVICE_GEM_NOC_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_odd_gemnoc =3D { + .name =3D "srvc_odd_gemnoc", + .id =3D SM8250_SLAVE_SERVICE_GEM_NOC_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_sys_gemnoc =3D { + .name =3D "srvc_sys_gemnoc", + .id =3D SM8250_SLAVE_SERVICE_GEM_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .id =3D SM8250_SLAVE_EBI_CH0, + .channels =3D 4, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf =3D { + .name =3D "qns_mem_noc_hf", + .id =3D SM8250_SLAVE_MNOC_HF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_sf =3D { + .name =3D "qns_mem_noc_sf", + .id =3D SM8250_SLAVE_MNOC_SF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8250_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc =3D { + .name =3D "srvc_mnoc", + .id =3D SM8250_SLAVE_SERVICE_MNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cal_dp0 =3D { + .name =3D "qhs_cal_dp0", + .id =3D SM8250_SLAVE_NPU_CAL_DP0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cal_dp1 =3D { + .name =3D "qhs_cal_dp1", + .id =3D SM8250_SLAVE_NPU_CAL_DP1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cp =3D { + .name =3D "qhs_cp", + .id =3D SM8250_SLAVE_NPU_CP, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_dma_bwmon =3D { + .name =3D "qhs_dma_bwmon", + .id =3D SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_dpm =3D { + .name =3D "qhs_dpm", + .id =3D SM8250_SLAVE_NPU_DPM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_isense =3D { + .name =3D "qhs_isense", + .id =3D SM8250_SLAVE_ISENSE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_llm =3D { + .name =3D "qhs_llm", + .id =3D SM8250_SLAVE_NPU_LLM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tcm =3D { + .name =3D "qhs_tcm", + .id =3D SM8250_SLAVE_NPU_TCM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_npu_sys =3D { + .name =3D "qns_npu_sys", + .id =3D SM8250_SLAVE_NPU_COMPUTE_NOC, + .channels =3D 2, + .buswidth =3D 32, +}; + +static struct qcom_icc_node srvc_noc =3D { + .name =3D "srvc_noc", + .id =3D SM8250_SLAVE_SERVICE_NPU_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_apss =3D { + .name =3D "qhs_apss", + .id =3D SM8250_SLAVE_APPSS, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qns_cnoc =3D { + .name =3D "qns_cnoc", + .id =3D SM8250_SNOC_CNOC_SLV, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_SNOC_CNOC_MAS }, +}; + +static struct qcom_icc_node qns_gemnoc_gc =3D { + .name =3D "qns_gemnoc_gc", + .id =3D SM8250_SLAVE_SNOC_GEM_NOC_GC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8250_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf =3D { + .name =3D "qns_gemnoc_sf", + .id =3D SM8250_SLAVE_SNOC_GEM_NOC_SF, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8250_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .id =3D SM8250_SLAVE_OCIMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qxs_pimem =3D { + .name =3D "qxs_pimem", + .id =3D SM8250_SLAVE_PIMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node srvc_snoc =3D { + .name =3D "srvc_snoc", + .id =3D SM8250_SLAVE_SERVICE_SNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_pcie_0 =3D { + .name =3D "xs_pcie_0", + .id =3D SM8250_SLAVE_PCIE_0, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node xs_pcie_1 =3D { + .name =3D "xs_pcie_1", + .id =3D SM8250_SLAVE_PCIE_1, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node xs_pcie_modem =3D { + .name =3D "xs_pcie_modem", + .id =3D SM8250_SLAVE_PCIE_2, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .id =3D SM8250_SLAVE_QDSS_STM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .id =3D SM8250_SLAVE_TCU, + .channels =3D 1, + .buswidth =3D 8, +}; =20 static struct qcom_icc_node qup0_core_master =3D { .name =3D "qup0_core_master", --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D95E9C001E0 for ; Tue, 11 Jul 2023 12:19:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232016AbjGKMT4 (ORCPT ); Tue, 11 Jul 2023 08:19:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231646AbjGKMT0 (ORCPT ); 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:45 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:13 +0200 Subject: [PATCH 14/53] interconnect: qcom: sm8350: Retire DEFINE_QNODE MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-14-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=46347; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=MBUJBtasIyeZJQqHT2qf34XR17jseRqW+X62JXRRHOs=; b=v8UyoAvE9jr47XwqXZz+UnNUTdHabx8f9JPCwg05MvNvnfgRc0p06D2TS4s7ziu0Fh/g91nma 4+sIDjgvk/DCRjc1ueXF5qIIfdbqnnoxxwu4S6E9YoPkl6vzOzSSgpA X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8350.c | 1488 ++++++++++++++++++++++++++++++++= ---- 1 file changed, 1338 insertions(+), 150 deletions(-) diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom= /sm8350.c index 5398e7c8d826..859549b176c8 100644 --- a/drivers/interconnect/qcom/sm8350.c +++ b/drivers/interconnect/qcom/sm8350.c @@ -14,156 +14,1344 @@ #include "icc-rpmh.h" #include "sm8350.h" =20 -DEFINE_QNODE(qhm_qspi, SM8350_MASTER_QSPI_0, 1, 4, SM8350_SLAVE_A1NOC_SNOC= ); -DEFINE_QNODE(qhm_qup0, SM8350_MASTER_QUP_0, 1, 4, SM8350_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qhm_qup1, SM8350_MASTER_QUP_1, 1, 4, SM8350_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(qhm_qup2, SM8350_MASTER_QUP_2, 1, 4, SM8350_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qnm_a1noc_cfg, SM8350_MASTER_A1NOC_CFG, 1, 4, SM8350_SLAVE_SE= RVICE_A1NOC); -DEFINE_QNODE(xm_sdc4, SM8350_MASTER_SDCC_4, 1, 8, SM8350_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_ufs_mem, SM8350_MASTER_UFS_MEM, 1, 8, SM8350_SLAVE_A1NOC_S= NOC); -DEFINE_QNODE(xm_usb3_0, SM8350_MASTER_USB3_0, 1, 8, SM8350_SLAVE_A1NOC_SNO= C); -DEFINE_QNODE(xm_usb3_1, SM8350_MASTER_USB3_1, 1, 8, SM8350_SLAVE_A1NOC_SNO= C); -DEFINE_QNODE(qhm_qdss_bam, SM8350_MASTER_QDSS_BAM, 1, 4, SM8350_SLAVE_A2NO= C_SNOC); -DEFINE_QNODE(qnm_a2noc_cfg, SM8350_MASTER_A2NOC_CFG, 1, 4, SM8350_SLAVE_SE= RVICE_A2NOC); -DEFINE_QNODE(qxm_crypto, SM8350_MASTER_CRYPTO, 1, 8, SM8350_SLAVE_A2NOC_SN= OC); -DEFINE_QNODE(qxm_ipa, SM8350_MASTER_IPA, 1, 8, SM8350_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_pcie3_0, SM8350_MASTER_PCIE_0, 1, 8, SM8350_SLAVE_ANOC_PCI= E_GEM_NOC); -DEFINE_QNODE(xm_pcie3_1, SM8350_MASTER_PCIE_1, 1, 8, SM8350_SLAVE_ANOC_PCI= E_GEM_NOC); -DEFINE_QNODE(xm_qdss_etr, SM8350_MASTER_QDSS_ETR, 1, 8, SM8350_SLAVE_A2NOC= _SNOC); -DEFINE_QNODE(xm_sdc2, SM8350_MASTER_SDCC_2, 1, 8, SM8350_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_ufs_card, SM8350_MASTER_UFS_CARD, 1, 8, SM8350_SLAVE_A2NOC= _SNOC); -DEFINE_QNODE(qnm_gemnoc_cnoc, SM8350_MASTER_GEM_NOC_CNOC, 1, 16, SM8350_SL= AVE_AHB2PHY_SOUTH, SM8350_SLAVE_AHB2PHY_NORTH, SM8350_SLAVE_AOSS, SM8350_SL= AVE_APPSS, SM8350_SLAVE_CAMERA_CFG, SM8350_SLAVE_CLK_CTL, SM8350_SLAVE_CDSP= _CFG, SM8350_SLAVE_RBCPR_CX_CFG, SM8350_SLAVE_RBCPR_MMCX_CFG, SM8350_SLAVE_= RBCPR_MX_CFG, SM8350_SLAVE_CRYPTO_0_CFG, SM8350_SLAVE_CX_RDPM, SM8350_SLAVE= _DCC_CFG, SM8350_SLAVE_DISPLAY_CFG, SM8350_SLAVE_GFX3D_CFG, SM8350_SLAVE_HW= KM, SM8350_SLAVE_IMEM_CFG, SM8350_SLAVE_IPA_CFG, SM8350_SLAVE_IPC_ROUTER_CF= G, SM8350_SLAVE_LPASS, SM8350_SLAVE_CNOC_MSS, SM8350_SLAVE_MX_RDPM, SM8350_= SLAVE_PCIE_0_CFG, SM8350_SLAVE_PCIE_1_CFG, SM8350_SLAVE_PDM, SM8350_SLAVE_P= IMEM_CFG, SM8350_SLAVE_PKA_WRAPPER_CFG, SM8350_SLAVE_PMU_WRAPPER_CFG, SM835= 0_SLAVE_QDSS_CFG, SM8350_SLAVE_QSPI_0, SM8350_SLAVE_QUP_0, SM8350_SLAVE_QUP= _1, SM8350_SLAVE_QUP_2, SM8350_SLAVE_SDCC_2, SM8350_SLAVE_SDCC_4, SM8350_SL= AVE_SECURITY, SM8350_SLAVE_SPSS_CFG, SM8350_SLAVE_TCSR, SM8350_SLAVE_TLMM, = SM8350_SLAVE_UFS_CARD_C FG, SM8350_SLAVE_UFS_MEM_CFG, SM8350_SLAVE_USB3_0, SM8350_SLAVE_USB3_1, SM= 8350_SLAVE_VENUS_CFG, SM8350_SLAVE_VSENSE_CTRL_CFG, SM8350_SLAVE_A1NOC_CFG,= SM8350_SLAVE_A2NOC_CFG, SM8350_SLAVE_DDRSS_CFG, SM8350_SLAVE_CNOC_MNOC_CFG= , SM8350_SLAVE_SNOC_CFG, SM8350_SLAVE_BOOT_IMEM, SM8350_SLAVE_IMEM, SM8350_= SLAVE_PIMEM, SM8350_SLAVE_SERVICE_CNOC, SM8350_SLAVE_QDSS_STM, SM8350_SLAVE= _TCU); -DEFINE_QNODE(qnm_gemnoc_pcie, SM8350_MASTER_GEM_NOC_PCIE_SNOC, 1, 8, SM835= 0_SLAVE_PCIE_0, SM8350_SLAVE_PCIE_1); -DEFINE_QNODE(xm_qdss_dap, SM8350_MASTER_QDSS_DAP, 1, 8, SM8350_SLAVE_AHB2P= HY_SOUTH, SM8350_SLAVE_AHB2PHY_NORTH, SM8350_SLAVE_AOSS, SM8350_SLAVE_APPSS= , SM8350_SLAVE_CAMERA_CFG, SM8350_SLAVE_CLK_CTL, SM8350_SLAVE_CDSP_CFG, SM8= 350_SLAVE_RBCPR_CX_CFG, SM8350_SLAVE_RBCPR_MMCX_CFG, SM8350_SLAVE_RBCPR_MX_= CFG, SM8350_SLAVE_CRYPTO_0_CFG, SM8350_SLAVE_CX_RDPM, SM8350_SLAVE_DCC_CFG,= SM8350_SLAVE_DISPLAY_CFG, SM8350_SLAVE_GFX3D_CFG, SM8350_SLAVE_HWKM, SM835= 0_SLAVE_IMEM_CFG, SM8350_SLAVE_IPA_CFG, SM8350_SLAVE_IPC_ROUTER_CFG, SM8350= _SLAVE_LPASS, SM8350_SLAVE_CNOC_MSS, SM8350_SLAVE_MX_RDPM, SM8350_SLAVE_PCI= E_0_CFG, SM8350_SLAVE_PCIE_1_CFG, SM8350_SLAVE_PDM, SM8350_SLAVE_PIMEM_CFG,= SM8350_SLAVE_PKA_WRAPPER_CFG, SM8350_SLAVE_PMU_WRAPPER_CFG, SM8350_SLAVE_Q= DSS_CFG, SM8350_SLAVE_QSPI_0, SM8350_SLAVE_QUP_0, SM8350_SLAVE_QUP_1, SM835= 0_SLAVE_QUP_2, SM8350_SLAVE_SDCC_2, SM8350_SLAVE_SDCC_4, SM8350_SLAVE_SECUR= ITY, SM8350_SLAVE_SPSS_CFG, SM8350_SLAVE_TCSR, SM8350_SLAVE_TLMM, SM8350_SL= AVE_UFS_CARD_CFG, SM835 0_SLAVE_UFS_MEM_CFG, SM8350_SLAVE_USB3_0, SM8350_SLAVE_USB3_1, SM8350_SLAV= E_VENUS_CFG, SM8350_SLAVE_VSENSE_CTRL_CFG, SM8350_SLAVE_A1NOC_CFG, SM8350_S= LAVE_A2NOC_CFG, SM8350_SLAVE_DDRSS_CFG, SM8350_SLAVE_CNOC_MNOC_CFG, SM8350_= SLAVE_SNOC_CFG, SM8350_SLAVE_BOOT_IMEM, SM8350_SLAVE_IMEM, SM8350_SLAVE_PIM= EM, SM8350_SLAVE_SERVICE_CNOC, SM8350_SLAVE_QDSS_STM, SM8350_SLAVE_TCU); -DEFINE_QNODE(qnm_cnoc_dc_noc, SM8350_MASTER_CNOC_DC_NOC, 1, 4, SM8350_SLAV= E_LLCC_CFG, SM8350_SLAVE_GEM_NOC_CFG); -DEFINE_QNODE(alm_gpu_tcu, SM8350_MASTER_GPU_TCU, 1, 8, SM8350_SLAVE_GEM_NO= C_CNOC, SM8350_SLAVE_LLCC); -DEFINE_QNODE(alm_sys_tcu, SM8350_MASTER_SYS_TCU, 1, 8, SM8350_SLAVE_GEM_NO= C_CNOC, SM8350_SLAVE_LLCC); -DEFINE_QNODE(chm_apps, SM8350_MASTER_APPSS_PROC, 2, 32, SM8350_SLAVE_GEM_N= OC_CNOC, SM8350_SLAVE_LLCC, SM8350_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qnm_cmpnoc, SM8350_MASTER_COMPUTE_NOC, 2, 32, SM8350_SLAVE_GE= M_NOC_CNOC, SM8350_SLAVE_LLCC); -DEFINE_QNODE(qnm_gemnoc_cfg, SM8350_MASTER_GEM_NOC_CFG, 1, 4, SM8350_SLAVE= _MSS_PROC_MS_MPU_CFG, SM8350_SLAVE_MCDMA_MS_MPU_CFG, SM8350_SLAVE_SERVICE_G= EM_NOC_1, SM8350_SLAVE_SERVICE_GEM_NOC_2, SM8350_SLAVE_SERVICE_GEM_NOC); -DEFINE_QNODE(qnm_gpu, SM8350_MASTER_GFX3D, 2, 32, SM8350_SLAVE_GEM_NOC_CNO= C, SM8350_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_hf, SM8350_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8350_SLA= VE_LLCC); -DEFINE_QNODE(qnm_mnoc_sf, SM8350_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8350_SLA= VE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC); -DEFINE_QNODE(qnm_pcie, SM8350_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8350_SLAV= E_GEM_NOC_CNOC, SM8350_SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_gc, SM8350_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8350_SLAV= E_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SM8350_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8350_SLA= VE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC, SM8350_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qhm_config_noc, SM8350_MASTER_CNOC_LPASS_AG_NOC, 1, 4, SM8350= _SLAVE_LPASS_CORE_CFG, SM8350_SLAVE_LPASS_LPI_CFG, SM8350_SLAVE_LPASS_MPU_C= FG, SM8350_SLAVE_LPASS_TOP_CFG, SM8350_SLAVE_SERVICES_LPASS_AML_NOC, SM8350= _SLAVE_SERVICE_LPASS_AG_NOC); -DEFINE_QNODE(llcc_mc, SM8350_MASTER_LLCC, 4, 4, SM8350_SLAVE_EBI1); -DEFINE_QNODE(qnm_camnoc_hf, SM8350_MASTER_CAMNOC_HF, 2, 32, SM8350_SLAVE_M= NOC_HF_MEM_NOC); -DEFINE_QNODE(qnm_camnoc_icp, SM8350_MASTER_CAMNOC_ICP, 1, 8, SM8350_SLAVE_= MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_camnoc_sf, SM8350_MASTER_CAMNOC_SF, 2, 32, SM8350_SLAVE_M= NOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_mnoc_cfg, SM8350_MASTER_CNOC_MNOC_CFG, 1, 4, SM8350_SLAVE= _SERVICE_MNOC); -DEFINE_QNODE(qnm_video0, SM8350_MASTER_VIDEO_P0, 1, 32, SM8350_SLAVE_MNOC_= SF_MEM_NOC); -DEFINE_QNODE(qnm_video1, SM8350_MASTER_VIDEO_P1, 1, 32, SM8350_SLAVE_MNOC_= SF_MEM_NOC); -DEFINE_QNODE(qnm_video_cvp, SM8350_MASTER_VIDEO_PROC, 1, 32, SM8350_SLAVE_= MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SM8350_MASTER_MDP0, 1, 32, SM8350_SLAVE_MNOC_HF_MEM= _NOC); -DEFINE_QNODE(qxm_mdp1, SM8350_MASTER_MDP1, 1, 32, SM8350_SLAVE_MNOC_HF_MEM= _NOC); -DEFINE_QNODE(qxm_rot, SM8350_MASTER_ROTATOR, 1, 32, SM8350_SLAVE_MNOC_SF_M= EM_NOC); -DEFINE_QNODE(qhm_nsp_noc_config, SM8350_MASTER_CDSP_NOC_CFG, 1, 4, SM8350_= SLAVE_SERVICE_NSP_NOC); -DEFINE_QNODE(qxm_nsp, SM8350_MASTER_CDSP_PROC, 2, 32, SM8350_SLAVE_CDSP_ME= M_NOC); -DEFINE_QNODE(qnm_aggre1_noc, SM8350_MASTER_A1NOC_SNOC, 1, 16, SM8350_SLAVE= _SNOC_GEM_NOC_SF); -DEFINE_QNODE(qnm_aggre2_noc, SM8350_MASTER_A2NOC_SNOC, 1, 16, SM8350_SLAVE= _SNOC_GEM_NOC_SF); -DEFINE_QNODE(qnm_snoc_cfg, SM8350_MASTER_SNOC_CFG, 1, 4, SM8350_SLAVE_SERV= ICE_SNOC); -DEFINE_QNODE(qxm_pimem, SM8350_MASTER_PIMEM, 1, 8, SM8350_SLAVE_SNOC_GEM_N= OC_GC); -DEFINE_QNODE(xm_gic, SM8350_MASTER_GIC, 1, 8, SM8350_SLAVE_SNOC_GEM_NOC_GC= ); -DEFINE_QNODE(qnm_mnoc_hf_disp, SM8350_MASTER_MNOC_HF_MEM_NOC_DISP, 2, 32, = SM8350_SLAVE_LLCC_DISP); -DEFINE_QNODE(qnm_mnoc_sf_disp, SM8350_MASTER_MNOC_SF_MEM_NOC_DISP, 2, 32, = SM8350_SLAVE_LLCC_DISP); -DEFINE_QNODE(llcc_mc_disp, SM8350_MASTER_LLCC_DISP, 4, 4, SM8350_SLAVE_EBI= 1_DISP); -DEFINE_QNODE(qxm_mdp0_disp, SM8350_MASTER_MDP0_DISP, 1, 32, SM8350_SLAVE_M= NOC_HF_MEM_NOC_DISP); -DEFINE_QNODE(qxm_mdp1_disp, SM8350_MASTER_MDP1_DISP, 1, 32, SM8350_SLAVE_M= NOC_HF_MEM_NOC_DISP); -DEFINE_QNODE(qxm_rot_disp, SM8350_MASTER_ROTATOR_DISP, 1, 32, SM8350_SLAVE= _MNOC_SF_MEM_NOC_DISP); -DEFINE_QNODE(qns_a1noc_snoc, SM8350_SLAVE_A1NOC_SNOC, 1, 16, SM8350_MASTER= _A1NOC_SNOC); -DEFINE_QNODE(srvc_aggre1_noc, SM8350_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(qns_a2noc_snoc, SM8350_SLAVE_A2NOC_SNOC, 1, 16, SM8350_MASTER= _A2NOC_SNOC); -DEFINE_QNODE(qns_pcie_mem_noc, SM8350_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM83= 50_MASTER_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(srvc_aggre2_noc, SM8350_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qhs_ahb2phy0, SM8350_SLAVE_AHB2PHY_SOUTH, 1, 4); -DEFINE_QNODE(qhs_ahb2phy1, SM8350_SLAVE_AHB2PHY_NORTH, 1, 4); -DEFINE_QNODE(qhs_aoss, SM8350_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_apss, SM8350_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qhs_camera_cfg, SM8350_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SM8350_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_compute_cfg, SM8350_SLAVE_CDSP_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SM8350_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mmcx, SM8350_SLAVE_RBCPR_MMCX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mx, SM8350_SLAVE_RBCPR_MX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SM8350_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_cx_rdpm, SM8350_SLAVE_CX_RDPM, 1, 4); -DEFINE_QNODE(qhs_dcc_cfg, SM8350_SLAVE_DCC_CFG, 1, 4); -DEFINE_QNODE(qhs_display_cfg, SM8350_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SM8350_SLAVE_GFX3D_CFG, 1, 8); -DEFINE_QNODE(qhs_hwkm, SM8350_SLAVE_HWKM, 1, 4); -DEFINE_QNODE(qhs_imem_cfg, SM8350_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SM8350_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_ipc_router, SM8350_SLAVE_IPC_ROUTER_CFG, 1, 4); -DEFINE_QNODE(qhs_lpass_cfg, SM8350_SLAVE_LPASS, 1, 4, SM8350_MASTER_CNOC_L= PASS_AG_NOC); -DEFINE_QNODE(qhs_mss_cfg, SM8350_SLAVE_CNOC_MSS, 1, 4); -DEFINE_QNODE(qhs_mx_rdpm, SM8350_SLAVE_MX_RDPM, 1, 4); -DEFINE_QNODE(qhs_pcie0_cfg, SM8350_SLAVE_PCIE_0_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie1_cfg, SM8350_SLAVE_PCIE_1_CFG, 1, 4); -DEFINE_QNODE(qhs_pdm, SM8350_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SM8350_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_pka_wrapper_cfg, SM8350_SLAVE_PKA_WRAPPER_CFG, 1, 4); -DEFINE_QNODE(qhs_pmu_wrapper_cfg, SM8350_SLAVE_PMU_WRAPPER_CFG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SM8350_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qspi, SM8350_SLAVE_QSPI_0, 1, 4); -DEFINE_QNODE(qhs_qup0, SM8350_SLAVE_QUP_0, 1, 4); -DEFINE_QNODE(qhs_qup1, SM8350_SLAVE_QUP_1, 1, 4); -DEFINE_QNODE(qhs_qup2, SM8350_SLAVE_QUP_2, 1, 4); -DEFINE_QNODE(qhs_sdc2, SM8350_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_sdc4, SM8350_SLAVE_SDCC_4, 1, 4); -DEFINE_QNODE(qhs_security, SM8350_SLAVE_SECURITY, 1, 4); -DEFINE_QNODE(qhs_spss_cfg, SM8350_SLAVE_SPSS_CFG, 1, 4); -DEFINE_QNODE(qhs_tcsr, SM8350_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm, SM8350_SLAVE_TLMM, 1, 4); -DEFINE_QNODE(qhs_ufs_card_cfg, SM8350_SLAVE_UFS_CARD_CFG, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SM8350_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3_0, SM8350_SLAVE_USB3_0, 1, 4); -DEFINE_QNODE(qhs_usb3_1, SM8350_SLAVE_USB3_1, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SM8350_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8350_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(qns_a1_noc_cfg, SM8350_SLAVE_A1NOC_CFG, 1, 4); -DEFINE_QNODE(qns_a2_noc_cfg, SM8350_SLAVE_A2NOC_CFG, 1, 4); -DEFINE_QNODE(qns_ddrss_cfg, SM8350_SLAVE_DDRSS_CFG, 1, 4); -DEFINE_QNODE(qns_mnoc_cfg, SM8350_SLAVE_CNOC_MNOC_CFG, 1, 4); -DEFINE_QNODE(qns_snoc_cfg, SM8350_SLAVE_SNOC_CFG, 1, 4); -DEFINE_QNODE(qxs_boot_imem, SM8350_SLAVE_BOOT_IMEM, 1, 8); -DEFINE_QNODE(qxs_imem, SM8350_SLAVE_IMEM, 1, 8); -DEFINE_QNODE(qxs_pimem, SM8350_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_cnoc, SM8350_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(xs_pcie_0, SM8350_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(xs_pcie_1, SM8350_SLAVE_PCIE_1, 1, 8); -DEFINE_QNODE(xs_qdss_stm, SM8350_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SM8350_SLAVE_TCU, 1, 8); -DEFINE_QNODE(qhs_llcc, SM8350_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qns_gemnoc, SM8350_SLAVE_GEM_NOC_CFG, 1, 4); -DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qhs_modem_ms_mpu_cfg, SM8350_SLAVE_MCDMA_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qns_gem_noc_cnoc, SM8350_SLAVE_GEM_NOC_CNOC, 1, 16, SM8350_MA= STER_GEM_NOC_CNOC); -DEFINE_QNODE(qns_llcc, SM8350_SLAVE_LLCC, 4, 16, SM8350_MASTER_LLCC); -DEFINE_QNODE(qns_pcie, SM8350_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8); -DEFINE_QNODE(srvc_even_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC_1, 1, 4); -DEFINE_QNODE(srvc_odd_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC_2, 1, 4); -DEFINE_QNODE(srvc_sys_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(qhs_lpass_core, SM8350_SLAVE_LPASS_CORE_CFG, 1, 4); -DEFINE_QNODE(qhs_lpass_lpi, SM8350_SLAVE_LPASS_LPI_CFG, 1, 4); -DEFINE_QNODE(qhs_lpass_mpu, SM8350_SLAVE_LPASS_MPU_CFG, 1, 4); -DEFINE_QNODE(qhs_lpass_top, SM8350_SLAVE_LPASS_TOP_CFG, 1, 4); -DEFINE_QNODE(srvc_niu_aml_noc, SM8350_SLAVE_SERVICES_LPASS_AML_NOC, 1, 4); -DEFINE_QNODE(srvc_niu_lpass_agnoc, SM8350_SLAVE_SERVICE_LPASS_AG_NOC, 1, 4= ); -DEFINE_QNODE(ebi, SM8350_SLAVE_EBI1, 4, 4); -DEFINE_QNODE(qns_mem_noc_hf, SM8350_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8350_M= ASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_sf, SM8350_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8350_M= ASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SM8350_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qns_nsp_gemnoc, SM8350_SLAVE_CDSP_MEM_NOC, 2, 32, SM8350_MAST= ER_COMPUTE_NOC); -DEFINE_QNODE(service_nsp_noc, SM8350_SLAVE_SERVICE_NSP_NOC, 1, 4); -DEFINE_QNODE(qns_gemnoc_gc, SM8350_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8350_MAS= TER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_gemnoc_sf, SM8350_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8350_MA= STER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(srvc_snoc, SM8350_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(qns_llcc_disp, SM8350_SLAVE_LLCC_DISP, 4, 16, SM8350_MASTER_L= LCC_DISP); -DEFINE_QNODE(ebi_disp, SM8350_SLAVE_EBI1_DISP, 4, 4); -DEFINE_QNODE(qns_mem_noc_hf_disp, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP, 2, 32= , SM8350_MASTER_MNOC_HF_MEM_NOC_DISP); -DEFINE_QNODE(qns_mem_noc_sf_disp, SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP, 2, 32= , SM8350_MASTER_MNOC_SF_MEM_NOC_DISP); +static struct qcom_icc_node qhm_qspi =3D { + .name =3D "qhm_qspi", + .id =3D SM8350_MASTER_QSPI_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup0 =3D { + .name =3D "qhm_qup0", + .id =3D SM8350_MASTER_QUP_0, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup1 =3D { + .name =3D "qhm_qup1", + .id =3D SM8350_MASTER_QUP_1, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup2 =3D { + .name =3D "qhm_qup2", + .id =3D SM8350_MASTER_QUP_2, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_a1noc_cfg =3D { + .name =3D "qnm_a1noc_cfg", + .id =3D SM8350_MASTER_A1NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node xm_sdc4 =3D { + .name =3D "xm_sdc4", + .id =3D SM8350_MASTER_SDCC_4, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_mem =3D { + .name =3D "xm_ufs_mem", + .id =3D SM8350_MASTER_UFS_MEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_0 =3D { + .name =3D "xm_usb3_0", + .id =3D SM8350_MASTER_USB3_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_1 =3D { + .name =3D "xm_usb3_1", + .id =3D SM8350_MASTER_USB3_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam =3D { + .name =3D "qhm_qdss_bam", + .id =3D SM8350_MASTER_QDSS_BAM, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_a2noc_cfg =3D { + .name =3D "qnm_a2noc_cfg", + .id =3D SM8350_MASTER_A2NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qxm_crypto =3D { + .name =3D "qxm_crypto", + .id =3D SM8350_MASTER_CRYPTO, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_ipa =3D { + .name =3D "qxm_ipa", + .id =3D SM8350_MASTER_IPA, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_pcie3_0 =3D { + .name =3D "xm_pcie3_0", + .id =3D SM8350_MASTER_PCIE_0, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_1 =3D { + .name =3D "xm_pcie3_1", + .id =3D SM8350_MASTER_PCIE_1, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_qdss_etr =3D { + .name =3D "xm_qdss_etr", + .id =3D SM8350_MASTER_QDSS_ETR, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc2 =3D { + .name =3D "xm_sdc2", + .id =3D SM8350_MASTER_SDCC_2, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_card =3D { + .name =3D "xm_ufs_card", + .id =3D SM8350_MASTER_UFS_CARD, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_gemnoc_cnoc =3D { + .name =3D "qnm_gemnoc_cnoc", + .id =3D SM8350_MASTER_GEM_NOC_CNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 56, + .links =3D { SM8350_SLAVE_AHB2PHY_SOUTH, + SM8350_SLAVE_AHB2PHY_NORTH, + SM8350_SLAVE_AOSS, + SM8350_SLAVE_APPSS, + SM8350_SLAVE_CAMERA_CFG, + SM8350_SLAVE_CLK_CTL, + SM8350_SLAVE_CDSP_CFG, + SM8350_SLAVE_RBCPR_CX_CFG, + SM8350_SLAVE_RBCPR_MMCX_CFG, + SM8350_SLAVE_RBCPR_MX_CFG, + SM8350_SLAVE_CRYPTO_0_CFG, + SM8350_SLAVE_CX_RDPM, + SM8350_SLAVE_DCC_CFG, + SM8350_SLAVE_DISPLAY_CFG, + SM8350_SLAVE_GFX3D_CFG, + SM8350_SLAVE_HWKM, + SM8350_SLAVE_IMEM_CFG, + SM8350_SLAVE_IPA_CFG, + SM8350_SLAVE_IPC_ROUTER_CFG, + SM8350_SLAVE_LPASS, + SM8350_SLAVE_CNOC_MSS, + SM8350_SLAVE_MX_RDPM, + SM8350_SLAVE_PCIE_0_CFG, + SM8350_SLAVE_PCIE_1_CFG, + SM8350_SLAVE_PDM, + SM8350_SLAVE_PIMEM_CFG, + SM8350_SLAVE_PKA_WRAPPER_CFG, + SM8350_SLAVE_PMU_WRAPPER_CFG, + SM8350_SLAVE_QDSS_CFG, + SM8350_SLAVE_QSPI_0, + SM8350_SLAVE_QUP_0, + SM8350_SLAVE_QUP_1, + SM8350_SLAVE_QUP_2, + SM8350_SLAVE_SDCC_2, + SM8350_SLAVE_SDCC_4, + SM8350_SLAVE_SECURITY, + SM8350_SLAVE_SPSS_CFG, + SM8350_SLAVE_TCSR, + SM8350_SLAVE_TLMM, + SM8350_SLAVE_UFS_CARD_CFG, + SM8350_SLAVE_UFS_MEM_CFG, + SM8350_SLAVE_USB3_0, + SM8350_SLAVE_USB3_1, + SM8350_SLAVE_VENUS_CFG, + SM8350_SLAVE_VSENSE_CTRL_CFG, + SM8350_SLAVE_A1NOC_CFG, + SM8350_SLAVE_A2NOC_CFG, + SM8350_SLAVE_DDRSS_CFG, + SM8350_SLAVE_CNOC_MNOC_CFG, + SM8350_SLAVE_SNOC_CFG, + SM8350_SLAVE_BOOT_IMEM, + SM8350_SLAVE_IMEM, + SM8350_SLAVE_PIMEM, + SM8350_SLAVE_SERVICE_CNOC, + SM8350_SLAVE_QDSS_STM, + SM8350_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie =3D { + .name =3D "qnm_gemnoc_pcie", + .id =3D SM8350_MASTER_GEM_NOC_PCIE_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM8350_SLAVE_PCIE_0, + SM8350_SLAVE_PCIE_1 + }, +}; + +static struct qcom_icc_node xm_qdss_dap =3D { + .name =3D "xm_qdss_dap", + .id =3D SM8350_MASTER_QDSS_DAP, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 56, + .links =3D { SM8350_SLAVE_AHB2PHY_SOUTH, + SM8350_SLAVE_AHB2PHY_NORTH, + SM8350_SLAVE_AOSS, + SM8350_SLAVE_APPSS, + SM8350_SLAVE_CAMERA_CFG, + SM8350_SLAVE_CLK_CTL, + SM8350_SLAVE_CDSP_CFG, + SM8350_SLAVE_RBCPR_CX_CFG, + SM8350_SLAVE_RBCPR_MMCX_CFG, + SM8350_SLAVE_RBCPR_MX_CFG, + SM8350_SLAVE_CRYPTO_0_CFG, + SM8350_SLAVE_CX_RDPM, + SM8350_SLAVE_DCC_CFG, + SM8350_SLAVE_DISPLAY_CFG, + SM8350_SLAVE_GFX3D_CFG, + SM8350_SLAVE_HWKM, + SM8350_SLAVE_IMEM_CFG, + SM8350_SLAVE_IPA_CFG, + SM8350_SLAVE_IPC_ROUTER_CFG, + SM8350_SLAVE_LPASS, + SM8350_SLAVE_CNOC_MSS, + SM8350_SLAVE_MX_RDPM, + SM8350_SLAVE_PCIE_0_CFG, + SM8350_SLAVE_PCIE_1_CFG, + SM8350_SLAVE_PDM, + SM8350_SLAVE_PIMEM_CFG, + SM8350_SLAVE_PKA_WRAPPER_CFG, + SM8350_SLAVE_PMU_WRAPPER_CFG, + SM8350_SLAVE_QDSS_CFG, + SM8350_SLAVE_QSPI_0, + SM8350_SLAVE_QUP_0, + SM8350_SLAVE_QUP_1, + SM8350_SLAVE_QUP_2, + SM8350_SLAVE_SDCC_2, + SM8350_SLAVE_SDCC_4, + SM8350_SLAVE_SECURITY, + SM8350_SLAVE_SPSS_CFG, + SM8350_SLAVE_TCSR, + SM8350_SLAVE_TLMM, + SM8350_SLAVE_UFS_CARD_CFG, + SM8350_SLAVE_UFS_MEM_CFG, + SM8350_SLAVE_USB3_0, + SM8350_SLAVE_USB3_1, + SM8350_SLAVE_VENUS_CFG, + SM8350_SLAVE_VSENSE_CTRL_CFG, + SM8350_SLAVE_A1NOC_CFG, + SM8350_SLAVE_A2NOC_CFG, + SM8350_SLAVE_DDRSS_CFG, + SM8350_SLAVE_CNOC_MNOC_CFG, + SM8350_SLAVE_SNOC_CFG, + SM8350_SLAVE_BOOT_IMEM, + SM8350_SLAVE_IMEM, + SM8350_SLAVE_PIMEM, + SM8350_SLAVE_SERVICE_CNOC, + SM8350_SLAVE_QDSS_STM, + SM8350_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_cnoc_dc_noc =3D { + .name =3D "qnm_cnoc_dc_noc", + .id =3D SM8350_MASTER_CNOC_DC_NOC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 2, + .links =3D { SM8350_SLAVE_LLCC_CFG, + SM8350_SLAVE_GEM_NOC_CFG + }, +}; + +static struct qcom_icc_node alm_gpu_tcu =3D { + .name =3D "alm_gpu_tcu", + .id =3D SM8350_MASTER_GPU_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node alm_sys_tcu =3D { + .name =3D "alm_sys_tcu", + .id =3D SM8350_MASTER_SYS_TCU, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 2, + .links =3D { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node chm_apps =3D { + .name =3D "chm_apps", + .id =3D SM8350_MASTER_APPSS_PROC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 3, + .links =3D { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC, + SM8350_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qnm_cmpnoc =3D { + .name =3D "qnm_cmpnoc", + .id =3D SM8350_MASTER_COMPUTE_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_gemnoc_cfg =3D { + .name =3D "qnm_gemnoc_cfg", + .id =3D SM8350_MASTER_GEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 5, + .links =3D { SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, + SM8350_SLAVE_MCDMA_MS_MPU_CFG, + SM8350_SLAVE_SERVICE_GEM_NOC_1, + SM8350_SLAVE_SERVICE_GEM_NOC_2, + SM8350_SLAVE_SERVICE_GEM_NOC + }, +}; + +static struct qcom_icc_node qnm_gpu =3D { + .name =3D "qnm_gpu", + .id =3D SM8350_MASTER_GFX3D, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_mnoc_hf =3D { + .name =3D "qnm_mnoc_hf", + .id =3D SM8350_MASTER_MNOC_HF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_sf =3D { + .name =3D "qnm_mnoc_sf", + .id =3D SM8350_MASTER_MNOC_SF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 2, + .links =3D { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_pcie =3D { + .name =3D "qnm_pcie", + .id =3D SM8350_MASTER_ANOC_PCIE_GEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 2, + .links =3D { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc =3D { + .name =3D "qnm_snoc_gc", + .id =3D SM8350_MASTER_SNOC_GC_MEM_NOC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf =3D { + .name =3D "qnm_snoc_sf", + .id =3D SM8350_MASTER_SNOC_SF_MEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 3, + .links =3D { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC, + SM8350_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qhm_config_noc =3D { + .name =3D "qhm_config_noc", + .id =3D SM8350_MASTER_CNOC_LPASS_AG_NOC, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 6, + .links =3D { SM8350_SLAVE_LPASS_CORE_CFG, + SM8350_SLAVE_LPASS_LPI_CFG, + SM8350_SLAVE_LPASS_MPU_CFG, + SM8350_SLAVE_LPASS_TOP_CFG, + SM8350_SLAVE_SERVICES_LPASS_AML_NOC, + SM8350_SLAVE_SERVICE_LPASS_AG_NOC + }, +}; + +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .id =3D SM8350_MASTER_LLCC, + .channels =3D 4, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_EBI1 }, +}; + +static struct qcom_icc_node qnm_camnoc_hf =3D { + .name =3D "qnm_camnoc_hf", + .id =3D SM8350_MASTER_CAMNOC_HF, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_icp =3D { + .name =3D "qnm_camnoc_icp", + .id =3D SM8350_MASTER_CAMNOC_ICP, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_sf =3D { + .name =3D "qnm_camnoc_sf", + .id =3D SM8350_MASTER_CAMNOC_SF, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mnoc_cfg =3D { + .name =3D "qnm_mnoc_cfg", + .id =3D SM8350_MASTER_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qnm_video0 =3D { + .name =3D "qnm_video0", + .id =3D SM8350_MASTER_VIDEO_P0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video1 =3D { + .name =3D "qnm_video1", + .id =3D SM8350_MASTER_VIDEO_P1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video_cvp =3D { + .name =3D "qnm_video_cvp", + .id =3D SM8350_MASTER_VIDEO_PROC, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 =3D { + .name =3D "qxm_mdp0", + .id =3D SM8350_MASTER_MDP0, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp1 =3D { + .name =3D "qxm_mdp1", + .id =3D SM8350_MASTER_MDP1, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_rot =3D { + .name =3D "qxm_rot", + .id =3D SM8350_MASTER_ROTATOR, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_nsp_noc_config =3D { + .name =3D "qhm_nsp_noc_config", + .id =3D SM8350_MASTER_CDSP_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_SERVICE_NSP_NOC }, +}; + +static struct qcom_icc_node qxm_nsp =3D { + .name =3D "qxm_nsp", + .id =3D SM8350_MASTER_CDSP_PROC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_CDSP_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc =3D { + .name =3D "qnm_aggre1_noc", + .id =3D SM8350_MASTER_A1NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_aggre2_noc =3D { + .name =3D "qnm_aggre2_noc", + .id =3D SM8350_MASTER_A2NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_snoc_cfg =3D { + .name =3D "qnm_snoc_cfg", + .id =3D SM8350_MASTER_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qxm_pimem =3D { + .name =3D "qxm_pimem", + .id =3D SM8350_MASTER_PIMEM, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node xm_gic =3D { + .name =3D "xm_gic", + .id =3D SM8350_MASTER_GIC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node qnm_mnoc_hf_disp =3D { + .name =3D "qnm_mnoc_hf_disp", + .id =3D SM8350_MASTER_MNOC_HF_MEM_NOC_DISP, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_LLCC_DISP }, +}; + +static struct qcom_icc_node qnm_mnoc_sf_disp =3D { + .name =3D "qnm_mnoc_sf_disp", + .id =3D SM8350_MASTER_MNOC_SF_MEM_NOC_DISP, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_LLCC_DISP }, +}; + +static struct qcom_icc_node llcc_mc_disp =3D { + .name =3D "llcc_mc_disp", + .id =3D SM8350_MASTER_LLCC_DISP, + .channels =3D 4, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_EBI1_DISP }, +}; + +static struct qcom_icc_node qxm_mdp0_disp =3D { + .name =3D "qxm_mdp0_disp", + .id =3D SM8350_MASTER_MDP0_DISP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_node qxm_mdp1_disp =3D { + .name =3D "qxm_mdp1_disp", + .id =3D SM8350_MASTER_MDP1_DISP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_node qxm_rot_disp =3D { + .name =3D "qxm_rot_disp", + .id =3D SM8350_MASTER_ROTATOR_DISP, + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_node qns_a1noc_snoc =3D { + .name =3D "qns_a1noc_snoc", + .id =3D SM8350_SLAVE_A1NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8350_MASTER_A1NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre1_noc =3D { + .name =3D "srvc_aggre1_noc", + .id =3D SM8350_SLAVE_SERVICE_A1NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc =3D { + .name =3D "qns_a2noc_snoc", + .id =3D SM8350_SLAVE_A2NOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8350_MASTER_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qns_pcie_mem_noc =3D { + .name =3D "qns_pcie_mem_noc", + .id =3D SM8350_SLAVE_ANOC_PCIE_GEM_NOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8350_MASTER_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc =3D { + .name =3D "srvc_aggre2_noc", + .id =3D SM8350_SLAVE_SERVICE_A2NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy0 =3D { + .name =3D "qhs_ahb2phy0", + .id =3D SM8350_SLAVE_AHB2PHY_SOUTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy1 =3D { + .name =3D "qhs_ahb2phy1", + .id =3D SM8350_SLAVE_AHB2PHY_NORTH, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .id =3D SM8350_SLAVE_AOSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_apss =3D { + .name =3D "qhs_apss", + .id =3D SM8350_SLAVE_APPSS, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_camera_cfg =3D { + .name =3D "qhs_camera_cfg", + .id =3D SM8350_SLAVE_CAMERA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .id =3D SM8350_SLAVE_CLK_CTL, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_compute_cfg =3D { + .name =3D "qhs_compute_cfg", + .id =3D SM8350_SLAVE_CDSP_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_cx =3D { + .name =3D "qhs_cpr_cx", + .id =3D SM8350_SLAVE_RBCPR_CX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_mmcx =3D { + .name =3D "qhs_cpr_mmcx", + .id =3D SM8350_SLAVE_RBCPR_MMCX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cpr_mx =3D { + .name =3D "qhs_cpr_mx", + .id =3D SM8350_SLAVE_RBCPR_MX_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg =3D { + .name =3D "qhs_crypto0_cfg", + .id =3D SM8350_SLAVE_CRYPTO_0_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_cx_rdpm =3D { + .name =3D "qhs_cx_rdpm", + .id =3D SM8350_SLAVE_CX_RDPM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_dcc_cfg =3D { + .name =3D "qhs_dcc_cfg", + .id =3D SM8350_SLAVE_DCC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_display_cfg =3D { + .name =3D "qhs_display_cfg", + .id =3D SM8350_SLAVE_DISPLAY_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg =3D { + .name =3D "qhs_gpuss_cfg", + .id =3D SM8350_SLAVE_GFX3D_CFG, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_hwkm =3D { + .name =3D "qhs_hwkm", + .id =3D SM8350_SLAVE_HWKM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .id =3D SM8350_SLAVE_IMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipa =3D { + .name =3D "qhs_ipa", + .id =3D SM8350_SLAVE_IPA_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipc_router =3D { + .name =3D "qhs_ipc_router", + .id =3D SM8350_SLAVE_IPC_ROUTER_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_lpass_cfg =3D { + .name =3D "qhs_lpass_cfg", + .id =3D SM8350_SLAVE_LPASS, + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .links =3D { SM8350_MASTER_CNOC_LPASS_AG_NOC }, +}; + +static struct qcom_icc_node qhs_mss_cfg =3D { + .name =3D "qhs_mss_cfg", + .id =3D SM8350_SLAVE_CNOC_MSS, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mx_rdpm =3D { + .name =3D "qhs_mx_rdpm", + .id =3D SM8350_SLAVE_MX_RDPM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie0_cfg =3D { + .name =3D "qhs_pcie0_cfg", + .id =3D SM8350_SLAVE_PCIE_0_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie1_cfg =3D { + .name =3D "qhs_pcie1_cfg", + .id =3D SM8350_SLAVE_PCIE_1_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pdm =3D { + .name =3D "qhs_pdm", + .id =3D SM8350_SLAVE_PDM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg =3D { + .name =3D "qhs_pimem_cfg", + .id =3D SM8350_SLAVE_PIMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pka_wrapper_cfg =3D { + .name =3D "qhs_pka_wrapper_cfg", + .id =3D SM8350_SLAVE_PKA_WRAPPER_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pmu_wrapper_cfg =3D { + .name =3D "qhs_pmu_wrapper_cfg", + .id =3D SM8350_SLAVE_PMU_WRAPPER_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .id =3D SM8350_SLAVE_QDSS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qspi =3D { + .name =3D "qhs_qspi", + .id =3D SM8350_SLAVE_QSPI_0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup0 =3D { + .name =3D "qhs_qup0", + .id =3D SM8350_SLAVE_QUP_0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup1 =3D { + .name =3D "qhs_qup1", + .id =3D SM8350_SLAVE_QUP_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup2 =3D { + .name =3D "qhs_qup2", + .id =3D SM8350_SLAVE_QUP_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc2 =3D { + .name =3D "qhs_sdc2", + .id =3D SM8350_SLAVE_SDCC_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc4 =3D { + .name =3D "qhs_sdc4", + .id =3D SM8350_SLAVE_SDCC_4, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_security =3D { + .name =3D "qhs_security", + .id =3D SM8350_SLAVE_SECURITY, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_spss_cfg =3D { + .name =3D "qhs_spss_cfg", + .id =3D SM8350_SLAVE_SPSS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .id =3D SM8350_SLAVE_TCSR, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm =3D { + .name =3D "qhs_tlmm", + .id =3D SM8350_SLAVE_TLMM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_card_cfg =3D { + .name =3D "qhs_ufs_card_cfg", + .id =3D SM8350_SLAVE_UFS_CARD_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg =3D { + .name =3D "qhs_ufs_mem_cfg", + .id =3D SM8350_SLAVE_UFS_MEM_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_0 =3D { + .name =3D "qhs_usb3_0", + .id =3D SM8350_SLAVE_USB3_0, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_1 =3D { + .name =3D "qhs_usb3_1", + .id =3D SM8350_SLAVE_USB3_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_venus_cfg =3D { + .name =3D "qhs_venus_cfg", + .id =3D SM8350_SLAVE_VENUS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { + .name =3D "qhs_vsense_ctrl_cfg", + .id =3D SM8350_SLAVE_VSENSE_CTRL_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_a1_noc_cfg =3D { + .name =3D "qns_a1_noc_cfg", + .id =3D SM8350_SLAVE_A1NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_a2_noc_cfg =3D { + .name =3D "qns_a2_noc_cfg", + .id =3D SM8350_SLAVE_A2NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_ddrss_cfg =3D { + .name =3D "qns_ddrss_cfg", + .id =3D SM8350_SLAVE_DDRSS_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_mnoc_cfg =3D { + .name =3D "qns_mnoc_cfg", + .id =3D SM8350_SLAVE_CNOC_MNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_snoc_cfg =3D { + .name =3D "qns_snoc_cfg", + .id =3D SM8350_SLAVE_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qxs_boot_imem =3D { + .name =3D "qxs_boot_imem", + .id =3D SM8350_SLAVE_BOOT_IMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .id =3D SM8350_SLAVE_IMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qxs_pimem =3D { + .name =3D "qxs_pimem", + .id =3D SM8350_SLAVE_PIMEM, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node srvc_cnoc =3D { + .name =3D "srvc_cnoc", + .id =3D SM8350_SLAVE_SERVICE_CNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_pcie_0 =3D { + .name =3D "xs_pcie_0", + .id =3D SM8350_SLAVE_PCIE_0, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node xs_pcie_1 =3D { + .name =3D "xs_pcie_1", + .id =3D SM8350_SLAVE_PCIE_1, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .id =3D SM8350_SLAVE_QDSS_STM, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .id =3D SM8350_SLAVE_TCU, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_llcc =3D { + .name =3D "qhs_llcc", + .id =3D SM8350_SLAVE_LLCC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_gemnoc =3D { + .name =3D "qns_gemnoc", + .id =3D SM8350_SLAVE_GEM_NOC_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg =3D { + .name =3D "qhs_mdsp_ms_mpu_cfg", + .id =3D SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_modem_ms_mpu_cfg =3D { + .name =3D "qhs_modem_ms_mpu_cfg", + .id =3D SM8350_SLAVE_MCDMA_MS_MPU_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_gem_noc_cnoc =3D { + .name =3D "qns_gem_noc_cnoc", + .id =3D SM8350_SLAVE_GEM_NOC_CNOC, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8350_MASTER_GEM_NOC_CNOC }, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .id =3D SM8350_SLAVE_LLCC, + .channels =3D 4, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8350_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_pcie =3D { + .name =3D "qns_pcie", + .id =3D SM8350_SLAVE_MEM_NOC_PCIE_SNOC, + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node srvc_even_gemnoc =3D { + .name =3D "srvc_even_gemnoc", + .id =3D SM8350_SLAVE_SERVICE_GEM_NOC_1, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_odd_gemnoc =3D { + .name =3D "srvc_odd_gemnoc", + .id =3D SM8350_SLAVE_SERVICE_GEM_NOC_2, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_sys_gemnoc =3D { + .name =3D "srvc_sys_gemnoc", + .id =3D SM8350_SLAVE_SERVICE_GEM_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_lpass_core =3D { + .name =3D "qhs_lpass_core", + .id =3D SM8350_SLAVE_LPASS_CORE_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_lpass_lpi =3D { + .name =3D "qhs_lpass_lpi", + .id =3D SM8350_SLAVE_LPASS_LPI_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_lpass_mpu =3D { + .name =3D "qhs_lpass_mpu", + .id =3D SM8350_SLAVE_LPASS_MPU_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_lpass_top =3D { + .name =3D "qhs_lpass_top", + .id =3D SM8350_SLAVE_LPASS_TOP_CFG, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_niu_aml_noc =3D { + .name =3D "srvc_niu_aml_noc", + .id =3D SM8350_SLAVE_SERVICES_LPASS_AML_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node srvc_niu_lpass_agnoc =3D { + .name =3D "srvc_niu_lpass_agnoc", + .id =3D SM8350_SLAVE_SERVICE_LPASS_AG_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .id =3D SM8350_SLAVE_EBI1, + .channels =3D 4, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf =3D { + .name =3D "qns_mem_noc_hf", + .id =3D SM8350_SLAVE_MNOC_HF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8350_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_sf =3D { + .name =3D "qns_mem_noc_sf", + .id =3D SM8350_SLAVE_MNOC_SF_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8350_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc =3D { + .name =3D "srvc_mnoc", + .id =3D SM8350_SLAVE_SERVICE_MNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_nsp_gemnoc =3D { + .name =3D "qns_nsp_gemnoc", + .id =3D SM8350_SLAVE_CDSP_MEM_NOC, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8350_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node service_nsp_noc =3D { + .name =3D "service_nsp_noc", + .id =3D SM8350_SLAVE_SERVICE_NSP_NOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_gemnoc_gc =3D { + .name =3D "qns_gemnoc_gc", + .id =3D SM8350_SLAVE_SNOC_GEM_NOC_GC, + .channels =3D 1, + .buswidth =3D 8, + .num_links =3D 1, + .links =3D { SM8350_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf =3D { + .name =3D "qns_gemnoc_sf", + .id =3D SM8350_SLAVE_SNOC_GEM_NOC_SF, + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8350_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_snoc =3D { + .name =3D "srvc_snoc", + .id =3D SM8350_SLAVE_SERVICE_SNOC, + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_llcc_disp =3D { + .name =3D "qns_llcc_disp", + .id =3D SM8350_SLAVE_LLCC_DISP, + .channels =3D 4, + .buswidth =3D 16, + .num_links =3D 1, + .links =3D { SM8350_MASTER_LLCC_DISP }, +}; + +static struct qcom_icc_node ebi_disp =3D { + .name =3D "ebi_disp", + .id =3D SM8350_SLAVE_EBI1_DISP, + .channels =3D 4, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf_disp =3D { + .name =3D "qns_mem_noc_hf_disp", + .id =3D SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8350_MASTER_MNOC_HF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_node qns_mem_noc_sf_disp =3D { + .name =3D "qns_mem_noc_sf_disp", + .id =3D SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP, + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .links =3D { SM8350_MASTER_MNOC_SF_MEM_NOC_DISP }, +}; =20 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C277C001DF for ; Tue, 11 Jul 2023 12:20:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231223AbjGKMT7 (ORCPT ); Tue, 11 Jul 2023 08:19:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231724AbjGKMT1 (ORCPT ); Tue, 11 Jul 2023 08:19:27 -0400 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E15D19B0 for ; Tue, 11 Jul 2023 05:18:49 -0700 (PDT) Received: by mail-lj1-x234.google.com with SMTP id 38308e7fff4ca-2b700e85950so85728631fa.3 for ; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:46 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:14 +0200 Subject: [PATCH 15/53] interconnect: qcom: icc-rpmh: Retire DEFINE_QNODE MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-15-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1035; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=kHFYhvlY9z4u9L1Ts/vi+fhd70LPx+luqOhBOolka64=; b=0xbIo75fo3cNjRAMFxhCFUs4IIy6AMpuo711GhCylZMRRZCFSfXpfzHqG92M16+O4q4Csl5zp GbYMrpa22bCAlI/WEeuiq5qaU0YpSMQiIHZ/lORQZ+CHF/PssjbYJ8C X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This helper has no users anymore. Kill it with heavy fire. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/icc-rpmh.h | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qc= om/icc-rpmh.h index 5634d302963a..e0b40e313f08 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -122,16 +122,6 @@ struct qcom_icc_desc { size_t num_bcms; }; =20 -#define DEFINE_QNODE(_name, _id, _channels, _buswidth, ...) \ - static struct qcom_icc_node _name =3D { \ - .id =3D _id, \ - .name =3D #_name, \ - .channels =3D _channels, \ - .buswidth =3D _buswidth, \ - .num_links =3D ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ - .links =3D { __VA_ARGS__ }, \ - } - int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, u32 peak_bw, u32 *agg_avg, u32 *agg_peak); int qcom_icc_set(struct icc_node *src, struct icc_node *dst); --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A883EB64DC for ; Tue, 11 Jul 2023 12:20:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231920AbjGKMUC (ORCPT ); Tue, 11 Jul 2023 08:20:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231737AbjGKMT2 (ORCPT ); Tue, 11 Jul 2023 08:19:28 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A276610F2 for ; Tue, 11 Jul 2023 05:18:50 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id 38308e7fff4ca-2b6f52e1c5cso88500841fa.1 for ; Tue, 11 Jul 2023 05:18:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689077928; x=1691669928; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=JV2NOHdhXQJvyF0fc5slrvpV1+3GiCLz+u7Y70t3daI=; b=RF7r80co6+7JAiqhVm/o6zgc1sERtm3oKQc+xsMeDyXGrM8h8i8K+DIjqJCr9HQxeu ZgRbimW0j8qeKzBSpWEpSBZnV8pTWM3+Rv9BTR9Ii27wvVc4PrdlDsW2xLybxjYTUsqZ 4Ban1NFmSGZDVMiUYGsX6mlltkSsGqa3o4Dl9HVMq5iiytKEBrnx/iM4lQjUavk0E/CJ jm/TRclWD+XzhJolCyG6mXZLbo+l1IRTDvYDsYqz15Ndv9TfALCPsAWHHTLKsJ3vWxCU l7xrw7ZmeDy6KkOae/hPlTtRbAemJ9+MtuE7vPQMlSWOFoCwKP84JRQgG8qJnNoRomba EOJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689077928; x=1691669928; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JV2NOHdhXQJvyF0fc5slrvpV1+3GiCLz+u7Y70t3daI=; b=kx4W6VDgrCYQ+by27gZOx8LANij85bES/xjBWbjBcwDmW1JClc/nCpzWiZiq8G3zR3 RSMIn1iJiqBbeyh19SYTPa9rBAttOI5CRqZC+3oZJ5nakN7O1Cn01M+Hz5GVoZ9U2N8i +W4zspor6xW3L7KpDLmXBcdu4GFdHPyoP1IqtShqkvEYV09RWILlqrE8aJF2bfCyVD6O BR71kHS3UtDNjUUfKU4+Y42BKyj1FNZUsYRHgv8pXPEshaVJzpE+6516EHMrF5UU+6fQ fU82AiR671PYLTHiAUu1E+69h6QjM0xQLL4SBWrZVpdYJjZzjR8BU05N6Sl4NHq5eMIa KNqw== X-Gm-Message-State: ABy/qLbBqQPYxO/TzY+GOiBm6kZ8gvSyYIZP5S09j45/2pA8b6anqfIJ y1NaExCp+Oho+Z7RJu7EEFL1bg== X-Google-Smtp-Source: APBJJlHu2FvrJIoWXBM6wuPl/9utO+3HwVtRyrdEOjehHQCrOn64z/yGaRjMC9VfvdvNvBOrkPgl1A== X-Received: by 2002:a2e:740a:0:b0:2b6:c4be:8397 with SMTP id p10-20020a2e740a000000b002b6c4be8397mr12824468ljc.20.1689077928500; Tue, 11 Jul 2023 05:18:48 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:48 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:15 +0200 Subject: [PATCH 16/53] interconnect: qcom: sc7180: Retire DEFINE_QBCM MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-16-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=8531; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=z5wK9eZaguqOGRFKwow1eBaPyqCaSpkZDfuYMwlOGz0=; b=lkxrf35BwbC2UuSnZtJLbD7icxmUVnr1eFa3xKWoGtYaeSGTrASIhgtVs6IhS77YPHhrUs2Fc SoppQwAXXkxCIZzArfY9UH+aAKHJtmGnPz5Svdxl7lBSSWYA/U/o9JM X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sc7180.c | 279 +++++++++++++++++++++++++++++++++= ---- 1 file changed, 255 insertions(+), 24 deletions(-) diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom= /sc7180.c index d1b0427f8781..3629dee4448b 100644 --- a/drivers/interconnect/qcom/sc7180.c +++ b/drivers/interconnect/qcom/sc7180.c @@ -1235,30 +1235,261 @@ static struct qcom_icc_node xs_sys_tcu_cfg =3D { .buswidth =3D 8, }; =20 -DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg= , &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aop, &qhs_aoss, &qhs_boot_rom, &qhs_= camera_cfg, &qhs_camera_nrt_throttle_cfg, &qhs_camera_rt_throttle_cfg, &qhs= _clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_dd= rss_cfg, &qhs_display_cfg, &qhs_display_rt_throttle_cfg, &qhs_display_throt= tle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, = &qhs_mss_cfg, &qhs_npu_cfg, &qhs_npu_dma_throttle_cfg, &qhs_npu_dsp_throttl= e_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_c= fg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlm= m_1, &qhs_tlmm_2, &qhs_tlmm_3, &qhs_ufs_mem_cfg, &qhs_usb3, &qhs_venus_cfg,= &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc); -DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1= _uncomp, &qxm_camnoc_sf_uncomp, &qhm_mnoc_cfg, &qxm_mdp0, &qxm_rot, &qxm_ve= nus0, &qxm_venus_arm9); -DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu); -DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup_core_master_1, &qup_core_master_= 2); -DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc); -DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps0); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf); -DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_cn1, "CN1", false, &qhm_qspi, &xm_sdc2, &xm_emmc, &qhs_ahb= 2phy2, &qhs_emmc_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2); -DEFINE_QBCM(bcm_sn2, "SN2", false, &qxm_pimem, &qns_gemnoc_gc); -DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu); -DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem); -DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp); -DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc); -DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre2_noc); -DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gemnoc); +static struct qcom_icc_bcm bcm_acv =3D { + .name =3D "ACV", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mc0 =3D { + .name =3D "MC0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_sh0 =3D { + .name =3D "SH0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_mm0 =3D { + .name =3D "MM0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_ce0 =3D { + .name =3D "CE0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 =3D { + .name =3D "CN0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 48, + .nodes =3D { &qnm_snoc, + &xm_qdss_dap, + &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_ahb2phy0, + &qhs_aop, + &qhs_aoss, + &qhs_boot_rom, + &qhs_camera_cfg, + &qhs_camera_nrt_throttle_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_clk_ctl, + &qhs_cpr_cx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_display_rt_throttle_cfg, + &qhs_display_throttle_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_mss_cfg, + &qhs_npu_cfg, + &qhs_npu_dma_throttle_cfg, + &qhs_npu_dsp_throttle_cfg, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qm_cfg, + &qhs_qm_mpu_cfg, + &qhs_qup0, + &qhs_qup1, + &qhs_security, + &qhs_snoc_cfg, + &qhs_tcsr, + &qhs_tlmm_1, + &qhs_tlmm_2, + &qhs_tlmm_3, + &qhs_ufs_mem_cfg, + &qhs_usb3, + &qhs_venus_cfg, + &qhs_venus_throttle_cfg, + &qhs_vsense_ctrl_cfg, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_mm1 =3D { + .name =3D "MM1", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 8, + .nodes =3D { &qxm_camnoc_hf0_uncomp, + &qxm_camnoc_hf1_uncomp, + &qxm_camnoc_sf_uncomp, + &qhm_mnoc_cfg, + &qxm_mdp0, + &qxm_rot, + &qxm_venus0, + &qxm_venus_arm9 + }, +}; + +static struct qcom_icc_bcm bcm_sh2 =3D { + .name =3D "SH2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &acm_sys_tcu }, +}; + +static struct qcom_icc_bcm bcm_mm2 =3D { + .name =3D "MM2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_qup0 =3D { + .name =3D "QUP0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qup_core_master_1, &qup_core_master_2 }, +}; + +static struct qcom_icc_bcm bcm_sh3 =3D { + .name =3D "SH3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_cmpnoc }, +}; + +static struct qcom_icc_bcm bcm_sh4 =3D { + .name =3D "SH4", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &acm_apps0 }, +}; + +static struct qcom_icc_bcm bcm_sn0 =3D { + .name =3D "SN0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_co0 =3D { + .name =3D "CO0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_cdsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_sn1 =3D { + .name =3D "SN1", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_cn1 =3D { + .name =3D "CN1", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 8, + .nodes =3D { &qhm_qspi, + &xm_sdc2, + &xm_emmc, + &qhs_ahb2phy2, + &qhs_emmc_cfg, + &qhs_pdm, + &qhs_qspi, + &qhs_sdc2 + }, +}; + +static struct qcom_icc_bcm bcm_sn2 =3D { + .name =3D "SN2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qxm_pimem, &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_co2 =3D { + .name =3D "CO2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_npu }, +}; + +static struct qcom_icc_bcm bcm_sn3 =3D { + .name =3D "SN3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_co3 =3D { + .name =3D "CO3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxm_npu_dsp }, +}; + +static struct qcom_icc_bcm bcm_sn4 =3D { + .name =3D "SN4", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn7 =3D { + .name =3D "SN7", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn9 =3D { + .name =3D "SN9", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn12 =3D { + .name =3D "SN12", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_gemnoc }, +}; =20 static struct qcom_icc_bcm * const aggre1_noc_bcms[] =3D { &bcm_cn1, --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0AF1EB64DD for ; Tue, 11 Jul 2023 12:20:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232052AbjGKMUG (ORCPT ); Tue, 11 Jul 2023 08:20:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231917AbjGKMT2 (ORCPT ); Tue, 11 Jul 2023 08:19:28 -0400 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B41E19BA for ; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:49 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:16 +0200 Subject: [PATCH 17/53] interconnect: qcom: sdm670: Retire DEFINE_QBCM MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-17-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=8074; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=8HeC5O9fAYtInntL0QiwX8CnifnzRAUfXIiKtq/eVkU=; b=R15de6emMH6T9UWZlbP6B9fTaKRaPR57Wh7xfaJn8rdLlWXHZ+fKMxLOhd1dJt8jJEERDH5bZ kyZukWSgye7AYuhvFzz+y7gZlwGtSJCKb+S+5WtZesmHdmpTRH8scb4 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sdm670.c | 263 +++++++++++++++++++++++++++++++++= ---- 1 file changed, 239 insertions(+), 24 deletions(-) diff --git a/drivers/interconnect/qcom/sdm670.c b/drivers/interconnect/qcom= /sdm670.c index 2c2cbe1b5197..c13ccdd5841d 100644 --- a/drivers/interconnect/qcom/sdm670.c +++ b/drivers/interconnect/qcom/sdm670.c @@ -1044,30 +1044,245 @@ static struct qcom_icc_node xs_sys_tcu_cfg =3D { .buswidth =3D 8, }; =20 -DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); -DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_apps_io); -DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_= uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0,= &qxm_mdp1); -DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_memnoc_snoc); -DEFINE_QBCM(bcm_mm2, "MM2", false, &qns2_mem_noc); -DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_tcu); -DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, = &qxm_venus1, &qxm_venus_arm9); -DEFINE_QBCM(bcm_sh5, "SH5", false, &qnm_apps); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_memnoc_sf); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &= qhs_a2_noc_cfg, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_co= mpute_dsp_cfg, &qhs_cpr_cx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg,= &qhs_display_cfg, &qhs_emmc_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, = &qhs_ipa, &qhs_mnoc_cfg, &qhs_pdm, &qhs_phy_refgen_south, &qhs_pimem_cfg, &= qhs_prng, &qhs_qdss_cfg, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qh= s_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_tcsr, &qhs_tlmm_north, &qhs_tlmm_sou= th, &qhs_tsif, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_venus_cfg, &qhs_vsense_c= trl_cfg, &qns_cnoc_a2noc, &srvc_cnoc); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_memnoc_gc); -DEFINE_QBCM(bcm_sn3, "SN3", false, &qns_cnoc); -DEFINE_QBCM(bcm_sn4, "SN4", false, &qxm_pimem, &qxs_pimem); -DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre1_noc, &srvc_aggre1_noc); -DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_aggre2_noc, &srvc_aggre2_noc); -DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gladiator_sodv, &xm_gic); -DEFINE_QBCM(bcm_sn13, "SN13", false, &qnm_memnoc); +static struct qcom_icc_bcm bcm_acv =3D { + .name =3D "ACV", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mc0 =3D { + .name =3D "MC0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_sh0 =3D { + .name =3D "SH0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_mm0 =3D { + .name =3D "MM0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_sh1 =3D { + .name =3D "SH1", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_apps_io }, +}; + +static struct qcom_icc_bcm bcm_mm1 =3D { + .name =3D "MM1", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 7, + .nodes =3D { &qxm_camnoc_hf0_uncomp, + &qxm_camnoc_hf1_uncomp, + &qxm_camnoc_sf_uncomp, + &qxm_camnoc_hf0, + &qxm_camnoc_hf1, + &qxm_mdp0, + &qxm_mdp1 + }, +}; + +static struct qcom_icc_bcm bcm_sh2 =3D { + .name =3D "SH2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_memnoc_snoc }, +}; + +static struct qcom_icc_bcm bcm_mm2 =3D { + .name =3D "MM2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns2_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_sh3 =3D { + .name =3D "SH3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &acm_tcu }, +}; + +static struct qcom_icc_bcm bcm_mm3 =3D { + .name =3D "MM3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 5, + .nodes =3D { &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_ven= us_arm9 }, +}; + +static struct qcom_icc_bcm bcm_sh5 =3D { + .name =3D "SH5", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 =3D { + .name =3D "SN0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_memnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_ce0 =3D { + .name =3D "CE0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 =3D { + .name =3D "CN0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 41, + .nodes =3D { &qhm_spdm, + &qnm_snoc, + &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_aop, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp_cfg, + &qhs_cpr_cx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_emmc_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_pdm, + &qhs_phy_refgen_south, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qupv3_north, + &qhs_qupv3_south, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_spdm, + &qhs_tcsr, + &qhs_tlmm_north, + &qhs_tlmm_south, + &qhs_tsif, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_qup0 =3D { + .name =3D "QUP0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qhm_qup1, &qhm_qup2 }, +}; + +static struct qcom_icc_bcm bcm_sn1 =3D { + .name =3D "SN1", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_sn2 =3D { + .name =3D "SN2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_memnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn3 =3D { + .name =3D "SN3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_cnoc }, +}; + +static struct qcom_icc_bcm bcm_sn4 =3D { + .name =3D "SN4", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qxm_pimem, &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn5 =3D { + .name =3D "SN5", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn8 =3D { + .name =3D "SN8", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qnm_aggre1_noc, &srvc_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn10 =3D { + .name =3D "SN10", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qnm_aggre2_noc, &srvc_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn11 =3D { + .name =3D "SN11", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qnm_gladiator_sodv, &xm_gic }, +}; + +static struct qcom_icc_bcm bcm_sn13 =3D { + .name =3D "SN13", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_memnoc }, +}; =20 static struct qcom_icc_bcm * const aggre1_noc_bcms[] =3D { &bcm_qup0, --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F26A1C001E0 for ; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:50 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:17 +0200 Subject: [PATCH 18/53] interconnect: qcom: sdm845: Retire DEFINE_QBCM MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-18-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=9245; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ssXuHafj1ZDCbbonhxge+YDkgDx8WaBw7/dlRD6KWU0=; b=kyUwAelmuHa0aGRAJw+drBSeWz4L0zOcjTagal7f6G16iGADNeYhg/vTHLQ0bD9pQBn42fBF1 apI5brH4xFtDwJ4xHyKuHhp78DkVP2p3IFDFWBVpIEsQbRhXmG29uYY X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sdm845.c | 305 +++++++++++++++++++++++++++++++++= ---- 1 file changed, 277 insertions(+), 28 deletions(-) diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom= /sdm845.c index 5caf6e5aeeca..26fade7a0ce5 100644 --- a/drivers/interconnect/qcom/sdm845.c +++ b/drivers/interconnect/qcom/sdm845.c @@ -1262,34 +1262,283 @@ static struct qcom_icc_node xs_sys_tcu_cfg =3D { .buswidth =3D 8, }; =20 -DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf); -DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_apps_io); -DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_= uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0,= &qxm_mdp1); -DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_memnoc_snoc); -DEFINE_QBCM(bcm_mm2, "MM2", false, &qns2_mem_noc); -DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_tcu); -DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, = &qxm_venus1, &qxm_venus_arm9); -DEFINE_QBCM(bcm_sh5, "SH5", false, &qnm_apps); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_memnoc_sf); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_cn0, "CN0", false, &qhm_spdm, &qhm_tic, &qnm_snoc, &xm_qds= s_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_aop, &qhs_aoss, &qhs_camera_c= fg, &qhs_clk_ctl, &qhs_compute_dsp_cfg, &qhs_cpr_cx, &qhs_crypto0_cfg, &qhs= _dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_= imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_pcie0_cfg, &qhs_pcie_gen3_cfg, &qhs= _pdm, &qhs_phy_refgen_south, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs= _qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_s= pdm, &qhs_spss_cfg, &qhs_tcsr, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tsif,= &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_= cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_memnoc_gc); -DEFINE_QBCM(bcm_sn3, "SN3", false, &qns_cnoc); -DEFINE_QBCM(bcm_sn4, "SN4", false, &qxm_pimem); -DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn6, "SN6", false, &qhs_apss, &srvc_snoc, &xs_sys_tcu_cfg); -DEFINE_QBCM(bcm_sn7, "SN7", false, &qxs_pcie); -DEFINE_QBCM(bcm_sn8, "SN8", false, &qxs_pcie_gen3); -DEFINE_QBCM(bcm_sn9, "SN9", false, &srvc_aggre1_noc, &qnm_aggre1_noc); -DEFINE_QBCM(bcm_sn11, "SN11", false, &srvc_aggre2_noc, &qnm_aggre2_noc); -DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gladiator_sodv, &xm_gic); -DEFINE_QBCM(bcm_sn14, "SN14", false, &qnm_pcie_anoc); -DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_memnoc); +static struct qcom_icc_bcm bcm_acv =3D { + .name =3D "ACV", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mc0 =3D { + .name =3D "MC0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_sh0 =3D { + .name =3D "SH0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_mm0 =3D { + .name =3D "MM0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_sh1 =3D { + .name =3D "SH1", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_apps_io }, +}; + +static struct qcom_icc_bcm bcm_mm1 =3D { + .name =3D "MM1", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 7, + .nodes =3D { &qxm_camnoc_hf0_uncomp, + &qxm_camnoc_hf1_uncomp, + &qxm_camnoc_sf_uncomp, + &qxm_camnoc_hf0, + &qxm_camnoc_hf1, + &qxm_mdp0, + &qxm_mdp1 + }, +}; + +static struct qcom_icc_bcm bcm_sh2 =3D { + .name =3D "SH2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_memnoc_snoc }, +}; + +static struct qcom_icc_bcm bcm_mm2 =3D { + .name =3D "MM2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns2_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_sh3 =3D { + .name =3D "SH3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &acm_tcu }, +}; + +static struct qcom_icc_bcm bcm_mm3 =3D { + .name =3D "MM3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 5, + .nodes =3D { &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_ven= us_arm9 }, +}; + +static struct qcom_icc_bcm bcm_sh5 =3D { + .name =3D "SH5", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 =3D { + .name =3D "SN0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_memnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_ce0 =3D { + .name =3D "CE0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 =3D { + .name =3D "CN0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 47, + .nodes =3D { &qhm_spdm, + &qhm_tic, + &qnm_snoc, + &xm_qdss_dap, + &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_aop, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp_cfg, + &qhs_cpr_cx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_pcie0_cfg, + &qhs_pcie_gen3_cfg, + &qhs_pdm, + &qhs_phy_refgen_south, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qupv3_north, + &qhs_qupv3_south, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_spdm, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm_north, + &qhs_tlmm_south, + &qhs_tsif, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_qup0 =3D { + .name =3D "QUP0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qhm_qup1, &qhm_qup2 }, +}; + +static struct qcom_icc_bcm bcm_sn1 =3D { + .name =3D "SN1", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_sn2 =3D { + .name =3D "SN2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_memnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn3 =3D { + .name =3D "SN3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_cnoc }, +}; + +static struct qcom_icc_bcm bcm_sn4 =3D { + .name =3D "SN4", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxm_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn5 =3D { + .name =3D "SN5", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn6 =3D { + .name =3D "SN6", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 3, + .nodes =3D { &qhs_apss, &srvc_snoc, &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_bcm bcm_sn7 =3D { + .name =3D "SN7", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxs_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn8 =3D { + .name =3D "SN8", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxs_pcie_gen3 }, +}; + +static struct qcom_icc_bcm bcm_sn9 =3D { + .name =3D "SN9", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &srvc_aggre1_noc, &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn11 =3D { + .name =3D "SN11", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &srvc_aggre2_noc, &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn12 =3D { + .name =3D "SN12", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qnm_gladiator_sodv, &xm_gic }, +}; + +static struct qcom_icc_bcm bcm_sn14 =3D { + .name =3D "SN14", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_pcie_anoc }, +}; + +static struct qcom_icc_bcm bcm_sn15 =3D { + .name =3D "SN15", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_memnoc }, +}; =20 static struct qcom_icc_bcm * const aggre1_noc_bcms[] =3D { &bcm_sn9, --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3929EC001E0 for ; Tue, 11 Jul 2023 12:20:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232118AbjGKMUV (ORCPT ); Tue, 11 Jul 2023 08:20:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231960AbjGKMTi (ORCPT ); Tue, 11 Jul 2023 08:19:38 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9252C1BDA for ; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:51 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:18 +0200 Subject: [PATCH 19/53] interconnect: qcom: sdx55: Retire DEFINE_QBCM MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-19-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=5432; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=R92aM77XVZAqKQuJtDwodh3d1IHCkhMpDQVlwb6kTv0=; b=ASDIVUzeQZ9QMHjM49gGjQWUBVfYt6YMoSX818QYw/+a/Q3qoJ8RNZ/VHzK4anO+KxSqsbUHf f4DOgaD4pyaAUjtd9IwCjIMLH32BgKxrDiIBpbODkXdiH8kIQKg0fnh X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sdx55.c | 180 +++++++++++++++++++++++++++++++++-= ---- 1 file changed, 159 insertions(+), 21 deletions(-) diff --git a/drivers/interconnect/qcom/sdx55.c b/drivers/interconnect/qcom/= sdx55.c index 2b5e8873eaa5..968b7b953912 100644 --- a/drivers/interconnect/qcom/sdx55.c +++ b/drivers/interconnect/qcom/sdx55.c @@ -642,27 +642,165 @@ static struct qcom_icc_node xs_sys_tcu_cfg =3D { .buswidth =3D 8, }; =20 -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_pn0, "PN0", false, &qhm_snoc_cfg); -DEFINE_QBCM(bcm_sh3, "SH3", false, &xm_apps_rdwr); -DEFINE_QBCM(bcm_sh4, "SH4", false, &qns_memnoc_snoc, &qns_sys_pcie); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_snoc_memnoc); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_pn1, "PN1", false, &xm_sdc1); -DEFINE_QBCM(bcm_pn2, "PN2", false, &qhm_audio, &qhm_spmi_fetcher1); -DEFINE_QBCM(bcm_sn3, "SN3", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_pn3, "PN3", false, &qhm_blsp1, &qhm_qpic); -DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_sys_tcu_cfg); -DEFINE_QBCM(bcm_pn5, "PN5", false, &qxm_crypto); -DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie); -DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre_noc, &xm_emac, &xm_emac, &xm= _usb3, - &qns_aggre_noc); -DEFINE_QBCM(bcm_sn8, "SN8", false, &qhm_qdss_bam, &xm_qdss_etr); -DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_memnoc); -DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_memnoc_pcie); -DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_ipa, &xm_ipa2pcie_slv); +static struct qcom_icc_bcm bcm_mc0 =3D { + .name =3D "MC0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_sh0 =3D { + .name =3D "SH0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_ce0 =3D { + .name =3D "CE0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_pn0 =3D { + .name =3D "PN0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qhm_snoc_cfg }, +}; + +static struct qcom_icc_bcm bcm_sh3 =3D { + .name =3D "SH3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &xm_apps_rdwr }, +}; + +static struct qcom_icc_bcm bcm_sh4 =3D { + .name =3D "SH4", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qns_memnoc_snoc, &qns_sys_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn0 =3D { + .name =3D "SN0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_snoc_memnoc }, +}; + +static struct qcom_icc_bcm bcm_sn1 =3D { + .name =3D "SN1", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_pn1 =3D { + .name =3D "PN1", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &xm_sdc1 }, +}; + +static struct qcom_icc_bcm bcm_pn2 =3D { + .name =3D "PN2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qhm_audio, &qhm_spmi_fetcher1 }, +}; + +static struct qcom_icc_bcm bcm_sn3 =3D { + .name =3D "SN3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_pn3 =3D { + .name =3D "PN3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qhm_blsp1, &qhm_qpic }, +}; + +static struct qcom_icc_bcm bcm_sn4 =3D { + .name =3D "SN4", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_bcm bcm_pn5 =3D { + .name =3D "PN5", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_sn6 =3D { + .name =3D "SN6", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &xs_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn7 =3D { + .name =3D "SN7", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 5, + .nodes =3D { &qnm_aggre_noc, &xm_emac, &xm_emac, &xm_usb3, &qns_aggre_noc= }, +}; + +static struct qcom_icc_bcm bcm_sn8 =3D { + .name =3D "SN8", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qhm_qdss_bam, &xm_qdss_etr }, +}; + +static struct qcom_icc_bcm bcm_sn9 =3D { + .name =3D "SN9", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_memnoc }, +}; + +static struct qcom_icc_bcm bcm_sn10 =3D { + .name =3D "SN10", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_memnoc_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn11 =3D { + .name =3D "SN11", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qnm_ipa, &xm_ipa2pcie_slv }, +}; =20 static struct qcom_icc_bcm * const mc_virt_bcms[] =3D { &bcm_mc0, --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 491F1C001DD for ; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:53 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:19 +0200 Subject: [PATCH 20/53] interconnect: qcom: sdx65: Retire DEFINE_QBCM MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-20-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=6218; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Fdsj7Q8qluuHDSxo4HSyUvvKfsGRHI1pvdy6XHDDsKo=; b=9lSQq6+ZIpxll0H/JERMHh/63NXuDH5sC5z5byZrPdLmDqG6Y8+4slb8XxQ7q3ZYznonHtN9K qAJ9iEaVbg2AqKcaNU5XSSrczELv5nOez3VrH5wqLB4XEs8xCQ1p/a1 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sdx65.c | 205 ++++++++++++++++++++++++++++++++++= ---- 1 file changed, 185 insertions(+), 20 deletions(-) diff --git a/drivers/interconnect/qcom/sdx65.c b/drivers/interconnect/qcom/= sdx65.c index bebed036fe7a..881a39c172e3 100644 --- a/drivers/interconnect/qcom/sdx65.c +++ b/drivers/interconnect/qcom/sdx65.c @@ -603,26 +603,191 @@ static struct qcom_icc_node xs_sys_tcu_cfg =3D { .buswidth =3D 8, }; =20 -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_pn0, "PN0", true, &qhm_snoc_cfg, &qhs_aoss, &qhs_apss, &qh= s_audio, &qhs_blsp1, &qhs_clk_ctl, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_e= cc_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mss_cfg, &qhs_pcie_parf, &qhs_pdm, &q= hs_prng, &qhs_qdss_cfg, &qhs_qpic, &qhs_sdc1, &qhs_snoc_cfg, &qhs_spmi_fetc= her, &qhs_spmi_vgi_coex, &qhs_tcsr, &qhs_tlmm, &qhs_usb3, &qhs_usb3_phy, &s= rvc_snoc); -DEFINE_QBCM(bcm_pn1, "PN1", false, &xm_sdc1); -DEFINE_QBCM(bcm_pn2, "PN2", false, &qhm_audio, &qhm_spmi_fetcher1); -DEFINE_QBCM(bcm_pn3, "PN3", false, &qhm_blsp1, &qhm_qpic); -DEFINE_QBCM(bcm_pn4, "PN4", false, &qxm_crypto); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_memnoc_snoc); -DEFINE_QBCM(bcm_sh3, "SH3", false, &xm_apps_rdwr); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_snoc_memnoc); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_sn2, "SN2", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn3, "SN3", false, &xs_sys_tcu_cfg); -DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie); -DEFINE_QBCM(bcm_sn6, "SN6", false, &qhm_qdss_bam, &xm_qdss_etr); -DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre_noc, &xm_pcie, &xm_usb3, &qn= s_aggre_noc); -DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_memnoc); -DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_memnoc_pcie); -DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_ipa, &xm_ipa2pcie_slv); +static struct qcom_icc_bcm bcm_ce0 =3D { + .name =3D "CE0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_mc0 =3D { + .name =3D "MC0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_pn0 =3D { + .name =3D "PN0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 26, + .nodes =3D { &qhm_snoc_cfg, + &qhs_aoss, + &qhs_apss, + &qhs_audio, + &qhs_blsp1, + &qhs_clk_ctl, + &qhs_crypto0_cfg, + &qhs_ddrss_cfg, + &qhs_ecc_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_pdm, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qpic, + &qhs_sdc1, + &qhs_snoc_cfg, + &qhs_spmi_fetcher, + &qhs_spmi_vgi_coex, + &qhs_tcsr, + &qhs_tlmm, + &qhs_usb3, + &qhs_usb3_phy, + &srvc_snoc + }, +}; + +static struct qcom_icc_bcm bcm_pn1 =3D { + .name =3D "PN1", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &xm_sdc1 }, +}; + +static struct qcom_icc_bcm bcm_pn2 =3D { + .name =3D "PN2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qhm_audio, &qhm_spmi_fetcher1 }, +}; + +static struct qcom_icc_bcm bcm_pn3 =3D { + .name =3D "PN3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qhm_blsp1, &qhm_qpic }, +}; + +static struct qcom_icc_bcm bcm_pn4 =3D { + .name =3D "PN4", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_sh0 =3D { + .name =3D "SH0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh1 =3D { + .name =3D "SH1", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_memnoc_snoc }, +}; + +static struct qcom_icc_bcm bcm_sh3 =3D { + .name =3D "SH3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &xm_apps_rdwr }, +}; + +static struct qcom_icc_bcm bcm_sn0 =3D { + .name =3D "SN0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_snoc_memnoc }, +}; + +static struct qcom_icc_bcm bcm_sn1 =3D { + .name =3D "SN1", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_sn2 =3D { + .name =3D "SN2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn3 =3D { + .name =3D "SN3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_bcm bcm_sn5 =3D { + .name =3D "SN5", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &xs_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn6 =3D { + .name =3D "SN6", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qhm_qdss_bam, &xm_qdss_etr }, +}; + +static struct qcom_icc_bcm bcm_sn7 =3D { + .name =3D "SN7", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 4, + .nodes =3D { &qnm_aggre_noc, &xm_pcie, &xm_usb3, &qns_aggre_noc }, +}; + +static struct qcom_icc_bcm bcm_sn8 =3D { + .name =3D "SN8", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_memnoc }, +}; + +static struct qcom_icc_bcm bcm_sn9 =3D { + .name =3D "SN9", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_memnoc_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn10 =3D { + .name =3D "SN10", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qnm_ipa, &xm_ipa2pcie_slv }, +}; =20 static struct qcom_icc_bcm * const mc_virt_bcms[] =3D { &bcm_mc0, --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 669E4C001DD for ; Tue, 11 Jul 2023 12:20:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231731AbjGKMUb (ORCPT ); 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:54 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:20 +0200 Subject: [PATCH 21/53] interconnect: qcom: sm6350: Retire DEFINE_QBCM MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-21-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=8416; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=SrAfEu7z7LDi+swPnqPTMHcA8pMC5/hLxqI6ZqZhaf0=; b=7WlneqnlYUMwfgEWnegCIMJfixgMc1PsRYVSsNGX2DEtr9WcXugI3RsfzMQZKXEXxhT053I17 5WznrJl7egfC0ejss8NmYrjEn1JX6/Cc84u1ixD848BDyOfR/6GCl1m X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm6350.c | 276 +++++++++++++++++++++++++++++++++= ---- 1 file changed, 251 insertions(+), 25 deletions(-) diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom= /sm6350.c index 7421eb4cd520..845d888f7634 100644 --- a/drivers/interconnect/qcom/sm6350.c +++ b/drivers/interconnect/qcom/sm6350.c @@ -1161,31 +1161,257 @@ static struct qcom_icc_node xs_sys_tcu_cfg =3D { .buswidth =3D 8, }; =20 -DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg= , &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg= , &qhs_camera_nrt_thrott_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &q= hs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qh= s_display_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_im= em_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_pimem_cfg= , &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_q= up1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_ufs_mem_cfg, &qhs_usb3_0= , &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc= ); -DEFINE_QBCM(bcm_cn1, "CN1", false, &xm_emmc, &xm_sdc2, &qhs_ahb2phy2, &qhs= _emmc_cfg, &qhs_pdm, &qhs_sdc2); -DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc); -DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu); -DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); -DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_icp_= uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf, &qxm_mdp0); -DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf); -DEFINE_QBCM(bcm_mm3, "MM3", false, &qhm_mnoc_cfg, &qnm_video0, &qnm_video_= cvp, &qxm_camnoc_sf); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup0_core_master, &qup1_core_master,= &qup0_core_slave, &qup1_core_slave); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu); -DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc); -DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc); -DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem); -DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn5, "SN5", false, &qnm_aggre1_noc); -DEFINE_QBCM(bcm_sn6, "SN6", false, &qnm_aggre2_noc); -DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_gemnoc); +static struct qcom_icc_bcm bcm_acv =3D { + .name =3D "ACV", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 =3D { + .name =3D "CE0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 =3D { + .name =3D "CN0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 41, + .nodes =3D { &qnm_snoc, + &xm_qdss_dap, + &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_ahb2phy0, + &qhs_aoss, + &qhs_boot_rom, + &qhs_camera_cfg, + &qhs_camera_nrt_thrott_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_clk_ctl, + &qhs_cpr_cx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_display_throttle_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_mss_cfg, + &qhs_npu_cfg, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qm_cfg, + &qhs_qm_mpu_cfg, + &qhs_qup0, + &qhs_qup1, + &qhs_security, + &qhs_snoc_cfg, + &qhs_tcsr, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_venus_cfg, + &qhs_venus_throttle_cfg, + &qhs_vsense_ctrl_cfg, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_cn1 =3D { + .name =3D "CN1", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 6, + .nodes =3D { &xm_emmc, + &xm_sdc2, + &qhs_ahb2phy2, + &qhs_emmc_cfg, + &qhs_pdm, + &qhs_sdc2 + }, +}; + +static struct qcom_icc_bcm bcm_co0 =3D { + .name =3D "CO0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_cdsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_co2 =3D { + .name =3D "CO2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_npu }, +}; + +static struct qcom_icc_bcm bcm_co3 =3D { + .name =3D "CO3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxm_npu_dsp }, +}; + +static struct qcom_icc_bcm bcm_mc0 =3D { + .name =3D "MC0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 =3D { + .name =3D "MM0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 =3D { + .name =3D "MM1", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 5, + .nodes =3D { &qxm_camnoc_hf0_uncomp, + &qxm_camnoc_icp_uncomp, + &qxm_camnoc_sf_uncomp, + &qxm_camnoc_hf, + &qxm_mdp0 + }, +}; + +static struct qcom_icc_bcm bcm_mm2 =3D { + .name =3D "MM2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_mm3 =3D { + .name =3D "MM3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 4, + .nodes =3D { &qhm_mnoc_cfg, &qnm_video0, &qnm_video_cvp, &qxm_camnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_qup0 =3D { + .name =3D "QUP0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 4, + .nodes =3D { &qup0_core_master, &qup1_core_master, &qup0_core_slave, &qup= 1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 =3D { + .name =3D "SH0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh2 =3D { + .name =3D "SH2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &acm_sys_tcu }, +}; + +static struct qcom_icc_bcm bcm_sh3 =3D { + .name =3D "SH3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_cmpnoc }, +}; + +static struct qcom_icc_bcm bcm_sh4 =3D { + .name =3D "SH4", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &acm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 =3D { + .name =3D "SN0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn1 =3D { + .name =3D "SN1", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_sn2 =3D { + .name =3D "SN2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn3 =3D { + .name =3D "SN3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn4 =3D { + .name =3D "SN4", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn5 =3D { + .name =3D "SN5", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn6 =3D { + .name =3D "SN6", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn10 =3D { + .name =3D "SN10", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_gemnoc }, +}; =20 static struct qcom_icc_bcm * const aggre1_noc_bcms[] =3D { &bcm_cn1, --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38B93EB64DD for ; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:56 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:21 +0200 Subject: [PATCH 22/53] interconnect: qcom: sm8150: Retire DEFINE_QBCM MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-22-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=9494; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=OR/aMRqrXjITcvDE45wlMNy7hvzhmiKeqYcGWttjB1Q=; b=uF+SFPLd6m6ntYCetsIlLhvgefSm5PCEEzcmxuit4atD5Re3IYmwtv545+LYKXsoSuT1jd13g uwfQDDEOZJwAjvrpTHYPMY4jF6Go5mE6iXfc2A93+DlTv7+0QvGxAAx X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8150.c | 311 +++++++++++++++++++++++++++++++++= ---- 1 file changed, 283 insertions(+), 28 deletions(-) diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom= /sm8150.c index 29f16899cf5d..91f68d91f12a 100644 --- a/drivers/interconnect/qcom/sm8150.c +++ b/drivers/interconnect/qcom/sm8150.c @@ -1279,34 +1279,289 @@ static struct qcom_icc_node xs_sys_tcu_cfg =3D { .buswidth =3D 8, }; =20 -DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); -DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1= _uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0= , &qxm_mdp1); -DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_gem_noc_snoc); -DEFINE_QBCM(bcm_mm2, "MM2", false, &qxm_camnoc_sf, &qns2_mem_noc); -DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_gpu_tcu, &acm_sys_tcu); -DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_rot, &qxm_venus0, &qxm_venus1, &qx= m_venus_arm9); -DEFINE_QBCM(bcm_sh4, "SH4", false, &qnm_cmpnoc); -DEFINE_QBCM(bcm_sh5, "SH5", false, &acm_apps); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf); -DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_co1, "CO1", false, &qnm_npu); -DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &= qhs_a2_noc_cfg, &qhs_ahb2phy_south, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &= qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qh= s_crypto0_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emac_cfg, &qhs_glm, &= qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_p= cie0_cfg, &qhs_pcie1_cfg, &qhs_phy_refgen_north, &qhs_pimem_cfg, &qhs_prng,= &qhs_qdss_cfg, &qhs_qspi, &qhs_qupv3_east, &qhs_qupv3_north, &qhs_qupv3_so= uth, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_ss= c_cfg, &qhs_tcsr, &qhs_tlmm_east, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tl= mm_west, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_= usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup0, &qhm_qup1, &qhm_qup2); -DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc); -DEFINE_QBCM(bcm_sn3, "SN3", false, &srvc_aggre1_noc, &srvc_aggre2_noc, &qn= s_cnoc); -DEFINE_QBCM(bcm_sn4, "SN4", false, &qxs_pimem); -DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn8, "SN8", false, &xs_pcie_0, &xs_pcie_1); -DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre1_noc); -DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_aggre2_noc); -DEFINE_QBCM(bcm_sn12, "SN12", false, &qxm_pimem, &xm_gic); -DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc); -DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_gemnoc); +static struct qcom_icc_bcm bcm_acv =3D { + .name =3D "ACV", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mc0 =3D { + .name =3D "MC0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_sh0 =3D { + .name =3D "SH0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_mm0 =3D { + .name =3D "MM0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 =3D { + .name =3D "MM1", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 7, + .nodes =3D { &qxm_camnoc_hf0_uncomp, + &qxm_camnoc_hf1_uncomp, + &qxm_camnoc_sf_uncomp, + &qxm_camnoc_hf0, + &qxm_camnoc_hf1, + &qxm_mdp0, + &qxm_mdp1 + }, +}; + +static struct qcom_icc_bcm bcm_sh2 =3D { + .name =3D "SH2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_gem_noc_snoc }, +}; + +static struct qcom_icc_bcm bcm_mm2 =3D { + .name =3D "MM2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qxm_camnoc_sf, &qns2_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_sh3 =3D { + .name =3D "SH3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &acm_gpu_tcu, &acm_sys_tcu }, +}; + +static struct qcom_icc_bcm bcm_mm3 =3D { + .name =3D "MM3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 4, + .nodes =3D { &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 }, +}; + +static struct qcom_icc_bcm bcm_sh4 =3D { + .name =3D "SH4", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_cmpnoc }, +}; + +static struct qcom_icc_bcm bcm_sh5 =3D { + .name =3D "SH5", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &acm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 =3D { + .name =3D "SN0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_co0 =3D { + .name =3D "CO0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_cdsp_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_ce0 =3D { + .name =3D "CE0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_sn1 =3D { + .name =3D "SN1", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_co1 =3D { + .name =3D "CO1", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_npu }, +}; + +static struct qcom_icc_bcm bcm_cn0 =3D { + .name =3D "CN0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 53, + .nodes =3D { &qhm_spdm, + &qnm_snoc, + &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_ahb2phy_south, + &qhs_aop, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp, + &qhs_cpr_cx, + &qhs_cpr_mmcx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_emac_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_npu_cfg, + &qhs_pcie0_cfg, + &qhs_pcie1_cfg, + &qhs_phy_refgen_north, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qspi, + &qhs_qupv3_east, + &qhs_qupv3_north, + &qhs_qupv3_south, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_spdm, + &qhs_spss_cfg, + &qhs_ssc_cfg, + &qhs_tcsr, + &qhs_tlmm_east, + &qhs_tlmm_north, + &qhs_tlmm_south, + &qhs_tlmm_west, + &qhs_tsif, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_qup0 =3D { + .name =3D "QUP0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 3, + .nodes =3D { &qhm_qup0, &qhm_qup1, &qhm_qup2 }, +}; + +static struct qcom_icc_bcm bcm_sn2 =3D { + .name =3D "SN2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn3 =3D { + .name =3D "SN3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 3, + .nodes =3D { &srvc_aggre1_noc, &srvc_aggre2_noc, &qns_cnoc }, +}; + +static struct qcom_icc_bcm bcm_sn4 =3D { + .name =3D "SN4", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn5 =3D { + .name =3D "SN5", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn8 =3D { + .name =3D "SN8", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &xs_pcie_0, &xs_pcie_1 }, +}; + +static struct qcom_icc_bcm bcm_sn9 =3D { + .name =3D "SN9", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn11 =3D { + .name =3D "SN11", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn12 =3D { + .name =3D "SN12", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qxm_pimem, &xm_gic }, +}; + +static struct qcom_icc_bcm bcm_sn14 =3D { + .name =3D "SN14", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_sn15 =3D { + .name =3D "SN15", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_gemnoc }, +}; =20 static struct qcom_icc_bcm * const aggre1_noc_bcms[] =3D { &bcm_qup0, --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85ABDC00528 for ; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:57 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:22 +0200 Subject: [PATCH 23/53] interconnect: qcom: sm8250: Retire DEFINE_QBCM MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-23-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=8980; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=t1pXtAGd50MXkyw2HwnChg2QcAcq+w7wwZSL8zvgYig=; b=FydPpyU0pYwqg60zuq5IyJ2PVzg0/iI6p7cPUx2AhRjBtXFm4HCWdX8PH8cssELO0FQQeKi8R aLRJXDCAkZ/Cn+szJAWmIJVylzJysAFfMd4IfaZZo3XfSrzDEpCb9q9 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8250.c | 294 +++++++++++++++++++++++++++++++++= ---- 1 file changed, 267 insertions(+), 27 deletions(-) diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom= /sm8250.c index d4123799c2c6..8cb032ac34bf 100644 --- a/drivers/interconnect/qcom/sm8250.c +++ b/drivers/interconnect/qcom/sm8250.c @@ -1394,33 +1394,273 @@ static struct qcom_icc_node qup2_core_slave =3D { .buswidth =3D 4, }; =20 -DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1); -DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu); -DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup0_core_master, &qup1_core_master,= &qup2_core_master); -DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc); -DEFINE_QBCM(bcm_mm3, "MM3", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_v= ideo0, &qnm_video1, &qnm_video_cvp); -DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf); -DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc); -DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg= , &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_camera_cfg= , &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, = &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_= cfg, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_lpass_c= fg, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pcie_= modem_cfg, &qhs_pdm, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &= qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_t= csr, &qhs_tlmm0, &qhs_tlmm1, &qhs_tlmm2, &qhs_tsif, &qhs_ufs_card_cfg, &qhs= _ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cf= g, &qns_cnoc_a2noc, &srvc_cnoc); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc); -DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu); -DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem); -DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie_modem); -DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie_0, &xs_pcie_1); -DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc); -DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc); -DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_gemnoc_pcie); -DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gemnoc); -DEFINE_QBCM(bcm_sn12, "SN12", false, &qns_pcie_modem_mem_noc, &qns_pcie_me= m_noc); +static struct qcom_icc_bcm bcm_acv =3D { + .name =3D "ACV", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mc0 =3D { + .name =3D "MC0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_sh0 =3D { + .name =3D "SH0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_mm0 =3D { + .name =3D "MM0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_ce0 =3D { + .name =3D "CE0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_mm1 =3D { + .name =3D "MM1", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 3, + .nodes =3D { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1 }, +}; + +static struct qcom_icc_bcm bcm_sh2 =3D { + .name =3D "SH2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &alm_gpu_tcu, &alm_sys_tcu }, +}; + +static struct qcom_icc_bcm bcm_mm2 =3D { + .name =3D "MM2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_qup0 =3D { + .name =3D "QUP0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 3, + .nodes =3D { &qup0_core_master, &qup1_core_master, &qup2_core_master }, +}; + +static struct qcom_icc_bcm bcm_sh3 =3D { + .name =3D "SH3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_cmpnoc }, +}; + +static struct qcom_icc_bcm bcm_mm3 =3D { + .name =3D "MM3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 5, + .nodes =3D { &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &= qnm_video_cvp }, +}; + +static struct qcom_icc_bcm bcm_sh4 =3D { + .name =3D "SH4", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &chm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 =3D { + .name =3D "SN0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_co0 =3D { + .name =3D "CO0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_cdsp_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_cn0 =3D { + .name =3D "CN0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 52, + .nodes =3D { &qnm_snoc, + &xm_qdss_dap, + &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp, + &qhs_cpr_cx, + &qhs_cpr_mmcx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_cx_rdpm, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_ipc_router, + &qhs_lpass_cfg, + &qhs_mnoc_cfg, + &qhs_npu_cfg, + &qhs_pcie0_cfg, + &qhs_pcie1_cfg, + &qhs_pcie_modem_cfg, + &qhs_pdm, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qspi, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_tcsr, + &qhs_tlmm0, + &qhs_tlmm1, + &qhs_tlmm2, + &qhs_tsif, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_sn1 =3D { + .name =3D "SN1", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_sn2 =3D { + .name =3D "SN2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_co2 =3D { + .name =3D "CO2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_npu }, +}; + +static struct qcom_icc_bcm bcm_sn3 =3D { + .name =3D "SN3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn4 =3D { + .name =3D "SN4", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn5 =3D { + .name =3D "SN5", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &xs_pcie_modem }, +}; + +static struct qcom_icc_bcm bcm_sn6 =3D { + .name =3D "SN6", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &xs_pcie_0, &xs_pcie_1 }, +}; + +static struct qcom_icc_bcm bcm_sn7 =3D { + .name =3D "SN7", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn8 =3D { + .name =3D "SN8", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn9 =3D { + .name =3D "SN9", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_gemnoc_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn11 =3D { + .name =3D "SN11", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_sn12 =3D { + .name =3D "SN12", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc }, +}; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:58 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:23 +0200 Subject: [PATCH 24/53] interconnect: qcom: sm8350: Retire DEFINE_QBCM MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-24-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=10048; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=7vRh6286jkOOStnKJOqywJgMBVBvPJLc59I7qoEIBjs=; b=BeU5lcKnloq3Tv9ibVtuGRjb29VlklFHbqYkVVLJgLUjBiQjoE6LpKiS6N8OucmxAwKV9Lg/e Fwc2wFonCPDD4VJb5ohkQgkVq0jbagT1ipLwUVJQQBrCbsmrI7XpM/H X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The struct definition macros are hard to read and comapre, expand them. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8350.c | 340 +++++++++++++++++++++++++++++++++= ---- 1 file changed, 308 insertions(+), 32 deletions(-) diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom= /sm8350.c index 859549b176c8..c48f96ff8575 100644 --- a/drivers/interconnect/qcom/sm8350.c +++ b/drivers/interconnect/qcom/sm8350.c @@ -1353,38 +1353,314 @@ static struct qcom_icc_node qns_mem_noc_sf_disp = =3D { .links =3D { SM8350_MASTER_MNOC_SF_MEM_NOC_DISP }, }; =20 -DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie); -DEFINE_QBCM(bcm_cn1, "CN1", false, &xm_qdss_dap, &qhs_ahb2phy0, &qhs_ahb2p= hy1, &qhs_aoss, &qhs_apss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_cfg,= &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &= qhs_dcc_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_hwkm, &qhs_imem_cfg, &q= hs_ipa, &qhs_ipc_router, &qhs_mss_cfg, &qhs_mx_rdpm, &qhs_pcie0_cfg, &qhs_p= cie1_cfg, &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, &qhs_pmu_wrapper_cfg, &qhs_= qdss_cfg, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_security, &qhs_spss_cfg, &q= hs_tcsr, &qhs_tlmm, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_= usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg, &qns_a2_noc_= cfg, &qns_ddrss_cfg, &qns_mnoc_cfg, &qns_snoc_cfg, &srvc_cnoc); -DEFINE_QBCM(bcm_cn2, "CN2", false, &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &q= hs_sdc2, &qhs_sdc4); -DEFINE_QBCM(bcm_co0, "CO0", false, &qns_nsp_gemnoc); -DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_nsp); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); -DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1); -DEFINE_QBCM(bcm_mm4, "MM4", false, &qns_mem_noc_sf); -DEFINE_QBCM(bcm_mm5, "MM5", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_v= ideo0, &qnm_video1, &qnm_video_cvp, &qxm_rot); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu); -DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc); -DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf); -DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc); -DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem); -DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn5, "SN5", false, &xm_pcie3_0); -DEFINE_QBCM(bcm_sn6, "SN6", false, &xm_pcie3_1); -DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc); -DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc); -DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc); -DEFINE_QBCM(bcm_acv_disp, "ACV", false, &ebi_disp); -DEFINE_QBCM(bcm_mc0_disp, "MC0", false, &ebi_disp); -DEFINE_QBCM(bcm_mm0_disp, "MM0", false, &qns_mem_noc_hf_disp); -DEFINE_QBCM(bcm_mm1_disp, "MM1", false, &qxm_mdp0_disp, &qxm_mdp1_disp); -DEFINE_QBCM(bcm_mm4_disp, "MM4", false, &qns_mem_noc_sf_disp); -DEFINE_QBCM(bcm_mm5_disp, "MM5", false, &qxm_rot_disp); -DEFINE_QBCM(bcm_sh0_disp, "SH0", false, &qns_llcc_disp); +static struct qcom_icc_bcm bcm_acv =3D { + .name =3D "ACV", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 =3D { + .name =3D "CE0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 =3D { + .name =3D "CN0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie }, +}; + +static struct qcom_icc_bcm bcm_cn1 =3D { + .name =3D "CN1", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 47, + .nodes =3D { &xm_qdss_dap, + &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_aoss, + &qhs_apss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_cfg, + &qhs_cpr_cx, + &qhs_cpr_mmcx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_cx_rdpm, + &qhs_dcc_cfg, + &qhs_display_cfg, + &qhs_gpuss_cfg, + &qhs_hwkm, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_ipc_router, + &qhs_mss_cfg, + &qhs_mx_rdpm, + &qhs_pcie0_cfg, + &qhs_pcie1_cfg, + &qhs_pimem_cfg, + &qhs_pka_wrapper_cfg, + &qhs_pmu_wrapper_cfg, + &qhs_qdss_cfg, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2, + &qhs_security, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_a1_noc_cfg, + &qns_a2_noc_cfg, + &qns_ddrss_cfg, + &qns_mnoc_cfg, + &qns_snoc_cfg, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_cn2 =3D { + .name =3D "CN2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 5, + .nodes =3D { &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4 }, +}; + +static struct qcom_icc_bcm bcm_co0 =3D { + .name =3D "CO0", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_co3 =3D { + .name =3D "CO3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxm_nsp }, +}; + +static struct qcom_icc_bcm bcm_mc0 =3D { + .name =3D "MC0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 =3D { + .name =3D "MM0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 =3D { + .name =3D "MM1", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 3, + .nodes =3D { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1 }, +}; + +static struct qcom_icc_bcm bcm_mm4 =3D { + .name =3D "MM4", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_mm5 =3D { + .name =3D "MM5", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 6, + .nodes =3D { &qnm_camnoc_icp, + &qnm_camnoc_sf, + &qnm_video0, + &qnm_video1, + &qnm_video_cvp, + &qxm_rot + }, +}; + +static struct qcom_icc_bcm bcm_sh0 =3D { + .name =3D "SH0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh2 =3D { + .name =3D "SH2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 2, + .nodes =3D { &alm_gpu_tcu, &alm_sys_tcu }, +}; + +static struct qcom_icc_bcm bcm_sh3 =3D { + .name =3D "SH3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_cmpnoc }, +}; + +static struct qcom_icc_bcm bcm_sh4 =3D { + .name =3D "SH4", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &chm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 =3D { + .name =3D "SN0", + .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn2 =3D { + .name =3D "SN2", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn3 =3D { + .name =3D "SN3", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn4 =3D { + .name =3D "SN4", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn5 =3D { + .name =3D "SN5", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &xm_pcie3_0 }, +}; + +static struct qcom_icc_bcm bcm_sn6 =3D { + .name =3D "SN6", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &xm_pcie3_1 }, +}; + +static struct qcom_icc_bcm bcm_sn7 =3D { + .name =3D "SN7", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn8 =3D { + .name =3D "SN8", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn14 =3D { + .name =3D "SN14", + .keepalive =3D false, + .voter_idx =3D ICC_BCM_VOTER_APPS, + .num_nodes =3D 1, + .nodes =3D { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_acv_disp =3D { + .name =3D "ACV", + .keepalive =3D false, + .voter_idx =3D 0, + .num_nodes =3D 1, + .nodes =3D { &ebi_disp }, +}; + +static struct qcom_icc_bcm bcm_mc0_disp =3D { + .name =3D "MC0", + .keepalive =3D false, + .voter_idx =3D 0, + .num_nodes =3D 1, + .nodes =3D { &ebi_disp }, +}; + +static struct qcom_icc_bcm bcm_mm0_disp =3D { + .name =3D "MM0", + .keepalive =3D false, + .voter_idx =3D 0, + .num_nodes =3D 1, + .nodes =3D { &qns_mem_noc_hf_disp }, +}; + +static struct qcom_icc_bcm bcm_mm1_disp =3D { + .name =3D "MM1", + .keepalive =3D false, + .voter_idx =3D 0, + .num_nodes =3D 2, + .nodes =3D { &qxm_mdp0_disp, &qxm_mdp1_disp }, +}; + +static struct qcom_icc_bcm bcm_mm4_disp =3D { + .name =3D "MM4", + .keepalive =3D false, + .voter_idx =3D 0, + .num_nodes =3D 1, + .nodes =3D { &qns_mem_noc_sf_disp }, +}; + +static struct qcom_icc_bcm bcm_mm5_disp =3D { + .name =3D "MM5", + .keepalive =3D false, + .voter_idx =3D 0, + .num_nodes =3D 1, + .nodes =3D { &qxm_rot_disp }, +}; + +static struct qcom_icc_bcm bcm_sh0_disp =3D { + .name =3D "SH0", + .keepalive =3D false, + .voter_idx =3D 0, + .num_nodes =3D 1, + .nodes =3D { &qns_llcc_disp }, +}; =20 static struct qcom_icc_bcm * const aggre1_noc_bcms[] =3D { }; --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B049C001DC for ; Tue, 11 Jul 2023 12:20:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231285AbjGKMUu (ORCPT ); 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.18.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:18:59 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:24 +0200 Subject: [PATCH 25/53] interconnect: qcom: icc-rpmh: Retire DEFINE_QBCM MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-25-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=963; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=4QbqX9qEiwnykOnp3T41q/aNjoSl3d0wkDdtwzmuC9Q=; b=KRB7LLVjGAZUDlQ6RmEwKiP2CeNYEuzZIz/3UkIO9aa7zYQPnhOJzN+j7mjNIJXqSehfercoh RO54QxvYyekB6AHJF4LoEHDTgGiagtGPZdFwxdVTK3Z7JOtfdppI723 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This helper has no users anymore. Kill it with heavy fire. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/bcm-voter.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/interconnect/qcom/bcm-voter.h b/drivers/interconnect/q= com/bcm-voter.h index 30b324fcb2ee..62cdee94b5ba 100644 --- a/drivers/interconnect/qcom/bcm-voter.h +++ b/drivers/interconnect/qcom/bcm-voter.h @@ -12,14 +12,6 @@ =20 #include "icc-rpmh.h" =20 -#define DEFINE_QBCM(_name, _bcmname, _keepalive, ...) \ -static struct qcom_icc_bcm _name =3D { \ - .name =3D _bcmname, \ - .keepalive =3D _keepalive, \ - .num_nodes =3D ARRAY_SIZE(((struct qcom_icc_node *[]){ __VA_ARGS__ })), \ - .nodes =3D { __VA_ARGS__ }, \ -} - void qcom_icc_bcm_voter_add(struct bcm_voter *voter, struct qcom_icc_bcm *= bcm); int qcom_icc_bcm_voter_commit(struct bcm_voter *voter); =20 --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26091EB64DD for ; Tue, 11 Jul 2023 12:20:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232241AbjGKMUx (ORCPT ); Tue, 11 Jul 2023 08:20:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231299AbjGKMUO (ORCPT ); Tue, 11 Jul 2023 08:20:14 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E577170B for ; Tue, 11 Jul 2023 05:19:25 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id 38308e7fff4ca-2b63e5f94f1so70073011fa.1 for ; Tue, 11 Jul 2023 05:19:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689077941; x=1691669941; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=yjEw0XoxZw/g1nfL12bHFSyvJYF4vER1wXRrobCe4VQ=; b=SO8G7gtbOhkPbaLWlVi2A26EGBnLGR8WhCcdISpfIxmVj2nnLs76mUyH9u5Yb2u/zl O23xnH972rd94DWKwWGzotqQfkg95kfDfWHlh5AwRuw1ZGZ4bY/8DqOBJTYTItniJ6Lj aQH/9+u3Vne8pGuwL8tZ738RoU25IpWGAj+cpGd8oqvT4Drh3wWkBBGPwZ8XTpE9+qxH YchmIVyssp9NL7wM2Ki7YOMCj60Qr+oA4/6793eA385fc9B6i2ASKEtGNhlj2cjXScM3 tYk8EidHxGtCZY+XbqdO+hQND0yUzPS0xkzjN/ddpZsPdYtnrTAi2iSvEz5n+XSYzQLU DmZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689077941; x=1691669941; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yjEw0XoxZw/g1nfL12bHFSyvJYF4vER1wXRrobCe4VQ=; b=KOFcQraVzhDlhU86fa0C8CKvPz2vEb+HNAwMzDdGhB5JXEhLgN/c4K93xtJHHYSVSn 5Uv77UJYidx85BjD6GQ8nnBEHuFcApOjQDghYp/tQoH0zOdxuuazhNIlgsb2WpkOUyxC ytnmj/Rc7MS6XdsYowNFfe8F1Yl/+tGu/WyU/XsOLhqB7XB4WSqfaSqZROjIfmHknBaZ gZ6bbfvCBloDlBbBomwVHbzytcupWhY/v/DgjkoznQUxU9EkUcUCVvHGHZq7MkPgpqt2 siE3an/FI8uEJnXUdtMBdt/ugGtzw0/9im2tewIhu5r/Ljv9JsfWinvYZwCOd8yqvfcB 6nzg== X-Gm-Message-State: ABy/qLaVgi5L1MLkjcF+L23cDjONezqZHHnSYanZSFr0TbknFcqoOu+k 0bIIlpb4Sv7AIMg//IZ4puBkGA== X-Google-Smtp-Source: APBJJlGKDLEVUmAQ4vDYyP+R6V2LmaGS1gibL6+XogxgT4lITsG4VyRmSVusTQuIFb+0n7h7tR0lUQ== X-Received: by 2002:a2e:8e35:0:b0:2b6:ee7a:f5ae with SMTP id r21-20020a2e8e35000000b002b6ee7af5aemr7635646ljk.16.1689077941421; Tue, 11 Jul 2023 05:19:01 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:01 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:25 +0200 Subject: [PATCH 26/53] interconnect: qcom: qdu1000: Explicitly assign voter_idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-26-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=2723; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=9xNumb4mlVPJURVONYP61q5QOzs9rfLdvbN1jnXwzpk=; b=IUepLalcILF7YN5hx4w8ucTFotgb8EVQk+WRRg8BB2vlIGoZ5lTxmAmV/VZbcNjfozWT0W6Bq V1lkz8druzNCYbmJ0YerskqCPBdQR+cpC3t0UpsAEdKCdRw2G5z5+Mu X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To avoid confusion, explicitly assign the BCM voter index. Note the assignment may be incorrect, but this commit brings no functional change. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/qdu1000.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/interconnect/qcom/qdu1000.c b/drivers/interconnect/qco= m/qdu1000.c index a4cf559de2b0..f9c54e9ad9d1 100644 --- a/drivers/interconnect/qcom/qdu1000.c +++ b/drivers/interconnect/qcom/qdu1000.c @@ -768,18 +768,21 @@ static struct qcom_icc_node xs_sys_tcu_cfg =3D { =20 static struct qcom_icc_bcm bcm_acv =3D { .name =3D "ACV", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &ebi }, }; =20 static struct qcom_icc_bcm bcm_ce0 =3D { .name =3D "CE0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qxm_crypto }, }; =20 static struct qcom_icc_bcm bcm_cn0 =3D { .name =3D "CN0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 44, .nodes =3D { &qhm_qpic, &qhm_qspi, &qnm_gemnoc_cnoc, &qnm_gemnoc_modem_slave, @@ -808,24 +811,28 @@ static struct qcom_icc_bcm bcm_cn0 =3D { =20 static struct qcom_icc_bcm bcm_mc0 =3D { .name =3D "MC0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &ebi }, }; =20 static struct qcom_icc_bcm bcm_qup0 =3D { .name =3D "QUP0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qup0_core_slave, &qup1_core_slave }, }; =20 static struct qcom_icc_bcm bcm_sh0 =3D { .name =3D "SH0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_bcm bcm_sh1 =3D { .name =3D "SH1", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 11, .nodes =3D { &alm_sys_tcu, &chm_apps, &qnm_ecpri_dma, &qnm_fec_2_gemnoc, @@ -838,12 +845,14 @@ static struct qcom_icc_bcm bcm_sh1 =3D { =20 static struct qcom_icc_bcm bcm_sn0 =3D { .name =3D "SN0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_bcm bcm_sn1 =3D { .name =3D "SN1", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 6, .nodes =3D { &qhm_gic, &qxm_pimem, &xm_gic, &xm_qdss_etr0, @@ -853,6 +862,7 @@ static struct qcom_icc_bcm bcm_sn1 =3D { =20 static struct qcom_icc_bcm bcm_sn2 =3D { .name =3D "SN2", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 5, .nodes =3D { &qnm_aggre_noc, &qxm_ecpri_gsi, &xm_ecpri_dma, &qns_anoc_snoc_gsi, @@ -862,6 +872,7 @@ static struct qcom_icc_bcm bcm_sn2 =3D { =20 static struct qcom_icc_bcm bcm_sn7 =3D { .name =3D "SN7", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qns_pcie_gemnoc, &xs_pcie }, }; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:02 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:26 +0200 Subject: [PATCH 27/53] interconnect: qcom: sa8775p: Explicitly assign voter_idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-27-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=6180; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=hOvbaOTw9Rft7PbhGwWzFvl3fJ55nEvjw1n3n0o+bvA=; b=bgBgJk9B9qnxSbwV2qtOwPqT0zxWHu4caPLE/qW7xFxyp0JDmlS4/+qKJ/fj7t1TS2QpTfbW1 k9/9xeqbpMyBVZ8bZBghyIsifPl/3HndxIGab11sgNllsV5rphubazj X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To avoid confusion, explicitly assign the BCM voter index. Note the assignment may be incorrect, but this commit brings no functional change. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sa8775p.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qco= m/sa8775p.c index f56538669de0..0c8ef127f8a8 100644 --- a/drivers/interconnect/qcom/sa8775p.c +++ b/drivers/interconnect/qcom/sa8775p.c @@ -1873,6 +1873,7 @@ static struct qcom_icc_node srvc_snoc =3D { =20 static struct qcom_icc_bcm bcm_acv =3D { .name =3D "ACV", + .voter_idx =3D ICC_BCM_VOTER_APPS, .enable_mask =3D 0x8, .num_nodes =3D 1, .nodes =3D { &ebi }, @@ -1880,6 +1881,7 @@ static struct qcom_icc_bcm bcm_acv =3D { =20 static struct qcom_icc_bcm bcm_ce0 =3D { .name =3D "CE0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qxm_crypto_0, &qxm_crypto_1 }, }; @@ -1887,12 +1889,14 @@ static struct qcom_icc_bcm bcm_ce0 =3D { static struct qcom_icc_bcm bcm_cn0 =3D { .name =3D "CN0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie }, }; =20 static struct qcom_icc_bcm bcm_cn1 =3D { .name =3D "CN1", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 76, .nodes =3D { &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_ahb2phy2, &qhs_ahb2phy3, @@ -1936,6 +1940,7 @@ static struct qcom_icc_bcm bcm_cn1 =3D { =20 static struct qcom_icc_bcm bcm_cn2 =3D { .name =3D "CN2", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 4, .nodes =3D { &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_qup3 }, @@ -1943,18 +1948,21 @@ static struct qcom_icc_bcm bcm_cn2 =3D { =20 static struct qcom_icc_bcm bcm_cn3 =3D { .name =3D "CN3", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &xs_pcie_0, &xs_pcie_1 }, }; =20 static struct qcom_icc_bcm bcm_gna0 =3D { .name =3D "GNA0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qxm_dsp0 }, }; =20 static struct qcom_icc_bcm bcm_gnb0 =3D { .name =3D "GNB0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qxm_dsp1 }, }; @@ -1962,6 +1970,7 @@ static struct qcom_icc_bcm bcm_gnb0 =3D { static struct qcom_icc_bcm bcm_mc0 =3D { .name =3D "MC0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &ebi }, }; @@ -1969,6 +1978,7 @@ static struct qcom_icc_bcm bcm_mc0 =3D { static struct qcom_icc_bcm bcm_mm0 =3D { .name =3D "MM0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 5, .nodes =3D { &qnm_camnoc_hf, &qnm_mdp0_0, &qnm_mdp0_1, &qnm_mdp1_0, @@ -1977,6 +1987,7 @@ static struct qcom_icc_bcm bcm_mm0 =3D { =20 static struct qcom_icc_bcm bcm_mm1 =3D { .name =3D "MM1", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 7, .nodes =3D { &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, @@ -1986,30 +1997,35 @@ static struct qcom_icc_bcm bcm_mm1 =3D { =20 static struct qcom_icc_bcm bcm_nsa0 =3D { .name =3D "NSA0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qns_hcp, &qns_nsp_gemnoc }, }; =20 static struct qcom_icc_bcm bcm_nsa1 =3D { .name =3D "NSA1", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qxm_nsp }, }; =20 static struct qcom_icc_bcm bcm_nsb0 =3D { .name =3D "NSB0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qns_nspb_gemnoc, &qns_nspb_hcp }, }; =20 static struct qcom_icc_bcm bcm_nsb1 =3D { .name =3D "NSB1", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qxm_nspb }, }; =20 static struct qcom_icc_bcm bcm_pci0 =3D { .name =3D "PCI0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_pcie_mem_noc }, }; @@ -2017,6 +2033,7 @@ static struct qcom_icc_bcm bcm_pci0 =3D { static struct qcom_icc_bcm bcm_qup0 =3D { .name =3D "QUP0", .vote_scale =3D 1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qup0_core_slave }, }; @@ -2024,6 +2041,7 @@ static struct qcom_icc_bcm bcm_qup0 =3D { static struct qcom_icc_bcm bcm_qup1 =3D { .name =3D "QUP1", .vote_scale =3D 1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qup1_core_slave }, }; @@ -2031,6 +2049,7 @@ static struct qcom_icc_bcm bcm_qup1 =3D { static struct qcom_icc_bcm bcm_qup2 =3D { .name =3D "QUP2", .vote_scale =3D 1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qup2_core_slave, &qup3_core_slave }, }; @@ -2038,12 +2057,14 @@ static struct qcom_icc_bcm bcm_qup2 =3D { static struct qcom_icc_bcm bcm_sh0 =3D { .name =3D "SH0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_bcm bcm_sh2 =3D { .name =3D "SH2", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &chm_apps }, }; @@ -2051,42 +2072,49 @@ static struct qcom_icc_bcm bcm_sh2 =3D { static struct qcom_icc_bcm bcm_sn0 =3D { .name =3D "SN0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_bcm bcm_sn1 =3D { .name =3D "SN1", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_bcm bcm_sn2 =3D { .name =3D "SN2", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qxs_pimem }, }; =20 static struct qcom_icc_bcm bcm_sn3 =3D { .name =3D "SN3", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qns_a1noc_snoc, &qnm_aggre1_noc }, }; =20 static struct qcom_icc_bcm bcm_sn4 =3D { .name =3D "SN4", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qns_a2noc_snoc, &qnm_aggre2_noc }, }; =20 static struct qcom_icc_bcm bcm_sn9 =3D { .name =3D "SN9", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qns_sysnoc, &qnm_lpass_noc }, }; =20 static struct qcom_icc_bcm bcm_sn10 =3D { .name =3D "SN10", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &xs_qdss_stm }, }; --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF592EB64DC for ; Tue, 11 Jul 2023 12:22:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232306AbjGKMVF (ORCPT ); Tue, 11 Jul 2023 08:21:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231977AbjGKMUV (ORCPT ); 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:03 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:27 +0200 Subject: [PATCH 28/53] interconnect: qcom: sc7280: Explicitly assign voter_idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-28-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=5586; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=nax1GmT400+SDmWYx677ggaJz8Q417oAUImc//sqRBI=; b=QZfN5DzZ+sQyvhBt7DAVOOwH1qwd9tG7nKc4auZp5i3QPCjza8KgAr17dKeTznGx/lQwfE2k4 gz3cbp2Cj8GB79VtLFoHEG9heBFxwEzRP59H5YWT+IFj7RrJXX/vZaj X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To avoid confusion, explicitly assign the BCM voter index. Note the assignment may be incorrect, but this commit brings no functional change. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sc7280.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom= /sc7280.c index 971f538bc98a..bb8b31612501 100644 --- a/drivers/interconnect/qcom/sc7280.c +++ b/drivers/interconnect/qcom/sc7280.c @@ -1284,12 +1284,14 @@ static struct qcom_icc_node srvc_snoc =3D { =20 static struct qcom_icc_bcm bcm_acv =3D { .name =3D "ACV", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &ebi }, }; =20 static struct qcom_icc_bcm bcm_ce0 =3D { .name =3D "CE0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qxm_crypto }, }; @@ -1297,12 +1299,14 @@ static struct qcom_icc_bcm bcm_ce0 =3D { static struct qcom_icc_bcm bcm_cn0 =3D { .name =3D "CN0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie }, }; =20 static struct qcom_icc_bcm bcm_cn1 =3D { .name =3D "CN1", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 47, .nodes =3D { &qnm_cnoc3_cnoc2, &xm_qdss_dap, &qhs_ahb2phy0, &qhs_ahb2phy1, @@ -1331,6 +1335,7 @@ static struct qcom_icc_bcm bcm_cn1 =3D { =20 static struct qcom_icc_bcm bcm_cn2 =3D { .name =3D "CN2", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 6, .nodes =3D { &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc1, @@ -1339,12 +1344,14 @@ static struct qcom_icc_bcm bcm_cn2 =3D { =20 static struct qcom_icc_bcm bcm_co0 =3D { .name =3D "CO0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_nsp_gemnoc }, }; =20 static struct qcom_icc_bcm bcm_co3 =3D { .name =3D "CO3", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qxm_nsp }, }; @@ -1352,6 +1359,7 @@ static struct qcom_icc_bcm bcm_co3 =3D { static struct qcom_icc_bcm bcm_mc0 =3D { .name =3D "MC0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &ebi }, }; @@ -1359,24 +1367,28 @@ static struct qcom_icc_bcm bcm_mc0 =3D { static struct qcom_icc_bcm bcm_mm0 =3D { .name =3D "MM0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_mem_noc_hf }, }; =20 static struct qcom_icc_bcm bcm_mm1 =3D { .name =3D "MM1", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qxm_camnoc_hf, &qxm_mdp0 }, }; =20 static struct qcom_icc_bcm bcm_mm4 =3D { .name =3D "MM4", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_mem_noc_sf }, }; =20 static struct qcom_icc_bcm bcm_mm5 =3D { .name =3D "MM5", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 3, .nodes =3D { &qnm_video0, &qxm_camnoc_icp, &qxm_camnoc_sf }, @@ -1385,6 +1397,7 @@ static struct qcom_icc_bcm bcm_mm5 =3D { static struct qcom_icc_bcm bcm_qup0 =3D { .name =3D "QUP0", .vote_scale =3D 1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qup0_core_slave }, }; @@ -1392,6 +1405,7 @@ static struct qcom_icc_bcm bcm_qup0 =3D { static struct qcom_icc_bcm bcm_qup1 =3D { .name =3D "QUP1", .vote_scale =3D 1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qup1_core_slave }, }; @@ -1399,24 +1413,28 @@ static struct qcom_icc_bcm bcm_qup1 =3D { static struct qcom_icc_bcm bcm_sh0 =3D { .name =3D "SH0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_bcm bcm_sh2 =3D { .name =3D "SH2", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &alm_gpu_tcu, &alm_sys_tcu }, }; =20 static struct qcom_icc_bcm bcm_sh3 =3D { .name =3D "SH3", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qnm_cmpnoc }, }; =20 static struct qcom_icc_bcm bcm_sh4 =3D { .name =3D "SH4", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &chm_apps }, }; @@ -1424,54 +1442,63 @@ static struct qcom_icc_bcm bcm_sh4 =3D { static struct qcom_icc_bcm bcm_sn0 =3D { .name =3D "SN0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_bcm bcm_sn2 =3D { .name =3D "SN2", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_bcm bcm_sn3 =3D { .name =3D "SN3", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qxs_pimem }, }; =20 static struct qcom_icc_bcm bcm_sn4 =3D { .name =3D "SN4", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &xs_qdss_stm }, }; =20 static struct qcom_icc_bcm bcm_sn5 =3D { .name =3D "SN5", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &xm_pcie3_0 }, }; =20 static struct qcom_icc_bcm bcm_sn6 =3D { .name =3D "SN6", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &xm_pcie3_1 }, }; =20 static struct qcom_icc_bcm bcm_sn7 =3D { .name =3D "SN7", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_bcm bcm_sn8 =3D { .name =3D "SN8", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_bcm bcm_sn14 =3D { .name =3D "SN14", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_pcie_mem_noc }, }; --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00BD8C04A94 for ; Tue, 11 Jul 2023 12:23:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232147AbjGKMXB (ORCPT ); Tue, 11 Jul 2023 08:23:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232161AbjGKMUh (ORCPT ); Tue, 11 Jul 2023 08:20:37 -0400 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D5301982 for ; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:04 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:28 +0200 Subject: [PATCH 29/53] interconnect: qcom: sc8180x: Explicitly assign voter_idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-29-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=4909; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=BvLWDzRk2sKY58qxMKk4+8yHkv9gScgVxizsgjWb+5A=; b=S4SWkBHlhYTPcaujc0sQmaZQyunPxhvKNOiG/aVsNj2bmQlmh2bfEHjGvop/VE8BQNX0Mqv9z syT8aKM70g1Ch4Hy4W1nWDuHW8XsS3yXKDu+KTMKwZD5fD7NOJZJLA8 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To avoid confusion, explicitly assign the BCM voter index. Note the assignment may be incorrect, but this commit brings no functional change. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sc8180x.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qco= m/sc8180x.c index c76e3a6a98cd..a811cbf2cd15 100644 --- a/drivers/interconnect/qcom/sc8180x.c +++ b/drivers/interconnect/qcom/sc8180x.c @@ -1344,6 +1344,7 @@ static struct qcom_icc_node slv_qup_core_2 =3D { =20 static struct qcom_icc_bcm bcm_acv =3D { .name =3D "ACV", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &slv_ebi } }; @@ -1351,6 +1352,7 @@ static struct qcom_icc_bcm bcm_acv =3D { static struct qcom_icc_bcm bcm_mc0 =3D { .name =3D "MC0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &slv_ebi } }; @@ -1358,24 +1360,28 @@ static struct qcom_icc_bcm bcm_mc0 =3D { static struct qcom_icc_bcm bcm_sh0 =3D { .name =3D "SH0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &slv_qns_llcc } }; =20 static struct qcom_icc_bcm bcm_mm0 =3D { .name =3D "MM0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &slv_qns_mem_noc_hf } }; =20 static struct qcom_icc_bcm bcm_co0 =3D { .name =3D "CO0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &slv_qns_cdsp_mem_noc } }; =20 static struct qcom_icc_bcm bcm_ce0 =3D { .name =3D "CE0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &mas_qxm_crypto } }; @@ -1383,6 +1389,7 @@ static struct qcom_icc_bcm bcm_ce0 =3D { static struct qcom_icc_bcm bcm_cn0 =3D { .name =3D "CN0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 57, .nodes =3D { &mas_qnm_snoc, &slv_qhs_a1_noc_cfg, @@ -1445,6 +1452,7 @@ static struct qcom_icc_bcm bcm_cn0 =3D { =20 static struct qcom_icc_bcm bcm_mm1 =3D { .name =3D "MM1", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 7, .nodes =3D { &mas_qxm_camnoc_hf0_uncomp, &mas_qxm_camnoc_hf1_uncomp, @@ -1457,6 +1465,7 @@ static struct qcom_icc_bcm bcm_mm1 =3D { =20 static struct qcom_icc_bcm bcm_qup0 =3D { .name =3D "QUP0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 3, .nodes =3D { &mas_qup_core_0, &mas_qup_core_1, @@ -1465,12 +1474,14 @@ static struct qcom_icc_bcm bcm_qup0 =3D { =20 static struct qcom_icc_bcm bcm_sh2 =3D { .name =3D "SH2", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &slv_qns_gem_noc_snoc } }; =20 static struct qcom_icc_bcm bcm_mm2 =3D { .name =3D "MM2", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 6, .nodes =3D { &mas_qxm_camnoc_sf, &mas_qxm_rot, @@ -1483,45 +1494,53 @@ static struct qcom_icc_bcm bcm_mm2 =3D { static struct qcom_icc_bcm bcm_sh3 =3D { .name =3D "SH3", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &mas_acm_apps } }; =20 static struct qcom_icc_bcm bcm_sn0 =3D { .name =3D "SN0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .nodes =3D { &slv_qns_gemnoc_sf } }; =20 static struct qcom_icc_bcm bcm_sn1 =3D { .name =3D "SN1", + .voter_idx =3D ICC_BCM_VOTER_APPS, .nodes =3D { &slv_qxs_imem } }; =20 static struct qcom_icc_bcm bcm_sn2 =3D { .name =3D "SN2", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .nodes =3D { &slv_qns_gemnoc_gc } }; =20 static struct qcom_icc_bcm bcm_co2 =3D { .name =3D "CO2", + .voter_idx =3D ICC_BCM_VOTER_APPS, .nodes =3D { &mas_qnm_npu } }; =20 static struct qcom_icc_bcm bcm_sn3 =3D { .name =3D "SN3", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .nodes =3D { &slv_srvc_aggre1_noc, &slv_qns_cnoc } }; =20 static struct qcom_icc_bcm bcm_sn4 =3D { .name =3D "SN4", + .voter_idx =3D ICC_BCM_VOTER_APPS, .nodes =3D { &slv_qxs_pimem } }; =20 static struct qcom_icc_bcm bcm_sn8 =3D { .name =3D "SN8", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 4, .nodes =3D { &slv_xs_pcie_0, &slv_xs_pcie_1, @@ -1531,18 +1550,21 @@ static struct qcom_icc_bcm bcm_sn8 =3D { =20 static struct qcom_icc_bcm bcm_sn9 =3D { .name =3D "SN9", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &mas_qnm_aggre1_noc } }; =20 static struct qcom_icc_bcm bcm_sn11 =3D { .name =3D "SN11", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &mas_qnm_aggre2_noc } }; =20 static struct qcom_icc_bcm bcm_sn14 =3D { .name =3D "SN14", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &slv_qns_pcie_mem_noc } }; @@ -1550,6 +1572,7 @@ static struct qcom_icc_bcm bcm_sn14 =3D { static struct qcom_icc_bcm bcm_sn15 =3D { .name =3D "SN15", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &mas_qnm_gemnoc } }; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:06 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:29 +0200 Subject: [PATCH 30/53] interconnect: qcom: sc8280xp: Explicitly assign voter_idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-30-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=6261; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=1S7DwAbbmJRlgdB0jUv8vg/oE5s08GOdcA66t7/JhZc=; b=vqcyWjtV/JprX614HAMpkTlFUQLjDMQQv8R0aAu5IsNbPK8j8+eSx7TI5kYXRFXHwdUaPAWMc Gdjwnz/iYQiATKZK2DH//eiLoYEHkOvpvT8Aw55TgVtLqg5AooIMaOQ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To avoid confusion, explicitly assign the BCM voter index. Note the assignment may be incorrect, but this commit brings no functional change. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sc8280xp.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/interconnect/qcom/sc8280xp.c b/drivers/interconnect/qc= om/sc8280xp.c index e56df893ec3e..2f595b78e2bc 100644 --- a/drivers/interconnect/qcom/sc8280xp.c +++ b/drivers/interconnect/qcom/sc8280xp.c @@ -1711,12 +1711,14 @@ static struct qcom_icc_node srvc_snoc =3D { =20 static struct qcom_icc_bcm bcm_acv =3D { .name =3D "ACV", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &ebi }, }; =20 static struct qcom_icc_bcm bcm_ce0 =3D { .name =3D "CE0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qxm_crypto }, }; @@ -1724,6 +1726,7 @@ static struct qcom_icc_bcm bcm_ce0 =3D { static struct qcom_icc_bcm bcm_cn0 =3D { .name =3D "CN0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 9, .nodes =3D { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, @@ -1739,6 +1742,7 @@ static struct qcom_icc_bcm bcm_cn0 =3D { =20 static struct qcom_icc_bcm bcm_cn1 =3D { .name =3D "CN1", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 67, .nodes =3D { &qhs_ahb2phy0, &qhs_ahb2phy1, @@ -1812,6 +1816,7 @@ static struct qcom_icc_bcm bcm_cn1 =3D { =20 static struct qcom_icc_bcm bcm_cn2 =3D { .name =3D "CN2", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 4, .nodes =3D { &qhs_qspi, &qhs_qup0, @@ -1822,6 +1827,7 @@ static struct qcom_icc_bcm bcm_cn2 =3D { =20 static struct qcom_icc_bcm bcm_cn3 =3D { .name =3D "CN3", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 3, .nodes =3D { &qxs_imem, &xs_smss, @@ -1832,6 +1838,7 @@ static struct qcom_icc_bcm bcm_cn3 =3D { static struct qcom_icc_bcm bcm_mc0 =3D { .name =3D "MC0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &ebi }, }; @@ -1839,6 +1846,7 @@ static struct qcom_icc_bcm bcm_mc0 =3D { static struct qcom_icc_bcm bcm_mm0 =3D { .name =3D "MM0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 5, .nodes =3D { &qnm_camnoc_hf, &qnm_mdp0_0, @@ -1850,6 +1858,7 @@ static struct qcom_icc_bcm bcm_mm0 =3D { =20 static struct qcom_icc_bcm bcm_mm1 =3D { .name =3D "MM1", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 8, .nodes =3D { &qnm_rot_0, &qnm_rot_1, @@ -1864,6 +1873,7 @@ static struct qcom_icc_bcm bcm_mm1 =3D { =20 static struct qcom_icc_bcm bcm_nsa0 =3D { .name =3D "NSA0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qns_nsp_gemnoc, &qxs_nsp_xfr @@ -1872,12 +1882,14 @@ static struct qcom_icc_bcm bcm_nsa0 =3D { =20 static struct qcom_icc_bcm bcm_nsa1 =3D { .name =3D "NSA1", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qxm_nsp }, }; =20 static struct qcom_icc_bcm bcm_nsb0 =3D { .name =3D "NSB0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qns_nspb_gemnoc, &qxs_nspb_xfr @@ -1886,12 +1898,14 @@ static struct qcom_icc_bcm bcm_nsb0 =3D { =20 static struct qcom_icc_bcm bcm_nsb1 =3D { .name =3D "NSB1", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qxm_nspb }, }; =20 static struct qcom_icc_bcm bcm_pci0 =3D { .name =3D "PCI0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_pcie_gem_noc }, }; @@ -1899,6 +1913,7 @@ static struct qcom_icc_bcm bcm_pci0 =3D { static struct qcom_icc_bcm bcm_qup0 =3D { .name =3D "QUP0", .vote_scale =3D 1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qup0_core_slave }, }; @@ -1906,6 +1921,7 @@ static struct qcom_icc_bcm bcm_qup0 =3D { static struct qcom_icc_bcm bcm_qup1 =3D { .name =3D "QUP1", .vote_scale =3D 1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qup1_core_slave }, }; @@ -1913,6 +1929,7 @@ static struct qcom_icc_bcm bcm_qup1 =3D { static struct qcom_icc_bcm bcm_qup2 =3D { .name =3D "QUP2", .vote_scale =3D 1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qup2_core_slave }, }; @@ -1920,12 +1937,14 @@ static struct qcom_icc_bcm bcm_qup2 =3D { static struct qcom_icc_bcm bcm_sh0 =3D { .name =3D "SH0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_llcc }, }; =20 static struct qcom_icc_bcm bcm_sh2 =3D { .name =3D "SH2", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &chm_apps }, }; @@ -1933,24 +1952,28 @@ static struct qcom_icc_bcm bcm_sh2 =3D { static struct qcom_icc_bcm bcm_sn0 =3D { .name =3D "SN0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_gemnoc_sf }, }; =20 static struct qcom_icc_bcm bcm_sn1 =3D { .name =3D "SN1", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_gemnoc_gc }, }; =20 static struct qcom_icc_bcm bcm_sn2 =3D { .name =3D "SN2", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qxs_pimem }, }; =20 static struct qcom_icc_bcm bcm_sn3 =3D { .name =3D "SN3", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qns_a1noc_snoc, &qnm_aggre1_noc @@ -1959,6 +1982,7 @@ static struct qcom_icc_bcm bcm_sn3 =3D { =20 static struct qcom_icc_bcm bcm_sn4 =3D { .name =3D "SN4", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qns_a2noc_snoc, &qnm_aggre2_noc @@ -1967,6 +1991,7 @@ static struct qcom_icc_bcm bcm_sn4 =3D { =20 static struct qcom_icc_bcm bcm_sn5 =3D { .name =3D "SN5", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qns_aggre_usb_snoc, &qnm_aggre_usb_noc @@ -1975,6 +2000,7 @@ static struct qcom_icc_bcm bcm_sn5 =3D { =20 static struct qcom_icc_bcm bcm_sn9 =3D { .name =3D "SN9", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qns_sysnoc, &qnm_lpass_noc @@ -1983,6 +2009,7 @@ static struct qcom_icc_bcm bcm_sn9 =3D { =20 static struct qcom_icc_bcm bcm_sn10 =3D { .name =3D "SN10", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &xs_qdss_stm }, }; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:07 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:30 +0200 Subject: [PATCH 31/53] interconnect: qcom: sm8450: Explicitly assign voter_idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-31-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=5852; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=I0m5AL+30JxxsGRzPqVcr4YQAJm2OVM5Cn2T0SByiyw=; b=WvhVcfnpVCw2fiB0NJVs0AmEGvXFtkSXcpGBzJbdk2JMg7zxPWG3lUNV9rCQc50aIayKpYc40 5xw4Gnu63tTCAUQIB5T6KtLbd7AU/VloMGOHlznCeW79Pic5gSqvTfE X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To avoid confusion, explicitly assign the BCM voter index. Note the assignment may be incorrect, but this commit brings no functional change. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8450.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom= /sm8450.c index e64c214b4020..989ae24f2be9 100644 --- a/drivers/interconnect/qcom/sm8450.c +++ b/drivers/interconnect/qcom/sm8450.c @@ -1338,12 +1338,14 @@ static struct qcom_icc_node qns_mem_noc_sf_disp =3D= { static struct qcom_icc_bcm bcm_acv =3D { .name =3D "ACV", .enable_mask =3D 0x8, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &ebi }, }; =20 static struct qcom_icc_bcm bcm_ce0 =3D { .name =3D "CE0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qxm_crypto }, }; @@ -1352,6 +1354,7 @@ static struct qcom_icc_bcm bcm_cn0 =3D { .name =3D "CN0", .enable_mask =3D 0x1, .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 55, .nodes =3D { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, &qhs_ahb2phy0, &qhs_ahb2phy1, @@ -1386,6 +1389,7 @@ static struct qcom_icc_bcm bcm_cn0 =3D { static struct qcom_icc_bcm bcm_co0 =3D { .name =3D "CO0", .enable_mask =3D 0x1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qxm_nsp, &qns_nsp_gemnoc }, }; @@ -1393,6 +1397,7 @@ static struct qcom_icc_bcm bcm_co0 =3D { static struct qcom_icc_bcm bcm_mc0 =3D { .name =3D "MC0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &ebi }, }; @@ -1400,6 +1405,7 @@ static struct qcom_icc_bcm bcm_mc0 =3D { static struct qcom_icc_bcm bcm_mm0 =3D { .name =3D "MM0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_mem_noc_hf }, }; @@ -1407,6 +1413,7 @@ static struct qcom_icc_bcm bcm_mm0 =3D { static struct qcom_icc_bcm bcm_mm1 =3D { .name =3D "MM1", .enable_mask =3D 0x1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 12, .nodes =3D { &qnm_camnoc_hf, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_mdp, @@ -1420,6 +1427,7 @@ static struct qcom_icc_bcm bcm_qup0 =3D { .name =3D "QUP0", .keepalive =3D true, .vote_scale =3D 1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qup0_core_slave }, }; @@ -1428,6 +1436,7 @@ static struct qcom_icc_bcm bcm_qup1 =3D { .name =3D "QUP1", .keepalive =3D true, .vote_scale =3D 1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qup1_core_slave }, }; @@ -1436,6 +1445,7 @@ static struct qcom_icc_bcm bcm_qup2 =3D { .name =3D "QUP2", .keepalive =3D true, .vote_scale =3D 1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qup2_core_slave }, }; @@ -1443,6 +1453,7 @@ static struct qcom_icc_bcm bcm_qup2 =3D { static struct qcom_icc_bcm bcm_sh0 =3D { .name =3D "SH0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_llcc }, }; @@ -1450,6 +1461,7 @@ static struct qcom_icc_bcm bcm_sh0 =3D { static struct qcom_icc_bcm bcm_sh1 =3D { .name =3D "SH1", .enable_mask =3D 0x1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 7, .nodes =3D { &alm_gpu_tcu, &alm_sys_tcu, &qnm_nsp_gemnoc, &qnm_pcie, @@ -1460,6 +1472,7 @@ static struct qcom_icc_bcm bcm_sh1 =3D { static struct qcom_icc_bcm bcm_sn0 =3D { .name =3D "SN0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_gemnoc_sf }, }; @@ -1467,6 +1480,7 @@ static struct qcom_icc_bcm bcm_sn0 =3D { static struct qcom_icc_bcm bcm_sn1 =3D { .name =3D "SN1", .enable_mask =3D 0x1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 4, .nodes =3D { &qhm_gic, &qxm_pimem, &xm_gic, &qns_gemnoc_gc }, @@ -1474,24 +1488,28 @@ static struct qcom_icc_bcm bcm_sn1 =3D { =20 static struct qcom_icc_bcm bcm_sn2 =3D { .name =3D "SN2", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_bcm bcm_sn3 =3D { .name =3D "SN3", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_bcm bcm_sn4 =3D { .name =3D "SN4", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qnm_lpass_noc }, }; =20 static struct qcom_icc_bcm bcm_sn7 =3D { .name =3D "SN7", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_pcie_mem_noc }, }; @@ -1499,18 +1517,21 @@ static struct qcom_icc_bcm bcm_sn7 =3D { static struct qcom_icc_bcm bcm_acv_disp =3D { .name =3D "ACV", .enable_mask =3D 0x1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &ebi_disp }, }; =20 static struct qcom_icc_bcm bcm_mc0_disp =3D { .name =3D "MC0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &ebi_disp }, }; =20 static struct qcom_icc_bcm bcm_mm0_disp =3D { .name =3D "MM0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_mem_noc_hf_disp }, }; @@ -1518,6 +1539,7 @@ static struct qcom_icc_bcm bcm_mm0_disp =3D { static struct qcom_icc_bcm bcm_mm1_disp =3D { .name =3D "MM1", .enable_mask =3D 0x1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 3, .nodes =3D { &qnm_mdp_disp, &qnm_rot_disp, &qns_mem_noc_sf_disp }, @@ -1525,6 +1547,7 @@ static struct qcom_icc_bcm bcm_mm1_disp =3D { =20 static struct qcom_icc_bcm bcm_sh0_disp =3D { .name =3D "SH0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_llcc_disp }, }; @@ -1532,6 +1555,7 @@ static struct qcom_icc_bcm bcm_sh0_disp =3D { static struct qcom_icc_bcm bcm_sh1_disp =3D { .name =3D "SH1", .enable_mask =3D 0x1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qnm_pcie_disp }, }; --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B112C001DC for ; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:09 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:31 +0200 Subject: [PATCH 32/53] interconnect: qcom: sm8550: Explicitly assign voter_idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-32-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=10160; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=R7Ecrvuc6qvo53FMgbNdmnfTrkm2nzBuT8JYA7NSeZg=; b=7JcPwfgfhW2pBVGCghP4NdB7PkYfC0k2m2pMPnzv11dSYaWGj0cVZJdQGSwPcJDvlV21poK3s 7cAfSr0Sh7zBiFLhY9Hx0cToOoP5VqlOZlfwm995wuMmRQ9SbjC+T4q X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To avoid confusion, explicitly assign the BCM voter index. Note the assignment may be incorrect, but this commit brings no functional change. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8550.c | 42 ++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 42 insertions(+) diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom= /sm8550.c index 0864ed285375..40740cf5e41d 100644 --- a/drivers/interconnect/qcom/sm8550.c +++ b/drivers/interconnect/qcom/sm8550.c @@ -1474,12 +1474,14 @@ static struct qcom_icc_node qns_mem_noc_sf_cam_ife_= 2 =3D { static struct qcom_icc_bcm bcm_acv =3D { .name =3D "ACV", .enable_mask =3D 0x8, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &ebi }, }; =20 static struct qcom_icc_bcm bcm_ce0 =3D { .name =3D "CE0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qxm_crypto }, }; @@ -1488,6 +1490,7 @@ static struct qcom_icc_bcm bcm_cn0 =3D { .name =3D "CN0", .enable_mask =3D 0x1, .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 54, .nodes =3D { &qsm_cfg, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_apss, @@ -1520,6 +1523,7 @@ static struct qcom_icc_bcm bcm_cn0 =3D { =20 static struct qcom_icc_bcm bcm_cn1 =3D { .name =3D "CN1", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qhs_display_cfg }, }; @@ -1527,12 +1531,14 @@ static struct qcom_icc_bcm bcm_cn1 =3D { static struct qcom_icc_bcm bcm_co0 =3D { .name =3D "CO0", .enable_mask =3D 0x1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qxm_nsp, &qns_nsp_gemnoc }, }; =20 static struct qcom_icc_bcm bcm_lp0 =3D { .name =3D "LP0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qnm_lpass_lpinoc, &qns_lpass_aggnoc }, }; @@ -1540,12 +1546,14 @@ static struct qcom_icc_bcm bcm_lp0 =3D { static struct qcom_icc_bcm bcm_mc0 =3D { .name =3D "MC0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &ebi }, }; =20 static struct qcom_icc_bcm bcm_mm0 =3D { .name =3D "MM0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_mem_noc_hf }, }; @@ -1553,6 +1561,7 @@ static struct qcom_icc_bcm bcm_mm0 =3D { static struct qcom_icc_bcm bcm_mm1 =3D { .name =3D "MM1", .enable_mask =3D 0x1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 8, .nodes =3D { &qnm_camnoc_hf, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_vapss_hcp, @@ -1564,6 +1573,7 @@ static struct qcom_icc_bcm bcm_qup0 =3D { .name =3D "QUP0", .keepalive =3D true, .vote_scale =3D 1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qup0_core_slave }, }; @@ -1572,6 +1582,7 @@ static struct qcom_icc_bcm bcm_qup1 =3D { .name =3D "QUP1", .keepalive =3D true, .vote_scale =3D 1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qup1_core_slave }, }; @@ -1580,6 +1591,7 @@ static struct qcom_icc_bcm bcm_qup2 =3D { .name =3D "QUP2", .keepalive =3D true, .vote_scale =3D 1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qup2_core_slave }, }; @@ -1587,6 +1599,7 @@ static struct qcom_icc_bcm bcm_qup2 =3D { static struct qcom_icc_bcm bcm_sh0 =3D { .name =3D "SH0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_llcc }, }; @@ -1594,6 +1607,7 @@ static struct qcom_icc_bcm bcm_sh0 =3D { static struct qcom_icc_bcm bcm_sh1 =3D { .name =3D "SH1", .enable_mask =3D 0x1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 13, .nodes =3D { &alm_gpu_tcu, &alm_sys_tcu, &chm_apps, &qnm_gpu, @@ -1607,6 +1621,7 @@ static struct qcom_icc_bcm bcm_sh1 =3D { static struct qcom_icc_bcm bcm_sn0 =3D { .name =3D "SN0", .keepalive =3D true, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_gemnoc_sf }, }; @@ -1614,6 +1629,7 @@ static struct qcom_icc_bcm bcm_sn0 =3D { static struct qcom_icc_bcm bcm_sn1 =3D { .name =3D "SN1", .enable_mask =3D 0x1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 3, .nodes =3D { &qhm_gic, &xm_gic, &qns_gemnoc_gc }, @@ -1621,18 +1637,21 @@ static struct qcom_icc_bcm bcm_sn1 =3D { =20 static struct qcom_icc_bcm bcm_sn2 =3D { .name =3D "SN2", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qnm_aggre1_noc }, }; =20 static struct qcom_icc_bcm bcm_sn3 =3D { .name =3D "SN3", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qnm_aggre2_noc }, }; =20 static struct qcom_icc_bcm bcm_sn7 =3D { .name =3D "SN7", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_pcie_mem_noc }, }; @@ -1640,24 +1659,28 @@ static struct qcom_icc_bcm bcm_sn7 =3D { static struct qcom_icc_bcm bcm_acv_disp =3D { .name =3D "ACV", .enable_mask =3D 0x1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &ebi_disp }, }; =20 static struct qcom_icc_bcm bcm_mc0_disp =3D { .name =3D "MC0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &ebi_disp }, }; =20 static struct qcom_icc_bcm bcm_mm0_disp =3D { .name =3D "MM0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_mem_noc_hf_disp }, }; =20 static struct qcom_icc_bcm bcm_sh0_disp =3D { .name =3D "SH0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_llcc_disp }, }; @@ -1665,6 +1688,7 @@ static struct qcom_icc_bcm bcm_sh0_disp =3D { static struct qcom_icc_bcm bcm_sh1_disp =3D { .name =3D "SH1", .enable_mask =3D 0x1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 2, .nodes =3D { &qnm_mnoc_hf_disp, &qnm_pcie_disp }, }; @@ -1672,18 +1696,21 @@ static struct qcom_icc_bcm bcm_sh1_disp =3D { static struct qcom_icc_bcm bcm_acv_cam_ife_0 =3D { .name =3D "ACV", .enable_mask =3D 0x0, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &ebi_cam_ife_0 }, }; =20 static struct qcom_icc_bcm bcm_mc0_cam_ife_0 =3D { .name =3D "MC0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &ebi_cam_ife_0 }, }; =20 static struct qcom_icc_bcm bcm_mm0_cam_ife_0 =3D { .name =3D "MM0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_mem_noc_hf_cam_ife_0 }, }; @@ -1691,6 +1718,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_0 =3D { static struct qcom_icc_bcm bcm_mm1_cam_ife_0 =3D { .name =3D "MM1", .enable_mask =3D 0x1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 4, .nodes =3D { &qnm_camnoc_hf_cam_ife_0, &qnm_camnoc_icp_cam_ife_0, &qnm_camnoc_sf_cam_ife_0, &qns_mem_noc_sf_cam_ife_0 }, @@ -1698,6 +1726,7 @@ static struct qcom_icc_bcm bcm_mm1_cam_ife_0 =3D { =20 static struct qcom_icc_bcm bcm_sh0_cam_ife_0 =3D { .name =3D "SH0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_llcc_cam_ife_0 }, }; @@ -1705,6 +1734,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_0 =3D { static struct qcom_icc_bcm bcm_sh1_cam_ife_0 =3D { .name =3D "SH1", .enable_mask =3D 0x1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 3, .nodes =3D { &qnm_mnoc_hf_cam_ife_0, &qnm_mnoc_sf_cam_ife_0, &qnm_pcie_cam_ife_0 }, @@ -1713,18 +1743,21 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_0 =3D { static struct qcom_icc_bcm bcm_acv_cam_ife_1 =3D { .name =3D "ACV", .enable_mask =3D 0x0, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &ebi_cam_ife_1 }, }; =20 static struct qcom_icc_bcm bcm_mc0_cam_ife_1 =3D { .name =3D "MC0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &ebi_cam_ife_1 }, }; =20 static struct qcom_icc_bcm bcm_mm0_cam_ife_1 =3D { .name =3D "MM0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_mem_noc_hf_cam_ife_1 }, }; @@ -1732,6 +1765,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_1 =3D { static struct qcom_icc_bcm bcm_mm1_cam_ife_1 =3D { .name =3D "MM1", .enable_mask =3D 0x1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 4, .nodes =3D { &qnm_camnoc_hf_cam_ife_1, &qnm_camnoc_icp_cam_ife_1, &qnm_camnoc_sf_cam_ife_1, &qns_mem_noc_sf_cam_ife_1 }, @@ -1739,6 +1773,7 @@ static struct qcom_icc_bcm bcm_mm1_cam_ife_1 =3D { =20 static struct qcom_icc_bcm bcm_sh0_cam_ife_1 =3D { .name =3D "SH0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_llcc_cam_ife_1 }, }; @@ -1746,6 +1781,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_1 =3D { static struct qcom_icc_bcm bcm_sh1_cam_ife_1 =3D { .name =3D "SH1", .enable_mask =3D 0x1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 3, .nodes =3D { &qnm_mnoc_hf_cam_ife_1, &qnm_mnoc_sf_cam_ife_1, &qnm_pcie_cam_ife_1 }, @@ -1754,18 +1790,21 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_1 =3D { static struct qcom_icc_bcm bcm_acv_cam_ife_2 =3D { .name =3D "ACV", .enable_mask =3D 0x0, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &ebi_cam_ife_2 }, }; =20 static struct qcom_icc_bcm bcm_mc0_cam_ife_2 =3D { .name =3D "MC0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &ebi_cam_ife_2 }, }; =20 static struct qcom_icc_bcm bcm_mm0_cam_ife_2 =3D { .name =3D "MM0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_mem_noc_hf_cam_ife_2 }, }; @@ -1773,6 +1812,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_2 =3D { static struct qcom_icc_bcm bcm_mm1_cam_ife_2 =3D { .name =3D "MM1", .enable_mask =3D 0x1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 4, .nodes =3D { &qnm_camnoc_hf_cam_ife_2, &qnm_camnoc_icp_cam_ife_2, &qnm_camnoc_sf_cam_ife_2, &qns_mem_noc_sf_cam_ife_2 }, @@ -1780,6 +1820,7 @@ static struct qcom_icc_bcm bcm_mm1_cam_ife_2 =3D { =20 static struct qcom_icc_bcm bcm_sh0_cam_ife_2 =3D { .name =3D "SH0", + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 1, .nodes =3D { &qns_llcc_cam_ife_2 }, }; @@ -1787,6 +1828,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_2 =3D { static struct qcom_icc_bcm bcm_sh1_cam_ife_2 =3D { .name =3D "SH1", .enable_mask =3D 0x1, + .voter_idx =3D ICC_BCM_VOTER_APPS, .num_nodes =3D 3, .nodes =3D { &qnm_mnoc_hf_cam_ife_2, &qnm_mnoc_sf_cam_ife_2, &qnm_pcie_cam_ife_2 }, --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0115EB64DD for ; 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[83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:10 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:32 +0200 Subject: [PATCH 33/53] arm64: dts: qcom: qdu1000: add qcom,bcm-voter-idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-33-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1029; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=FFJMPSVIi/rnzhslrYEk6oNnRd5UMA/I/qlOvdMR/JA=; b=1yoDTc6kd8ZvHVFgmFdyi2Or4zbatDVvuAKn9V2a+ZPcKRh3aahwUN+dQ9O/e0E7q3U+zQUKY A6JH7xgCmDPA/3U9dZqnoHUGhGOMqWgfPbfvh9DBdnTZkFkZgICqPHi X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qc= om/qdu1000.dtsi index 1c0e5d271e91..6e4e049b1c29 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -1366,6 +1367,7 @@ apps_rsc: rsc@17a00000 { =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; + qcom,bcm-voter-idx =3D ; }; =20 rpmhcc: clock-controller { --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA2C8C00528 for ; Tue, 11 Jul 2023 12:21:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232415AbjGKMV0 (ORCPT ); Tue, 11 Jul 2023 08:21:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232270AbjGKMVA (ORCPT ); Tue, 11 Jul 2023 08:21:00 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 370E319A4 for ; Tue, 11 Jul 2023 05:19:53 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id 38308e7fff4ca-2b5c2433134so70398161fa.0 for ; Tue, 11 Jul 2023 05:19:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689077952; x=1691669952; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=pfbv/J9UlljbpfQkbJ1RQZoYi8S5NISMbRChDv8nMFA=; b=L5HgpV8Udn4sW3t9PDmOv15HQ9F6WlMBljK+t2VMRkrIIiM2b3fuP5PzAGSeJUHrtN V4FXNZOp0+hDlyo7mjjcM8J9IG9Kf1U6OocmKy6Vlv8lH5Sbkj5Hilz+TFDw73sTh52o z0vEcdtYEvMbXws5ujeCpQIRvECW0GAHBw/M+a/LqoUi1Ae/F+hce/FaJjjo29E6OCkH CgOh1bSLW7M3dYUnbOsE8LUFDV9CriIvDMnFprO0B7HFGnhhvotl78xU2M2JE5ZOUn30 70jKeMHgIl4GvCNpWsJkSzG4slhgZvAzM6PSpdL9Y9Z9zGzNrMVPV4lgipuM642UuhPi PdoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689077952; x=1691669952; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pfbv/J9UlljbpfQkbJ1RQZoYi8S5NISMbRChDv8nMFA=; b=etcKU4p06UgVriDWVBjjUuruoJXHqOsDSmXUFQjNEy3tlkyggb/tbGCO5AvI0wNMBW pXaOkG5XaZwNz2t7hWMBZ37NIeC5rlJht2ZYlgT1DXoe8grXI54xe02XWJAik88IfYXQ Zo7ji0sV9/Pdz4M0io2lc9OnMUNAJdXXp9St+4MueAbMWp8byEJsE3ZiNZbMfS/Zmmy8 BSH3Z7okZ2+YgSHXYQ61cCTT5O50XtoDAOJSIDlrw0CTAl1SFYOBxmrdVMovmbcHAxat oTbuDbkmXbD4kLhGcpHhJuVvWfGh0H8tl/alesv/MJjlclXXJbNdt4UhkIv9Lu0ws+eW 3akw== X-Gm-Message-State: ABy/qLZMn+NDdDAYXZznoZ+X8L7ZWoFfV42OlOnNcJhFXqrWNdyex3ub suUjJg7FGBB1s+r8GesQRW92Jg== X-Google-Smtp-Source: APBJJlHWMJd8XJU3a0oV2Zgz1d7jAlMWXwwV5ij8yhcJB0LV4nihkRh4yfeLMtprJ56gdLV17Zz61A== X-Received: by 2002:a2e:2417:0:b0:2b6:d47f:2a4 with SMTP id k23-20020a2e2417000000b002b6d47f02a4mr6482909ljk.13.1689077952048; Tue, 11 Jul 2023 05:19:12 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:11 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:33 +0200 Subject: [PATCH 34/53] arm64: dts: qcom: sa8775p: add qcom,bcm-voter-idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-34-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=670; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=J+YzV1ysLrALsNig4GY1Hu1u/TnFl+lfs1ry3Cimg4c=; b=RnXcZb42j9gisrdfBq2D0dwqm5OBc1WiW3QgOhaAD3dwMseB7SUn+nM5Ps3f99EzJaYT0vBQ1 tCFypJ1rmhqAkCv6CuZsCvsUEQh2WU6TvIVwHQcQJq3Dp5uIp1YLfiD X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index 59eedfc9c2cb..e38cb436ed1f 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2243,6 +2243,7 @@ apps_rsc: rsc@18200000 { =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; + qcom,bcm-voter-idx =3D ; }; =20 rpmhcc: clock-controller { --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DD6BC001DC for ; Tue, 11 Jul 2023 12:21:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232353AbjGKMVl (ORCPT ); Tue, 11 Jul 2023 08:21:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232331AbjGKMVH (ORCPT ); Tue, 11 Jul 2023 08:21:07 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15F5A10FD for ; Tue, 11 Jul 2023 05:19:58 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-4fbc0314a7bso9040843e87.2 for ; Tue, 11 Jul 2023 05:19:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689077953; x=1691669953; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=fUYkKYV4ujMuk/ZAzUO3GhIfjlSDACYKMYMpvbHOS0o=; b=OgunhkVOF31gy38IhMYvZho9KhSZ47S9iBORV+B36TBHEI1JAGoOya2CnSx0xvAq5v liYYiSZKkzTxHN0eE1ZHZN8GnyINqoW4vX9CzMfKqC0hymDNkSlYMuuikfxmmc7P/9/7 QnYrYgoJYopuQIMsxEfvJ9kVIrNI0I+g4ADspVcr0fibplX7pI1EzGfRHHMgQ6Np0IHL yDbYoAPrLD0IkK/WKk8gep9brzNYyxwTw+8+AuldU48HIUA9tUlOECSDy4iFX7z/fabW wyBC95Ln+K65PUff0VbhhPeTvbTFVNiXgUcujfvrW4UsdN2Qh5whMTACusaKtp54t7FN uAqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689077953; x=1691669953; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fUYkKYV4ujMuk/ZAzUO3GhIfjlSDACYKMYMpvbHOS0o=; b=hLvsR//0oQfrWlsmZ+ssYjWnVxBGP49BI/99cHZUdqh5dwKe8XMY6qNAdgPnlwOeLV lXQnMh8JvPeaQKGTtCBSOGEvJd3Zx0/73akZB2MrouaUPfvdl+KAkLaYWNQ/QHmVNbzz +M4biW8pxaqc93km3fXU4jnb0bfKllXvO+ggcxRaRC0L8c/SOZEi9WR4BTYMww2C4+ER avWMDE8Tox9y8bliIgGg83/qj2Cu0LPNRvu48QyBjQpIPExhDns/i7GM2vYmUwLveU2f oTmaiduJc99225JTOlgrGByW7S6LF6rqryKVmET76nhDIFyVVtn5pIdnh61hqMNceR2W VdBQ== X-Gm-Message-State: ABy/qLadcdTx3pvz3/4K46gig9Zcu3N6IHdxBC+DaaygxViKMcAyx5WI 3bZF1EjU2HuOrKB984JJfngzvQ== X-Google-Smtp-Source: APBJJlFPUmyPSwMDVSzJWoSM+iefcHajI+de62524A0AkTML6/JzXuMpkaVh+NTJM4H+MO9OfFHL7w== X-Received: by 2002:a2e:8210:0:b0:2b6:dec9:2813 with SMTP id w16-20020a2e8210000000b002b6dec92813mr12673229ljg.29.1689077953345; Tue, 11 Jul 2023 05:19:13 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:13 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:34 +0200 Subject: [PATCH 35/53] arm64: dts: qcom: sc7180: add qcom,bcm-voter-idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-35-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=644; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=xdrbax/ndnKE1dzVNPWI8e+2pkkV5TGwm4Tup9sPjbw=; b=ULJhbO/N8xan2DF4ZAbAkoTD8jZOS6LFAS8q/YqNYtwsRloh0iYcbUBoTNfPR7QB3ush0REIq 9YjPh6F2yYjATxZuvg5kiiV3rlOj8Y9dltoQtB+QSLrRjusYdbPNHcU X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qco= m/sc7180.dtsi index 179544ba12db..cf12f358fabb 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3653,6 +3653,7 @@ rpmhpd_opp_turbo_l1: opp11 { =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; + qcom,bcm-voter-idx =3D ; }; }; =20 --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00304EB64DC for ; Tue, 11 Jul 2023 12:21:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232060AbjGKMVp (ORCPT ); Tue, 11 Jul 2023 08:21:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53010 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230305AbjGKMVI (ORCPT ); Tue, 11 Jul 2023 08:21:08 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23C3219BA for ; Tue, 11 Jul 2023 05:20:01 -0700 (PDT) Received: by mail-lj1-x22f.google.com with SMTP id 38308e7fff4ca-2b701e41cd3so92160741fa.3 for ; Tue, 11 Jul 2023 05:20:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689077954; x=1691669954; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=3pF+62BSgddTAPKCaWz/3Ipd5EEzHkODMPLMBcdfC3I=; b=QQ6AVn8GkrhIPnn/Y25w2TGlQrJrTSjFw41oH5TzJ4FrG9nVw8HqxfVHy8BTdGBLp2 sk8n1svoqhyPqEMcJGZyQ/H4/XNUFgdbhh3HmBpYWNbPmQdeFnnc7ULooJ5MT44745v7 CPNoa7axo7RE5VaQh8RxWhNzuE+aTpdXXk0vR8p6PlA0ZC9PKHjyMYX18vHXH7kqe/cR bVXUneJq2tb8f5uOlSFKS168MfuPXfKDXP+LS/0wMY2D8C6sejbZYOgYYYzfxX/LdyOy eQQEx+M07uBSxv1yPjcuQWpjrdR9NMd90RKi65DszrCdtdI0kck5RSpxT1oqpO+jJuEk zPQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689077954; x=1691669954; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3pF+62BSgddTAPKCaWz/3Ipd5EEzHkODMPLMBcdfC3I=; b=YsKZ5gDO9b/P9i/6qru5BPIKN7SDEHT63OlPxiTTmjmWZ068jL+biW/S+vj1d6LVJu mNIKaaFq84kCksX1c3h+dyjNCQjnjwipZQSl5ZLH/SLYNv6/X8Cx74ewQXplMgs+DwvZ Me5MrqWFwQdlS+KUOT8+0ggXBhRDoDXptkjsweye9iaLbrFnzIMRps7eT6yiUp6p8yAp Au4K+ufIeVNEEGQL04zUFhUTt+g0kCwjgEvjHqT0Fh1KgQzX6Z3qLfIbpPWisteYRGHL wEzcq1yrJ/GNH0/SavgXCWGiSx1+5onPG99NKqwHxygt9Iczi+ufYijiNyYWqwI0L+8q hNjA== X-Gm-Message-State: ABy/qLZRqHPava3pJ8igtoRef0zQdv+mhJcTkkzP2LjuKBHf7v/50itm nKjQbuQOUFWT08NmZUnTinjocA== X-Google-Smtp-Source: APBJJlEOmCRxgEtcuv4MoDu09F3K6BxvXNh08C+sZ++tsAMXi1rnHdDQ08daifSH/QIk0TMHxBeiwg== X-Received: by 2002:a2e:8085:0:b0:2b6:d9b0:875d with SMTP id i5-20020a2e8085000000b002b6d9b0875dmr13300282ljg.34.1689077954579; Tue, 11 Jul 2023 05:19:14 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:14 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:35 +0200 Subject: [PATCH 36/53] arm64: dts: qcom: sc7280: add qcom,bcm-voter-idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-36-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1025; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=nytm9EolJCU+y++LKFvuDAt/1VSGVvY9ubKWLH3kdjQ=; b=MXIbUp80VLgVzHgAsczbdl+x2lP+g4cVPrIPNIvPVACY8QAdMnLDpC+0PiIwuQ9UpX4LYTGEF j+ER9dzS1+7CkKnv6yiBlm4fqAn81IIWTPxCW61QjC8EHSbst3oJToZ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 925428a5f6ae..a45d9e12eb97 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -5294,6 +5295,7 @@ apps_rsc: rsc@18200000 { =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; + qcom,bcm-voter-idx =3D ; }; =20 rpmhpd: power-controller { --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CE9FEB64DD for ; Tue, 11 Jul 2023 12:21:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232159AbjGKMVu (ORCPT ); Tue, 11 Jul 2023 08:21:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230482AbjGKMVO (ORCPT ); Tue, 11 Jul 2023 08:21:14 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D7C642705 for ; Tue, 11 Jul 2023 05:20:03 -0700 (PDT) Received: by mail-lj1-x22f.google.com with SMTP id 38308e7fff4ca-2b6f52e1c5cso88512171fa.1 for ; Tue, 11 Jul 2023 05:20:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689077956; x=1691669956; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=RreYIt3ZnMFF0R9LfEKzWTch1LksZzSPzwy9Jv7pG2k=; b=UwgYDVcLVGsIgP/ul5vpQw0hx6+bu2iy8Agkr7kA9N8pBiK3//ng6xrO25UP4qL1ZW YvBrCHpSDUUr5VGPC49Oj0guxiEAeuTT1fP2CgJVXJfnv0eFa2I+jWRZjMnSci9HoRje 1gac9xsR9b2FN1iB+n3+2BG6iAHDYNAo/HJU/VwF0jfELddSI+ohQWheRi5uu86jmxNM ro6d0hvVDe4n3s8YYwZMjfrlNpYdWGpYJubRJs5MgIprExCpBDGcxww/MhD0Db5lqmfh oqK2cr8KK2r2a1uWmwbFyvIOVZTFKFW59abQwt7RXqSixEs1GG0ireUHukqvWskJVr7Z HhZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689077956; x=1691669956; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RreYIt3ZnMFF0R9LfEKzWTch1LksZzSPzwy9Jv7pG2k=; b=bf6uAG0Q//CtJJHUDxPoz2siKko6e7P011KGKYtAAEGH2M/zR5Voq6018G7tjfX8vK sId3zZf3lBGQoPNUc40jQz3yBK2m94RzCeGaufAPck0seu0snDuc3jcxuvJM5O3zvXJW 7G26o00Lxa+TTCt7XS6ZWBEsQEYGxwlhMTI3DWq7pp0EtLaztmzxwm2dhvAt1qFX1jCD Q+G4vy/WchQ975VU2VJ4J97zEGThNtqrl5DLF+HUwgJAIejwSY22T69+cHQTXQeykbYA 65p4Zl56MOtrMcGDdiO/1yY3EwEvb61tN2bs62Wg0SzQIlMRbrydUorenwM6QFnyNFDI 3jIA== X-Gm-Message-State: ABy/qLaznUlqs8zqhyHE42ANGUiGmxwyz+KtqFTBQ9Y2xIxmYwsewsS5 WTHGocWdoEhIB6/VfcfJ3e7cUw== X-Google-Smtp-Source: APBJJlHQ3oe1G8p+PWR24oULJ5EqoNFC0vkRQ/1PtF1/nlVMR1EgTq9h3Rr/GNdy+Qyd37/obOIDoQ== X-Received: by 2002:a2e:99d3:0:b0:2b6:e3e2:5045 with SMTP id l19-20020a2e99d3000000b002b6e3e25045mr14566230ljj.18.1689077955830; Tue, 11 Jul 2023 05:19:15 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:15 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:36 +0200 Subject: [PATCH 37/53] arm64: dts: qcom: sc8180x: add qcom,bcm-voter-idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-37-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1043; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=QsxBAhmF4V+7cAeh292jLOJ0EyFZPEAL/VdNYG6uwy0=; b=EcINMFAuqr9POkjtP9ouV28bSDwaunALS/IJtAXkha5ZPq8MnvKlayBi1+JHun4UsH1AaxL5q VCJU1VpxMvoBWzhtrdtBzwPXQ4C90YZjC7B812kmR/BQepghhNjS74J X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qc= om/sc8180x.dtsi index 11dcad9c6e94..b12d6d573678 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -3500,6 +3501,7 @@ apps_rsc: rsc@18200000 { =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; + qcom,bcm-voter-idx =3D ; }; =20 rpmhcc: clock-controller { --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 280A6C00528 for ; Tue, 11 Jul 2023 12:21:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232539AbjGKMV6 (ORCPT ); Tue, 11 Jul 2023 08:21:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232062AbjGKMVR (ORCPT ); Tue, 11 Jul 2023 08:21:17 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D4ED2271B for ; Tue, 11 Jul 2023 05:20:08 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id 38308e7fff4ca-2b701e1c80fso85717841fa.2 for ; Tue, 11 Jul 2023 05:20:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689077957; x=1691669957; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=9mLuew5zgjzaN+tG4LFNS3rreDraB5w4e3ZMY58XgsY=; b=vvxaGnbe11lhmDT+XdN0kJ6KKJi8aF2RjRLtmlE9A/ihPsDkHXzLPSlE6cBUKFMRKM ocULQm3cZBjoFQypFWDT3lKvD1WbYymmmLBoVzWPFBrEJl1ATzRP7D9ZGf8j6fMmEDXj GFWVLox34nTPw8KEs4hgvmcVUvxw1mI2T8AhkrNfkWsCsQ53Lt4PjvzKY2fNeZ+T+BNl BzeEg2oLZ59EXJsGvwvIanyHuxiUZOXOoVwvnApm7/Q1Ihu7eCOXH66xo75DaneWTE0M z2yzJcCn52VOdB91xGdqjsrC4fDKpINgZf1v3B4KSRwza6xjj5dEMShVNtOj6y4M8zJj p+Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689077957; x=1691669957; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9mLuew5zgjzaN+tG4LFNS3rreDraB5w4e3ZMY58XgsY=; b=WSEjHpTJeUa5DheXHyzWY8Zlq4RoeoDJrjIHMhKa8cYsIKq1Z8De4fKlCE7UXCUyVm pzgbp1jcnuBU5Ex+e3FQ/Ua+BuYA2pXogRVcNzF9DqqgMaAv2MRI3O+6inV+7ld8r9zw SEb5FNGHTm1BvoDTpRbLBrxvVe0MoVD32x2u/R0pv0QhMKw5xRx4G1wRiXOPfrXQcjsf CRuH5iyAWuAWVh6y2uCPbBL28mJEHJZG3/MS8egqm3eo2x5Id1MYTs3IcxgEISrO9mLP j4bIz7zntYdKjaMOrJzmWnWU/oSbgqgy2lfUgbgdN8RZuDdw840cT42Q2iQt9lAwujo8 f86A== X-Gm-Message-State: ABy/qLbthZHM0VZx7wvxuuVqy1nO20yuDZ1jrU+qzr7LmNGBvF3opSNw yHZw5+DgLqNJnRcjkTxEwiTsVg== X-Google-Smtp-Source: APBJJlGa6PYiX6RAqLPgNrp8RP+7cwVVc6VZfagMsHb1oIMItRTj5g4Ls+QLw0+n+gYFG/dfd9Yrjg== X-Received: by 2002:a2e:7802:0:b0:2b6:fcd0:2aa1 with SMTP id t2-20020a2e7802000000b002b6fcd02aa1mr14053280ljc.43.1689077957095; Tue, 11 Jul 2023 05:19:17 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:16 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:37 +0200 Subject: [PATCH 38/53] arm64: dts: qcom: sc8280xp: add qcom,bcm-voter-idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-38-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1056; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=hBBGgOqK76JiEy1Y4zr3la6Mn+bAAjoLLiY2eeUBjv0=; b=JKLU4Q8Oos+cK0u7H0/xlo8WQFeN27LnL/bSuf2rwkYhgICdcFnbjGEyukSjuv1FZhS/9OfPN H61d300OZhTBmJtnuW1aUe/Gejqhqj2u6mQF5et6yp7IJjx8G6/JlGE X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 0756b7c141ff..67fe019b3c89 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -4303,6 +4304,7 @@ apps_rsc: rsc@18200000 { =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; + qcom,bcm-voter-idx =3D ; }; =20 rpmhcc: clock-controller { --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B1AEC001DC for ; Tue, 11 Jul 2023 12:22:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232402AbjGKMWB (ORCPT ); Tue, 11 Jul 2023 08:22:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232237AbjGKMVS (ORCPT ); Tue, 11 Jul 2023 08:21:18 -0400 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D28432723 for ; Tue, 11 Jul 2023 05:20:10 -0700 (PDT) Received: by mail-lj1-x22c.google.com with SMTP id 38308e7fff4ca-2b6fdaf6eefso87515511fa.0 for ; Tue, 11 Jul 2023 05:20:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689077958; x=1691669958; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=t7SX5vYNZ+wh+FjSCpRImtxC2bIIfmNAdRBfKIkKVN4=; b=l8E9UNCsvpEfG8fWIlzVtSQXLQ5/GbhyW8cFcqDBQcTujSUr9tjyEIYebotXGdA4wA VluiBtuxVvmZ5DIENTY53xRWpQALZCkcU/jqEk5W30743ivnBEob0uVsM/yZnifOeZUw w1q0pnGVuFbJ2yPlM6mrYpoQ8wGl00UzI3FCCwnd1qzkYajJGAbf0JITE2XZR5lljqt7 K1Ag4BYL0p5ETEiVBYZU18Yb9y1on59Wt2XWwAYeNI0dAuAjZuxn6XAqWyAddd1rZs5F NQCQ7AiZmKyhUhhxsTvLFzfWySsE1Yb10o01vqzWOsnCJFdBlzRxX5fN+PFaXYrYkzP+ SBLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689077958; x=1691669958; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=t7SX5vYNZ+wh+FjSCpRImtxC2bIIfmNAdRBfKIkKVN4=; b=RUozo9I7ZHmPOAEuSsdztj7q/Ur4M3FHMMQhs590TY8eB4ddRU+tMMRMFiu66eQCD9 QPi7Ze+u0kkT4kDbFdxb4xjPjjmGUOfrIAX/i8Mn12cyKCxd+N3QZMCpHSabIoO+UlMR ZHwcZ3TPRgsHtjhQWVDyd6gcF9YIBDQhe65HvzXTtWPlZIC4SuLGPY65GWVvGi4kzovh m5IEnp45cmHGdpTEwikTS8StaG2QMoM6pcbh23IJMtMbWpQBLBjhRhBtTGL9bm4caDho rJiCwaQHd9NS9SN1zMoaXrP0qpOPACUiF+xfURRMSFxMHXmjHjp0e+Vi+odpAodeFVOa Ck5Q== X-Gm-Message-State: ABy/qLZ6Ekq2XVu38XBG1H9c9mX9JCGb8zKRQUOaTGhrUMmru1eMbFWZ n/SBs9onA9799Vt8YSdbX2x/5Q== X-Google-Smtp-Source: APBJJlEvZPjbKWwtLDyi+m7uZe8apYx172lgwNKreWCH0nz12Ju4Bh1onulqt53ikGX0xnMnpF3nUA== X-Received: by 2002:a2e:9250:0:b0:2b6:fe3c:c3c1 with SMTP id v16-20020a2e9250000000b002b6fe3cc3c1mr13217950ljg.4.1689077958296; Tue, 11 Jul 2023 05:19:18 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:17 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:38 +0200 Subject: [PATCH 39/53] arm64: dts: qcom: sdm670: add qcom,bcm-voter-idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-39-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1014; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=RqHxnyd+iOCRwffNFe4siVguI4dHOX8Md4wGpVAKjsQ=; b=0n0uMxCZbiXY2lhF4JTtMPW5JgVP+Mrojo/yroWgbTCvcMU7OiW/Y/lZB03SHvLVohu61Lg9L XMw6pk6FW5xCFkJ5DdmkDzEt6hTEfZaiOBNO7wrancWerQ9KPhUv5y4 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qco= m/sdm670.dtsi index a1c207c0266d..377e6ba57807 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -1286,6 +1287,7 @@ apps_rsc: rsc@179c0000 { =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; + qcom,bcm-voter-idx =3D ; }; =20 rpmhcc: clock-controller { --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6019EB64DD for ; Tue, 11 Jul 2023 12:22:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232416AbjGKMWF (ORCPT ); Tue, 11 Jul 2023 08:22:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232386AbjGKMVW (ORCPT ); Tue, 11 Jul 2023 08:21:22 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6D3F19BE for ; Tue, 11 Jul 2023 05:20:11 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id 38308e7fff4ca-2b702319893so89303591fa.3 for ; Tue, 11 Jul 2023 05:20:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689077959; x=1691669959; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=V7PIgAp3e9OzKKcu+9DEgLawk9vSlyfAdloqW5xIZPE=; b=rb2eqLzMyPowvQydSZAKsa4tE7xgx2HK+piNpPl+c142180UXSSAP0CZM8UPq29NsJ E1kXvMsMzJVzR0BPspMCFUolGplvI+uWgtsBwk3STmGA3ZYw228Cjy0Uk9NlLbpquLsB DAcs3ML9TxoxotbAYbMupJQg27QHvsjeifwlqiyY1XEoqIyrkv4mb2clImqLX0Gw24RA 5TBo4ajaappxa1VHP0fBYEhPMxyrDNLz5F+ej0jqSopP3kadcqc6ctE/+MqTDslqwLTi Nvc21l69DnUkZWnt11/Z3ppIV6GRWURhBixKkEkhNP3+CpSB+lSPeg8748AbJTFvFGK2 5Fag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689077959; x=1691669959; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V7PIgAp3e9OzKKcu+9DEgLawk9vSlyfAdloqW5xIZPE=; b=hoDNh+1ki5XGcBrIm9rU0OHWSgqFpiBw/aEnKOvON6OYSq2mEfiTDFoy7AZcJicvph nOcz558U5THsUgV1zaWLxCx9g7lKADmHJtB0MbrE9gA1t9PZPzo60svRrtw3Yy/dowPt 4IJ7ipAoiguDaqJ9hITpGcMP7NVqYTi1SVBz7YQLg9XHkYb3mrnkcxeqHVRb7lhCJrER aJ7+nqxpUyYkbrEKwvrc1Jx4cf3mMfukUEuRtN1AZYx8LUNa/kZDgzktpK3/oiUyZ7JG 17ZfaZuUo7qng+uI8aGf/6R7X5b5qT+H/JBx8lYImI7PJe3Qb4WQbCI0uPVfH+SMgEiU HLCw== X-Gm-Message-State: ABy/qLaJMxOB0bud7tfxs8NNR/1MlebQ1lNXRe3/EHTMJKsA+4s15dCF r6lNt2Q9DkkZZucrkhVnyfsv3Q== X-Google-Smtp-Source: APBJJlH39BSC3oxdxluViBIlLqHBe02rhLvZ88xnOKpeR0xFV/NYTTVPmgj7i9LIgHLywRq39YKs1Q== X-Received: by 2002:a2e:9194:0:b0:2b6:e6cc:9057 with SMTP id f20-20020a2e9194000000b002b6e6cc9057mr11591328ljg.51.1689077959542; Tue, 11 Jul 2023 05:19:19 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:19 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:39 +0200 Subject: [PATCH 40/53] arm64: dts: qcom: sdm845: add qcom,bcm-voter-idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-40-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1017; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=FtWJXYwgz7AFS7yftzfhIEpRiM9nqdnApDQ7r1Yxt6E=; b=NFHseIjlf47+cZ7Y6inhcqRB3z2xw6piO4cnR2TvPF9RTvIX0K9ceVjHDtw1I7mK95oxWRDkf 121F9bjlnUEDmKoJMmA69oNbSbvnO6A6uOwcOntrUzTwqLmTS4wZsxc X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qco= m/sdm845.dtsi index 02a6ea0b8b2c..afe0712ad808 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -5142,6 +5143,7 @@ apps_rsc: rsc@179c0000 { =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; + qcom,bcm-voter-idx =3D ; }; =20 rpmhcc: clock-controller { --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 578C1EB64DC for ; Tue, 11 Jul 2023 12:22:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232427AbjGKMWH (ORCPT ); Tue, 11 Jul 2023 08:22:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231704AbjGKMVd (ORCPT ); Tue, 11 Jul 2023 08:21:33 -0400 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D2371BCC for ; Tue, 11 Jul 2023 05:20:17 -0700 (PDT) Received: by mail-lj1-x22e.google.com with SMTP id 38308e7fff4ca-2b698937f85so91827591fa.2 for ; Tue, 11 Jul 2023 05:20:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689077960; x=1691669960; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=gGY16j5dFZopf3fqhp0nExOr4gAGTapoNrzo7XeioLg=; b=pDq7+w+SWQCkI6+nEShRxNEtGCjtrQl5KtZ7oHlSdmsu3JgMT73x0vQifOdE42tTQl FsjZR4t4GhDOOWApa90xhVRxj5eERZKWmBT9OWburgqZ+T+NJ9nv0gVyURy/RfDoZGBs T47XzCfvyxIGsYS5LyamRu6I4d9RtuGP6domPKbbF4ZHhnqJDMOS8dyfz5Uf2dN0Kc9Z F2n5Vw7Ua+Ek+/2BaKVQv6OkWtBPFSWJQV8koY+CQikTh5mArOUmlgDLoQDjK9+EBIu1 gsl+bSnt5uxiUZ5bUaEBJ+OCo+36+erXwFy7PN1WjGq1piG7nj+YyVRgghSNSUOBJuE2 K8tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689077960; x=1691669960; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gGY16j5dFZopf3fqhp0nExOr4gAGTapoNrzo7XeioLg=; b=bMjkVc3WMs2w08nVeFR96qCKD0FujM/w5pcBgmpamraaRXJzFSb4iZ3zayeVeCU1gM 6rbg/LJ2il8VBM/Ji68yLccfW0sxVXZQPV4xicucPxAdhtIMmyTlUQ7lHr2JXJLcxjI8 wVQ0of0AOVrUMgjJeZI18YAMl2tKtJSOx1EKllkGzgjrIjTwBf8+ajORpSo5lOlgASCa KV6A6mfvsOBw/CkJMd72Dk8W1WxpoFlqlffgDYVENIE/7qlkJTmkPTXscgmo/aQaCcjn tfX89t1bsmgXy6LNdF0smOV9EvmLl6IyEtQTrAfJ0tDmaj0q/Cdqm10DKJyksWJcAxYN IaLw== X-Gm-Message-State: ABy/qLZGOs83IE4trZ0tjYV1lXgcJ9Zm/Fw6pZPeu7KBgPniFzGzrNY8 gwVwEpOg+DuqvBTBVBwFAsMcRQ== X-Google-Smtp-Source: APBJJlHH1du20h2dGbFyCfXBkhu0RcGK1O4c+R+VQ49+VkH4LKSqs0anMfFjKgYXCmu1PgU+sxLdjA== X-Received: by 2002:a2e:95c4:0:b0:2ac:82c1:5a3d with SMTP id y4-20020a2e95c4000000b002ac82c15a3dmr13236574ljh.23.1689077960776; Tue, 11 Jul 2023 05:19:20 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:20 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:40 +0200 Subject: [PATCH 41/53] arm64: dts: qcom: sdx75: add qcom,bcm-voter-idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-41-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=924; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=EOUtHrbyChcnQ5Qb2DspxglgtLr61gwWppeXGW3x820=; b=z+vn8kUSfJ9dq9Q3yWFJseduC5gaarOE21ft8/BpJ1DYsiiGJy1Iry2wojZWxxk5c6ozrLP54 XHiO1PMI0YuDmRCGUL6rqp7lsMQT+e9vr33lkPKPEqerL6t1HY7Ma9k X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom= /sdx75.dtsi index 7d39a615f4f7..ecb194aece80 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -8,6 +8,7 @@ =20 #include #include +#include #include #include =20 @@ -635,6 +636,7 @@ apps_rsc: rsc@17a00000 { =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; + qcom,bcm-voter-idx =3D ; }; =20 rpmhcc: clock-controller { --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56A89EB64DD for ; Tue, 11 Jul 2023 12:35:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232597AbjGKMfB (ORCPT ); Tue, 11 Jul 2023 08:35:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232530AbjGKMev (ORCPT ); Tue, 11 Jul 2023 08:34:51 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E73241717 for ; Tue, 11 Jul 2023 05:34:22 -0700 (PDT) Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-51e57870becso2863079a12.2 for ; Tue, 11 Jul 2023 05:34:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689078791; x=1691670791; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=G9v4ZXfNPn9qlJhxs+gp/ant1A453p1BhRobLNcBnVk=; b=Up4HteXzXYxshse/QHhHUUPRI35rS5r2DpZ1dqojER5Nsx9EfvRga46A0W6XK7jJuP 0E0A7OYk7sGh52rWkSHT/pjzFdGjUmebLkEDHjy7wtyCWw52DNKQxUauW7M+Ee0Pa7QB 5FkDpnMCEVrb5nQfAmxJ2XArqydsQBRics47K55MGq3A1ne6LGkpsbBVh92dPYd/1Jks h5d/a3mFlLiMHGjLkQ6Ye9/cxq9rh6oZJ+1APGwZBMeZzuFTPmAvX9HTjgbM7XCts9Y3 7eq0IYf+SG9Nn271arN4tSaeiqztkV6vo8dq3NQYYQKe7XRS0BYsqagn5Ggcd41xL4qu +N6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689078791; x=1691670791; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G9v4ZXfNPn9qlJhxs+gp/ant1A453p1BhRobLNcBnVk=; b=iyAOeNxh+VicZLmujcyyIyLpuWCmbSQM30kIezaecwrewalDKV6YuvCCZdU7xjYN0w jzdSejExdZTtlIRoePD+ugM4D3VnI+KOgVgBiYLvx3z058lASE7iArNMLA3V76iAIrVh I7RpgSW2aoQgmqZmThmVg1zLOaMmNsoZNFyHb0vlQyWjRLWkwBU8hbqHUvOVlJBETbJD 1ye0mvgHFb8PNSWHjF/qUOr945bbg75VHHU5QqxQ8WGeoQ+LZ9QufG/0w20EONMuRvMT 5ap0NfuX1uaQ2Ksp0aODLmuRD5ZgqzwIDwVsjfxlExVCKPHlTHIO4ebQDxWHKJRUsahb yN4g== X-Gm-Message-State: ABy/qLZX6HwnCqNYALDdALqtG0Dqy3Mdt5OLEpgt7eZh1TKUksXni7FT 7eQN4TvLWnMjPYor5DKKM/3mXu6wysJCw1Bku9DhZQ== X-Google-Smtp-Source: APBJJlGt975r1L3ME9SiPu7XfWBzrD6W9t9yg+ez2+RHTRoOIxDF6/VsWrx6pvoj7Iig1uZMdsOG9g== X-Received: by 2002:a2e:9c07:0:b0:2b6:e17c:151e with SMTP id s7-20020a2e9c07000000b002b6e17c151emr12101413lji.48.1689077961981; Tue, 11 Jul 2023 05:19:21 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:21 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:41 +0200 Subject: [PATCH 42/53] arm64: dts: qcom: sm6350: add qcom,bcm-voter-idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-42-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=644; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=3BXN4Qsquy4y5qOl9KpHX7nLXTZ8ImSw5T4ipGBkQ1A=; b=L4P2R1cTX0Mx5tC2KxNyNlk0tY9lOiawmJDvaVn06l3qHluLU/5INXihMYZKQCkrUV54h+PyO evh0Q52kgDYDMKkfN9XL1doUqB6VtMhBVyMInXNS4GKDnYkZ4s3SEBh X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index c2b5d56ba242..1f52f63c5a57 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -2563,6 +2563,7 @@ rpmhpd_opp_turbo_l1: opp10 { =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; + qcom,bcm-voter-idx =3D ; }; }; =20 --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF01FEB64DC for ; Tue, 11 Jul 2023 12:35:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232565AbjGKMfU (ORCPT ); Tue, 11 Jul 2023 08:35:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232606AbjGKMfJ (ORCPT ); Tue, 11 Jul 2023 08:35:09 -0400 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA8E91989 for ; Tue, 11 Jul 2023 05:34:40 -0700 (PDT) Received: by mail-lj1-x22e.google.com with SMTP id 38308e7fff4ca-2b6b98ac328so86259941fa.0 for ; Tue, 11 Jul 2023 05:34:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689078817; x=1691670817; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=mouIVN5aOfpssmEDC+p5ObsXA9SRTIu++fiUoxbGev4=; b=yqyRBtgA93ViYXXk1ZCxyqsdoP6lzQKy2jPekghjI5CckcikX8k/0b/Vr8cjjcCLOe dzBhxDUfVJqERKC8tr5LDVelbh7Flq/u5stlQkjm9QS+StLyL1/HyXd+WhHEBWtK5o3R ZcT7U0p+GuaaujXleu+n44dSDG3nfxr7d/kDOKfhpb10X8Uc4cFmvuWqNdpxgrfj9mDJ ccygmomvpdj/Jl+2i0JvtxGdLKwnN4PjKfwzBB0hT5gTyWuaDnSCpDrMkAmc6C4vCoif Lf5a8yhTyZLnBcwKIZieb+roA3KQcKCyQxL3XwNxUbkQtd9lXr4sNn642ElSdlavar15 K48A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689078817; x=1691670817; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mouIVN5aOfpssmEDC+p5ObsXA9SRTIu++fiUoxbGev4=; b=d6dyeYUOugUeTqOx5N5iISepYadwVXQPD8aW39Q2KWUg0jQHh/G8AShRD71VLQcCBm o+nXbBn3NZQTX6+6Fof5vSidy1WUTlgRVA3b9WH5NBMnTQV1xyiV4CRgyuUM99fpJNzh eMc4rWuLohZPJVoSXAJ2FdjiLIuGRnrcncYoRRO5IAM3EHNr3Xy8U36C5YmIJw+L68Fr LYjbWbXrjO4yAkhwMGiSouWuVysvcz6/C+WyvnqDnU38jnxe2ssIwmwfWXLvfZnDUCve QGTOd4NMaGmXHMk58mHnI7YyzjX0IB9zq8q7PGQuKTc+YBJBtrDQNVcjHv3EHo7H1Y7q hH5w== X-Gm-Message-State: ABy/qLbRystDwPyQDLUnThcSiZnfR45E/IYHxxCrJNP7R9doPmdIjdmR LOsyBIfi03u3hsfaAmEglMLPNXOmWQLGtiN88shp1g== X-Google-Smtp-Source: APBJJlHf7yZI2vtKJX4P2V9vqBIPPM59NaTPvsu2eRHNcNAUC+aIqXx/owlrcF2ZViyku+o0Bd677w== X-Received: by 2002:a2e:6e0e:0:b0:2b6:eb5a:d377 with SMTP id j14-20020a2e6e0e000000b002b6eb5ad377mr12645471ljc.5.1689077963176; Tue, 11 Jul 2023 05:19:23 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:22 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:42 +0200 Subject: [PATCH 43/53] arm64: dts: qcom: sm8150: add qcom,bcm-voter-idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-43-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1013; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=x0zGLJs0yoPS/RlnCeGNLi2dqlpoVvi8tNVTarjGkbE=; b=FSfXcsHn89MM1aKOUdCdC6mngIske/lMAzWCWPFQwrEpmxxUCYs9/p7KkltfVx0irKTji+kGL lJuu/TUXpvyD7WNEkqwsIUPvSbBK8HeL20eBfb7txG1n4B36T2oWkBK X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index 0cd580920a92..151cc60de9cd 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -4332,6 +4333,7 @@ rpmhpd_opp_turbo_l1: opp11 { =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; + qcom,bcm-voter-idx =3D ; }; }; =20 --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98936EB64DC for ; Tue, 11 Jul 2023 12:32:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232477AbjGKMc1 (ORCPT ); Tue, 11 Jul 2023 08:32:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232193AbjGKMcV (ORCPT ); Tue, 11 Jul 2023 08:32:21 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78767100 for ; Tue, 11 Jul 2023 05:31:53 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-3fbf1b82d9cso58863955e9.2 for ; Tue, 11 Jul 2023 05:31:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689078660; x=1691670660; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=F+HpM+HCeMpSefmXK16C9YcJaoau/C3nDGJIkf8i7cM=; b=ul0ok/tUjWblWmfDJyReJiMIRQ1ASPlslx/+OFGEndbIsdI6qoghJHW3uq3VjT7ivG JSRc4Jp+rHawPfoElLxK9MFg2cHlU2P9JL1c/JUrwUWiO5QQmQOlJPYX01WcoH0qg/ag tjUNTZNm2MQUCyCMM6rMp2bjC+Zd99ntL8WcYDM+UluhSKF5v/2fmaYuopaHlKyD9F6a t9DTEd+hzlTLAemviU5FVteR1BldVq6+zdQQojlVQonNulCWHmqH8bQqvuyFJu/VClDm 9Cye8wM7NVIrQhPxI8Jh+tegg2IcYSI1zMZ45nzLynPgafLNKCR1h6T8PWjH/e6HaeNv qfvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689078660; x=1691670660; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F+HpM+HCeMpSefmXK16C9YcJaoau/C3nDGJIkf8i7cM=; b=V9NulMMHoNk8ngANogbiNugYNrbJtD+4qiiAfX2z05P+GRRRAn3Cu6F5doVytfyF0O scFdFoI/VhrzGvlYpZV96JcSucNUYvk7Lla50csUKmY4Xe2YY+EAXJUMOpcvaSlyd2Js Ldo/qAuXpUvLZDHAqQzZDSQ58RUYbd4PAVEzm0FOF5+BwVUZOKiIS5ziXAFPS2oEtjWn mJuy+mLM0KYJ6MmaNZr1kczAfuF9NkXA9+UObyjN9fdHf4FLqjqt4rtGmBgu6eWr37rd r90ESyyLLchuIxsqE0OZPFJOGqIgHRsCkqm2vTBxBi5M8Ft4js1eDhPyZsVJf55CmA/w TxKw== X-Gm-Message-State: ABy/qLZMQOPA0VTn5MS1+SSv2ZjMaz2GHLy3EgvdSq8q+jpeTXAA5GDn 4+Mmmy71qRmMl71GL5wOlymzrJ0j0c7UyT0c3S5p2g== X-Google-Smtp-Source: APBJJlEQupFlCuRT7R8SseW9Y2wdzGnv9aFcooCUZ4hnjXBLeIT4wGij8HdFQ5+TYBuRWwliDkKCtg== X-Received: by 2002:a05:651c:211:b0:2b6:da64:321 with SMTP id y17-20020a05651c021100b002b6da640321mr12309325ljn.45.1689077964399; Tue, 11 Jul 2023 05:19:24 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:24 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:43 +0200 Subject: [PATCH 44/53] arm64: dts: qcom: sm8250: add qcom,bcm-voter-idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-44-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=999; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ebMrQjKmDTgpWjkINs/Atf2PQmSY9dkU3TIUUbwBPoQ=; b=2OP9+lUs6pA/83Z+vE3WXtNyqzqPquNrM8XqK7DknAXmP1+1Lj4UX4sVKsct2f4C6r3LDSIVi Etb83M3eBHhC59EcuJBb6ILh6z46QOGZc8myu/aS85weLkvbSCKm7x7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index e03007e23e91..29994aae897c 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -5674,6 +5675,7 @@ rpmhpd_opp_turbo_l1: opp10 { =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; + qcom,bcm-voter-idx =3D ; }; }; =20 --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0300DC0015E for ; Tue, 11 Jul 2023 12:33:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232445AbjGKMdS (ORCPT ); Tue, 11 Jul 2023 08:33:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231515AbjGKMdP (ORCPT ); Tue, 11 Jul 2023 08:33:15 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C81BA19A3 for ; Tue, 11 Jul 2023 05:32:36 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id 38308e7fff4ca-2b6b98ac328so86207141fa.0 for ; Tue, 11 Jul 2023 05:32:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689078664; x=1691670664; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=tO2vJbTBxTqUwo+iDtN9cED0N0PugFhOskIkVSgcZoE=; b=gDL3B6RQTMtmvP9JiFU1ZOrVv5yz/6ZOKwiBPaHsEOeuk2aD9HHNrhErb4gOOyMkzt cAuTuCh8T8gx7EiZS5xc64AZtcQmZmRo1G78c3G4lplKqvGK7TnxnykrIyv67/aYG+sb A7xXJQ8OFv9OO42SpQmoGjfTYz/NIIH6h7pDgueMvi6ADoBnSGppi4km2tycDIwRlDu1 8ZRYVRrnkw4+RKr8fg1GoZpT9Sw6Oe0XjRemXyV/MXK2vx6m5mb/OlK7kYLRkQZX2Mq5 Ix837kRFiCZPLA+u7lVb5KTqO0f0lzjTxY2Xs6n5eORwoRg0rmQDFuUf1QKz8jmZ4zan 1GSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689078664; x=1691670664; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tO2vJbTBxTqUwo+iDtN9cED0N0PugFhOskIkVSgcZoE=; b=igPQ6it/+dMqhe4CZ8oaNxTWMusleG9KQhMAyw6XvzjXXM2Y5pL3GUE23YrvahutxF +xE3hCjLWo6zTIUBi0/2mg/K6MKz8RQbvZCyMvRGIQFy0i91rcOZwEILXTZyMkUsFQpQ f8R2FBE8TuRePZr60gFtfXsB64eCtrrSYidolSyfnkdIhpb+lNFOlq+CcP5rRyfhKPkE Wnwnr4vJ1RnAHl8/PQC1GV/KS2T+G15O+YaAVza8SBMuyiXJTbKn6zlHVBQjxBuoDS3S a5bJK6jbVoWPjLE6UfJ070dG06aUKRTZRmej0ECJClbzzTI+ZgeHaECWUQxPvH55gW/e y/cQ== X-Gm-Message-State: ABy/qLabdcTIdZQUlmBam2ItWQ13iOM2/YTcnfpeczbqbmcxpeDUdJUM PDFCXHDI0VUBehYqtCadccVSPSlxbmnKYHbuh4IWsg== X-Google-Smtp-Source: APBJJlHNsNXP3jQQq1fy4YfORvSV68I8r5L1JF7OUxsZTSrTBKxKrW5XrMOsxibOaatxVd9HmtLFGQ== X-Received: by 2002:a2e:8784:0:b0:2b4:7f2e:a42d with SMTP id n4-20020a2e8784000000b002b47f2ea42dmr13840703lji.41.1689077965633; Tue, 11 Jul 2023 05:19:25 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:25 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:44 +0200 Subject: [PATCH 45/53] arm64: dts: qcom: sm8350: add qcom,bcm-voter-idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-45-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=921; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=zd8n6/BI+I7iSUydn8vszsfz3OyuMkqkyuxPFIRsJhE=; b=E57CxKs72PQD3kiuEmwIYLAntDVsPXBSfYzwul/8gYNvLIixxKL1h9182RVK5JNqZz+6KgOal yDZg5Nh7opvDSGBwll1qr94NW+/GRz5K7PzqECKnGB2muUSSiDiiq8n X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index 557a3d8e889b..fc8779a2fa96 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2020, Linaro Limited */ =20 +#include #include #include #include @@ -3397,6 +3398,7 @@ rpmhpd_opp_turbo_l1: opp10 { =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; + qcom,bcm-voter-idx =3D ; }; }; =20 --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10C0FEB64DC for ; Tue, 11 Jul 2023 12:22:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232137AbjGKMWW (ORCPT ); Tue, 11 Jul 2023 08:22:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232331AbjGKMVm (ORCPT ); Tue, 11 Jul 2023 08:21:42 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E41F01FC7 for ; Tue, 11 Jul 2023 05:20:21 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id 38308e7fff4ca-2b701e1c80fso85721301fa.2 for ; Tue, 11 Jul 2023 05:20:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689077967; x=1691669967; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=B4NULi+Pg3BzaFa9S+uijdnxcMxII5T4dtt9x/IhMZ8=; b=W51lFjiu6a9R1/lJNF1ZBGOFoMD7fqaxsfek7DTQrhsBd504k/wpfWeVhedCDuV2aI qIxxz5nCWhOd8mTqmZrpv/Yd7mbKAqG+f8kVW+3TkWle7RF+57hvdoVVE5tId+4wstBT KKnQEOgkzR61RmsOJuGAkWRBj1zdJqK9sISHGMpRm0IeQNADDnNxEVdl9Z6XNvfyXGP5 u9jzlOWga5t1c+XMXnT8J2s0ZAR/yMWWmyWIw12hqDou+Prc4Z/7UIW8osFTMJkpP0YI +749AH9e7aGwn2DRqPmbsJ9c4x9ofeqpzMfyhiO7eAxgMJPRUFttJS6QiSXl6sgtAb7H WdxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689077967; x=1691669967; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B4NULi+Pg3BzaFa9S+uijdnxcMxII5T4dtt9x/IhMZ8=; b=DdPjKTNuyZLRJBVJ5aiS8LXOp5wGCvA7PK1R9skpYjThCJI9ORXYqcAu2FqTL/jC6s aLmoLeAtVu7TO8gGVJs1ifeS8H45KOJadrGOI7tkwun+shY5swSkokD3P0868+Mu/i7g WzZ8IAqYiNsbc3OiAJkshj2AhjRf8J98QsDn16YU3VX8yfWx/rwDQhnotaYIO741aV+A E8AeodAnsVLPMmo0+x4ZrUcroOknhhkeyGNYy0lU63Ns0Mf+ql7Ruv+Eag4ocxD+XvgE ryNt12Z3g+WKuCb80NrCjzA92EhHM0h302EqlF2qygiVMbmnreLcbbm8qa+ejsOThANT vD/Q== X-Gm-Message-State: ABy/qLYzdKLyHrcKzyPTpQRGH6KHbcINg3rBf7f4C2tiQGPqStgI6The 8N/gNi5maGKM6ycdFJLgUm+ZtQ== X-Google-Smtp-Source: APBJJlG9xsUvTuE03igdC3Ho1c17TBaguMFId7SIKc7FOSZ2/1jZ/jWeJIIt+HonBcxtInnXGwgTqQ== X-Received: by 2002:a2e:7215:0:b0:2b6:efc7:2aee with SMTP id n21-20020a2e7215000000b002b6efc72aeemr12050313ljc.51.1689077967029; Tue, 11 Jul 2023 05:19:27 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:26 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:45 +0200 Subject: [PATCH 46/53] arm64: dts: qcom: sm8450: add qcom,bcm-voter-idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-46-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1005; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=SQpHj4TfmA+4UsCzDDjRNhiu3Ox+vTnH5LdKeWnrUM4=; b=5TQbA1R0ncEPLIqSN9iQ3lNCQ1W1zper+KD3P7WyAqNmnUuh156FuhAQ4i0R2vj4WhJnt0hdW 1FI94sDsjs4CxRHVepToXuIcyfT1PtDipM1ijKn6MOvhS5so+AWerUl X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 1668d97ce459..9c9645809af7 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -4008,6 +4009,7 @@ apps_rsc: rsc@17a00000 { =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; + qcom,bcm-voter-idx =3D ; }; =20 rpmhcc: clock-controller { --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9874DEB64DC for ; Tue, 11 Jul 2023 12:27:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231822AbjGKM1a (ORCPT ); Tue, 11 Jul 2023 08:27:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230478AbjGKM11 (ORCPT ); Tue, 11 Jul 2023 08:27:27 -0400 Received: from mail-lj1-f181.google.com (mail-lj1-f181.google.com [209.85.208.181]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD8E3A8 for ; Tue, 11 Jul 2023 05:27:00 -0700 (PDT) Received: by mail-lj1-f181.google.com with SMTP id 38308e7fff4ca-2b703caf344so85773971fa.1 for ; Tue, 11 Jul 2023 05:27:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689077968; x=1691669968; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=IQLBnYw5pfVzQylFNgskr7H7oEW4uSiPIu84jcjkQCk=; b=VuL7tBUVpKwm0E8VYa3YxI4GLD3j9N+kI7pdvvPJj/+jxXvrfTFuxOy12F2CaBz/HF sN0z5yMN9SQ4RLjBjiJSK+RP2jDbcXKyWpDyVprDeiCicPUtkP28bTHnoH/6GIaElnvk l1MazyYCLLnZXkMfyxUQOCYkQMmByamThDVsRvQ342OHg7hWo8PsAPc4cVWFhv6RgRjS Vk62VuCZ7XvPZYsAsX8G0sBw387elQNYidznrlY96WT16f8qQ/PK4mEqopOqM3OCb9tO BLT/9Bf6DG2IJzr9obCW5Bqqnm2swgLDHQHUcHWvdtXP8jq3vM1e9/fbTkwVRdk6iLty dhCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689077968; x=1691669968; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IQLBnYw5pfVzQylFNgskr7H7oEW4uSiPIu84jcjkQCk=; b=MonHmauGSuQjjL6+sfNV0jZZPZAcvvtGPUQjhGp9EWMcFjSZX7F0sjHIeO1h5YJCjz iAhYLpQfOc40C8Q7CmQslstx3h8sUhK36AO/6DCXck6h151utoJdVL4hvAoOzVT63pvf GbaFsr236zPCaFKrlbCgbEIpJOT+fa6YJblsO5nWaF+drB3QR9pOil+AxWkt+CuXru+8 c1rjOPgDFemje0JJCRkIEEnlBfcR1Z5obR0s8WGqvKPgFTzVFbJJNz2hllwm2sBa586E CSBmWWWg9PkGH7SCtnpQ+XZFe2H9bRYQTUj7IS/SF523FGX7bzVL2cRD40EeHKykmEAL mGZg== X-Gm-Message-State: ABy/qLYMNu3PaQiLHWXUouw0TEGAvKLLKsXshOR0nHkOQtwno1u5eNQL 66+3Hs2hep4AQG+yJ9LLNwCtAg== X-Google-Smtp-Source: APBJJlH5jgTV6clHkuAbdLyaxwSZbX0NQWlWbozqxx3ivhQVSBF6LhXWQmS5O3CgizbKk35ErOwtyA== X-Received: by 2002:a2e:6a04:0:b0:2b7:14d4:ce6d with SMTP id f4-20020a2e6a04000000b002b714d4ce6dmr7721930ljc.48.1689077968298; Tue, 11 Jul 2023 05:19:28 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:27 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:46 +0200 Subject: [PATCH 47/53] arm64: dts: qcom: sm8550: add qcom,bcm-voter-idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-47-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1014; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=2n73VwmB8gd6z5jxJWL0kWv1/JV05PWG3zpj6M//Tvs=; b=6cAucdktEPv499aSOqbmljlM2KKvs2eSJ07hrXrAq/GVNAj6ilgikTUSIcX93dYozWDDDBb7g UwYMsvaySf6AKgM7Tyt09TTWQN7rdv3hVkop9AW3R7L1dPXgX0KPAkN X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 6e8aba256931..d54b0ac6d0a3 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -3714,6 +3715,7 @@ apps_rsc: rsc@17a00000 { =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; + qcom,bcm-voter-idx =3D ; }; =20 rpmhcc: clock-controller { --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D04CEB64DD for ; Tue, 11 Jul 2023 12:32:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231924AbjGKMcT (ORCPT ); Tue, 11 Jul 2023 08:32:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230215AbjGKMcQ (ORCPT ); Tue, 11 Jul 2023 08:32:16 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE6F8170D for ; Tue, 11 Jul 2023 05:31:48 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-3128fcd58f3so6153741f8f.1 for ; Tue, 11 Jul 2023 05:31:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689078656; x=1691670656; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=NaXHvKCxI7KxVS1KmSwJhdeP1kNsqjjvViQ53Us8p1Y=; b=f5mqGPJoyH1ZwY5D3NZJMvQUnZTPoDC5M49QDQrD9ozzyq2e/W15C9T1y4QyWIxbvw +ap5J9kSErGcoDIfLSSCR7TU/wWp0oxXANKV14LkF0v8fViRbxBQye3k8GB2F3ijed3I ytT9U4jRW+cF+AYgcnPaIt06BciicdR8j3kXnFz+UmVQqH2hjuSqsH+dkH5ssmyu8uwR dIlk99XWiRff/8TtJ+6XOVRtCz9onPBkRyBtS2ZVMEFePHo1q2bVqJMAm3t0akGAqEEK llNKjvVGpQ+hXw9S5WI9IN5Wf8TGALceOrJ30Xyx998tFy+xc+F5fltTw9PmMHy3lNo9 vyWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689078656; x=1691670656; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NaXHvKCxI7KxVS1KmSwJhdeP1kNsqjjvViQ53Us8p1Y=; b=fo9jLMyVQ46OaC52lEjha8lVsstwA8vxHyZlGlP/R8ag86qM+ixRvDhO5mOHIpY90I ROrw7W9u9xKP2CwwYVNSFmZ3P3q1VDAB1W8GFHsaIwHSMxHdxRaoMvZkx0b22LqiCaHg e/3/icUQ5SM7jqkAFlV2KBGeN7DRoADpKCtP7OjZAPPlNIBTi5YGy+vzDZAk6Rz+eAyP 6YFynImxNrS3guMjCp3QYuOSIV4S+/ITYZq99MDXAp+qkXPzmiOrOYtr/D1gXLP5hsI3 YOr/yVbUBGegoEUaWVJaNVEa7q1nj9GV1rG9LL3Z382Bgi0TywHfXu8VDRLnt8cnh7Vn 890Q== X-Gm-Message-State: ABy/qLbjacEM4fAxVpuCI24x57O83xoBKWAcU/x5Wb0c/CA/0MaL7Hyy oLoZbRWEOnG8cXQJucIqyMvKOJZ9+cJ4RpV4gU/GKg== X-Google-Smtp-Source: APBJJlF/Un+4BrkKuR/dQAlc7XT7zlceCutSzyx8Jl8oQZGTFTrVsq9POqO6fXg5OIxvXghJ/47yww== X-Received: by 2002:a2e:95ce:0:b0:2b6:ad79:a4fb with SMTP id y14-20020a2e95ce000000b002b6ad79a4fbmr2655685ljh.1.1689077969500; Tue, 11 Jul 2023 05:19:29 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:29 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:47 +0200 Subject: [PATCH 48/53] arm64: dts: qcom: sdx55: add qcom,bcm-voter-idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-48-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=655; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=GVqmsSMX0fxTkDbnjbH1iljfmht9W+hSLX9r25Tevic=; b=N2eLJQMNYylLqqzdwgHQFGEzhpfNvaREkV3iEByCL6wCEZDNiZPaLzavwd1ss+OBo43FniXsU RRR1dXkYRonD06UpBTkLnP8XTQEYWZWmKVNEQ4fmb2GknWU1iYc98KI X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qco= m/qcom-sdx55.dtsi index 55ce87b75253..35519e018ab2 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -866,6 +866,7 @@ rpmhpd_opp_turbo_l1: opp10 { =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; + qcom,bcm-voter-idx =3D ; }; }; }; --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C00BEEB64DD for ; Tue, 11 Jul 2023 12:26:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231775AbjGKM0O (ORCPT ); Tue, 11 Jul 2023 08:26:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230478AbjGKM0L (ORCPT ); Tue, 11 Jul 2023 08:26:11 -0400 Received: from mail-lj1-f178.google.com (mail-lj1-f178.google.com [209.85.208.178]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5BA9219B4 for ; Tue, 11 Jul 2023 05:25:45 -0700 (PDT) Received: by mail-lj1-f178.google.com with SMTP id 38308e7fff4ca-2b6ef64342aso89541601fa.3 for ; Tue, 11 Jul 2023 05:25:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689077971; x=1691669971; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=aAnqUE/WHV036dx6NEY6D3p5kApQ1y3z3qzTH1W8xaQ=; b=uzLoKddos5zRyt4BzSBDOjkRGPZL0rCy09oarN2v4QLyGWFmZ/dKXZyT0s/Aq+awVZ LS+GzAbZXZBKY0Rk4KneajlEirkCJxcbeXq1tA+b3xE913fKd6XwC9YZQxbFU4Ix+5PT hhwN5769ed9EXuTlJa3YoChQYIxuswSs20NUQX3PFzJROVwe1b8NxPgfdIFxj4yAeMCU WIOgTbPUXgn69aI+UsRcuso8YSlfECB6PhO/SdEEjh/kcPECcc/cF5zYmK+/H+/l28PR zYvrLJU6EgcUFjgrw2/cAnb5QTnHhhLp/lzvA9uW7H68mZH93YCDQbWIu3Fl6SHGqDeC 6k/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689077971; x=1691669971; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aAnqUE/WHV036dx6NEY6D3p5kApQ1y3z3qzTH1W8xaQ=; b=aR4aOA6qtYDDh62alh0vXJ99jo6Dy2lxT10zeOUgNK2PFy8f421McNNce5gPKusBew vHygoA64d5FGsRuCqYtugVhC+CxV8ZY4GKp9rM2VvejpBppQlM0ndn/pQHxmYJKQoRVK j187PM2dkOJ+dpX8UfujNTqW+PRtp2Fyww4wbtI3w7lM7QLFwDjFxPbXGVx4ayfNAMk5 dWfi9fvTQ9I4ctkFaTLLjA+jxzfDJMzdQXGLn2Bzl+bwqcd227ylpzwnf4MOPZve2dpt SJZArxSnDwin81IMvpVOObmz4vVv59WdXBBH4rhTsGLmgYjZJxDwG2edEAU4fqdnUet8 08jg== X-Gm-Message-State: ABy/qLaG1bgyZX5W8rvxQjTrcRkVOn5FnwVQZI5gbeliiN0Rw86xhe3B Oa/acaZ2PWmi7O9NNPaNjt8mZg== X-Google-Smtp-Source: APBJJlHkKTM9ihSn8V3T9xMNbl03fyANS2QLVE+ICIFcS1RM0++00HN+HZZQ1KnCKxZq4VFyL6y+Mw== X-Received: by 2002:a2e:9455:0:b0:2b7:29b:d5a5 with SMTP id o21-20020a2e9455000000b002b7029bd5a5mr12393829ljh.34.1689077970895; Tue, 11 Jul 2023 05:19:30 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:30 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:48 +0200 Subject: [PATCH 49/53] arm64: dts: qcom: sdx65: add qcom,bcm-voter-idx MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-49-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=652; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=QPuW3Rel3JulR94tJfYoeAL03RliO6PUnmcXiEkxKJ0=; b=opllT+GF9a/Bed6/37yPX0plczgSYkuJUB3jZRB8+yo4DeCEiTP93/R6hdGMr7/rzPqNVd68W wutnZ86z2tyBySDI8bN7TTvFabHscB2+atTO98lTHMANJcn9Wutslt+ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org To improve the representation and ease handling, identify each BCM voter Signed-off-by: Konrad Dybcio --- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qco= m/qcom-sdx65.dtsi index 1a3583029a64..7efdcb2a7a0e 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -795,6 +795,7 @@ rpmhpd_opp_turbo_l1: opp10 { =20 apps_bcm_voter: bcm-voter { compatible =3D "qcom,bcm-voter"; + qcom,bcm-voter-idx =3D ; }; =20 }; --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD44BEB64DC for ; Tue, 11 Jul 2023 12:22:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232500AbjGKMW0 (ORCPT ); Tue, 11 Jul 2023 08:22:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232158AbjGKMVr (ORCPT ); Tue, 11 Jul 2023 08:21:47 -0400 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B64872D41 for ; Tue, 11 Jul 2023 05:20:27 -0700 (PDT) Received: by mail-lj1-x22b.google.com with SMTP id 38308e7fff4ca-2b70404a5a0so88494261fa.2 for ; Tue, 11 Jul 2023 05:20:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689077972; x=1691669972; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=/asgZ03NiEjGsv4yFwqtkX/wMZgRigqk79OQqEY/FpA=; b=hCpfqLd/vx3JOsEpmrJXLGzzXybtv+LRYxi+h82MiJ/qjN8JRURSOuDN3mSd8QSGXv mGm85+F+w5pTBox1tnm6Qyu3TXgZtgLGS8xw8Rrzzd9K0U4Op132J+eptkFEcTFqX+dJ ub3IvrGz8bPuqYRFspKOHujpDwTh7HciqFoRmyLckyezZqb5sVQ4jwQ8G8tdzwkbdtXA mH2fGxNfFdD+/jw4LGILvnRWI8tmVkv49YRvrDIm0n4vpygk5PZJSDBUQS31KNLOc90O 4zs1LFTcjh3lGauXF1nOQvHPXuycCbKYgwam2pL1L2HHxcdm1sjgQx/ESfAdk25xRWjQ T9fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689077972; x=1691669972; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/asgZ03NiEjGsv4yFwqtkX/wMZgRigqk79OQqEY/FpA=; b=ffGO4HqdpQiVhcfHhdcL9Wxt2lZ+aryIyKv2YZjjWmsdR09otwnGm3B1GxLo1AcwjX 7Qom8bAQRPURsdsUveohjtSriJezKBnts0lEorPE/uvQB1/lwVt8sHLxAJWq5vNepBPy VB6ZrqtzR3D9I27Hj7nCjtM3Wa+BLro2OmhLNS97Qp+wgEKM1ECWeNn3KdLH5wUFQs0/ qn6+q5w+zfGfvg5geqWWcNf0N4DAiCYbEzZSAxXWq2o8dP9JVz34pNYRS/ttz0NWEXta vUNGbtIPupf3U2dSNpTmIk6mxUynT37wiEYGpEQdZfz59aDca4MjD0/8xrIEG87zqr+N 3p1Q== X-Gm-Message-State: ABy/qLZ5glL/nlOUQvWTsbNNP19oK1yhYigo/AsZ6+InSWvVJ/GreTEf 5j1RSPUS01t+puQqJla8G0h9fw== X-Google-Smtp-Source: APBJJlGydSY5p6okL4PaU6GFDJfbxqkpBMjvgZKcHal05MTStl5cNcj28rvD3wzeEz2DDLdvr8RZag== X-Received: by 2002:a05:651c:102f:b0:2b5:85a9:7e9b with SMTP id w15-20020a05651c102f00b002b585a97e9bmr14905048ljm.33.1689077972306; Tue, 11 Jul 2023 05:19:32 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:31 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:49 +0200 Subject: [PATCH 50/53] interconnect: qcom: sm8350: Point display paths to the display RSC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-50-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=2325; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=4cN3u17a4Tjp9KwmLVHyYCuynLOUrKPYJniM89DUm8c=; b=TCiw8Gn5E+kROybJ7eM9HDAHOFyDwfav4mFNcXKQuvK0+BeKxlWbuCdcJLWAdcb6awXlEbvSA 6TqOK3Ni0LHAsoY4ARc1sb+WTzVrou+euI5hOGVp7EXrDzsuyVwnFNu X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The _DISP paths are expected to go through the DISP RSC. Point them to the correct place. Fixes: d26a56674497 ("interconnect: qcom: Add SM8350 interconnect provider = driver") Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8350.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom= /sm8350.c index c48f96ff8575..0466ba5d939a 100644 --- a/drivers/interconnect/qcom/sm8350.c +++ b/drivers/interconnect/qcom/sm8350.c @@ -1609,7 +1609,7 @@ static struct qcom_icc_bcm bcm_sn14 =3D { static struct qcom_icc_bcm bcm_acv_disp =3D { .name =3D "ACV", .keepalive =3D false, - .voter_idx =3D 0, + .voter_idx =3D 1, .num_nodes =3D 1, .nodes =3D { &ebi_disp }, }; @@ -1617,7 +1617,7 @@ static struct qcom_icc_bcm bcm_acv_disp =3D { static struct qcom_icc_bcm bcm_mc0_disp =3D { .name =3D "MC0", .keepalive =3D false, - .voter_idx =3D 0, + .voter_idx =3D 1, .num_nodes =3D 1, .nodes =3D { &ebi_disp }, }; @@ -1625,7 +1625,7 @@ static struct qcom_icc_bcm bcm_mc0_disp =3D { static struct qcom_icc_bcm bcm_mm0_disp =3D { .name =3D "MM0", .keepalive =3D false, - .voter_idx =3D 0, + .voter_idx =3D 1, .num_nodes =3D 1, .nodes =3D { &qns_mem_noc_hf_disp }, }; @@ -1633,7 +1633,7 @@ static struct qcom_icc_bcm bcm_mm0_disp =3D { static struct qcom_icc_bcm bcm_mm1_disp =3D { .name =3D "MM1", .keepalive =3D false, - .voter_idx =3D 0, + .voter_idx =3D 1, .num_nodes =3D 2, .nodes =3D { &qxm_mdp0_disp, &qxm_mdp1_disp }, }; @@ -1641,7 +1641,7 @@ static struct qcom_icc_bcm bcm_mm1_disp =3D { static struct qcom_icc_bcm bcm_mm4_disp =3D { .name =3D "MM4", .keepalive =3D false, - .voter_idx =3D 0, + .voter_idx =3D 1, .num_nodes =3D 1, .nodes =3D { &qns_mem_noc_sf_disp }, }; @@ -1649,7 +1649,7 @@ static struct qcom_icc_bcm bcm_mm4_disp =3D { static struct qcom_icc_bcm bcm_mm5_disp =3D { .name =3D "MM5", .keepalive =3D false, - .voter_idx =3D 0, + .voter_idx =3D 1, .num_nodes =3D 1, .nodes =3D { &qxm_rot_disp }, }; @@ -1657,7 +1657,7 @@ static struct qcom_icc_bcm bcm_mm5_disp =3D { static struct qcom_icc_bcm bcm_sh0_disp =3D { .name =3D "SH0", .keepalive =3D false, - .voter_idx =3D 0, + .voter_idx =3D 1, .num_nodes =3D 1, .nodes =3D { &qns_llcc_disp }, }; --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F26EEB64DD for ; Tue, 11 Jul 2023 12:36:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232111AbjGKMgG (ORCPT ); Tue, 11 Jul 2023 08:36:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231244AbjGKMgE (ORCPT ); Tue, 11 Jul 2023 08:36:04 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7ED641721 for ; Tue, 11 Jul 2023 05:35:38 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-3fbdfda88f4so57795285e9.1 for ; Tue, 11 Jul 2023 05:35:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689078886; x=1691670886; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=9qEI9ih7CsEfqqcZVsPdCla2s3zGk1zpIvdrNZp7GUo=; b=Q446X4P+7xWTaxlN5MbzUN6wW5rmmDPu9wNZS/3DVYHxaPbSkAESGhsNZplga/OIMq U773HB36h26/H9lPo876fzdqKNICmWgatPzSm3FF/bxjMdkm5NMAfjn/pRnOhdwuPTHx tEOSTiSq7mvpDdI+wPL3vAIgo2KWj4aehk4whaMVrbp5qKnUJ+qVkCUPU/Kw+LNV/fm9 9xiO5Bv4/usDUO0yCNlt26rtdH5z7k1yGSJmcL3HrIQTfY20X/u2D8jsPoA1BPlB+TnV mJs0cozjAGcb8vNXL2vXOnVsdi5E9bhwZ+Y8ookpD6AbQWOI/BXYOFmkCK1dbbMJCVjU iWsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689078886; x=1691670886; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9qEI9ih7CsEfqqcZVsPdCla2s3zGk1zpIvdrNZp7GUo=; b=T/YijyvHr3ao2H3sFpv9tzR4WkzbOu+YYA8toPzVfVbiMyJhTts43KTADxQs74wL/x tZ+K5QyQpJIEalAdSdOazMSZIIBwrMNJzlsATzvVpn0sxo6sNqDrLjHVhwPyrvBh+LLX P2He+3N60c0GcrP5G+guS9ZP9T3Lqj3dXuWWZtbpFBpG58/Xi9wCK1S1HzWqTgFuRK8q ysFSkC7KK85kPZ+EHQFVtgy/tN0c2VataQTFDeXXf034HTl4SPVIZB6lsJR24fTBU20j ME9idswKCHEtreB/RyUk66ne/0kFtvHtkSOP1A3iF1drLJV+B2D5KNvjcKjF98snzsEB KO6Q== X-Gm-Message-State: ABy/qLaUVxOElJb91gzu5SngoYZMhUwd0JAS8QiXq35ftEN+Uho43z3v YHtD8XrnyDGi7nv+8hwtFa9CYi5K5AKW8GRXcJBNAA== X-Google-Smtp-Source: APBJJlERwY5Ah/kFYLm9KWUQ1ixR3SDh15gYAU7TZOHqrhoESjYXLBqCwASCR5Xt40UjYu3EHMbB/A== X-Received: by 2002:a2e:9f4d:0:b0:2b6:e151:791e with SMTP id v13-20020a2e9f4d000000b002b6e151791emr13433971ljk.43.1689077973594; Tue, 11 Jul 2023 05:19:33 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:33 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:50 +0200 Subject: [PATCH 51/53] interconnect: qcom: sm8450: Point display paths to the display RSC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-51-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=2103; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=GAWOUV4QJe60q6M3sv3YLGxilMGxFFgLlCxXc4BU++I=; b=n6mHwI5Knlo8QwAZ9UuQJZ5TSMk5uicF8dPrneNhYlmJUFzK9gguKI0KQoyfgn83kx8zxL6qu BLXqqqUvr/lAd5PsnBNC3JILtU6yS5lpYZClOMClAFtFiipSLnQ2MVw X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The _DISP paths are expected to go through the DISP RSC. Point them to the correct place. Fixes: fafc114a468e ("interconnect: qcom: Add SM8450 interconnect provider = driver") Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8450.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom= /sm8450.c index 989ae24f2be9..6f42b1d693b4 100644 --- a/drivers/interconnect/qcom/sm8450.c +++ b/drivers/interconnect/qcom/sm8450.c @@ -1517,21 +1517,21 @@ static struct qcom_icc_bcm bcm_sn7 =3D { static struct qcom_icc_bcm bcm_acv_disp =3D { .name =3D "ACV", .enable_mask =3D 0x1, - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_DISP, .num_nodes =3D 1, .nodes =3D { &ebi_disp }, }; =20 static struct qcom_icc_bcm bcm_mc0_disp =3D { .name =3D "MC0", - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_DISP, .num_nodes =3D 1, .nodes =3D { &ebi_disp }, }; =20 static struct qcom_icc_bcm bcm_mm0_disp =3D { .name =3D "MM0", - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_DISP, .num_nodes =3D 1, .nodes =3D { &qns_mem_noc_hf_disp }, }; @@ -1539,7 +1539,7 @@ static struct qcom_icc_bcm bcm_mm0_disp =3D { static struct qcom_icc_bcm bcm_mm1_disp =3D { .name =3D "MM1", .enable_mask =3D 0x1, - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_DISP, .num_nodes =3D 3, .nodes =3D { &qnm_mdp_disp, &qnm_rot_disp, &qns_mem_noc_sf_disp }, @@ -1547,7 +1547,7 @@ static struct qcom_icc_bcm bcm_mm1_disp =3D { =20 static struct qcom_icc_bcm bcm_sh0_disp =3D { .name =3D "SH0", - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_DISP, .num_nodes =3D 1, .nodes =3D { &qns_llcc_disp }, }; @@ -1555,7 +1555,7 @@ static struct qcom_icc_bcm bcm_sh0_disp =3D { static struct qcom_icc_bcm bcm_sh1_disp =3D { .name =3D "SH1", .enable_mask =3D 0x1, - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_DISP, .num_nodes =3D 1, .nodes =3D { &qnm_pcie_disp }, }; --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD789EB64DD for ; Tue, 11 Jul 2023 12:30:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232397AbjGKMa4 (ORCPT ); Tue, 11 Jul 2023 08:30:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229637AbjGKMav (ORCPT ); Tue, 11 Jul 2023 08:30:51 -0400 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D5D01734 for ; Tue, 11 Jul 2023 05:30:14 -0700 (PDT) Received: by mail-ed1-x52a.google.com with SMTP id 4fb4d7f45d1cf-51e526e0fe4so4224734a12.3 for ; Tue, 11 Jul 2023 05:30:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689078553; x=1691670553; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=K8XB0b36gPmdiQ9so1TqDakH13y4NHB3DOms10+ba6o=; b=Q23OvF0AgDrYzoTIr6QUmbbxXaoC1rc0ckxutCZxnPuRnZSd3FxFbG2Ja2izBoP4Gj KNUlySRQ832eju90cyH+Qo5Aup8vG+taYBLX/nEcT+mAuG+I1CrMPVKLDTICbvsNQioe Cmk9gu+plAwF4n8XEUDehR5DXVFke7KWgyuBp33lTL4vqM5O2HScUVQA9KrBBlG7PE04 tjvpDc7/D5nX2cVJ1DsZ5zCaM/KoHh2ysUbEjEd5BZEvBi/qKIMY/IRUSS+ygEoe3LHw zgei/fUGp2VxeXDUh6aESbU1Mpqyjg9uSWoCd8GRYbCdThECVsO+rdyowe72UFrltIQH RPkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689078553; x=1691670553; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K8XB0b36gPmdiQ9so1TqDakH13y4NHB3DOms10+ba6o=; b=UlyIQpOUliUVrxBO+Emp8DK5fTr08XQ3rA0NbJn9HMlrXNO/jyBaMGYBB9DL91E20F ADqqXaPcFbm6tlnaIGPhjOL5SSUHU4EBnxbt2FZXjHzBvPdLeQScFNMRnXD89UhMtNjM 26afMdzE89ltbSY4MDOwDiJ7UvtWsQS/8+cBNDKmTqfzcOwXOlJ9cp3mX+YSp5qtpIWh 0ANIgCl9+5uY+NgwglL285hwk3UJgfaFv6hRfzc3rFn4w95QzLs5fRG9oy3QIMTSoIMs fRMXQkRKeVt98Sff6HJ2bJbPXsuuEd7LiN4MXqVnu2wQwAchqL0jbX6ldYkK3iKJVy8j RKaw== X-Gm-Message-State: ABy/qLa85/jQi+Dk7qea+/SoZHpYROhIfs4hT/xznUvKHSncjCXprT1B ccxBuZMOb9G3ZVJaLK0ZFCNKEp/9xvNtQ3P2dzThnQ== X-Google-Smtp-Source: APBJJlE2RazEk7jWnWIxzhvB388i+Jz4v5pKbVm5lv2aHkI0z0joWOUIEUNAb0Q0D9yXNDXQA3SC2A== X-Received: by 2002:a2e:7802:0:b0:2b6:fcd0:2aa1 with SMTP id t2-20020a2e7802000000b002b6fcd02aa1mr14054251ljc.43.1689077974872; Tue, 11 Jul 2023 05:19:34 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:34 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:51 +0200 Subject: [PATCH 52/53] interconnect: qcom: sm8550: Point display paths to the display RSC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-52-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=1733; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=JL7o0mask7WGyT5OOgpXbZTfu4QypRbPSv6ivg1xHjk=; b=g5PEcaastA0+757hGRpamUu4K391F2PnVaPxUU5BCcKmXycbS8JudpIcZ1n14tPUfV/YxXGAr u3V8Yb4LTMMDYFOs18dH266Gk0UlXoW91XeF42ZqHdbF8MAGoK9VKp+ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The _DISP paths are expected to go through the DISP RSC. Point them to the correct place. Fixes: e6f0d6a30f73 ("interconnect: qcom: Add SM8550 interconnect provider = driver") Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8550.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom= /sm8550.c index 40740cf5e41d..41314b214cbe 100644 --- a/drivers/interconnect/qcom/sm8550.c +++ b/drivers/interconnect/qcom/sm8550.c @@ -1659,28 +1659,28 @@ static struct qcom_icc_bcm bcm_sn7 =3D { static struct qcom_icc_bcm bcm_acv_disp =3D { .name =3D "ACV", .enable_mask =3D 0x1, - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_DISP, .num_nodes =3D 1, .nodes =3D { &ebi_disp }, }; =20 static struct qcom_icc_bcm bcm_mc0_disp =3D { .name =3D "MC0", - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_DISP, .num_nodes =3D 1, .nodes =3D { &ebi_disp }, }; =20 static struct qcom_icc_bcm bcm_mm0_disp =3D { .name =3D "MM0", - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_DISP, .num_nodes =3D 1, .nodes =3D { &qns_mem_noc_hf_disp }, }; =20 static struct qcom_icc_bcm bcm_sh0_disp =3D { .name =3D "SH0", - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_DISP, .num_nodes =3D 1, .nodes =3D { &qns_llcc_disp }, }; @@ -1688,7 +1688,7 @@ static struct qcom_icc_bcm bcm_sh0_disp =3D { static struct qcom_icc_bcm bcm_sh1_disp =3D { .name =3D "SH1", .enable_mask =3D 0x1, - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_DISP, .num_nodes =3D 2, .nodes =3D { &qnm_mnoc_hf_disp, &qnm_pcie_disp }, }; --=20 2.41.0 From nobody Mon Feb 9 18:07:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7AFBC001DC for ; Tue, 11 Jul 2023 12:22:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232646AbjGKMWr (ORCPT ); Tue, 11 Jul 2023 08:22:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232148AbjGKMWX (ORCPT ); Tue, 11 Jul 2023 08:22:23 -0400 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F1C61716 for ; Tue, 11 Jul 2023 05:20:46 -0700 (PDT) Received: by mail-lj1-x22e.google.com with SMTP id 38308e7fff4ca-2b70404a5a0so88495501fa.2 for ; Tue, 11 Jul 2023 05:20:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689077976; x=1691669976; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hSHC4l0gplSJLLulVhlWKIZdx5+fKnKYFEmJEyGDU+A=; b=foJDSaBicnp7FQezuElZP030n0/FHiLPO9Fb9DgJh3gvHDsN4ZzbB8v0voLZ5iMeGs Qcd0tb880CQOtwLeCPMGv69H30FrFJuXxr03VgECOk5Z/AJkkWQ0zFF4qIh8CwOVZaqO Fc8xciynpGkbZbzdsWxDZukLIk49LO65y/9rYUjCG/gpRIeFUlK67IujuMqvTQK9kQJG PNrXavuemFDYZ+E8xqZ2cWe/hS2ImNg15AK/sAG4QyMJozRzbaYIklRs3g4mBnEx1Mdj ZwMdn8IcsY/aY4qjkUkh+DAbvApgYvXuGaOIF7k09F/BPEzzQiEiUc7o6FdMD7PFzxRq LEfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689077976; x=1691669976; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hSHC4l0gplSJLLulVhlWKIZdx5+fKnKYFEmJEyGDU+A=; b=PJ9JlRhgTmq+5LKfEt9GDHF7U8a8hzCX2h/YRgxKjTURb5WSSiJi1sk6meY5vWdXL8 u9fdxd91E0NfXUCNOhFhXXbVUY/zbi7a7iScSZqx/cHXTXXS+TVli5MjM7SSLgKeDkLr s/43bw4E/jXx/vK6/+K2s0pLd8CrACljrfJSkgRHv75TM+NEeHUy8BrRjfqE+hyDEkMO W7YZGex20GreYpeaB8tCzi1GsrIn38s4mBfBpgdopADsKI/s4DA/vrjF0sQ3CA42C7Je kxLl+wu7RlpskuW6zBbJEx3NGcnub/3TrANOm9sYCFXyK7NS4biK/Shoo9+w+7GmmpeQ lHkg== X-Gm-Message-State: ABy/qLaY4g06dfLj8LR78IZFz0bph5TY8U9dmCh/lj4gg+17ReDT5nIn JzbJ6pb/zh83mSwwPbBN7idD5A== X-Google-Smtp-Source: APBJJlEU9I11aEXrAvD0lMzre2JXwbJszN+iFqWDfzBtJ6UCVwR0/JRGXW5+TgQ8uUK8clcH2V8gUQ== X-Received: by 2002:a2e:990f:0:b0:2b7:1c0f:f215 with SMTP id v15-20020a2e990f000000b002b71c0ff215mr6566247lji.2.1689077976203; Tue, 11 Jul 2023 05:19:36 -0700 (PDT) Received: from [192.168.1.101] (abyl96.neoplus.adsl.tpnet.pl. [83.9.31.96]) by smtp.gmail.com with ESMTPSA id d18-20020a2e96d2000000b002b708450951sm435563ljj.88.2023.07.11.05.19.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 05:19:35 -0700 (PDT) From: Konrad Dybcio Date: Tue, 11 Jul 2023 14:18:52 +0200 Subject: [PATCH 53/53] interconnect: qcom: sm8550: Point camera paths to the camera RSC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230708-topic-rpmh_icc_rsc-v1-53-b223bd2ac8dd@linaro.org> References: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> In-Reply-To: <20230708-topic-rpmh_icc_rsc-v1-0-b223bd2ac8dd@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689077904; l=5762; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=W6na5tQubESsXoW9+LUn1M9R9sjGfLBb8AasT+sD/gg=; b=LJKdtd94KUc+CXD5JNWf2ab3MiRf13typSRJvQgEbZhLudJiAhYDUF0t9U94EeCcSdhQdDg6d QOliq5sd1MMASebL8OKCdJ1d1h0gofCmuRajrDkEZu5wA0dZ9sXu5ii X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The _CAM_n paths are expected to go through the respective channels of the CAM RSC. Point them to the correct places. Fixes: e6f0d6a30f73 ("interconnect: qcom: Add SM8550 interconnect provider = driver") Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/sm8550.c | 36 ++++++++++++++++++----------------= -- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom= /sm8550.c index 41314b214cbe..8970fd6505f5 100644 --- a/drivers/interconnect/qcom/sm8550.c +++ b/drivers/interconnect/qcom/sm8550.c @@ -1696,21 +1696,21 @@ static struct qcom_icc_bcm bcm_sh1_disp =3D { static struct qcom_icc_bcm bcm_acv_cam_ife_0 =3D { .name =3D "ACV", .enable_mask =3D 0x0, - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_CAM0, .num_nodes =3D 1, .nodes =3D { &ebi_cam_ife_0 }, }; =20 static struct qcom_icc_bcm bcm_mc0_cam_ife_0 =3D { .name =3D "MC0", - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_CAM0, .num_nodes =3D 1, .nodes =3D { &ebi_cam_ife_0 }, }; =20 static struct qcom_icc_bcm bcm_mm0_cam_ife_0 =3D { .name =3D "MM0", - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_CAM0, .num_nodes =3D 1, .nodes =3D { &qns_mem_noc_hf_cam_ife_0 }, }; @@ -1718,7 +1718,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_0 =3D { static struct qcom_icc_bcm bcm_mm1_cam_ife_0 =3D { .name =3D "MM1", .enable_mask =3D 0x1, - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_CAM0, .num_nodes =3D 4, .nodes =3D { &qnm_camnoc_hf_cam_ife_0, &qnm_camnoc_icp_cam_ife_0, &qnm_camnoc_sf_cam_ife_0, &qns_mem_noc_sf_cam_ife_0 }, @@ -1726,7 +1726,7 @@ static struct qcom_icc_bcm bcm_mm1_cam_ife_0 =3D { =20 static struct qcom_icc_bcm bcm_sh0_cam_ife_0 =3D { .name =3D "SH0", - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_CAM0, .num_nodes =3D 1, .nodes =3D { &qns_llcc_cam_ife_0 }, }; @@ -1734,7 +1734,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_0 =3D { static struct qcom_icc_bcm bcm_sh1_cam_ife_0 =3D { .name =3D "SH1", .enable_mask =3D 0x1, - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_CAM0, .num_nodes =3D 3, .nodes =3D { &qnm_mnoc_hf_cam_ife_0, &qnm_mnoc_sf_cam_ife_0, &qnm_pcie_cam_ife_0 }, @@ -1743,21 +1743,21 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_0 =3D { static struct qcom_icc_bcm bcm_acv_cam_ife_1 =3D { .name =3D "ACV", .enable_mask =3D 0x0, - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_CAM1, .num_nodes =3D 1, .nodes =3D { &ebi_cam_ife_1 }, }; =20 static struct qcom_icc_bcm bcm_mc0_cam_ife_1 =3D { .name =3D "MC0", - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_CAM1, .num_nodes =3D 1, .nodes =3D { &ebi_cam_ife_1 }, }; =20 static struct qcom_icc_bcm bcm_mm0_cam_ife_1 =3D { .name =3D "MM0", - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_CAM1, .num_nodes =3D 1, .nodes =3D { &qns_mem_noc_hf_cam_ife_1 }, }; @@ -1765,7 +1765,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_1 =3D { static struct qcom_icc_bcm bcm_mm1_cam_ife_1 =3D { .name =3D "MM1", .enable_mask =3D 0x1, - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_CAM1, .num_nodes =3D 4, .nodes =3D { &qnm_camnoc_hf_cam_ife_1, &qnm_camnoc_icp_cam_ife_1, &qnm_camnoc_sf_cam_ife_1, &qns_mem_noc_sf_cam_ife_1 }, @@ -1773,7 +1773,7 @@ static struct qcom_icc_bcm bcm_mm1_cam_ife_1 =3D { =20 static struct qcom_icc_bcm bcm_sh0_cam_ife_1 =3D { .name =3D "SH0", - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_CAM1, .num_nodes =3D 1, .nodes =3D { &qns_llcc_cam_ife_1 }, }; @@ -1781,7 +1781,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_1 =3D { static struct qcom_icc_bcm bcm_sh1_cam_ife_1 =3D { .name =3D "SH1", .enable_mask =3D 0x1, - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_CAM1, .num_nodes =3D 3, .nodes =3D { &qnm_mnoc_hf_cam_ife_1, &qnm_mnoc_sf_cam_ife_1, &qnm_pcie_cam_ife_1 }, @@ -1790,21 +1790,21 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_1 =3D { static struct qcom_icc_bcm bcm_acv_cam_ife_2 =3D { .name =3D "ACV", .enable_mask =3D 0x0, - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_CAM2, .num_nodes =3D 1, .nodes =3D { &ebi_cam_ife_2 }, }; =20 static struct qcom_icc_bcm bcm_mc0_cam_ife_2 =3D { .name =3D "MC0", - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_CAM2, .num_nodes =3D 1, .nodes =3D { &ebi_cam_ife_2 }, }; =20 static struct qcom_icc_bcm bcm_mm0_cam_ife_2 =3D { .name =3D "MM0", - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_CAM2, .num_nodes =3D 1, .nodes =3D { &qns_mem_noc_hf_cam_ife_2 }, }; @@ -1812,7 +1812,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_2 =3D { static struct qcom_icc_bcm bcm_mm1_cam_ife_2 =3D { .name =3D "MM1", .enable_mask =3D 0x1, - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_CAM2, .num_nodes =3D 4, .nodes =3D { &qnm_camnoc_hf_cam_ife_2, &qnm_camnoc_icp_cam_ife_2, &qnm_camnoc_sf_cam_ife_2, &qns_mem_noc_sf_cam_ife_2 }, @@ -1820,7 +1820,7 @@ static struct qcom_icc_bcm bcm_mm1_cam_ife_2 =3D { =20 static struct qcom_icc_bcm bcm_sh0_cam_ife_2 =3D { .name =3D "SH0", - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_CAM2, .num_nodes =3D 1, .nodes =3D { &qns_llcc_cam_ife_2 }, }; @@ -1828,7 +1828,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_2 =3D { static struct qcom_icc_bcm bcm_sh1_cam_ife_2 =3D { .name =3D "SH1", .enable_mask =3D 0x1, - .voter_idx =3D ICC_BCM_VOTER_APPS, + .voter_idx =3D ICC_BCM_VOTER_CAM2, .num_nodes =3D 3, .nodes =3D { &qnm_mnoc_hf_cam_ife_2, &qnm_mnoc_sf_cam_ife_2, &qnm_pcie_cam_ife_2 }, --=20 2.41.0