From nobody Sun Feb 8 14:34:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B72F3EB64DA for ; Fri, 7 Jul 2023 05:33:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231666AbjGGFd5 (ORCPT ); Fri, 7 Jul 2023 01:33:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229529AbjGGFdu (ORCPT ); Fri, 7 Jul 2023 01:33:50 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 41925171D; Thu, 6 Jul 2023 22:33:49 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C82591063; Thu, 6 Jul 2023 22:34:30 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.48.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id ACB703F740; Thu, 6 Jul 2023 22:33:44 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Ryan Roberts , Mark Rutland , Andrew Morton , David Hildenbrand , Jonathan Corbet , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: [RFC 1/4] arm64/mm: Add SW and HW dirty state helpers Date: Fri, 7 Jul 2023 11:03:28 +0530 Message-Id: <20230707053331.510041-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230707053331.510041-1-anshuman.khandual@arm.com> References: <20230707053331.510041-1-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This factors out low level SW and HW state changes i.e make and clear into separate helpers making them explicit improving readability. This also adds pte_rdonly() helper as well. No functional change is intended. Cc: Catalin Marinas Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/pgtable.h | 52 ++++++++++++++++++++++++++------ 1 file changed, 42 insertions(+), 10 deletions(-) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgta= ble.h index 0bd18de9fd97..fb03be697819 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -103,6 +103,7 @@ static inline pteval_t __phys_to_pte_val(phys_addr_t ph= ys) #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) +#define pte_rdonly(pte) (!!(pte_val(pte) & PTE_RDONLY)) #define pte_user(pte) (!!(pte_val(pte) & PTE_USER)) #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) @@ -120,7 +121,7 @@ static inline pteval_t __phys_to_pte_val(phys_addr_t ph= ys) (__boundary - 1 < (end) - 1) ? __boundary : (end); \ }) =20 -#define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) +#define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte)) #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) =20 @@ -174,6 +175,39 @@ static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t = prot) return pmd; } =20 +static inline pte_t pte_hw_mkdirty(pte_t pte) +{ + if (pte_write(pte)) + pte =3D clear_pte_bit(pte, __pgprot(PTE_RDONLY)); + + return pte; +} + +static inline pte_t pte_sw_mkdirty(pte_t pte) +{ + return set_pte_bit(pte, __pgprot(PTE_DIRTY)); +} + +static inline __always_unused pte_t pte_hw_clr_dirty(pte_t pte) +{ + return set_pte_bit(pte, __pgprot(PTE_RDONLY)); +} + +static inline pte_t pte_sw_clr_dirty(pte_t pte) +{ + pte =3D clear_pte_bit(pte, __pgprot(PTE_DIRTY)); + + /* + * Clearing the software dirty state requires clearing + * the PTE_DIRTY bit along with setting the PTE_RDONLY + * ensuring a page fault on subsequent write access. + * + * NOTE: Setting the PTE_RDONLY (as a coincident) also + * implies clearing the HW dirty state. + */ + return set_pte_bit(pte, __pgprot(PTE_RDONLY)); +} + static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot) { pmd_val(pmd) |=3D pgprot_val(prot); @@ -189,19 +223,17 @@ static inline pte_t pte_mkwrite(pte_t pte) =20 static inline pte_t pte_mkclean(pte_t pte) { - pte =3D clear_pte_bit(pte, __pgprot(PTE_DIRTY)); - pte =3D set_pte_bit(pte, __pgprot(PTE_RDONLY)); - - return pte; + /* + * Subsequent call to pte_hw_clr_dirty() is not required + * because pte_sw_clr_dirty() in turn does that as well. + */ + return pte_sw_clr_dirty(pte); } =20 static inline pte_t pte_mkdirty(pte_t pte) { - pte =3D set_pte_bit(pte, __pgprot(PTE_DIRTY)); - - if (pte_write(pte)) - pte =3D clear_pte_bit(pte, __pgprot(PTE_RDONLY)); - + pte =3D pte_sw_mkdirty(pte); + pte =3D pte_hw_mkdirty(pte); return pte; } =20 --=20 2.30.2 From nobody Sun Feb 8 14:34:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6A25EB64D9 for ; Fri, 7 Jul 2023 05:34:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231991AbjGGFd7 (ORCPT ); Fri, 7 Jul 2023 01:33:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231950AbjGGFdz (ORCPT ); Fri, 7 Jul 2023 01:33:55 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 6DFB01BF4; Thu, 6 Jul 2023 22:33:54 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 025DAD75; Thu, 6 Jul 2023 22:34:36 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.48.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9B77D3F740; Thu, 6 Jul 2023 22:33:49 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Ryan Roberts , Mark Rutland , Andrew Morton , David Hildenbrand , Jonathan Corbet , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: [RFC 2/4] arm64/mm: Call pte_sw_mkdirty() while preserving the HW dirty state Date: Fri, 7 Jul 2023 11:03:29 +0530 Message-Id: <20230707053331.510041-3-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230707053331.510041-1-anshuman.khandual@arm.com> References: <20230707053331.510041-1-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" pte_mkdirty() creates dirty states both in SW and HW bits which is really not required either in pte_wrprotect() or pte_modify() for preserving the HW dirty state. Instead pte_sw_mkdirty() is sufficient. Cc: Catalin Marinas Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/pgtable.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgta= ble.h index fb03be697819..dd20b752ed48 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -244,7 +244,7 @@ static inline pte_t pte_wrprotect(pte_t pte) * clear), set the PTE_DIRTY bit. */ if (pte_hw_dirty(pte)) - pte =3D pte_mkdirty(pte); + pte =3D pte_sw_mkdirty(pte); =20 pte =3D clear_pte_bit(pte, __pgprot(PTE_WRITE)); pte =3D set_pte_bit(pte, __pgprot(PTE_RDONLY)); @@ -855,7 +855,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newp= rot) PTE_ATTRINDX_MASK; /* preserve the hardware dirty information */ if (pte_hw_dirty(pte)) - pte =3D pte_mkdirty(pte); + pte =3D pte_sw_mkdirty(pte); pte_val(pte) =3D (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); return pte; } --=20 2.30.2 From nobody Sun Feb 8 14:34:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12956EB64DA for ; Fri, 7 Jul 2023 05:34:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231965AbjGGFeJ (ORCPT ); Fri, 7 Jul 2023 01:34:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232177AbjGGFeE (ORCPT ); Fri, 7 Jul 2023 01:34:04 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A5D991FEB; Thu, 6 Jul 2023 22:33:59 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4F865D75; Thu, 6 Jul 2023 22:34:41 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.48.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C10AE3F740; Thu, 6 Jul 2023 22:33:55 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Ryan Roberts , Mark Rutland , Andrew Morton , David Hildenbrand , Jonathan Corbet , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: [RFC 3/4] arm64/mm: Add pte_preserve_hw_dirty() Date: Fri, 7 Jul 2023 11:03:30 +0530 Message-Id: <20230707053331.510041-4-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230707053331.510041-1-anshuman.khandual@arm.com> References: <20230707053331.510041-1-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Preserving the HW dirty state via SW PTE dirty bit, should be made explicit ensuring greater clarity and readability. This adds pte_preserve_hw_dirty() helper for that effect. No functional change is intended. Cc: Catalin Marinas Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/pgtable.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgta= ble.h index dd20b752ed48..5344e71a58b2 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -237,7 +237,7 @@ static inline pte_t pte_mkdirty(pte_t pte) return pte; } =20 -static inline pte_t pte_wrprotect(pte_t pte) +static inline pte_t pte_preserve_hw_dirty(pte_t pte) { /* * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY @@ -246,6 +246,12 @@ static inline pte_t pte_wrprotect(pte_t pte) if (pte_hw_dirty(pte)) pte =3D pte_sw_mkdirty(pte); =20 + return pte; +} + +static inline pte_t pte_wrprotect(pte_t pte) +{ + pte =3D pte_preserve_hw_dirty(pte); pte =3D clear_pte_bit(pte, __pgprot(PTE_WRITE)); pte =3D set_pte_bit(pte, __pgprot(PTE_RDONLY)); return pte; @@ -853,9 +859,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newp= rot) const pteval_t mask =3D PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP | PTE_ATTRINDX_MASK; - /* preserve the hardware dirty information */ - if (pte_hw_dirty(pte)) - pte =3D pte_sw_mkdirty(pte); + pte =3D pte_preserve_hw_dirty(pte); pte_val(pte) =3D (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); return pte; } --=20 2.30.2 From nobody Sun Feb 8 14:34:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C324C001DE for ; Fri, 7 Jul 2023 05:34:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232151AbjGGFeS (ORCPT ); Fri, 7 Jul 2023 01:34:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232408AbjGGFeK (ORCPT ); Fri, 7 Jul 2023 01:34:10 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 3DADB210B; Thu, 6 Jul 2023 22:34:04 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B029112FC; Thu, 6 Jul 2023 22:34:45 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.48.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 114983F740; Thu, 6 Jul 2023 22:33:59 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Ryan Roberts , Mark Rutland , Andrew Morton , David Hildenbrand , Jonathan Corbet , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: [RFC 4/4] docs: arm64: Add help document for pte dirty state management Date: Fri, 7 Jul 2023 11:03:31 +0530 Message-Id: <20230707053331.510041-5-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230707053331.510041-1-anshuman.khandual@arm.com> References: <20230707053331.510041-1-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" PTE dirty state management is non-trivial on arm64 platform. This document explains how both software and hardware come together in correctly tracking PTE ditry state across various page table transactions. Cc: Catalin Marinas Cc: Will Deacon Cc: Jonathan Corbet Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-doc@vger.kernel.org Signed-off-by: Anshuman Khandual --- Documentation/arch/arm64/index.rst | 1 + Documentation/arch/arm64/pte-dirty.rst | 95 ++++++++++++++++++++++++++ 2 files changed, 96 insertions(+) create mode 100644 Documentation/arch/arm64/pte-dirty.rst diff --git a/Documentation/arch/arm64/index.rst b/Documentation/arch/arm64/= index.rst index d08e924204bf..522f887f2a60 100644 --- a/Documentation/arch/arm64/index.rst +++ b/Documentation/arch/arm64/index.rst @@ -22,6 +22,7 @@ ARM64 Architecture perf pointer-authentication ptdump + pte-dirty silicon-errata sme sve diff --git a/Documentation/arch/arm64/pte-dirty.rst b/Documentation/arch/ar= m64/pte-dirty.rst new file mode 100644 index 000000000000..a6401696f6a3 --- /dev/null +++ b/Documentation/arch/arm64/pte-dirty.rst @@ -0,0 +1,95 @@ +.. SPDX-License-Identifier: GPL-2.0 +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Page Table Entry - Dirty State Management +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +1. Introduction +--------------- + +arm64 platform defines pte_dirty() to determine if the pte has been dirtied +i.e pte has been written info after the previous clean procedure. The dirty +state tracking could be achieved, either via software or hardware pte dirty +bit mechanism. On arm64 platform, pte_dirty() is implemented utilizing both +software and hardware dirty bits, making it non intuitive unlike many other +platforms. + +2. PTE Dirty Bits (SW and HW) +----------------------------- +Following are relevant PTE bit positions for dirty state tracking. + +- PTE_DIRTY is a software bit (55) in the PTE +- PTE_RDONLY is a hardware bit (7) in the PTE +- PTE_DBM is a hardware bit (51) in the PTE +- PTE_WRITE is a hardware bit (51) in the PTE - share position with PTE_DBM + +3. PTE Dirty State Tracking +--------------------------- +Without ARM64_HW_AFDBM enabled, PTE dirty state is tracked only in the SW. +PTE is marked read-only in HW, subsequent write access generates page fault +which can update the SW dirty bit and clear the read-only access in HW. + +With ARM64_HW_AFDBM enabled, PTE dirty state is tracked both in SW and HW. +PTE is marked read-only in HW while also enabling DBM tracking. Any write +access will clear the read-only bit while also preventing a page fault. As +PTE_DBM and PTE_WRITE share the same bit position, a dirty non-writable PTE +state cannot be tracked in hardware. This in turn necessitates dirty state +tracking (ARM64_HW_AFDBM enabled) to accommodate both software and hardware +PTE bits. This helps in avoiding a runtime check for ARM64_HW_AFDBM feature +being enabled on a given implementation. + +Testing and clearing PTE dirty state is relatively simple - + +#define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte)) +#define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) +#define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) + +static inline pte_t pte_mkclean(pte_t pte) +{ + /* + * Subsequent call to pte_hw_clr_dirty() is not required + * because pte_sw_clr_dirty() in turn does that as well. + */ + return pte_sw_clr_dirty(pte); +} + +But marking a dirty state, creating a write protected entry etc now becomes +bit non-trivial in hardware. as PTE_RDONLY bit could only be cleared if the +write bit is also set. + +static inline pte_t pte_hw_mkdirty(pte_t pte) +{ + if (pte_write(pte)) + return clear_pte_bit(pte, __pgprot(PTE_RDONLY)); + + return pte; +} + +Hence marking a dirty state triggers marking both SW and HW dirty bits, so +that if the HW suppoprt is unavailable or insufficient (dirty non-writable) +, SW mechanism would still put it in a dirty state. + +static inline pte_t pte_mkdirty(pte_t pte) +{ + pte =3D pte_sw_mkdirty(pte); + pte =3D pte_hw_mkdirty(pte); + return pte; +} + +4. Preserving PTE HW Dirty State +-------------------------------- +If for some reason HW dirty bits (PTE_WRITE, PTE_RDONLY) need to be cleared +the dirty state must be transferred as SW dirty bit ensuring persistence of +the dirty state across the operation. + +static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) +{ + ..... + pte =3D pte_preserve_hw_dirty(pte_t pte); + ..... +} + +static inline pte_t pte_wrprotect(pte_t pte) +{ + pte =3D pte_preserve_hw_dirty(pte_t pte); + ..... +} --=20 2.30.2