From nobody Sun Feb 8 11:26:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FC65EB64D9 for ; Thu, 6 Jul 2023 18:29:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232181AbjGFS3h (ORCPT ); Thu, 6 Jul 2023 14:29:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57028 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232068AbjGFS3d (ORCPT ); Thu, 6 Jul 2023 14:29:33 -0400 Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B04771BF3 for ; Thu, 6 Jul 2023 11:29:32 -0700 (PDT) Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-668704a5b5bso838051b3a.0 for ; Thu, 06 Jul 2023 11:29:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1688668172; x=1691260172; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:from:to:cc:subject:date:message-id:reply-to; bh=j9gx9gtWQG17bITJPaSQX1DW1aPQRO9lN+pwis8si+8=; b=P65PhZndeCPsnBvFcnO8CzzWjX3j29Bukb4sbpVkPhyCLc/2sznDZKw7SaM5eP4jq+ ij+bvwEpDhQHUBgGKxHAAalB+uWcZ90BK3E6+Nts9wbeU7jTmDXFbjRC0dbuPYX2jhgk W+UFbhI82CrV2se6KffgLlYFYaexYnmjnucaY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688668172; x=1691260172; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=j9gx9gtWQG17bITJPaSQX1DW1aPQRO9lN+pwis8si+8=; b=ShU8b9LML4u/Wwk2EPsAaNm+rJudnqjwc3KuAaxsP6hrmQTk/q8zK/ooPmyDhluq+C poYKkBaP7HpTCljBZzrMIOIp3l6GNd6MS4RbwtCVba0r82ZJjBN2dv3N5DCzd4Q5OwQU bLHCbhYqBXQM0PNrohQZh9oWT0WbDZuv3+BZybaf1bvMO7QRv3HoiZ0hLsrtrSAzbTSA lGR+6qMJagxaP5yC0LqJllgKQPAUKVhvanTqWUuzy9w2drmstKvL40FbUUTEFCZ4c4iJ eYxlUMLDu1EKXR2hcDPB8j9wUafsJlvd79btgrlnrGx4YuTUnVQu7UL3NcJ/2mWGw0zH 5dQA== X-Gm-Message-State: ABy/qLaVjLS99K9xzLH90YyCp56VjrPYQHVfZCXdq2eT9IXVhtFYkkSw zP3RFFCQ+uWD/U1uwuGGEsgSVw== X-Google-Smtp-Source: APBJJlEjg7JwSn4mraB2/E3bDWIi+CypfPtHWvh14VYuBYxS37W/ubIg7uCL1RjmyuoQCPSFbTrvaQ== X-Received: by 2002:a05:6a00:2d20:b0:67a:a906:9edb with SMTP id fa32-20020a056a002d2000b0067aa9069edbmr3425198pfb.30.1688668171981; Thu, 06 Jul 2023 11:29:31 -0700 (PDT) Received: from ubuntu-22.localdomain ([192.19.222.250]) by smtp.gmail.com with ESMTPSA id y13-20020aa7804d000000b006826c9e4397sm1580871pfm.48.2023.07.06.11.29.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 11:29:31 -0700 (PDT) From: William Zhang To: Broadcom Kernel List , Linux MTD List Cc: f.fainelli@gmail.com, rafal@milecki.pl, kursad.oney@broadcom.com, joel.peshkin@broadcom.com, computersforpeace@gmail.com, anand.gore@broadcom.com, dregan@mail.com, kamal.dasu@broadcom.com, tomer.yacoby@broadcom.com, dan.beygelman@broadcom.com, William Zhang , Florian Fainelli , stable@vger.kernel.org, Rob Herring , linux-kernel@vger.kernel.org, Vignesh Raghavendra , Miquel Raynal , Richard Weinberger , Boris Brezillon , Kamal Dasu Subject: [PATCH v4 1/5] mtd: rawnand: brcmnand: Fix ECC level field setting for v7.2 controller Date: Thu, 6 Jul 2023 11:29:05 -0700 Message-Id: <20230706182909.79151-2-william.zhang@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230706182909.79151-1-william.zhang@broadcom.com> References: <20230706182909.79151-1-william.zhang@broadcom.com> MIME-Version: 1.0 Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="00000000000090121a05ffd5b2d5" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --00000000000090121a05ffd5b2d5 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" v7.2 controller has different ECC level field size and shift in the acc control register than its predecessor and successor controller. It needs to be set specifically. Fixes: decba6d47869 ("mtd: brcmnand: Add v7.2 controller support") Signed-off-by: William Zhang Reviewed-by: Florian Fainelli Cc: stable@vger.kernel.org --- Changes in v4: - Move ACC_CONTROL_ECC*_SHIFT definitions out of the enum definition - Add cc stable tag Changes in v3: None Changes in v2: - Use driver static data for ECC level shift drivers/mtd/nand/raw/brcmnand/brcmnand.c | 74 +++++++++++++----------- 1 file changed, 41 insertions(+), 33 deletions(-) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/ra= w/brcmnand/brcmnand.c index 2e9c2e2d9c9f..9ea96911d16b 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -272,6 +272,7 @@ struct brcmnand_controller { const unsigned int *page_sizes; unsigned int page_size_shift; unsigned int max_oob; + u32 ecc_level_shift; u32 features; =20 /* for low-power standby/resume only */ @@ -596,6 +597,34 @@ enum { INTFC_CTLR_READY =3D BIT(31), }; =20 +/*********************************************************************** + * NAND ACC CONTROL bitfield + * + * Some bits have remained constant throughout hardware revision, while + * others have shifted around. + ***********************************************************************/ + +/* Constant for all versions (where supported) */ +enum { + /* See BRCMNAND_HAS_CACHE_MODE */ + ACC_CONTROL_CACHE_MODE =3D BIT(22), + + /* See BRCMNAND_HAS_PREFETCH */ + ACC_CONTROL_PREFETCH =3D BIT(23), + + ACC_CONTROL_PAGE_HIT =3D BIT(24), + ACC_CONTROL_WR_PREEMPT =3D BIT(25), + ACC_CONTROL_PARTIAL_PAGE =3D BIT(26), + ACC_CONTROL_RD_ERASED =3D BIT(27), + ACC_CONTROL_FAST_PGM_RDIN =3D BIT(28), + ACC_CONTROL_WR_ECC =3D BIT(30), + ACC_CONTROL_RD_ECC =3D BIT(31), +}; + +#define ACC_CONTROL_ECC_SHIFT 16 +/* Only for v7.2 */ +#define ACC_CONTROL_ECC_EXT_SHIFT 13 + static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctrl) { #if IS_ENABLED(CONFIG_MTD_NAND_BRCMNAND_BCMA) @@ -737,6 +766,12 @@ static int brcmnand_revision_init(struct brcmnand_cont= roller *ctrl) else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp")) ctrl->features |=3D BRCMNAND_HAS_WP; =20 + /* v7.2 has different ecc level shift in the acc register */ + if (ctrl->nand_version =3D=3D 0x0702) + ctrl->ecc_level_shift =3D ACC_CONTROL_ECC_EXT_SHIFT; + else + ctrl->ecc_level_shift =3D ACC_CONTROL_ECC_SHIFT; + return 0; } =20 @@ -931,30 +966,6 @@ static inline int brcmnand_cmd_shift(struct brcmnand_c= ontroller *ctrl) return 0; } =20 -/*********************************************************************** - * NAND ACC CONTROL bitfield - * - * Some bits have remained constant throughout hardware revision, while - * others have shifted around. - ***********************************************************************/ - -/* Constant for all versions (where supported) */ -enum { - /* See BRCMNAND_HAS_CACHE_MODE */ - ACC_CONTROL_CACHE_MODE =3D BIT(22), - - /* See BRCMNAND_HAS_PREFETCH */ - ACC_CONTROL_PREFETCH =3D BIT(23), - - ACC_CONTROL_PAGE_HIT =3D BIT(24), - ACC_CONTROL_WR_PREEMPT =3D BIT(25), - ACC_CONTROL_PARTIAL_PAGE =3D BIT(26), - ACC_CONTROL_RD_ERASED =3D BIT(27), - ACC_CONTROL_FAST_PGM_RDIN =3D BIT(28), - ACC_CONTROL_WR_ECC =3D BIT(30), - ACC_CONTROL_RD_ECC =3D BIT(31), -}; - static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctr= l) { if (ctrl->nand_version =3D=3D 0x0702) @@ -967,18 +978,15 @@ static inline u32 brcmnand_spare_area_mask(struct brc= mnand_controller *ctrl) return GENMASK(4, 0); } =20 -#define NAND_ACC_CONTROL_ECC_SHIFT 16 -#define NAND_ACC_CONTROL_ECC_EXT_SHIFT 13 - static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl) { u32 mask =3D (ctrl->nand_version >=3D 0x0600) ? 0x1f : 0x0f; =20 - mask <<=3D NAND_ACC_CONTROL_ECC_SHIFT; + mask <<=3D ACC_CONTROL_ECC_SHIFT; =20 /* v7.2 includes additional ECC levels */ - if (ctrl->nand_version >=3D 0x0702) - mask |=3D 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT; + if (ctrl->nand_version =3D=3D 0x0702) + mask |=3D 0x7 << ACC_CONTROL_ECC_EXT_SHIFT; =20 return mask; } @@ -992,8 +1000,8 @@ static void brcmnand_set_ecc_enabled(struct brcmnand_h= ost *host, int en) =20 if (en) { acc_control |=3D ecc_flags; /* enable RD/WR ECC */ - acc_control |=3D host->hwcfg.ecc_level - << NAND_ACC_CONTROL_ECC_SHIFT; + acc_control &=3D ~brcmnand_ecc_level_mask(ctrl); + acc_control |=3D host->hwcfg.ecc_level << ctrl->ecc_level_shift; } else { acc_control &=3D ~ecc_flags; /* disable RD/WR ECC */ acc_control &=3D ~brcmnand_ecc_level_mask(ctrl); @@ -2561,7 +2569,7 @@ static int brcmnand_set_cfg(struct brcmnand_host *hos= t, tmp &=3D ~brcmnand_ecc_level_mask(ctrl); tmp &=3D ~brcmnand_spare_area_mask(ctrl); if (ctrl->nand_version >=3D 0x0302) { - tmp |=3D cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT; + tmp |=3D cfg->ecc_level << ctrl->ecc_level_shift; tmp |=3D cfg->spare_area_size; } nand_writereg(ctrl, acc_control_offs, tmp); --=20 2.37.3 --00000000000090121a05ffd5b2d5 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