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Shenoy" , Mark Rutland , Peter Zijlstra , Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Krzysztof Kozlowski , Evan Green , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC V2 PATCH 7/9] riscv: report misaligned accesses emulation to hwprobe Date: Tue, 4 Jul 2023 16:09:22 +0200 Message-Id: <20230704140924.315594-8-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230704140924.315594-1-cleger@rivosinc.com> References: <20230704140924.315594-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org hwprobe provides a way to report if misaligned access are emulated. In order to correctly populate that feature, if the SBI delegated us misaligned access handling, then we can check if it actually traps when doing a misaligned access. This can be checked using an exception table entry which will actually be used when a misaligned access is done from kernel mode. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/include/asm/cpufeature.h | 2 ++ arch/riscv/kernel/setup.c | 2 ++ arch/riscv/kernel/traps_misaligned.c | 32 ++++++++++++++++++++++++++++ 3 files changed, 36 insertions(+) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index 808d5403f2ac..7e968499db49 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -20,4 +20,6 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); =20 DECLARE_PER_CPU(long, misaligned_access_speed); =20 +void __init misaligned_emulation_init(void); + #endif diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 36b026057503..820a8158e4f7 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -23,6 +23,7 @@ =20 #include #include +#include #include #include #include @@ -284,6 +285,7 @@ void __init setup_arch(char **cmdline_p) =20 init_resources(); sbi_init(); + misaligned_emulation_init(); =20 #ifdef CONFIG_KASAN kasan_init(); diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index 39ec6caa6234..243ef9314734 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include =20 #define INSN_MATCH_LB 0x3 #define INSN_MASK_LB 0x707f @@ -441,3 +443,33 @@ int handle_misaligned_store(struct pt_regs *regs) =20 return 0; } + +void __init misaligned_emulation_init(void) +{ + int cpu; + unsigned long emulated =3D 1, tmp_var; + + /* Temporarily disable unaligned accesses support so that we fixup the + * exception for code below. + */ + unaligned_enabled =3D 0; + + __asm__ __volatile__ ( + "1:\n" + " ld %[tmp], 1(%[ptr])\n" + " li %[emulated], 0\n" + "2:\n" + _ASM_EXTABLE(1b, 2b) + : [emulated] "+r" (emulated), [tmp] "=3Dr" (tmp_var) + : [ptr] "r" (&tmp_var) + : "memory" ); + + unaligned_enabled =3D 1; + if (!emulated) + return; + + for_each_possible_cpu(cpu) { + per_cpu(misaligned_access_speed, cpu) =3D + RISCV_HWPROBE_MISALIGNED_EMULATED; + } +} --=20 2.40.1