From nobody Mon Feb 9 06:49:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A58DBC001DB for ; Mon, 3 Jul 2023 03:51:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230033AbjGCDvG (ORCPT ); Sun, 2 Jul 2023 23:51:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229901AbjGCDvE (ORCPT ); Sun, 2 Jul 2023 23:51:04 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [IPv6:2001:df5:b000:5::4]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30E721BE for ; Sun, 2 Jul 2023 20:51:02 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 0CDBC2C04A2; Mon, 3 Jul 2023 15:50:49 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1688356249; bh=V/moquzw94k+RD/17vle2ubXDMwNpgVNQy7Yswy0IyY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qHO2p0ily3m712nHX8LWyPpjiQlm23Fam3ARpukZt087eBjBNucFeF3VU2roiZ/S+ 0q8+47P+il/rzpiG/f2DpU12GpN43stuU7PiMPYuZlN8yoBp9FK3ARVU8mRbkUHCdP 7jKce2+WN2/C9pTUDarOwRO0ly58tJA17owHlxm4/IOASpPdrCYGRJD7RkgoK8dpPP Te6chOyVzujhqdlvJmjE199l1y4sp8UHj+9zsgAk7jcELpArJMOizOTVMzSOnub8eP I72ElAxREHBQGugA4YgAmCRfauO4ziZCdpJgVO0MbJlrp0GmDkVdpYobGFUxXcBF5T Kk65muAFzUS0g== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Mon, 03 Jul 2023 15:50:48 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id A208413EE4C; Mon, 3 Jul 2023 15:50:48 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id A13A5280011; Mon, 3 Jul 2023 15:50:48 +1200 (NZST) From: Chris Packham To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, gregory.clement@bootlin.com Cc: linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham Subject: [PATCH v3 1/3] dt-bindings: mtd: Add AC5 specific binding Date: Mon, 3 Jul 2023 15:50:42 +1200 Message-ID: <20230703035044.2063303-2-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230703035044.2063303-1-chris.packham@alliedtelesis.co.nz> References: <20230703035044.2063303-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SEG-SpamProfiler-Analysis: v=2.3 cv=NPqrBHyg c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=ws7JD89P4LkA:10 a=XYAwZIGsAAAA:8 a=egi5vsMYxoiYnfbZUMcA:9 a=E8ToXWR_bxluHZ7gmE-Z:22 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add binding for AC5 SoC. This SoC only supports NAND SDR timings up to mode 3 so a specific compatible value is needed. Signed-off-by: Chris Packham Acked-by: Conor Dooley --- Notes: Changes in v3: - Collect ack from Conor Changes in v2: - Keep compatibles in alphabetical order - Explain AC5 limitations in commit message .../devicetree/bindings/mtd/marvell,nand-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.= yaml b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml index a10729bb1840..1ecea848e8b9 100644 --- a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml +++ b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml @@ -16,6 +16,7 @@ properties: - const: marvell,armada-8k-nand-controller - const: marvell,armada370-nand-controller - enum: + - marvell,ac5-nand-controller - marvell,armada370-nand-controller - marvell,pxa3xx-nand-controller - description: legacy bindings --=20 2.41.0 From nobody Mon Feb 9 06:49:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 855AAEB64DC for ; Mon, 3 Jul 2023 03:51:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230080AbjGCDvN (ORCPT ); Sun, 2 Jul 2023 23:51:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230004AbjGCDvE (ORCPT ); Sun, 2 Jul 2023 23:51:04 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [IPv6:2001:df5:b000:5::4]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 309F91B2 for ; Sun, 2 Jul 2023 20:51:02 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id EC60B2C03B6; Mon, 3 Jul 2023 15:50:48 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1688356248; bh=fFPDvwsEHFCxrfnhOHQlIvQXqw4Sj7FMlVCBiiLdjZU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B4VMwn/4y7NAsbIZGk/TQzUjJy2Y6mMHh5qgHDzrvavmATvL0GNM4FciqO6fc6qZz VhH/oFDwxyDIc9kmhjd7KPMvjAmZc0IdnaikZSfj9XkBYaoCYIBpAU4PqmVJcXU+sx KKQ0fIbQ4sO2S8BwREZrrDV+Jj6IR35Fq0QzcrHjSnftqh1Jt7tafStyaoh3Dj3d9r r6ke93IGsnoxNHEMtbMYuKxM10okXg3kUcTq2V7Q9Nvz2sAOUoyEVfi9m055vj5/15 MXjq8Y+EiF7xkenTWme+HWVlaX5fubjaUQk0PTFX+YxvCfr6cXlbPK9wMIMX4Pt0VZ yedFmj+IL4k9Q== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Mon, 03 Jul 2023 15:50:48 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id A30BA13EE63; Mon, 3 Jul 2023 15:50:48 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id A2361283B14; Mon, 3 Jul 2023 15:50:48 +1200 (NZST) From: Chris Packham To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, gregory.clement@bootlin.com Cc: linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham Subject: [PATCH v3 2/3] arm64: dts: marvell: Add NAND flash controller to AC5 Date: Mon, 3 Jul 2023 15:50:43 +1200 Message-ID: <20230703035044.2063303-3-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230703035044.2063303-1-chris.packham@alliedtelesis.co.nz> References: <20230703035044.2063303-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SEG-SpamProfiler-Analysis: v=2.3 cv=NPqrBHyg c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=ws7JD89P4LkA:10 a=AWclJRrDGzD0f9BZm7oA:9 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The AC5/AC5X SoC has a NAND flash controller (NFC). Add this to the base SoC dtsi file as a disabled node. The NFC integration on the AC5/AC5X only supports SDR timing modes up to 3 so requires a dedicated compatible property so this limitation can be enforced. Signed-off-by: Chris Packham --- Notes: Changes in v3: - Use correct clock for NFC Changes in v2: - New. arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boo= t/dts/marvell/ac5-98dx25xx.dtsi index c9ce1010c415..c64aaf51deb8 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -297,6 +297,16 @@ spi1: spi@805a8000 { status =3D "disabled"; }; =20 + nand: nand-controller@805b0000 { + compatible =3D "marvell,ac5-nand-controller"; + reg =3D <0x0 0x805b0000 0x0 0x00000054>; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + interrupts =3D ; + clocks =3D <&nand_clock>; + status =3D "disabled"; + }; + gic: interrupt-controller@80600000 { compatible =3D "arm,gic-v3"; #interrupt-cells =3D <3>; @@ -319,5 +329,11 @@ spi_clock: spi-clock { #clock-cells =3D <0>; clock-frequency =3D <200000000>; }; + + nand_clock: nand-clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <400000000>; + }; }; }; --=20 2.41.0 From nobody Mon Feb 9 06:49:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93461EB64DC for ; Mon, 3 Jul 2023 03:51:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230101AbjGCDvQ (ORCPT ); Sun, 2 Jul 2023 23:51:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230003AbjGCDvE (ORCPT ); Sun, 2 Jul 2023 23:51:04 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30D401B7 for ; Sun, 2 Jul 2023 20:51:02 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 0BAF62C049B; Mon, 3 Jul 2023 15:50:49 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1688356249; bh=+XmE3h4JR9jmL93Rq94bj5aEzeXvD+l2Bfqms27UMGE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kbYkkQmL4/7/Ze7FV7f9QCgt9/TGe6ZNLVYJV/+vri52xvcSbBqA/lo5/7lAy1uMj sVIQaiNcWagWfhc+K6gUCA9m1ot6m45WTOL80gJtHPGYXLWyThOaG4fPFJjIQW3Zu0 wsIOyD5rmvwxGU7tE9XshX0d38j/oG4QVZkJ/uODF/J4vPpiclEynvoU66tGLDgsf8 og/wiHf44i+KE+t/ILgMUDKBzDbYqlQVrXP7oGLhrJVLd/b1ioikFdrYbwpZvZ8rtU Yfk7DtB434bHr9r2oy7ZAHKlb9hwDCh8hPtTWcbSbj17IPV0QJq7h7Dgn5CZocLIuZ drwtFtTn/zx0Q== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Mon, 03 Jul 2023 15:50:48 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id A436E13EE82; Mon, 3 Jul 2023 15:50:48 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id A5931283B6B; Mon, 3 Jul 2023 15:50:48 +1200 (NZST) From: Chris Packham To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, gregory.clement@bootlin.com Cc: linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham Subject: [PATCH v3 3/3] mtd: rawnand: marvell: add support for AC5 SoC Date: Mon, 3 Jul 2023 15:50:44 +1200 Message-ID: <20230703035044.2063303-4-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230703035044.2063303-1-chris.packham@alliedtelesis.co.nz> References: <20230703035044.2063303-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SEG-SpamProfiler-Analysis: v=2.3 cv=NPqrBHyg c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=ws7JD89P4LkA:10 a=FN2KoAgMzK-72ix3NDkA:9 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for the AC5/AC5X SoC from Marvell. The NFC on this SoC only supports SDR modes up to 3. Marvell's SDK includes some predefined values for the ndtr registers. These haven't been incorporated as the existing code seems to get good values based on measurements taken with an oscilloscope. Signed-off-by: Chris Packham --- Notes: Changes in v3: - None Changes in v2: - None drivers/mtd/nand/raw/Kconfig | 2 +- drivers/mtd/nand/raw/marvell_nand.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index b523354dfb00..0f4cbb497010 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -160,7 +160,7 @@ config MTD_NAND_MARVELL including: - PXA3xx processors (NFCv1) - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2) - - 64-bit Aramda platforms (7k, 8k) (NFCv2) + - 64-bit Aramda platforms (7k, 8k, ac5) (NFCv2) =20 config MTD_NAND_SLC_LPC32XX tristate "NXP LPC32xx SLC NAND controller" diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/mar= vell_nand.c index 30c15e4e1cc0..b9a8dd324211 100644 --- a/drivers/mtd/nand/raw/marvell_nand.c +++ b/drivers/mtd/nand/raw/marvell_nand.c @@ -375,6 +375,7 @@ static inline struct marvell_nand_chip_sel *to_nand_sel= (struct marvell_nand_chip * BCH error detection and correction algorithm, * NDCB3 register has been added * @use_dma: Use dma for data transfers + * @max_mode_number: Maximum timing mode supported by the controller */ struct marvell_nfc_caps { unsigned int max_cs_nb; @@ -383,6 +384,7 @@ struct marvell_nfc_caps { bool legacy_of_bindings; bool is_nfcv2; bool use_dma; + unsigned int max_mode_number; }; =20 /** @@ -2376,6 +2378,9 @@ static int marvell_nfc_setup_interface(struct nand_ch= ip *chip, int chipnr, if (IS_ERR(sdr)) return PTR_ERR(sdr); =20 + if (nfc->caps->max_mode_number && nfc->caps->max_mode_number < conf->timi= ngs.mode) + return -EOPNOTSUPP; + /* * SDR timings are given in pico-seconds while NFC timings must be * expressed in NAND controller clock cycles, which is half of the @@ -3073,6 +3078,13 @@ static const struct marvell_nfc_caps marvell_armada_= 8k_nfc_caps =3D { .is_nfcv2 =3D true, }; =20 +static const struct marvell_nfc_caps marvell_ac5_caps =3D { + .max_cs_nb =3D 2, + .max_rb_nb =3D 1, + .is_nfcv2 =3D true, + .max_mode_number =3D 3, +}; + static const struct marvell_nfc_caps marvell_armada370_nfc_caps =3D { .max_cs_nb =3D 4, .max_rb_nb =3D 2, @@ -3121,6 +3133,10 @@ static const struct of_device_id marvell_nfc_of_ids[= ] =3D { .compatible =3D "marvell,armada-8k-nand-controller", .data =3D &marvell_armada_8k_nfc_caps, }, + { + .compatible =3D "marvell,ac5-nand-controller", + .data =3D &marvell_ac5_caps, + }, { .compatible =3D "marvell,armada370-nand-controller", .data =3D &marvell_armada370_nfc_caps, --=20 2.41.0