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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT042.mail.protection.outlook.com (10.13.173.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6500.49 via Frontend Transport; Fri, 30 Jun 2023 23:17:12 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Fri, 30 Jun 2023 18:17:11 -0500 From: Terry Bowman To: , , , , , , , CC: , , , Subject: [PATCH v8 02/14] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Date: Fri, 30 Jun 2023 18:16:23 -0500 Message-ID: <20230630231635.3132638-3-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230630231635.3132638-1-terry.bowman@amd.com> References: <20230630231635.3132638-1-terry.bowman@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT042:EE_|MW4PR12MB7013:EE_ X-MS-Office365-Filtering-Correlation-Id: 4c367885-104f-4aec-91a8-08db79c02292 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2023 23:17:12.2988 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4c367885-104f-4aec-91a8-08db79c02292 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT042.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7013 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Robert Richter Same as for ports and dports, also store the endpoint's Component Register mappings, use struct cxl_dev_state for that. Keep the Component Register base address @component_reg_phys a bit to not break functionality. It will be removed after the transition in a later patch. Signed-off-by: Robert Richter Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang --- drivers/cxl/cxlmem.h | 2 ++ drivers/cxl/pci.c | 9 +++++---- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index 79e99c873ca2..607ee34b0ce7 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -382,6 +382,7 @@ enum cxl_devtype { * * @dev: The device associated with this CXL state * @cxlmd: The device representing the CXL.mem capabilities of @dev + * @comp_map: component register capability mappings * @regs: Parsed register blocks * @cxl_dvsec: Offset to the PCIe device DVSEC * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an = RCH) @@ -396,6 +397,7 @@ enum cxl_devtype { struct cxl_dev_state { struct device *dev; struct cxl_memdev *cxlmd; + struct cxl_register_map comp_map; struct cxl_regs regs; int cxl_dvsec; bool rcd; diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 48f88d96029d..054cfa2f6a2d 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -836,15 +836,16 @@ static int cxl_pci_probe(struct pci_dev *pdev, const = struct pci_device_id *id) * still be useful for management functions so don't return an error. */ cxlds->component_reg_phys =3D CXL_RESOURCE_NONE; - rc =3D cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map); + rc =3D cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, + &cxlds->comp_map); if (rc) dev_warn(&pdev->dev, "No component registers (%d)\n", rc); - else if (!map.component_map.ras.valid) + else if (!cxlds->comp_map.component_map.ras.valid) dev_dbg(&pdev->dev, "RAS registers not found\n"); =20 - cxlds->component_reg_phys =3D map.resource; + cxlds->component_reg_phys =3D cxlds->comp_map.resource; =20 - rc =3D cxl_map_component_regs(&map, &cxlds->regs.component, + rc =3D cxl_map_component_regs(&cxlds->comp_map, &cxlds->regs.component, BIT(CXL_CM_CAP_CAP_ID_RAS)); if (rc) dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); --=20 2.34.1