From nobody Sun Feb 8 15:58:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C814EB64DA for ; Fri, 30 Jun 2023 20:18:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231778AbjF3USZ (ORCPT ); Fri, 30 Jun 2023 16:18:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231899AbjF3USI (ORCPT ); Fri, 30 Jun 2023 16:18:08 -0400 Received: from unicorn.mansr.com (unicorn.mansr.com [81.2.72.234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53F722D52 for ; Fri, 30 Jun 2023 13:18:07 -0700 (PDT) Received: from raven.mansr.com (raven.mansr.com [IPv6:2001:8b0:ca0d:1::3]) by unicorn.mansr.com (Postfix) with ESMTPS id 61C4715362; Fri, 30 Jun 2023 21:18:03 +0100 (BST) Received: by raven.mansr.com (Postfix, from userid 51770) id 4E3CC21A9CD; Fri, 30 Jun 2023 21:18:03 +0100 (BST) From: Mans Rullgard To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard Cc: Daniel Lezcano , Thomas Gleixner , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [PATCH 2/3] clocksource: sun5i: remove pointless struct Date: Fri, 30 Jun 2023 21:01:27 +0100 Message-ID: <20230630201800.16501-3-mans@mansr.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230630201800.16501-1-mans@mansr.com> References: <20230630201800.16501-1-mans@mansr.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Remove the pointless struct added in the previous patch to make the diff smaller. Signed-off-by: Mans Rullgard Acked-by: Jernej Skrabec --- drivers/clocksource/timer-sun5i.c | 49 ++++++++++++++----------------- 1 file changed, 22 insertions(+), 27 deletions(-) diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-= sun5i.c index e0ca97cf80cb..3ca427e54daf 100644 --- a/drivers/clocksource/timer-sun5i.c +++ b/drivers/clocksource/timer-sun5i.c @@ -35,22 +35,17 @@ =20 #define TIMER_SYNC_TICKS 3 =20 -/* Pointless struct to minimise diff */ -struct _sun5i_timer { +struct sun5i_timer { void __iomem *base; struct clk *clk; struct notifier_block clk_rate_cb; u32 ticks_per_jiffy; -}; - -struct sun5i_timer { - struct _sun5i_timer timer; struct clocksource clksrc; struct clock_event_device clkevt; }; =20 #define nb_to_sun5i_timer(x) \ - container_of(x, struct sun5i_timer, timer.clk_rate_cb) + container_of(x, struct sun5i_timer, clk_rate_cb) #define clksrc_to_sun5i_timer(x) \ container_of(x, struct sun5i_timer, clksrc) #define clkevt_to_sun5i_timer(x) \ @@ -64,28 +59,28 @@ struct sun5i_timer { */ static void sun5i_clkevt_sync(struct sun5i_timer *ce) { - u32 old =3D readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1)); + u32 old =3D readl(ce->base + TIMER_CNTVAL_LO_REG(1)); =20 - while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYN= C_TICKS) + while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICK= S) cpu_relax(); } =20 static void sun5i_clkevt_time_stop(struct sun5i_timer *ce, u8 timer) { - u32 val =3D readl(ce->timer.base + TIMER_CTL_REG(timer)); - writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer)); + u32 val =3D readl(ce->base + TIMER_CTL_REG(timer)); + writel(val & ~TIMER_CTL_ENABLE, ce->base + TIMER_CTL_REG(timer)); =20 sun5i_clkevt_sync(ce); } =20 static void sun5i_clkevt_time_setup(struct sun5i_timer *ce, u8 timer, u32 = delay) { - writel(delay, ce->timer.base + TIMER_INTVAL_LO_REG(timer)); + writel(delay, ce->base + TIMER_INTVAL_LO_REG(timer)); } =20 static void sun5i_clkevt_time_start(struct sun5i_timer *ce, u8 timer, bool= periodic) { - u32 val =3D readl(ce->timer.base + TIMER_CTL_REG(timer)); + u32 val =3D readl(ce->base + TIMER_CTL_REG(timer)); =20 if (periodic) val &=3D ~TIMER_CTL_ONESHOT; @@ -93,7 +88,7 @@ static void sun5i_clkevt_time_start(struct sun5i_timer *c= e, u8 timer, bool perio val |=3D TIMER_CTL_ONESHOT; =20 writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, - ce->timer.base + TIMER_CTL_REG(timer)); + ce->base + TIMER_CTL_REG(timer)); } =20 static int sun5i_clkevt_shutdown(struct clock_event_device *clkevt) @@ -118,7 +113,7 @@ static int sun5i_clkevt_set_periodic(struct clock_event= _device *clkevt) struct sun5i_timer *ce =3D clkevt_to_sun5i_timer(clkevt); =20 sun5i_clkevt_time_stop(ce, 0); - sun5i_clkevt_time_setup(ce, 0, ce->timer.ticks_per_jiffy); + sun5i_clkevt_time_setup(ce, 0, ce->ticks_per_jiffy); sun5i_clkevt_time_start(ce, 0, true); return 0; } @@ -139,7 +134,7 @@ static irqreturn_t sun5i_timer_interrupt(int irq, void = *dev_id) { struct sun5i_timer *ce =3D dev_id; =20 - writel(0x1, ce->timer.base + TIMER_IRQ_ST_REG); + writel(0x1, ce->base + TIMER_IRQ_ST_REG); ce->clkevt.event_handler(&ce->clkevt); =20 return IRQ_HANDLED; @@ -149,7 +144,7 @@ static u64 sun5i_clksrc_read(struct clocksource *clksrc) { struct sun5i_timer *cs =3D clksrc_to_sun5i_timer(clksrc); =20 - return ~readl(cs->timer.base + TIMER_CNTVAL_LO_REG(1)); + return ~readl(cs->base + TIMER_CNTVAL_LO_REG(1)); } =20 static int sun5i_rate_cb(struct notifier_block *nb, @@ -166,7 +161,7 @@ static int sun5i_rate_cb(struct notifier_block *nb, case POST_RATE_CHANGE: clocksource_register_hz(&cs->clksrc, ndata->new_rate); clockevents_update_freq(&cs->clkevt, ndata->new_rate); - cs->timer.ticks_per_jiffy =3D DIV_ROUND_UP(ndata->new_rate, HZ); + cs->ticks_per_jiffy =3D DIV_ROUND_UP(ndata->new_rate, HZ); break; =20 default: @@ -180,7 +175,7 @@ static int __init sun5i_setup_clocksource(struct device= _node *node, struct sun5i_timer *cs, unsigned long rate) { - void __iomem *base =3D cs->timer.base; + void __iomem *base =3D cs->base; int ret; =20 writel(~0, base + TIMER_INTVAL_LO_REG(1)); @@ -206,7 +201,7 @@ static int __init sun5i_setup_clockevent(struct device_= node *node, struct sun5i_timer *ce, unsigned long rate, int irq) { - void __iomem *base =3D ce->timer.base; + void __iomem *base =3D ce->base; int ret; u32 val; =20 @@ -282,13 +277,13 @@ static int __init sun5i_timer_init(struct device_node= *node) goto err_disable_clk; } =20 - st->timer.base =3D timer_base; - st->timer.ticks_per_jiffy =3D DIV_ROUND_UP(rate, HZ); - st->timer.clk =3D clk; - st->timer.clk_rate_cb.notifier_call =3D sun5i_rate_cb; - st->timer.clk_rate_cb.next =3D NULL; + st->base =3D timer_base; + st->ticks_per_jiffy =3D DIV_ROUND_UP(rate, HZ); + st->clk =3D clk; + st->clk_rate_cb.notifier_call =3D sun5i_rate_cb; + st->clk_rate_cb.next =3D NULL; =20 - ret =3D clk_notifier_register(clk, &st->timer.clk_rate_cb); + ret =3D clk_notifier_register(clk, &st->clk_rate_cb); if (ret) { pr_err("Unable to register clock notifier.\n"); goto err_disable_clk; @@ -305,7 +300,7 @@ static int __init sun5i_timer_init(struct device_node *= node) return sun5i_setup_clockevent(node, st, rate, irq); =20 err_remove_notifier: - clk_notifier_unregister(clk, &st->timer.clk_rate_cb); + clk_notifier_unregister(clk, &st->clk_rate_cb); err_disable_clk: clk_disable_unprepare(clk); err_free: --=20 2.41.0