From nobody Sun Feb 8 23:06:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A11DEEB64DD for ; Fri, 30 Jun 2023 08:32:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231546AbjF3Icy (ORCPT ); Fri, 30 Jun 2023 04:32:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42398 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232555AbjF3Icn (ORCPT ); Fri, 30 Jun 2023 04:32:43 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CCCA61FC1 for ; Fri, 30 Jun 2023 01:32:41 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-3fa93d61d48so17952505e9.0 for ; Fri, 30 Jun 2023 01:32:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1688113960; x=1690705960; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YVY/yta8MPWmg9iGDhd2QZ8qAlvFNnDO2cXvkrgJQ+E=; b=kl/TPhm6ikHmXXieyToZuU/DsVCjRsYDu5avotvuqaFc6tZ03SeeW4FBKpCi/Mw0WK wYwR3smgKyTmD/+jwch8XyufhBtdkF3f7qT76g3QLFIxycHhxqlDuelvEeFLcQBDGwtt c99+4W37R5ubiuAV02MC9TfgLz/gSE7K7R4yhEbEZr5+7p6QH5R3OjwwnSQN3sEOn7tW RKj4BSD6VxbchcdMJw22xXR3zLMu8PcBAKcXWWpZR1RwCBliqolg8sKRbGtF44CNGBjW 9CyHSusDkCPt0CnofvgfwI9NFxWhPuDzw6CUyYduupu1PMRz4yXtfiSFdQwWM5irvYAE GdrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688113960; x=1690705960; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YVY/yta8MPWmg9iGDhd2QZ8qAlvFNnDO2cXvkrgJQ+E=; b=FW+b1947Wb1HNWT7zREPjSNnmp0tSY/CUCzltgLwSkldvH+3LmgDZ3+CY+ueXbpyl3 XY7JMmIelhZM+Ub3OKD/Zw41i2KQRyZt/3mrp3PBoiGBGfFNXRlyHdw8TUmqEZ+RbEka ULHiRoMafd+7/IOX4PqUi07539lK0S0e8V5zyWo6JNg3bVVPhrIsFBvC0rjgEMNVBcxD YqvAWdUJ6CdkUY1EMC+c8Y5QQ+r6sl61V18M0DUBSM/0DN0U11+pI4q4W7TLN8qnGYhd 3PbLRzxAbzJlDxrorr8GD/C9566CNokG+ID9x0Nldpr0zEYU42SXyvMiV4wi/lHjNYMM eMhw== X-Gm-Message-State: AC+VfDxNVjV/WRB//elcj19sCMxL2JzLBE2I399JhgI6Se7tGAt6Fqhl gbeWaUZXNnaVcROfCb7Uy5tC5Un1KaD/zaslaiI= X-Google-Smtp-Source: ACHHUZ4sOZab/Xe9VR+3s2W1uRvunuBxqP1Egjt8iE/RBBaYrC98a4RA8h5p4k6wwDyYphRxgmB5tw== X-Received: by 2002:a1c:7c05:0:b0:3f6:2ae:230e with SMTP id x5-20020a1c7c05000000b003f602ae230emr1443811wmc.3.1688113960321; Fri, 30 Jun 2023 01:32:40 -0700 (PDT) Received: from alex-rivos.ba.rivosinc.com (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id v4-20020a05600c214400b003fa95890484sm13846402wml.20.2023.06.30.01.32.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 01:32:40 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Rob Herring , Andrew Jones , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Cc: Alexandre Ghiti , Atish Patra Subject: [PATCH v3 01/10] perf: Fix wrong comment about default event_idx Date: Fri, 30 Jun 2023 10:30:04 +0200 Message-Id: <20230630083013.102334-2-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230630083013.102334-1-alexghiti@rivosinc.com> References: <20230630083013.102334-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since commit c719f56092ad ("perf: Fix and clean up initialization of pmu::event_idx"), event_idx default implementation has returned 0, not idx + 1, so fix the comment that can be misleading. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Atish Patra --- include/linux/perf_event.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index d5628a7b5eaa..56fe43b20966 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -442,7 +442,8 @@ struct pmu { =20 /* * Will return the value for perf_event_mmap_page::index for this event, - * if no implementation is provided it will default to: event->hw.idx + 1. + * if no implementation is provided it will default to 0 (see + * perf_event_idx_default). */ int (*event_idx) (struct perf_event *event); /*optional */ =20 --=20 2.39.2 From nobody Sun Feb 8 23:06:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5678FEB64D7 for ; Fri, 30 Jun 2023 08:33:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232590AbjF3Idv (ORCPT ); Fri, 30 Jun 2023 04:33:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230256AbjF3Ido (ORCPT ); Fri, 30 Jun 2023 04:33:44 -0400 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A9DE1BE1 for ; Fri, 30 Jun 2023 01:33:43 -0700 (PDT) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-3fbc244d386so10595245e9.2 for ; Fri, 30 Jun 2023 01:33:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1688114021; x=1690706021; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nFKT0CCXN0CmmHE2x8MUQw5sccSB1SdakxOhkM1UsG4=; b=YGAogcVzokF+D0qjqmU3kpfxHH4NCQmZL5hxdf7X6SSw33kykvLvK6O3yH62Wh5KJs AI+kFCJ+XKcyflz03tZeBSOK3mdSvkfolRUwvwoE2OoTCMNudeW3PdTVP95e6GocLU/N YygZJOZT/1wW8FkrtFxcSBXYCawVlOJln1BQSnbywabffKuPzm96PK063d/COMXtlZoM RfVe8d3eFPxGt8MI4tg2xzpfBf6tCr8koxakv9E5o1JNI2//NwB2JCt6o9+Vh8ajvvu+ lKsjBGdikrwy1dWQPmQywiFnnCn9wnpbQ1KHhOw4ctZqEtIougO0WReOzYJMEwk93dxp UkBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688114021; x=1690706021; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nFKT0CCXN0CmmHE2x8MUQw5sccSB1SdakxOhkM1UsG4=; b=ebO+wh9QIEqBfMdTYyILlmZkWL3E7y+PYAGjHjYDsrMO3vr0cUI/NtGVkinxy+niBU UZ70oW53NIthHHl1Vm6zv1D7pvK+Zl57TkoeSmH46rAfVY/+KsfmIr39wddHufKWwFhs tpJk3JqY1/J2O+oZ1Zzb3PLqWhtnaRXIcBgiR8ZoKQOgTjMQ3Xh/RP0hVEji+NjB1+TP USJtYGQuySadDRR5ZBvv6qqxojwfha8oymjA8YeK0HhDYcA8STWtPMGirLA1YerHNY6t DIPBAUE6Mv0NUBNWMis1h+7M5Ek3Cj+KdFOMzlTwok5IsP6Z6t8VJuqV5IT4Wz/QBwFw SiVw== X-Gm-Message-State: AC+VfDynThvNmv0b9R8D6dLLYU33PdiY//DtPNhMml7+4Fh7PcUHjdHa EN3iOhkDBqvXHAhBXzuiGHkbMw== X-Google-Smtp-Source: ACHHUZ7Qad/4yQ+SzjVoKc4hjwSg7WrVeGOPcXS9LsZnNjqu+cFkrpDtf3BchhUp9ScTeVkytqKaOg== X-Received: by 2002:a05:600c:2292:b0:3f8:fc2a:c7eb with SMTP id 18-20020a05600c229200b003f8fc2ac7ebmr1334297wmf.5.1688114021658; Fri, 30 Jun 2023 01:33:41 -0700 (PDT) Received: from alex-rivos.ba.rivosinc.com (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id n20-20020a7bcbd4000000b003fb739d27aesm10273826wmi.35.2023.06.30.01.33.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 01:33:41 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Rob Herring , Andrew Jones , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Cc: Alexandre Ghiti , Conor Dooley , Atish Patra Subject: [PATCH v3 02/10] include: riscv: Fix wrong include guard in riscv_pmu.h Date: Fri, 30 Jun 2023 10:30:05 +0200 Message-Id: <20230630083013.102334-3-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230630083013.102334-1-alexghiti@rivosinc.com> References: <20230630083013.102334-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The current include guard prevents the inclusion of asm/perf_event.h which uses the same include guard: fix the one in riscv_pmu.h so that it matches the file name. Signed-off-by: Alexandre Ghiti Reviewed-by: Conor Dooley Reviewed-by: Andrew Jones Reviewed-by: Atish Patra --- include/linux/perf/riscv_pmu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index 43fc892aa7d9..9f70d94942e0 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -6,8 +6,8 @@ * */ =20 -#ifndef _ASM_RISCV_PERF_EVENT_H -#define _ASM_RISCV_PERF_EVENT_H +#ifndef _RISCV_PMU_H +#define _RISCV_PMU_H =20 #include #include @@ -81,4 +81,4 @@ int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw= _ctr); =20 #endif /* CONFIG_RISCV_PMU */ =20 -#endif /* _ASM_RISCV_PERF_EVENT_H */ +#endif /* _RISCV_PMU_H */ --=20 2.39.2 From nobody Sun Feb 8 23:06:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1837AEB64DD for ; Fri, 30 Jun 2023 08:35:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231899AbjF3IfK (ORCPT ); Fri, 30 Jun 2023 04:35:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232585AbjF3Ier (ORCPT ); Fri, 30 Jun 2023 04:34:47 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FB201BE1 for ; Fri, 30 Jun 2023 01:34:45 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-311394406d0so1744378f8f.2 for ; Fri, 30 Jun 2023 01:34:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1688114083; x=1690706083; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0N3S2PdFA0VnOMrqOiiJN/oJrFso6OovUf1itxoBYAA=; b=J5Sn0TMa0823JltcKEUSImQM6e0Z43AXFTNAAN1zqIBSWgR1tJ1Eg/He+/E288Nuc6 AiyPl3/mzz7/zpY0QSkNwH2x57OXfJxna4a2FF8tBbBwJE+W1DnoEz0LKGRiK4PgcPCU po/VfBnBmAiZTj1BZuiuDn8AgiOei/Wz/lcP8Xk2igyM/S8bCC98ZSXOv592eNKw+nIG NmwcFrPAEBYmkK1d/ZvVdkOrhalki00+AidE81IPGrA95cXp/6BmiEEQgAA9qlU7fNQM etWeXu/FmWC+q12PA+iyqB0oMo5nmGNbzuc1QFNCOu3aUh+9hzI4u0M/PfvWaI+aG/HP wz5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688114083; x=1690706083; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0N3S2PdFA0VnOMrqOiiJN/oJrFso6OovUf1itxoBYAA=; b=dKrDfAz1OErI0KvWYQryRl+hYldDKA7t4f+bLiGeAHftfbe3M05b56HJZYla4NsWYb d032SGygILIEyNXrer9PB1+BUIHsN1BiMyQBfI0fJwHEWrHu53o8jDE2hAmW6vp5ChaP cWARA5Fiv2FOEzKMpEEQKkzPVicixYB5VrJVYf1SzzWtYV/2WkETjKtzy0OFsZpIqC1g H79IbXbpXVZwD1EsGE5/lLumn1kLAdln98hDnppRQjAqyxyJr/oqU9cP3P+HCaFswbvW yjrDCahUO83eo0qSpcWn8ScoekwT7C4xYpEBdfFFG9RBe31EL8gozx0NADoVXthP2M0P qohg== X-Gm-Message-State: ABy/qLbQ4u5QObF3ekc8G3FqsZNWf/iTm/httEEw2nidoJShVa7zR14d sM3ZvzOjeTDPOHyRdhrLI7vhkg== X-Google-Smtp-Source: APBJJlEgKPYrVDEFl+Qq2I9oLtumgWiJSroN7sH+vO/yUwUUT/VtoZcK+tKhR7P0/qWi0SE0EQP+OA== X-Received: by 2002:a5d:518c:0:b0:314:fe8:94d8 with SMTP id k12-20020a5d518c000000b003140fe894d8mr1704004wrv.31.1688114083209; Fri, 30 Jun 2023 01:34:43 -0700 (PDT) Received: from alex-rivos.ba.rivosinc.com (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id a11-20020a056000050b00b003110dc7f408sm17885607wrf.41.2023.06.30.01.34.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 01:34:42 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Rob Herring , Andrew Jones , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Cc: Alexandre Ghiti Subject: [PATCH v3 03/10] riscv: Make legacy counter enum match the HW numbering Date: Fri, 30 Jun 2023 10:30:06 +0200 Message-Id: <20230630083013.102334-4-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230630083013.102334-1-alexghiti@rivosinc.com> References: <20230630083013.102334-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" RISCV_PMU_LEGACY_INSTRET used to be set to 1 whereas the offset of this hardware counter from CSR_CYCLE is actually 2: make this offset match the real hw offset so that we can directly expose those values to userspace. Signed-off-by: Alexandre Ghiti --- drivers/perf/riscv_pmu_legacy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legac= y.c index ca9e20bfc7ac..6a000abc28bb 100644 --- a/drivers/perf/riscv_pmu_legacy.c +++ b/drivers/perf/riscv_pmu_legacy.c @@ -13,7 +13,7 @@ #include =20 #define RISCV_PMU_LEGACY_CYCLE 0 -#define RISCV_PMU_LEGACY_INSTRET 1 +#define RISCV_PMU_LEGACY_INSTRET 2 =20 static bool pmu_init_done; =20 --=20 2.39.2 From nobody Sun Feb 8 23:06:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65788EB64D7 for ; Fri, 30 Jun 2023 08:36:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232647AbjF3IgS (ORCPT ); Fri, 30 Jun 2023 04:36:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232375AbjF3Ifr (ORCPT ); Fri, 30 Jun 2023 04:35:47 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C34735BD for ; Fri, 30 Jun 2023 01:35:46 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id 2adb3069b0e04-4f973035d60so2607886e87.3 for ; Fri, 30 Jun 2023 01:35:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1688114144; x=1690706144; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4ourpCES+L8D+Sf3DlwDnrKMPgPuj2Rb0Ie1m7RKO9o=; b=0KLssk8HRfE90130xKoKTzd8QqIpNNmEGYyeL+ivfM59890lBfIuxPh/YTTtxMCeJu HilIlZL6yYJHT+NSdn2sWN1C3I33DwQxN5PPXQk69+hLlbGiOnTa3XOfshkprJru9dCp AeDmMl1VoQDpxwaI+8E2wJD1THYAUCwr1Zaa0GHElk3IDp8gkCxpUazrlnegNSdrthgC JBuREIxskFXjzwLrlDfKLochEuX5EBp/lfz3dW1Ko/jbOkZn5tzbNH7Xy/WEQlTW29Mw zbe10nFdCWzgoKjjn4/cjhnuLG9yl9b+oDWEOXNbIRq2mQX+Hv0MyM55crAam+humX+M /6LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688114144; x=1690706144; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4ourpCES+L8D+Sf3DlwDnrKMPgPuj2Rb0Ie1m7RKO9o=; b=USCZW7w4kFn/wUpcKu4QG83Is2n2g8FOOivATw33cn5EDkL2MNwRmHbV7Cw3JmC7Q/ sai3EqG/QOx+ouKrnUZR3WMb9LZ6pxy0nHdQFdQjpBRvLhQ/pb+mw/wVJ8ELiH9v90m4 E3DIwCz+ZRuBUWv7PmyIa9NrFS6qTjaE8X7x3cQGhhrFau9Nv/Nrg0gqpM735vdoN0u9 OtGX3m7vFs6OLozHo1AcoEUGydXUGS+N7x+QY25z//2kA0Ss+imkWpe91oib81ajlKKE DmYJISVLzFOpmvPr2tzE5/3An9UVlKBRL82WwQO00cP4koOPJPG5/IcjMxoxZeRetUed xTzw== X-Gm-Message-State: ABy/qLZK8+lxpFBBgfaY7wPE6WKYwTYASfL/ynDeAZvAklBq6kAGZAmm PdGipNWs05mnCtOmu0snfd8+kfelRao6Cl6Iec8= X-Google-Smtp-Source: APBJJlEKmo6oGA8BhKLYpuMDCbIqFVI+6Q81fGGqSIHo2vLevwphPX4q4nQy50JIRXqiJIM8dj26WQ== X-Received: by 2002:a19:9110:0:b0:4fb:8ee0:b8a5 with SMTP id t16-20020a199110000000b004fb8ee0b8a5mr1396269lfd.46.1688114144613; Fri, 30 Jun 2023 01:35:44 -0700 (PDT) Received: from alex-rivos.ba.rivosinc.com (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id s15-20020adfeccf000000b003127741d7desm6286799wro.58.2023.06.30.01.35.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 01:35:44 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Rob Herring , Andrew Jones , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Cc: Alexandre Ghiti Subject: [PATCH v3 04/10] drivers: perf: Rename riscv pmu sbi driver Date: Fri, 30 Jun 2023 10:30:07 +0200 Message-Id: <20230630083013.102334-5-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230630083013.102334-1-alexghiti@rivosinc.com> References: <20230630083013.102334-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" That's just cosmetic, no functional changes. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones --- drivers/perf/riscv_pmu_sbi.c | 4 ++-- include/linux/perf/riscv_pmu.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 4f3ac296b3e2..83c3f1c4d2f1 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -914,7 +914,7 @@ static int pmu_sbi_device_probe(struct platform_device = *pdev) static struct platform_driver pmu_sbi_driver =3D { .probe =3D pmu_sbi_device_probe, .driver =3D { - .name =3D RISCV_PMU_PDEV_NAME, + .name =3D RISCV_PMU_SBI_PDEV_NAME, }, }; =20 @@ -941,7 +941,7 @@ static int __init pmu_sbi_devinit(void) if (ret) return ret; =20 - pdev =3D platform_device_register_simple(RISCV_PMU_PDEV_NAME, -1, NULL, 0= ); + pdev =3D platform_device_register_simple(RISCV_PMU_SBI_PDEV_NAME, -1, NUL= L, 0); if (IS_ERR(pdev)) { platform_driver_unregister(&pmu_sbi_driver); return PTR_ERR(pdev); diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index 9f70d94942e0..5deeea0be7cb 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -21,7 +21,7 @@ =20 #define RISCV_MAX_COUNTERS 64 #define RISCV_OP_UNSUPP (-EOPNOTSUPP) -#define RISCV_PMU_PDEV_NAME "riscv-pmu" +#define RISCV_PMU_SBI_PDEV_NAME "riscv-pmu-sbi" #define RISCV_PMU_LEGACY_PDEV_NAME "riscv-pmu-legacy" =20 #define RISCV_PMU_STOP_FLAG_RESET 1 --=20 2.39.2 From nobody Sun Feb 8 23:06:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CDE8EB64DA for ; Fri, 30 Jun 2023 08:37:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232342AbjF3IhT (ORCPT ); Fri, 30 Jun 2023 04:37:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232321AbjF3Igu (ORCPT ); Fri, 30 Jun 2023 04:36:50 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CAFC1BCA for ; Fri, 30 Jun 2023 01:36:48 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-3fbc59de0e2so6807415e9.3 for ; Fri, 30 Jun 2023 01:36:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1688114206; x=1690706206; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XbFrV/q7Aw3mH90ZjkDcoZb78N1NQiIc7nnyXH9eDMc=; b=lk4ROx+445tjGoiFoANbfoxzkU/tTN0mTJrJx7aWYCV262XC66c5hSNLo6pJryncjC FaAZsSwUMZVVIGrUk2nq0JvLfgk4zShuHsZDCgmzBUpYcbFKpkHwLDlg4Wz8ysOW83Ko TieV7rqnvdXVDf+yeoLeOYUADZ7zHQZZ/CwEFEBNhZX26aXYy7qI3gFc/m2tmtWQbpLw Mn/N/+AzNfGZ4garHVqizQAh0/Pl5TdSiegTXP2bCOYPbaf4BDsq6xtDmz2sDKuV24dc +6SoRTE7RPAHsY8jra+nTGvLlPBQTB7lgBxh4sXnbvIY0pskHqVSaJdDVxiZIe8M172Q 97sA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688114206; x=1690706206; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XbFrV/q7Aw3mH90ZjkDcoZb78N1NQiIc7nnyXH9eDMc=; b=KdFip7pfb19k6LCNCYM9CkScxwQGs0Pp9+JDb+G30bXiqob5wrdf/wSa6zgLUH0OCV vyZU/O0/A0WlpdaajIcNE8GCOQJJXbuJ9PmMPUuzd2qtYqCq+P8MvJHvGrFYaGAfbhpR o5GXSy5qS513ZDTgtt4QMdwisxcynkSoWvGWgJjJhqBjj3M5Gpo2ZvvmHSqBE2oyZ/iw 0Nk8kI5EZls0zzC1LZtVggSQL8QmyfFUfWMquIoBeH5E4XumFfHYndqmSI1zyoQrdxtc gC/IwEh33pKCOxSgCRzO1bvhajLL09lA4cJhdyt+52MgFte/+SpqvRy3o29zsIf1/S6c iX9A== X-Gm-Message-State: AC+VfDx65DbHYpetks/Hdtlj+wXY+ktoM1gMaPof5w6RE28PXL+NAcU/ xmhhONZgjV0lIdo6cGaCPStfLA== X-Google-Smtp-Source: ACHHUZ5E6Ts0FdjdtogyYoZnx3gLffIu8xGsaINIU3rFCRVUCOnwwLWUUeKyhOEVWUyaOE/vpwyl5Q== X-Received: by 2002:a1c:7706:0:b0:3fb:b61f:c719 with SMTP id t6-20020a1c7706000000b003fbb61fc719mr1388538wmi.33.1688114206421; Fri, 30 Jun 2023 01:36:46 -0700 (PDT) Received: from alex-rivos.ba.rivosinc.com (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id 12-20020a05600c028c00b003fbaade072dsm8024200wmk.23.2023.06.30.01.36.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 01:36:45 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Rob Herring , Andrew Jones , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Cc: Alexandre Ghiti Subject: [PATCH v3 05/10] riscv: Prepare for user-space perf event mmap support Date: Fri, 30 Jun 2023 10:30:08 +0200 Message-Id: <20230630083013.102334-6-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230630083013.102334-1-alexghiti@rivosinc.com> References: <20230630083013.102334-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Provide all the necessary bits in the generic riscv pmu driver to be able to mmap perf events in userspace: the heavy lifting lies in the driver backend, namely the legacy and sbi implementations. Note that arch_perf_update_userpage is almost a copy of arm64 code. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones --- drivers/perf/riscv_pmu.c | 106 +++++++++++++++++++++++++++++++++ include/linux/perf/riscv_pmu.h | 4 ++ 2 files changed, 110 insertions(+) diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c index ebca5eab9c9b..e1b0992f34df 100644 --- a/drivers/perf/riscv_pmu.c +++ b/drivers/perf/riscv_pmu.c @@ -14,9 +14,74 @@ #include #include #include +#include =20 #include =20 +static bool riscv_perf_user_access(struct perf_event *event) +{ + return ((event->attr.type =3D=3D PERF_TYPE_HARDWARE) || + (event->attr.type =3D=3D PERF_TYPE_HW_CACHE) || + (event->attr.type =3D=3D PERF_TYPE_RAW)) && + !!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT); +} + +void arch_perf_update_userpage(struct perf_event *event, + struct perf_event_mmap_page *userpg, u64 now) +{ + struct clock_read_data *rd; + unsigned int seq; + u64 ns; + + userpg->cap_user_time =3D 0; + userpg->cap_user_time_zero =3D 0; + userpg->cap_user_time_short =3D 0; + userpg->cap_user_rdpmc =3D riscv_perf_user_access(event); + + if (userpg->cap_user_rdpmc) + userpg->pmc_width =3D 64; + + do { + rd =3D sched_clock_read_begin(&seq); + + userpg->time_mult =3D rd->mult; + userpg->time_shift =3D rd->shift; + userpg->time_zero =3D rd->epoch_ns; + userpg->time_cycles =3D rd->epoch_cyc; + userpg->time_mask =3D rd->sched_clock_mask; + + /* + * Subtract the cycle base, such that software that + * doesn't know about cap_user_time_short still 'works' + * assuming no wraps. + */ + ns =3D mul_u64_u32_shr(rd->epoch_cyc, rd->mult, rd->shift); + userpg->time_zero -=3D ns; + + } while (sched_clock_read_retry(seq)); + + userpg->time_offset =3D userpg->time_zero - now; + + /* + * time_shift is not expected to be greater than 31 due to + * the original published conversion algorithm shifting a + * 32-bit value (now specifies a 64-bit value) - refer + * perf_event_mmap_page documentation in perf_event.h. + */ + if (userpg->time_shift =3D=3D 32) { + userpg->time_shift =3D 31; + userpg->time_mult >>=3D 1; + } + + /* + * Internal timekeeping for enabled/running/stopped times + * is always computed with the sched_clock. + */ + userpg->cap_user_time =3D 1; + userpg->cap_user_time_zero =3D 1; + userpg->cap_user_time_short =3D 1; +} + static unsigned long csr_read_num(int csr_num) { #define switchcase_csr_read(__csr_num, __val) {\ @@ -171,6 +236,8 @@ int riscv_pmu_event_set_period(struct perf_event *event) =20 local64_set(&hwc->prev_count, (u64)-left); =20 + perf_event_update_userpage(event); + return overflow; } =20 @@ -267,6 +334,9 @@ static int riscv_pmu_event_init(struct perf_event *even= t) hwc->idx =3D -1; hwc->event_base =3D mapped_event; =20 + if (rvpmu->event_init) + rvpmu->event_init(event); + if (!is_sampling_event(event)) { /* * For non-sampling runs, limit the sample_period to half @@ -283,6 +353,39 @@ static int riscv_pmu_event_init(struct perf_event *eve= nt) return 0; } =20 +static int riscv_pmu_event_idx(struct perf_event *event) +{ + struct riscv_pmu *rvpmu =3D to_riscv_pmu(event->pmu); + + if (!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT)) + return 0; + + if (rvpmu->csr_index) + return rvpmu->csr_index(event) + 1; + + return 0; +} + +static void riscv_pmu_event_mapped(struct perf_event *event, struct mm_str= uct *mm) +{ + struct riscv_pmu *rvpmu =3D to_riscv_pmu(event->pmu); + + if (rvpmu->event_mapped) { + rvpmu->event_mapped(event, mm); + perf_event_update_userpage(event); + } +} + +static void riscv_pmu_event_unmapped(struct perf_event *event, struct mm_s= truct *mm) +{ + struct riscv_pmu *rvpmu =3D to_riscv_pmu(event->pmu); + + if (rvpmu->event_unmapped) { + rvpmu->event_unmapped(event, mm); + perf_event_update_userpage(event); + } +} + struct riscv_pmu *riscv_pmu_alloc(void) { struct riscv_pmu *pmu; @@ -307,6 +410,9 @@ struct riscv_pmu *riscv_pmu_alloc(void) } pmu->pmu =3D (struct pmu) { .event_init =3D riscv_pmu_event_init, + .event_mapped =3D riscv_pmu_event_mapped, + .event_unmapped =3D riscv_pmu_event_unmapped, + .event_idx =3D riscv_pmu_event_idx, .add =3D riscv_pmu_add, .del =3D riscv_pmu_del, .start =3D riscv_pmu_start, diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index 5deeea0be7cb..43282e22ebe1 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -55,6 +55,10 @@ struct riscv_pmu { void (*ctr_start)(struct perf_event *event, u64 init_val); void (*ctr_stop)(struct perf_event *event, unsigned long flag); int (*event_map)(struct perf_event *event, u64 *config); + void (*event_init)(struct perf_event *event); + void (*event_mapped)(struct perf_event *event, struct mm_struct *mm); + void (*event_unmapped)(struct perf_event *event, struct mm_struct *mm); + uint8_t (*csr_index)(struct perf_event *event); =20 struct cpu_hw_events __percpu *hw_events; struct hlist_node node; --=20 2.39.2 From nobody Sun Feb 8 23:06:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A760BEB64D7 for ; Fri, 30 Jun 2023 08:38:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231499AbjF3IiA (ORCPT ); Fri, 30 Jun 2023 04:38:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45574 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232623AbjF3Ihy (ORCPT ); Fri, 30 Jun 2023 04:37:54 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 973E735B0 for ; Fri, 30 Jun 2023 01:37:49 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-313f18f5295so1900625f8f.3 for ; Fri, 30 Jun 2023 01:37:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1688114268; x=1690706268; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rvJvx6RMtbDuAT1323RkBbGas4rmn6vZDZsiVVfiSsE=; b=lWYkSVEYk5z1FejtVVUA0klldRhytVUq4PVf4APQO/bNNLW/bXq2VaOOZVOHGfJo0O BoiDmTkHr4BJGzf9seJQJSJWO4tDokNB9OYnzyZ9xNSeJpd/4l9Cw3LYv2YWRbwKkPer cpYZTFs3FNiAgtWi/HbXsX6KJ6ti6gDFyhxO0m+hPO62v2Nzayz78ya/YGGdx3ahDrla NaD5ITslJvXdKypZQhW3fQZDMwKaiO2M0Gc7BNqUcEoQXxKdIbAhuUFjt90uq+1HtX6X Cw665ivPIqqU5u4yQz+OKSxIg2E766BxHZiRcVrVuGpi5q3pnpJFT/KRyebn+/o6G7Ry PRGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688114268; x=1690706268; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rvJvx6RMtbDuAT1323RkBbGas4rmn6vZDZsiVVfiSsE=; b=do322ssrZ0t02NmznyTNQZjRNBr/9lWkQ4bNmDvFlBjDjgPUlZUfzjWPM9SNgZU/aO tX52ks4WVu7JKWXqAMoTNaf/4sNOxlrHAqXjNSARx7aJAS6qOpvVExu/XtIn/Y7QoJSJ MbdKVI13HkMLZbG7pIaFq6/UW4b/y4UA4G9LjZd4ibyhxBg+g+9xzIA9BvBwZZQGGVxp nVug2NnYk91BdFDEgTWopdZ54/GWWtLvtCOQPZiJqySYifl/inXWDAihsZT+J39Ve5sq aA1TDcBWBrsDnZGZYyFj7WpskD8CXKjVDMrXLU70eg1AVWDTy8BasEyY3Rv9lcOYh/vy C+xA== X-Gm-Message-State: ABy/qLalhL4Kyi9X+qD5qHm3gzMEykxai+lzYVm79OckvsIO/apEpWLI m+RD9iHkuS4R04txjlLQHNVjKQ== X-Google-Smtp-Source: APBJJlG6zuYcHOK0e1CApmkChpZ6WGYLrjfJBoOIUDquuicfotpS+IYjw6DMOOQWgIsvHOVOFPC1aQ== X-Received: by 2002:adf:f6c7:0:b0:313:f60d:4958 with SMTP id y7-20020adff6c7000000b00313f60d4958mr1674659wrp.53.1688114268066; Fri, 30 Jun 2023 01:37:48 -0700 (PDT) Received: from alex-rivos.ba.rivosinc.com (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id i10-20020a5d630a000000b003141f5aff08sm1576732wru.82.2023.06.30.01.37.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 01:37:47 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Rob Herring , Andrew Jones , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Cc: Alexandre Ghiti Subject: [PATCH v3 06/10] drivers: perf: Implement perf event mmap support in the legacy backend Date: Fri, 30 Jun 2023 10:30:09 +0200 Message-Id: <20230630083013.102334-7-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230630083013.102334-1-alexghiti@rivosinc.com> References: <20230630083013.102334-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Implement the needed callbacks in the legacy driver so that we can directly access the counters through perf in userspace. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones --- drivers/perf/riscv_pmu_legacy.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legac= y.c index 6a000abc28bb..79fdd667922e 100644 --- a/drivers/perf/riscv_pmu_legacy.c +++ b/drivers/perf/riscv_pmu_legacy.c @@ -71,6 +71,29 @@ static void pmu_legacy_ctr_start(struct perf_event *even= t, u64 ival) local64_set(&hwc->prev_count, initial_val); } =20 +static uint8_t pmu_legacy_csr_index(struct perf_event *event) +{ + return event->hw.idx; +} + +static void pmu_legacy_event_mapped(struct perf_event *event, struct mm_st= ruct *mm) +{ + if (event->attr.config !=3D PERF_COUNT_HW_CPU_CYCLES && + event->attr.config !=3D PERF_COUNT_HW_INSTRUCTIONS) + return; + + event->hw.flags |=3D PERF_EVENT_FLAG_USER_READ_CNT; +} + +static void pmu_legacy_event_unmapped(struct perf_event *event, struct mm_= struct *mm) +{ + if (event->attr.config !=3D PERF_COUNT_HW_CPU_CYCLES && + event->attr.config !=3D PERF_COUNT_HW_INSTRUCTIONS) + return; + + event->hw.flags &=3D ~PERF_EVENT_FLAG_USER_READ_CNT; +} + /* * This is just a simple implementation to allow legacy implementations * compatible with new RISC-V PMU driver framework. @@ -91,6 +114,9 @@ static void pmu_legacy_init(struct riscv_pmu *pmu) pmu->ctr_get_width =3D NULL; pmu->ctr_clear_idx =3D NULL; pmu->ctr_read =3D pmu_legacy_read_ctr; + pmu->event_mapped =3D pmu_legacy_event_mapped; + pmu->event_unmapped =3D pmu_legacy_event_unmapped; + pmu->csr_index =3D pmu_legacy_csr_index; =20 perf_pmu_register(&pmu->pmu, "cpu", PERF_TYPE_RAW); } --=20 2.39.2 From nobody Sun Feb 8 23:06:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36CA3EB64DD for ; Fri, 30 Jun 2023 08:38:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232155AbjF3Ii4 (ORCPT ); Fri, 30 Jun 2023 04:38:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229459AbjF3Iix (ORCPT ); Fri, 30 Jun 2023 04:38:53 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0262F1FCD for ; Fri, 30 Jun 2023 01:38:51 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-313e34ab99fso1763104f8f.1 for ; Fri, 30 Jun 2023 01:38:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1688114329; x=1690706329; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=POAApKb4kVM3/xye4PBEtZC2woRrAYSgFcWBBuvz70k=; b=mXPjn1aehaCWaOlFbSR8XhorITIIHxenS5bMC9i70HTYeD5mJOZ1ToISK/TbyRAc5x FMMLaKZAgkw+jFm9p1rnBk9vmFfff4kCxAOIb8I1ImvUAVzb33E3Cd8Obhw8/dnMbigf y+m8jYXjnTEaWCs3lRPHhRKs9pqQBkSkfYBAq2W8ybiQ+3WenhzwRK7tW0uDUSBHiyL6 ThOmBAMj7CJv9enW1tuCCJLVFfklRKDKGSsH63NmMwJtvw3sLIaFiV/D6x6VyUaoc3Xu SGeMJuB4tUuVts2YKXdleFYgNLUVXwVQMihE5MxKNHsYvUhIQ47ZqH7TlmL94t6VSmk+ pFPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688114329; x=1690706329; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=POAApKb4kVM3/xye4PBEtZC2woRrAYSgFcWBBuvz70k=; b=PJQT3+ZaSEfFe3std+K1eRdX54gAdZNkd4A3D19HGfGbaRtDl0s16bjpck1mwgjXWb SQsuUVPZT6vWfVnqw7cDUfNQOmHoAPE+ggmfM858jwc3y5fg412km1SOvL3/IekylF9W JagKbmkhAjT8SmDq3kYiLgsaozLnzOQCoavLsz7KB3nNDDAMqwhWYpeA8Wpjsf5uxk9C 8SV8MUpnAvftR7KKoVunxpvFRs6oWRz9FRSRq+tpaxMJsVMBnXpZ0hJQurWWyy2gWoVp omDx+xMHfRn7RBx3sYUy2Mff2zDz+ZriF4efGFYJo6HF27FUKVxk/Yb4kon3Pr2peze7 Y3RA== X-Gm-Message-State: ABy/qLZyvzn4/SR7clvZB7Zn9kPwPXBofJTppMwDD1TMRXIsrLMw81c+ nm17KYTSL+AxnDGKN1pAGB/7GA== X-Google-Smtp-Source: APBJJlE012vchpdZHwC6upxek3lX/eYddaQLY8p5FCpw+gRnTCeNjhDzJ/HNJJxuRxn62WNfjLGAEA== X-Received: by 2002:a05:6000:92e:b0:313:f862:6e3e with SMTP id cx14-20020a056000092e00b00313f8626e3emr1578891wrb.40.1688114329365; Fri, 30 Jun 2023 01:38:49 -0700 (PDT) Received: from alex-rivos.ba.rivosinc.com (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id d13-20020a5d4f8d000000b003063db8f45bsm17740422wru.23.2023.06.30.01.38.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 01:38:49 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Rob Herring , Andrew Jones , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Cc: Alexandre Ghiti Subject: [PATCH v3 07/10] drivers: perf: Implement perf event mmap support in the SBI backend Date: Fri, 30 Jun 2023 10:30:10 +0200 Message-Id: <20230630083013.102334-8-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230630083013.102334-1-alexghiti@rivosinc.com> References: <20230630083013.102334-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We used to unconditionnally expose the cycle and instret csrs to userspace, which gives rise to security concerns. So now we only allow access to hw counters from userspace through the perf framework which will handle context switches, per-task events...etc. But as we cannot break userspace, we give the user the choice to go back to the previous behaviour by setting the sysctl perf_user_access. Signed-off-by: Alexandre Ghiti --- drivers/perf/riscv_pmu.c | 9 +- drivers/perf/riscv_pmu_sbi.c | 192 +++++++++++++++++++++++++++++++++-- 2 files changed, 194 insertions(+), 7 deletions(-) diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c index e1b0992f34df..80c052e93f9e 100644 --- a/drivers/perf/riscv_pmu.c +++ b/drivers/perf/riscv_pmu.c @@ -38,8 +38,15 @@ void arch_perf_update_userpage(struct perf_event *event, userpg->cap_user_time_short =3D 0; userpg->cap_user_rdpmc =3D riscv_perf_user_access(event); =20 +#ifdef CONFIG_RISCV_PMU + /* + * The counters are 64-bit but the priv spec doesn't mandate all the + * bits to be implemented: that's why, counter width can vary based on + * the cpu vendor. + */ if (userpg->cap_user_rdpmc) - userpg->pmc_width =3D 64; + userpg->pmc_width =3D to_riscv_pmu(event->pmu)->ctr_get_width(event->hw.= idx) + 1; +#endif =20 do { rd =3D sched_clock_read_begin(&seq); diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 83c3f1c4d2f1..acabb6c273c1 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -24,6 +24,14 @@ #include #include =20 +#define SYSCTL_NO_USER_ACCESS 0 +#define SYSCTL_USER_ACCESS 1 +#define SYSCTL_LEGACY 2 + +#define PERF_EVENT_FLAG_NO_USER_ACCESS BIT(SYSCTL_NO_USER_ACCESS) +#define PERF_EVENT_FLAG_USER_ACCESS BIT(SYSCTL_USER_ACCESS) +#define PERF_EVENT_FLAG_LEGACY BIT(SYSCTL_LEGACY) + PMU_FORMAT_ATTR(event, "config:0-47"); PMU_FORMAT_ATTR(firmware, "config:63"); =20 @@ -43,6 +51,9 @@ static const struct attribute_group *riscv_pmu_attr_group= s[] =3D { NULL, }; =20 +/* Allow user mode access by default */ +static int sysctl_perf_user_access __read_mostly =3D SYSCTL_USER_ACCESS; + /* * RISC-V doesn't have heterogeneous harts yet. This need to be part of * per_cpu in case of harts with different pmu counters @@ -301,6 +312,11 @@ int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num= _hw_ctr) } EXPORT_SYMBOL_GPL(riscv_pmu_get_hpm_info); =20 +static uint8_t pmu_sbi_csr_index(struct perf_event *event) +{ + return pmu_ctr_list[event->hw.idx].csr - CSR_CYCLE; +} + static unsigned long pmu_sbi_get_filter_flags(struct perf_event *event) { unsigned long cflags =3D 0; @@ -329,18 +345,34 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *eve= nt) struct cpu_hw_events *cpuc =3D this_cpu_ptr(rvpmu->hw_events); struct sbiret ret; int idx; - uint64_t cbase =3D 0; + uint64_t cbase =3D 0, cmask =3D rvpmu->cmask; unsigned long cflags =3D 0; =20 cflags =3D pmu_sbi_get_filter_flags(event); + + /* + * In legacy mode, we have to force the fixed counters for those events + * but not in the user access mode as we want to use the other counters + * that support sampling/filtering. + */ + if (hwc->flags & PERF_EVENT_FLAG_LEGACY) { + if (event->attr.config =3D=3D PERF_COUNT_HW_CPU_CYCLES) { + cflags |=3D SBI_PMU_CFG_FLAG_SKIP_MATCH; + cmask =3D 1; + } else if (event->attr.config =3D=3D PERF_COUNT_HW_INSTRUCTIONS) { + cflags |=3D SBI_PMU_CFG_FLAG_SKIP_MATCH; + cmask =3D 1UL << (CSR_INSTRET - CSR_CYCLE); + } + } + /* retrieve the available counter index */ #if defined(CONFIG_32BIT) ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, - rvpmu->cmask, cflags, hwc->event_base, hwc->config, + cmask, cflags, hwc->event_base, hwc->config, hwc->config >> 32); #else ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, - rvpmu->cmask, cflags, hwc->event_base, hwc->config, 0); + cmask, cflags, hwc->event_base, hwc->config, 0); #endif if (ret.error) { pr_debug("Not able to find a counter for event %lx config %llx\n", @@ -474,6 +506,14 @@ static u64 pmu_sbi_ctr_read(struct perf_event *event) return val; } =20 +static void pmu_sbi_set_scounteren(void *arg) +{ + struct perf_event *event =3D (struct perf_event *)arg; + + csr_write(CSR_SCOUNTEREN, + csr_read(CSR_SCOUNTEREN) | (1 << pmu_sbi_csr_index(event))); +} + static void pmu_sbi_ctr_start(struct perf_event *event, u64 ival) { struct sbiret ret; @@ -490,6 +530,18 @@ static void pmu_sbi_ctr_start(struct perf_event *event= , u64 ival) if (ret.error && (ret.error !=3D SBI_ERR_ALREADY_STARTED)) pr_err("Starting counter idx %d failed with error %d\n", hwc->idx, sbi_err_map_linux_errno(ret.error)); + + if (hwc->flags & PERF_EVENT_FLAG_USER_ACCESS && + hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT) + pmu_sbi_set_scounteren((void *)event); +} + +static void pmu_sbi_reset_scounteren(void *arg) +{ + struct perf_event *event =3D (struct perf_event *)arg; + + csr_write(CSR_SCOUNTEREN, + csr_read(CSR_SCOUNTEREN) & ~(1 << pmu_sbi_csr_index(event))); } =20 static void pmu_sbi_ctr_stop(struct perf_event *event, unsigned long flag) @@ -497,6 +549,10 @@ static void pmu_sbi_ctr_stop(struct perf_event *event,= unsigned long flag) struct sbiret ret; struct hw_perf_event *hwc =3D &event->hw; =20 + if (hwc->flags & PERF_EVENT_FLAG_USER_ACCESS && + hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT) + pmu_sbi_reset_scounteren((void *)event); + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, hwc->idx, 1, fla= g, 0, 0, 0); if (ret.error && (ret.error !=3D SBI_ERR_ALREADY_STOPPED) && flag !=3D SBI_PMU_STOP_FLAG_RESET) @@ -704,10 +760,13 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, str= uct hlist_node *node) struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); =20 /* - * Enable the access for CYCLE, TIME, and INSTRET CSRs from userspace, - * as is necessary to maintain uABI compatibility. + * We keep enabling userspace access to CYCLE, TIME and INSRET via the + * legacy option but that will be removed in the future. */ - csr_write(CSR_SCOUNTEREN, 0x7); + if (sysctl_perf_user_access =3D=3D SYSCTL_LEGACY) + csr_write(CSR_SCOUNTEREN, 0x7); + else + csr_write(CSR_SCOUNTEREN, 0x2); =20 /* Stop all the counters so that they can be enabled from perf */ pmu_sbi_stop_all(pmu); @@ -851,6 +910,121 @@ static void riscv_pmu_destroy(struct riscv_pmu *pmu) cpuhp_state_remove_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node); } =20 +static void pmu_sbi_event_init(struct perf_event *event) +{ + /* + * The permissions are set at event_init so that we do not depend + * on the sysctl value that can change. + */ + if (sysctl_perf_user_access =3D=3D SYSCTL_NO_USER_ACCESS) + event->hw.flags |=3D PERF_EVENT_FLAG_NO_USER_ACCESS; + else if (sysctl_perf_user_access =3D=3D SYSCTL_USER_ACCESS) + event->hw.flags |=3D PERF_EVENT_FLAG_USER_ACCESS; + else + event->hw.flags |=3D PERF_EVENT_FLAG_LEGACY; +} + +static void pmu_sbi_event_mapped(struct perf_event *event, struct mm_struc= t *mm) +{ + if (event->hw.flags & PERF_EVENT_FLAG_NO_USER_ACCESS) + return; + + if (event->hw.flags & PERF_EVENT_FLAG_LEGACY) { + if (event->attr.config !=3D PERF_COUNT_HW_CPU_CYCLES && + event->attr.config !=3D PERF_COUNT_HW_INSTRUCTIONS) { + return; + } + } + + /* + * The user mmapped the event to directly access it: this is where + * we determine based on sysctl_perf_user_access if we grant userspace + * the direct access to this event. That means that within the same + * task, some events may be directly accessible and some other may not, + * if the user changes the value of sysctl_perf_user_accesss in the + * meantime. + */ + + event->hw.flags |=3D PERF_EVENT_FLAG_USER_READ_CNT; + + /* + * We must enable userspace access *before* advertising in the user page + * that it is possible to do so to avoid any race. + * And we must notify all cpus here because threads that currently run + * on other cpus will try to directly access the counter too without + * calling pmu_sbi_ctr_start. + */ + if (event->hw.flags & PERF_EVENT_FLAG_USER_ACCESS) + on_each_cpu_mask(mm_cpumask(mm), + pmu_sbi_set_scounteren, (void *)event, 1); +} + +static void pmu_sbi_event_unmapped(struct perf_event *event, struct mm_str= uct *mm) +{ + if (event->hw.flags & PERF_EVENT_FLAG_NO_USER_ACCESS) + return; + + if (event->hw.flags & PERF_EVENT_FLAG_LEGACY) { + if (event->attr.config !=3D PERF_COUNT_HW_CPU_CYCLES && + event->attr.config !=3D PERF_COUNT_HW_INSTRUCTIONS) { + return; + } + } + + /* + * Here we can directly remove user access since the user does not have + * access to the user page anymore so we avoid the racy window where the + * user could have read cap_user_rdpmc to true right before we disable + * it. + */ + event->hw.flags &=3D ~PERF_EVENT_FLAG_USER_READ_CNT; + + if (event->hw.flags & PERF_EVENT_FLAG_USER_ACCESS) + on_each_cpu_mask(mm_cpumask(mm), + pmu_sbi_reset_scounteren, (void *)event, 1); +} + +static void riscv_pmu_update_counter_access(void *info) +{ + if (sysctl_perf_user_access =3D=3D SYSCTL_LEGACY) + csr_write(CSR_SCOUNTEREN, 0x7); + else + csr_write(CSR_SCOUNTEREN, 0x2); +} + +static int riscv_pmu_proc_user_access_handler(struct ctl_table *table, + int write, void *buffer, + size_t *lenp, loff_t *ppos) +{ + int prev =3D sysctl_perf_user_access; + int ret =3D proc_dointvec_minmax(table, write, buffer, lenp, ppos); + + /* + * Test against the previous value since we clear SCOUNTEREN when + * sysctl_perf_user_access is set to SYSCTL_USER_ACCESS, but we should + * not do that if that was already the case. + */ + if (ret || !write || prev =3D=3D sysctl_perf_user_access) + return ret; + + on_each_cpu(riscv_pmu_update_counter_access, NULL, 1); + + return 0; +} + +static struct ctl_table sbi_pmu_sysctl_table[] =3D { + { + .procname =3D "perf_user_access", + .data =3D &sysctl_perf_user_access, + .maxlen =3D sizeof(unsigned int), + .mode =3D 0644, + .proc_handler =3D riscv_pmu_proc_user_access_handler, + .extra1 =3D SYSCTL_ZERO, + .extra2 =3D SYSCTL_TWO, + }, + { } +}; + static int pmu_sbi_device_probe(struct platform_device *pdev) { struct riscv_pmu *pmu =3D NULL; @@ -888,6 +1062,10 @@ static int pmu_sbi_device_probe(struct platform_devic= e *pdev) pmu->ctr_get_width =3D pmu_sbi_ctr_get_width; pmu->ctr_clear_idx =3D pmu_sbi_ctr_clear_idx; pmu->ctr_read =3D pmu_sbi_ctr_read; + pmu->event_init =3D pmu_sbi_event_init; + pmu->event_mapped =3D pmu_sbi_event_mapped; + pmu->event_unmapped =3D pmu_sbi_event_unmapped; + pmu->csr_index =3D pmu_sbi_csr_index; =20 ret =3D cpuhp_state_add_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node= ); if (ret) @@ -901,6 +1079,8 @@ static int pmu_sbi_device_probe(struct platform_device= *pdev) if (ret) goto out_unregister; =20 + register_sysctl("kernel", sbi_pmu_sysctl_table); + return 0; =20 out_unregister: --=20 2.39.2 From nobody Sun Feb 8 23:06:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 494E5C001B1 for ; Fri, 30 Jun 2023 08:40:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232688AbjF3IkV (ORCPT ); Fri, 30 Jun 2023 04:40:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46532 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232666AbjF3Ijx (ORCPT ); Fri, 30 Jun 2023 04:39:53 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80E442100 for ; Fri, 30 Jun 2023 01:39:52 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-4fb77f21c63so2539535e87.2 for ; Fri, 30 Jun 2023 01:39:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1688114391; x=1690706391; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EOVYMufG9/FqBaKJMl/ssTpZw9h9Tbb5FABAwd0Y76o=; b=EBbwFVdpIP6AbRzaCcRxUMVywY4aT8TXXYQBzuXycm69Am66X12dUUj6ysptXYgNIr kGTOqS2hMSiKkr9t8z64Utml0NDzDblWb9Ih06lJFn88rRYmLS/ZPqlg6vNJLf55epe+ mfrndHAolhwfEvfAkLITFEqkTzZdBDYfiD5T/qT4GIQHOmdzObxuWC0UwwP9TFrFmFpM bOPDk4nWuDmSYim/muDHyo6QJDgHMVwWgX305aJ7W6a9SKOfVaW1r9NQOFu5pEKK5lfc w7NUfhwrRVI6RlDSQw5InTNym6I+xWKhvZhPrW4P4cphlohLHplbvosEpLUxq3VL/KAk 2BsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688114391; x=1690706391; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EOVYMufG9/FqBaKJMl/ssTpZw9h9Tbb5FABAwd0Y76o=; b=MJg06Cr+IB/QwSFzr9KLq6ZT1I9oR33W8DOYVHMbsrggtwwfe7zXMKHy88L/7VIltF h9fFdwfhqbv8RBCMXDQ3zX7+kxHCpf4Hg0evrbt4rKZemVMz96fiHiNR8/CerUxoDZeC 451lx8e7l9fOmNCxbhY1IvBkNf8zdnov3wcAqe9sQpg8d++WQdld9tn5s32oRR0LQ7IM N+ayeU7OXxB6cjcW3BbI3kX2YJ57kKPfDNtwlmVWhXQ/ucgtXrv7lGk0+K5r+xttQS6G qv12x3rMC+gnhAbiHVXAB4puPkB5dEHyB6hvZId8VtSEVUyUWcWALt1Z/ej9EhfhRlzL 74Bg== X-Gm-Message-State: ABy/qLauAR1XKWjXqOllk9FfHFUWcOdWk6T//K0H0NI6ZlDo1PP/PeJU eP2qB0FAraCdqwFFNxI377ddmA== X-Google-Smtp-Source: APBJJlGNGYeNhgyNFQCIWRKRLA0RLNxSwiPewnnuJneE3RkbWYcI3Hv4y5MnEIudbxWchriJpKLCFg== X-Received: by 2002:a05:6512:31d4:b0:4f8:5f32:b1da with SMTP id j20-20020a05651231d400b004f85f32b1damr2010376lfe.24.1688114390713; Fri, 30 Jun 2023 01:39:50 -0700 (PDT) Received: from alex-rivos.ba.rivosinc.com (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id l6-20020adff486000000b00313fd294d6csm9704615wro.7.2023.06.30.01.39.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 01:39:50 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Rob Herring , Andrew Jones , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Cc: Alexandre Ghiti Subject: [PATCH v3 08/10] Documentation: admin-guide: Add riscv sysctl_perf_user_access Date: Fri, 30 Jun 2023 10:30:11 +0200 Message-Id: <20230630083013.102334-9-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230630083013.102334-1-alexghiti@rivosinc.com> References: <20230630083013.102334-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" riscv now uses this sysctl so document its usage for this architecture. Signed-off-by: Alexandre Ghiti --- Documentation/admin-guide/sysctl/kernel.rst | 26 +++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/ad= min-guide/sysctl/kernel.rst index d85d90f5d000..c376692b372b 100644 --- a/Documentation/admin-guide/sysctl/kernel.rst +++ b/Documentation/admin-guide/sysctl/kernel.rst @@ -941,16 +941,34 @@ enabled, otherwise writing to this file will return `= `-EBUSY``. The default value is 8. =20 =20 -perf_user_access (arm64 only) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D +perf_user_access (arm64 and riscv only) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Controls user space access for reading perf event counters. =20 -Controls user space access for reading perf event counters. When set to 1, -user space can read performance monitor counter registers directly. +arm64 +=3D=3D=3D=3D=3D =20 The default value is 0 (access disabled). +When set to 1, user space can read performance monitor counter registers +directly. =20 See Documentation/arm64/perf.rst for more information. =20 +riscv +=3D=3D=3D=3D=3D + +When set to 0, user access is disabled. + +When set to 1, user space can read performance monitor counter registers +directly only through perf, any direct access without perf intervention wi= ll +trigger an illegal instruction. + +The default value is 2, which enables legacy mode (user space has direct +access to cycle and insret CSRs only). Note that this legacy value +is deprecated and will be removed once all userspace applications are fixe= d. + +Note that the time CSR is for now always accessible to all modes. =20 pid_max =3D=3D=3D=3D=3D=3D=3D --=20 2.39.2 From nobody Sun Feb 8 23:06:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98965EB64DA for ; Fri, 30 Jun 2023 08:42:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232719AbjF3ImB (ORCPT ); Fri, 30 Jun 2023 04:42:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232712AbjF3Il3 (ORCPT ); Fri, 30 Jun 2023 04:41:29 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E972C421C for ; Fri, 30 Jun 2023 01:40:53 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-311099fac92so1923343f8f.0 for ; Fri, 30 Jun 2023 01:40:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1688114452; x=1690706452; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xmbgD3BkRBunB0DFWSt+ANLkIPsXQvCtttyk0nyN3eI=; b=xBb3tY6aRK51y+KAOkApMFJQ7mXklF1vW4Q8accpKYblAmqI6K0z8vW9G1W4XT5TYM 2EX8fpWxNmwCgc4GVXIr4CkGfhBo6gRUxnYbz/El7AY1G1BhjLCjkz9wFpGlSKXBr2c9 H2vpjBsJSbQ6fUaSiEk9c89ACweAwT6/EWkY5Y211Uonx3JBQfEpsNp9Qs6/QjFT+O16 HgozLlmjm6OUqQb3+6nH22wKCGnLJPQqJQwUv2GA8/gLgXIJ0BiW8GFXJZJN+SPnDd2t Dyg+/kaHM1UTgmhc5hAcCkQxw2jZJ7l1RXzLPZy6VYlE4MDeVUNkPNoDRstWIAZBHvCa uDUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688114452; x=1690706452; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xmbgD3BkRBunB0DFWSt+ANLkIPsXQvCtttyk0nyN3eI=; b=ke+G73PGhvQoeq5fUzBfQs9UwN/fAIkPUAtmI59thLszNES1pqq2R7upcLgEKjE8N0 Q7mPlRKkw5e6+Mhd4lPP8ti+k11zHY19uV+wr+gFW45QkfdoyhGwqQy6E6tBuUz3UQag J7BWvTvVOSR8mwqXtiFFTnwe5LrbG0vG+hA34A8wM+rbBlhi1W9XxTrJp4Q7qPIuCD5U ekgsUR/sHJhcdy5xumpySYItLpb0mAXbsLiKPEW0f2oJ46XCG3imh8U8ytb4ibr1xGOc W4XRkPaGt9J+Bsqem0caTBqR2vMxnzLoB+xE4MncImHG6D0e2UurIBB6lg6QiUe16/pr th/Q== X-Gm-Message-State: ABy/qLbiU5fpFnZv+nv6ewGazBAScXhYhyqL6Ak1uA8Q9ycEQPYUUrkg rp6bv3Rf3ntkLeKI9ylTk6sCzQ== X-Google-Smtp-Source: APBJJlGdPg2iyQ/a+BDt1aLZTv0Yk22uI/nygPWAvXy7YUewA8v5fcDT/TyEnCnUoiJVNGcrcvKwnQ== X-Received: by 2002:a5d:4ac2:0:b0:313:e161:d013 with SMTP id y2-20020a5d4ac2000000b00313e161d013mr1634786wrs.15.1688114452123; Fri, 30 Jun 2023 01:40:52 -0700 (PDT) Received: from alex-rivos.ba.rivosinc.com (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id x2-20020a5d54c2000000b003142439c7bcsm740391wrv.80.2023.06.30.01.40.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 01:40:51 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Rob Herring , Andrew Jones , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Cc: Alexandre Ghiti Subject: [PATCH v3 09/10] tools: lib: perf: Implement riscv mmap support Date: Fri, 30 Jun 2023 10:30:12 +0200 Message-Id: <20230630083013.102334-10-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230630083013.102334-1-alexghiti@rivosinc.com> References: <20230630083013.102334-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" riscv now supports mmaping hardware counters so add what's needed to take advantage of that in libperf. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones --- tools/lib/perf/mmap.c | 65 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/tools/lib/perf/mmap.c b/tools/lib/perf/mmap.c index 0d1634cedf44..378a163f0554 100644 --- a/tools/lib/perf/mmap.c +++ b/tools/lib/perf/mmap.c @@ -392,6 +392,71 @@ static u64 read_perf_counter(unsigned int counter) =20 static u64 read_timestamp(void) { return read_sysreg(cntvct_el0); } =20 +#elif __riscv_xlen =3D=3D 64 + +/* TODO: implement rv32 support */ + +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 + +#define csr_read(csr) \ +({ \ + register unsigned long __v; \ + __asm__ __volatile__ ("csrr %0, " #csr \ + : "=3Dr" (__v) : \ + : "memory"); \ + __v; \ +}) + +static unsigned long csr_read_num(int csr_num) +{ +#define switchcase_csr_read(__csr_num, __val) {\ + case __csr_num: \ + __val =3D csr_read(__csr_num); \ + break; } +#define switchcase_csr_read_2(__csr_num, __val) {\ + switchcase_csr_read(__csr_num + 0, __val) \ + switchcase_csr_read(__csr_num + 1, __val)} +#define switchcase_csr_read_4(__csr_num, __val) {\ + switchcase_csr_read_2(__csr_num + 0, __val) \ + switchcase_csr_read_2(__csr_num + 2, __val)} +#define switchcase_csr_read_8(__csr_num, __val) {\ + switchcase_csr_read_4(__csr_num + 0, __val) \ + switchcase_csr_read_4(__csr_num + 4, __val)} +#define switchcase_csr_read_16(__csr_num, __val) {\ + switchcase_csr_read_8(__csr_num + 0, __val) \ + switchcase_csr_read_8(__csr_num + 8, __val)} +#define switchcase_csr_read_32(__csr_num, __val) {\ + switchcase_csr_read_16(__csr_num + 0, __val) \ + switchcase_csr_read_16(__csr_num + 16, __val)} + + unsigned long ret =3D 0; + + switch (csr_num) { + switchcase_csr_read_32(CSR_CYCLE, ret) + default: + break; + } + + return ret; +#undef switchcase_csr_read_32 +#undef switchcase_csr_read_16 +#undef switchcase_csr_read_8 +#undef switchcase_csr_read_4 +#undef switchcase_csr_read_2 +#undef switchcase_csr_read +} + +static u64 read_perf_counter(unsigned int counter) +{ + return csr_read_num(CSR_CYCLE + counter); +} + +static u64 read_timestamp(void) +{ + return csr_read_num(CSR_TIME); +} + #else static u64 read_perf_counter(unsigned int counter __maybe_unused) { return= 0; } static u64 read_timestamp(void) { return 0; } --=20 2.39.2 From nobody Sun Feb 8 23:06:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F40EEC0015E for ; Fri, 30 Jun 2023 08:42:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232730AbjF3Ims (ORCPT ); Fri, 30 Jun 2023 04:42:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232738AbjF3ImT (ORCPT ); Fri, 30 Jun 2023 04:42:19 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C31B3C04 for ; Fri, 30 Jun 2023 01:41:55 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-4faaaa476a9so2625483e87.2 for ; Fri, 30 Jun 2023 01:41:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1688114513; x=1690706513; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uDd0P6Z6Y37kRPaqqHaNAC3kQrjxk6Pu8HaK2zooeKg=; b=Y41VrW8/WSTU5UZ0jha3wwL0Ej0Tqd3A2qkgrwAyZodUC/Uz8mWxFXPieMXCL9Qgkc aCxnf9L5pPkNT/eeVpj05gNJZy/aSu0i+l4K1alIFaVSt15uuOkO1E6tqT2Jw85snBkt eBMVD67kXwSAZmYJxN6xoMJp0H+pOyoW3QN4+hUahcRJSus8PGYrRNm9+d7On6kDNC7b g3jjB7S7COhraUHuWtlOaXR0UlBpzLL2bWINQ2J4KfkEAXDJXOOk2OggifnX6rcvyHeG nXSybsUY3tIMMztv3/UeobmrRZ0vqFQvg+NAjIoAuQfRago5a4TDxH3y3gIH4MfF24+s PliA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688114513; x=1690706513; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uDd0P6Z6Y37kRPaqqHaNAC3kQrjxk6Pu8HaK2zooeKg=; b=aeIhEgUTBHfeX0DU3rGbUNQ01QdhC/NQ8uPogl3KJN6pL1nccwn7riT+WbJvJLtJc3 goehSyghyAfR4j8fA3+6DqDxZn8Pvo5/KuUfI/sm43MZbbevj6hlOD7KzM6bYSFwqnjX mPWQgUFW7IWSTbzTEMlL2GnVhBRc3BZjRQvzP0U9J5oLeZOtpu8yN4Lrlii+VtkCHz2o s05681n1fk51qpfIiSHT4Eoq7GfhYiUmms/bJTSodDOHwfwbvZaroO+9lyxSp+rgqMH4 g99cuoHYNHg2pWTFvBCV76q3iHR0zNkgpQOjiehpLdoZ80mC0oJO+Z37UN633XgAY/V8 LIXg== X-Gm-Message-State: ABy/qLbxhxfeWLzhJtGeRs8ude2+02rpAgBj7GVV0AokZiLKRLTYzGSE z5djh+yd3lv72p1eJChc5dy1Bg== X-Google-Smtp-Source: APBJJlH7485mFBkMkfiINnyjXjrffdesyhHF/v8B35gqPVeTtnbEfcY+mPVgYOVbdZDlPoNQQNysmg== X-Received: by 2002:a19:8c19:0:b0:4f1:4cdc:ec03 with SMTP id o25-20020a198c19000000b004f14cdcec03mr1476845lfd.18.1688114513557; Fri, 30 Jun 2023 01:41:53 -0700 (PDT) Received: from alex-rivos.ba.rivosinc.com (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id v11-20020adff68b000000b0031424950a99sm649850wrp.81.2023.06.30.01.41.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 01:41:53 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Will Deacon , Rob Herring , Andrew Jones , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Cc: Alexandre Ghiti Subject: [PATCH v3 10/10] perf: tests: Adapt mmap-basic.c for riscv Date: Fri, 30 Jun 2023 10:30:13 +0200 Message-Id: <20230630083013.102334-11-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230630083013.102334-1-alexghiti@rivosinc.com> References: <20230630083013.102334-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" riscv now supports mmaping hardware counters to userspace so adapt the test to run on this architecture. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones --- tools/perf/tests/mmap-basic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/perf/tests/mmap-basic.c b/tools/perf/tests/mmap-basic.c index e68ca6229756..f5075ca774f8 100644 --- a/tools/perf/tests/mmap-basic.c +++ b/tools/perf/tests/mmap-basic.c @@ -284,7 +284,7 @@ static struct test_case tests__basic_mmap[] =3D { "permissions"), TEST_CASE_REASON("User space counter reading of instructions", mmap_user_read_instr, -#if defined(__i386__) || defined(__x86_64__) || defined(__aarch64__) +#if defined(__i386__) || defined(__x86_64__) || defined(__aarch64__) || __= riscv_xlen =3D=3D 64 "permissions" #else "unsupported" @@ -292,7 +292,7 @@ static struct test_case tests__basic_mmap[] =3D { ), TEST_CASE_REASON("User space counter reading of cycles", mmap_user_read_cycles, -#if defined(__i386__) || defined(__x86_64__) || defined(__aarch64__) +#if defined(__i386__) || defined(__x86_64__) || defined(__aarch64__) || __= riscv_xlen =3D=3D 64 "permissions" #else "unsupported" --=20 2.39.2