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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT025.mail.protection.outlook.com (10.13.172.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6500.49 via Frontend Transport; Fri, 30 Jun 2023 05:39:13 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Fri, 30 Jun 2023 00:38:54 -0500 Received: from xhdsneeli40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Fri, 30 Jun 2023 00:38:50 -0500 From: Sarath Babu Naidu Gaddam To: , , , , , CC: , , , , , , , , , , , Subject: [PATCH net-next V4 1/3] dt-bindings: net: xlnx,axi-ethernet: Introduce DMA support Date: Fri, 30 Jun 2023 11:08:42 +0530 Message-ID: <20230630053844.1366171-2-sarath.babu.naidu.gaddam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230630053844.1366171-1-sarath.babu.naidu.gaddam@amd.com> References: <20230630053844.1366171-1-sarath.babu.naidu.gaddam@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT025:EE_|BN9PR12MB5227:EE_ X-MS-Office365-Filtering-Correlation-Id: 67bed9fa-1f78-44fa-f8f6-08db792c55ff X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2023 05:39:13.0636 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 67bed9fa-1f78-44fa-f8f6-08db792c55ff X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5227 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Radhey Shyam Pandey The axiethernet will use dmaengine framework to communicate with dma controller IP instead of built-in dma programming sequence. To request dma transmit and receive channels the axiethernet uses generic dmas, dma-names properties. Axiethernet may use AXI DMA or MCDMA. DMA has only two channels where as MCDMA has 16 Tx, 16 Rx channels. To uniquely identify each channel, we are using 'chan' suffix. Depending on the usecase AXI ethernet driver can request any combination of multichannel DMA channels. Example: dma-names =3D tx_chan0, rx_chan0, tx_chan1, rx_chan1; Also to support the backward compatibility, use "dmas" property to identify as it should use dmaengine framework or legacy driver(built-in dma programming). At this point it is recommended to use dmaengine framework but it's optional. Once the solution is stable will make dmas as required properties. Signed-off-by: Radhey Shyam Pandey Signed-off-by: Sarath Babu Naidu Gaddam --- Changes in V4: 1) Updated commit description about tx/rx channels name. 2) Removed "dt-bindings" and "dmaengine" strings in subject. 3) Extended dmas and dma-names to support MCDMA channel names. 1) Remove "driver" from commit message. 2) Use pattern/regex for dma-names property. Changes in V3: 1) Reverted reg and interrupts property to support backward compatibility. 2) Moved dmas and dma-names properties from Required properties. Changes in V2: - None. --- .../bindings/net/xlnx,axi-ethernet.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml b= /Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml index 1d33d80af11c..ea203504b8d4 100644 --- a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml +++ b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml @@ -122,6 +122,20 @@ properties: and "phy-handle" should point to an external PHY if exists. maxItems: 1 =20 + dmas: + minItems: 2 + maxItems: 32 + description: DMA Channel phandle and DMA request line number + + dma-names: + items: + pattern: "^[tr]x_chan[0-9]|1[0-5]$" + description: + Should be "tx_chan0", "tx_chan1" ... "tx_chan15" for DMA Tx channel + Should be "rx_chan0", "rx_chan1" ... "rx_chan15" for DMA Rx channel + minItems: 2 + maxItems: 32 + required: - compatible - interrupts @@ -143,6 +157,8 @@ examples: clocks =3D <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>; phy-mode =3D "mii"; reg =3D <0x40c00000 0x40000>,<0x50c00000 0x40000>; + dmas =3D <&xilinx_dma 0>, <&xilinx_dma 1>; + dma-names =3D "tx_chan0", "rx_chan0"; xlnx,rxcsum =3D <0x2>; xlnx,rxmem =3D <0x800>; xlnx,txcsum =3D <0x2>; --=20 2.25.1 From nobody Mon Feb 9 07:44:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7678EB64DA for ; Fri, 30 Jun 2023 05:41:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232174AbjF3FlV (ORCPT ); Fri, 30 Jun 2023 01:41:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230309AbjF3FlN (ORCPT ); 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Fri, 30 Jun 2023 00:39:00 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Fri, 30 Jun 2023 00:38:59 -0500 Received: from xhdsneeli40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Fri, 30 Jun 2023 00:38:55 -0500 From: Sarath Babu Naidu Gaddam To: , , , , , CC: , , , , , , , , , , , Subject: [PATCH net-next V4 2/3] net: axienet: Preparatory changes for dmaengine support Date: Fri, 30 Jun 2023 11:08:43 +0530 Message-ID: <20230630053844.1366171-3-sarath.babu.naidu.gaddam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230630053844.1366171-1-sarath.babu.naidu.gaddam@amd.com> References: <20230630053844.1366171-1-sarath.babu.naidu.gaddam@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT068:EE_|CH2PR12MB4889:EE_ X-MS-Office365-Filtering-Correlation-Id: 0315422e-222a-4627-0306-08db792c5070 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2023 05:39:03.7315 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0315422e-222a-4627-0306-08db792c5070 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT068.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4889 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The axiethernet driver has in-built dma programming. The aim is to remove axiethernet axidma programming after some time and instead use the dmaengine framework to communicate with existing xilinx DMAengine controller(xilinx_dma) driver. Keep the axidma programming code under use_dmaengine check so that dmaengine changes can be added later. Perform minor code reordering to minimize conditional use_dmaengine checks and there is no functional change. It uses "dmas" property to identify whether it should use a dmaengine framework or axiethernet axidma programming. Signed-off-by: Sarath Babu Naidu Gaddam --- Changes in V4: 1) Renamed has_dmas to use_dmaegine. 2) Removed the AXIENET_USE_DMA. 1) Changed the start_xmit_** functions description. Changes in V3: 1) New patch --- drivers/net/ethernet/xilinx/xilinx_axienet.h | 2 + .../net/ethernet/xilinx/xilinx_axienet_main.c | 317 +++++++++++------- 2 files changed, 191 insertions(+), 128 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/eth= ernet/xilinx/xilinx_axienet.h index 575ff9de8985..3ead0bac597b 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h @@ -435,6 +435,7 @@ struct axidma_bd { * @coalesce_usec_rx: IRQ coalesce delay for RX * @coalesce_count_tx: Store the irq coalesce on TX side. * @coalesce_usec_tx: IRQ coalesce delay for TX + * @use_dmaengine: flag to check dmaengine framework usage. */ struct axienet_local { struct net_device *ndev; @@ -499,6 +500,7 @@ struct axienet_local { u32 coalesce_usec_rx; u32 coalesce_count_tx; u32 coalesce_usec_tx; + u8 use_dmaengine; }; =20 /** diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/ne= t/ethernet/xilinx/xilinx_axienet_main.c index 3e310b55bce2..1fa67bb09625 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -588,10 +588,6 @@ static int axienet_device_reset(struct net_device *nde= v) struct axienet_local *lp =3D netdev_priv(ndev); int ret; =20 - ret =3D __axienet_device_reset(lp); - if (ret) - return ret; - lp->max_frm_size =3D XAE_MAX_VLAN_FRAME_SIZE; lp->options |=3D XAE_OPTION_VLAN; lp->options &=3D (~XAE_OPTION_JUMBO); @@ -605,11 +601,17 @@ static int axienet_device_reset(struct net_device *nd= ev) lp->options |=3D XAE_OPTION_JUMBO; } =20 - ret =3D axienet_dma_bd_init(ndev); - if (ret) { - netdev_err(ndev, "%s: descriptor allocation failed\n", - __func__); - return ret; + if (!lp->use_dmaengine) { + ret =3D __axienet_device_reset(lp); + if (ret) + return ret; + + ret =3D axienet_dma_bd_init(ndev); + if (ret) { + netdev_err(ndev, "%s: descriptor allocation failed\n", + __func__); + return ret; + } } =20 axienet_status =3D axienet_ior(lp, XAE_RCW1_OFFSET); @@ -775,20 +777,20 @@ static int axienet_tx_poll(struct napi_struct *napi, = int budget) } =20 /** - * axienet_start_xmit - Starts the transmission. + * axienet_start_xmit_legacy - Starts the transmission. * @skb: sk_buff pointer that contains data to be Txed. * @ndev: Pointer to net_device structure. * * Return: NETDEV_TX_OK, on success * NETDEV_TX_BUSY, if any of the descriptors are not free * - * This function is invoked from upper layers to initiate transmission. The + * This function is invoked from axienet_start_xmit to initiate transmissi= on. The * function uses the next available free BDs and populates their fields to * start the transmission. Additionally if checksum offloading is supporte= d, * it populates AXI Stream Control fields with appropriate values. */ static netdev_tx_t -axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev) +axienet_start_xmit_legacy(struct sk_buff *skb, struct net_device *ndev) { u32 ii; u32 num_frag; @@ -890,6 +892,27 @@ axienet_start_xmit(struct sk_buff *skb, struct net_dev= ice *ndev) return NETDEV_TX_OK; } =20 +/** + * axienet_start_xmit - Invoke the transmission function + * @skb: sk_buff pointer that contains data to be Txed. + * @ndev: Pointer to net_device structure. + * + * Return: NETDEV_TX_OK, on success + * NETDEV_TX_BUSY, if any of the descriptors are not free + * + * This function is invoked from upper layers to initiate transmission + */ +static netdev_tx_t +axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev) +{ + struct axienet_local *lp =3D netdev_priv(ndev); + + if (!lp->use_dmaengine) + return axienet_start_xmit_legacy(skb, ndev); + else + return NETDEV_TX_BUSY; +} + /** * axienet_rx_poll - Triggered by RX ISR to complete the BD processing. * @napi: Pointer to NAPI structure. @@ -1124,41 +1147,22 @@ static irqreturn_t axienet_eth_irq(int irq, void *_= ndev) static void axienet_dma_err_handler(struct work_struct *work); =20 /** - * axienet_open - Driver open routine. - * @ndev: Pointer to net_device structure + * axienet_init_legacy_dma - init the dma legacy code. + * @ndev: Pointer to net_device structure * * Return: 0, on success. - * non-zero error value on failure + * non-zero error value on failure + * + * This is the dma initialization code. It also allocates interrupt + * service routines, enables the interrupt lines and ISR handling. * - * This is the driver open routine. It calls phylink_start to start the - * PHY device. - * It also allocates interrupt service routines, enables the interrupt lin= es - * and ISR handling. Axi Ethernet core is reset through Axi DMA core. Buff= er - * descriptors are initialized. */ -static int axienet_open(struct net_device *ndev) + +static inline int axienet_init_legacy_dma(struct net_device *ndev) { int ret; struct axienet_local *lp =3D netdev_priv(ndev); =20 - dev_dbg(&ndev->dev, "axienet_open()\n"); - - /* When we do an Axi Ethernet reset, it resets the complete core - * including the MDIO. MDIO must be disabled before resetting. - * Hold MDIO bus lock to avoid MDIO accesses during the reset. - */ - axienet_lock_mii(lp); - ret =3D axienet_device_reset(ndev); - axienet_unlock_mii(lp); - - ret =3D phylink_of_phy_connect(lp->phylink, lp->dev->of_node, 0); - if (ret) { - dev_err(lp->dev, "phylink_of_phy_connect() failed: %d\n", ret); - return ret; - } - - phylink_start(lp->phylink); - /* Enable worker thread for Axi DMA error handling */ INIT_WORK(&lp->dma_err_task, axienet_dma_err_handler); =20 @@ -1192,13 +1196,62 @@ static int axienet_open(struct net_device *ndev) err_tx_irq: napi_disable(&lp->napi_tx); napi_disable(&lp->napi_rx); - phylink_stop(lp->phylink); - phylink_disconnect_phy(lp->phylink); cancel_work_sync(&lp->dma_err_task); dev_err(lp->dev, "request_irq() failed\n"); return ret; } =20 +/** + * axienet_open - Driver open routine. + * @ndev: Pointer to net_device structure + * + * Return: 0, on success. + * non-zero error value on failure + * + * This is the driver open routine. It calls phylink_start to start the + * PHY device. + * It also allocates interrupt service routines, enables the interrupt lin= es + * and ISR handling. Axi Ethernet core is reset through Axi DMA core. Buff= er + * descriptors are initialized. + */ +static int axienet_open(struct net_device *ndev) +{ + int ret; + struct axienet_local *lp =3D netdev_priv(ndev); + + dev_dbg(&ndev->dev, "%s\n", __func__); + + /* When we do an Axi Ethernet reset, it resets the complete core + * including the MDIO. MDIO must be disabled before resetting. + * Hold MDIO bus lock to avoid MDIO accesses during the reset. + */ + axienet_lock_mii(lp); + ret =3D axienet_device_reset(ndev); + axienet_unlock_mii(lp); + + ret =3D phylink_of_phy_connect(lp->phylink, lp->dev->of_node, 0); + if (ret) { + dev_err(lp->dev, "phylink_of_phy_connect() failed: %d\n", ret); + return ret; + } + + phylink_start(lp->phylink); + + if (!lp->use_dmaengine) { + ret =3D axienet_init_legacy_dma(ndev); + if (ret) + goto error_code; + } + + return 0; + +error_code: + phylink_stop(lp->phylink); + phylink_disconnect_phy(lp->phylink); + + return ret; +} + /** * axienet_stop - Driver stop routine. * @ndev: Pointer to net_device structure @@ -1215,8 +1268,10 @@ static int axienet_stop(struct net_device *ndev) =20 dev_dbg(&ndev->dev, "axienet_close()\n"); =20 - napi_disable(&lp->napi_tx); - napi_disable(&lp->napi_rx); + if (!lp->use_dmaengine) { + napi_disable(&lp->napi_tx); + napi_disable(&lp->napi_rx); + } =20 phylink_stop(lp->phylink); phylink_disconnect_phy(lp->phylink); @@ -1224,18 +1279,18 @@ static int axienet_stop(struct net_device *ndev) axienet_setoptions(ndev, lp->options & ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN)); =20 - axienet_dma_stop(lp); + if (!lp->use_dmaengine) { + axienet_dma_stop(lp); + cancel_work_sync(&lp->dma_err_task); + free_irq(lp->tx_irq, ndev); + free_irq(lp->rx_irq, ndev); + axienet_dma_bd_release(ndev); + } =20 axienet_iow(lp, XAE_IE_OFFSET, 0); =20 - cancel_work_sync(&lp->dma_err_task); - if (lp->eth_irq > 0) free_irq(lp->eth_irq, ndev); - free_irq(lp->tx_irq, ndev); - free_irq(lp->rx_irq, ndev); - - axienet_dma_bd_release(ndev); return 0; } =20 @@ -1411,14 +1466,16 @@ static void axienet_ethtools_get_regs(struct net_de= vice *ndev, data[29] =3D axienet_ior(lp, XAE_FMI_OFFSET); data[30] =3D axienet_ior(lp, XAE_AF0_OFFSET); data[31] =3D axienet_ior(lp, XAE_AF1_OFFSET); - data[32] =3D axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); - data[33] =3D axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET); - data[34] =3D axienet_dma_in32(lp, XAXIDMA_TX_CDESC_OFFSET); - data[35] =3D axienet_dma_in32(lp, XAXIDMA_TX_TDESC_OFFSET); - data[36] =3D axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); - data[37] =3D axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET); - data[38] =3D axienet_dma_in32(lp, XAXIDMA_RX_CDESC_OFFSET); - data[39] =3D axienet_dma_in32(lp, XAXIDMA_RX_TDESC_OFFSET); + if (!lp->use_dmaengine) { + data[32] =3D axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); + data[33] =3D axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET); + data[34] =3D axienet_dma_in32(lp, XAXIDMA_TX_CDESC_OFFSET); + data[35] =3D axienet_dma_in32(lp, XAXIDMA_TX_TDESC_OFFSET); + data[36] =3D axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); + data[37] =3D axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET); + data[38] =3D axienet_dma_in32(lp, XAXIDMA_RX_CDESC_OFFSET); + data[39] =3D axienet_dma_in32(lp, XAXIDMA_RX_TDESC_OFFSET); + } } =20 static void @@ -1878,9 +1935,6 @@ static int axienet_probe(struct platform_device *pdev) u64_stats_init(&lp->rx_stat_sync); u64_stats_init(&lp->tx_stat_sync); =20 - netif_napi_add(ndev, &lp->napi_rx, axienet_rx_poll); - netif_napi_add(ndev, &lp->napi_tx, axienet_tx_poll); - lp->axi_clk =3D devm_clk_get_optional(&pdev->dev, "s_axi_lite_clk"); if (!lp->axi_clk) { /* For backward compatibility, if named AXI clock is not present, @@ -2006,75 +2060,80 @@ static int axienet_probe(struct platform_device *pd= ev) goto cleanup_clk; } =20 - /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */ - np =3D of_parse_phandle(pdev->dev.of_node, "axistream-connected", 0); - if (np) { - struct resource dmares; + if (!of_find_property(pdev->dev.of_node, "dmas", NULL)) { + /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */ + np =3D of_parse_phandle(pdev->dev.of_node, "axistream-connected", 0); =20 - ret =3D of_address_to_resource(np, 0, &dmares); - if (ret) { - dev_err(&pdev->dev, - "unable to get DMA resource\n"); + if (np) { + struct resource dmares; + + ret =3D of_address_to_resource(np, 0, &dmares); + if (ret) { + dev_err(&pdev->dev, + "unable to get DMA resource\n"); + of_node_put(np); + goto cleanup_clk; + } + lp->dma_regs =3D devm_ioremap_resource(&pdev->dev, + &dmares); + lp->rx_irq =3D irq_of_parse_and_map(np, 1); + lp->tx_irq =3D irq_of_parse_and_map(np, 0); of_node_put(np); + lp->eth_irq =3D platform_get_irq_optional(pdev, 0); + } else { + /* Check for these resources directly on the Ethernet node. */ + lp->dma_regs =3D devm_platform_get_and_ioremap_resource(pdev, 1, NULL); + lp->rx_irq =3D platform_get_irq(pdev, 1); + lp->tx_irq =3D platform_get_irq(pdev, 0); + lp->eth_irq =3D platform_get_irq_optional(pdev, 2); + } + if (IS_ERR(lp->dma_regs)) { + dev_err(&pdev->dev, "could not map DMA regs\n"); + ret =3D PTR_ERR(lp->dma_regs); + goto cleanup_clk; + } + if (lp->rx_irq <=3D 0 || lp->tx_irq <=3D 0) { + dev_err(&pdev->dev, "could not determine irqs\n"); + ret =3D -ENOMEM; goto cleanup_clk; } - lp->dma_regs =3D devm_ioremap_resource(&pdev->dev, - &dmares); - lp->rx_irq =3D irq_of_parse_and_map(np, 1); - lp->tx_irq =3D irq_of_parse_and_map(np, 0); - of_node_put(np); - lp->eth_irq =3D platform_get_irq_optional(pdev, 0); - } else { - /* Check for these resources directly on the Ethernet node. */ - lp->dma_regs =3D devm_platform_get_and_ioremap_resource(pdev, 1, NULL); - lp->rx_irq =3D platform_get_irq(pdev, 1); - lp->tx_irq =3D platform_get_irq(pdev, 0); - lp->eth_irq =3D platform_get_irq_optional(pdev, 2); - } - if (IS_ERR(lp->dma_regs)) { - dev_err(&pdev->dev, "could not map DMA regs\n"); - ret =3D PTR_ERR(lp->dma_regs); - goto cleanup_clk; - } - if ((lp->rx_irq <=3D 0) || (lp->tx_irq <=3D 0)) { - dev_err(&pdev->dev, "could not determine irqs\n"); - ret =3D -ENOMEM; - goto cleanup_clk; - } =20 - /* Autodetect the need for 64-bit DMA pointers. - * When the IP is configured for a bus width bigger than 32 bits, - * writing the MSB registers is mandatory, even if they are all 0. - * We can detect this case by writing all 1's to one such register - * and see if that sticks: when the IP is configured for 32 bits - * only, those registers are RES0. - * Those MSB registers were introduced in IP v7.1, which we check first. - */ - if ((axienet_ior(lp, XAE_ID_OFFSET) >> 24) >=3D 0x9) { - void __iomem *desc =3D lp->dma_regs + XAXIDMA_TX_CDESC_OFFSET + 4; - - iowrite32(0x0, desc); - if (ioread32(desc) =3D=3D 0) { /* sanity check */ - iowrite32(0xffffffff, desc); - if (ioread32(desc) > 0) { - lp->features |=3D XAE_FEATURE_DMA_64BIT; - addr_width =3D 64; - dev_info(&pdev->dev, - "autodetected 64-bit DMA range\n"); - } + /* Autodetect the need for 64-bit DMA pointers. + * When the IP is configured for a bus width bigger than 32 bits, + * writing the MSB registers is mandatory, even if they are all 0. + * We can detect this case by writing all 1's to one such register + * and see if that sticks: when the IP is configured for 32 bits + * only, those registers are RES0. + * Those MSB registers were introduced in IP v7.1, which we check first. + */ + if ((axienet_ior(lp, XAE_ID_OFFSET) >> 24) >=3D 0x9) { + void __iomem *desc =3D lp->dma_regs + XAXIDMA_TX_CDESC_OFFSET + 4; + iowrite32(0x0, desc); + if (ioread32(desc) =3D=3D 0) { /* sanity check */ + iowrite32(0xffffffff, desc); + if (ioread32(desc) > 0) { + lp->features |=3D XAE_FEATURE_DMA_64BIT; + addr_width =3D 64; + dev_info(&pdev->dev, + "autodetected 64-bit DMA range\n"); + } + iowrite32(0x0, desc); + } + } + if (!IS_ENABLED(CONFIG_64BIT) && lp->features & XAE_FEATURE_DMA_64BIT) { + dev_err(&pdev->dev, "64-bit addressable DMA is not compatible with 32-b= it archecture\n"); + ret =3D -EINVAL; + goto cleanup_clk; } - } - if (!IS_ENABLED(CONFIG_64BIT) && lp->features & XAE_FEATURE_DMA_64BIT) { - dev_err(&pdev->dev, "64-bit addressable DMA is not compatible with 32-bi= t archecture\n"); - ret =3D -EINVAL; - goto cleanup_clk; - } =20 - ret =3D dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_width)); - if (ret) { - dev_err(&pdev->dev, "No suitable DMA available\n"); - goto cleanup_clk; + ret =3D dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_width)); + if (ret) { + dev_err(&pdev->dev, "No suitable DMA available\n"); + goto cleanup_clk; + } + netif_napi_add(ndev, &lp->napi_rx, axienet_rx_poll); + netif_napi_add(ndev, &lp->napi_tx, axienet_tx_poll); } =20 /* Check for Ethernet core IRQ (optional) */ @@ -2092,14 +2151,16 @@ static int axienet_probe(struct platform_device *pd= ev) } =20 lp->coalesce_count_rx =3D XAXIDMA_DFT_RX_THRESHOLD; - lp->coalesce_usec_rx =3D XAXIDMA_DFT_RX_USEC; lp->coalesce_count_tx =3D XAXIDMA_DFT_TX_THRESHOLD; - lp->coalesce_usec_tx =3D XAXIDMA_DFT_TX_USEC; =20 - /* Reset core now that clocks are enabled, prior to accessing MDIO */ - ret =3D __axienet_device_reset(lp); - if (ret) - goto cleanup_clk; + if (!lp->use_dmaengine) { + lp->coalesce_usec_rx =3D XAXIDMA_DFT_RX_USEC; + lp->coalesce_usec_tx =3D XAXIDMA_DFT_TX_USEC; + /* Reset core now that clocks are enabled, prior to accessing MDIO */ + ret =3D __axienet_device_reset(lp); + if (ret) + goto cleanup_clk; + } =20 ret =3D axienet_mdio_setup(lp); if (ret) --=20 2.25.1 From nobody Mon Feb 9 07:44:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D6B1EB64D7 for ; Fri, 30 Jun 2023 05:41:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232113AbjF3Fld (ORCPT ); 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Fri, 30 Jun 2023 00:39:00 -0500 From: Sarath Babu Naidu Gaddam To: , , , , , CC: , , , , , , , , , , , Subject: [PATCH net-next V4 3/3] net: axienet: Introduce dmaengine support Date: Fri, 30 Jun 2023 11:08:44 +0530 Message-ID: <20230630053844.1366171-4-sarath.babu.naidu.gaddam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230630053844.1366171-1-sarath.babu.naidu.gaddam@amd.com> References: <20230630053844.1366171-1-sarath.babu.naidu.gaddam@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT084:EE_|SJ0PR12MB8614:EE_ X-MS-Office365-Filtering-Correlation-Id: ad3adf12-9f3a-40c5-fb50-08db792c575e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RxriUZKX0Q5wda1mfUXe2jUYLifgv3fbW2X7NpwYmwTw53XZ+f2YHysJwYbltyKpKdNCR1fGZ4YlY6nRXWi5z3hkZ9dEHIoNPB4U4fV2OFJNi3/7c6QFad+exhzjRR9jTS9wVmZlmecaOEL/TW9zWl9+4YOPbB7BpTE9GMKLXKir/Y5qSdl7K1tuyXr7vOVCj7xXrJ2CXkPPd/+QW+D/s87zyKY+tQ7vh4buwcLxQwmmx9nVnXeANwBk507n/F0zEPXAtckSHahSJ+qbBwx+Xst+N+nqjxZ5ceIFu0FoiAp9CAZrgZns9Wq+4NBISh7luhv7VKSAirxqtejQ6n+0/B5U2f9IOz5DDznK5g8zCOYqO/Cq1adnZ5AvOvoIOZGgjGn3e+pavYtSQYR/vUVoat0zIu9gsSLPlwzaB03KqU+HUqs4cI7Nghtt/PKglFCsDQwh+vs8JpB3jsef++rPJ4vyDlWm8IUQYlPHfAa/c9Td83eX4Bi+FipE1RpnVUvrAA3sfnKVz645eAhNtKHPs1hQFfSeSCbvK8Z1hjw5y1U82ldyfLmqPCqTL8bI+6ENfRTFvNWwSssCWV/AS0dyfeRMlpAz8s9bxcxA1gy+WwXlqGlhfqIpkjGOVvqYWrxJG6CGmElo447Q6/V9JkSWkLek8Tip5Vdxyg3aLRbWE8VQ1ibSCSRSpjZMY/+4guyWSzkPvSbKoMQcZNWALUl30olVpJWpHNa/4J6TaUnybaVVmVU3HHbbm5JCt7ipZoCQ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(396003)(39860400002)(346002)(136003)(451199021)(36840700001)(40470700004)(46966006)(26005)(4326008)(82310400005)(8936002)(36860700001)(966005)(110136005)(2616005)(478600001)(1076003)(336012)(54906003)(426003)(2906002)(6666004)(83380400001)(186003)(356005)(103116003)(30864003)(70206006)(7416002)(47076005)(36756003)(82740400003)(81166007)(40480700001)(70586007)(5660300002)(86362001)(40460700003)(8676002)(41300700001)(316002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2023 05:39:15.3484 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ad3adf12-9f3a-40c5-fb50-08db792c575e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT084.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB8614 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add dmaengine framework to communicate with the xilinx DMAengine driver(AXIDMA). Axi ethernet driver uses separate channels for transmit and receive. Add support for these channels to handle TX and RX with skb and appropriate callbacks. Also add axi ethernet core interrupt for dmaengine framework support. The dmaengine framework was extended for metadata API support during the axidma RFC[1] discussion. However it still needs further enhancements to make it well suited for ethernet usecases. The ethernet features i.e ethtool set/get of DMA IP properties, ndo_poll_controller,(mentioned in TODO) and it requires follow-up discussion and dma framework enhancement. Introducing dmaengine support has a dependency on xilinx_dma. It uses one of xilinx_dma API to reset the DMA. DMA needs to be reset prior to accessing MDIO. [1]: https://lore.kernel.org/lkml/1522665546-10035-1-git-send-email- radheys@xilinx.com Signed-off-by: Radhey Shyam Pandey Signed-off-by: Sarath Babu Naidu Gaddam --- Changes in V4: 1) Remove the AXIENET_USE_DMA. 2) Add dev_err_probe for dma_request_chan error handling. 3) Add kmem_cache_destroy for create in axienet_setup_dma_chan. 4) Add XILINX_DMA dependency in ethernet drier Kconfig file. 5) move setup_dma_channel to init_dmaengine func 6) Remove unlikely if (unlikely(ret < 0)) 7) if (ret =3D=3D 0) to if (!ret) 8) Rename DMA_MEM_TO_DEV to DMA_TO_DEVICE 9) Remove else check for lp->use_dmaengine =3D 1; in the probe. Changes in V3: 1) New patch for dmaengine framework support. --- drivers/net/ethernet/xilinx/Kconfig | 1 + drivers/net/ethernet/xilinx/xilinx_axienet.h | 6 + .../net/ethernet/xilinx/xilinx_axienet_main.c | 309 +++++++++++++++++- 3 files changed, 314 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/xilinx/Kconfig b/drivers/net/ethernet/xil= inx/Kconfig index 0014729b8865..35d96c633a33 100644 --- a/drivers/net/ethernet/xilinx/Kconfig +++ b/drivers/net/ethernet/xilinx/Kconfig @@ -26,6 +26,7 @@ config XILINX_EMACLITE config XILINX_AXI_EMAC tristate "Xilinx 10/100/1000 AXI Ethernet support" depends on HAS_IOMEM + depends on XILINX_DMA select PHYLINK help This driver supports the 10/100/1000 Ethernet from Xilinx for the diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/eth= ernet/xilinx/xilinx_axienet.h index 3ead0bac597b..726c14d1470a 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h @@ -436,6 +436,9 @@ struct axidma_bd { * @coalesce_count_tx: Store the irq coalesce on TX side. * @coalesce_usec_tx: IRQ coalesce delay for TX * @use_dmaengine: flag to check dmaengine framework usage. + * @tx_chan: TX DMA channel. + * @rx_chan: RX DMA channel. + * @skb_cache: Custom skb slab allocator */ struct axienet_local { struct net_device *ndev; @@ -501,6 +504,9 @@ struct axienet_local { u32 coalesce_count_tx; u32 coalesce_usec_tx; u8 use_dmaengine; + struct dma_chan *tx_chan; + struct dma_chan *rx_chan; + struct kmem_cache *skb_cache; }; =20 /** diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/ne= t/ethernet/xilinx/xilinx_axienet_main.c index 1fa67bb09625..ea7321703155 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -37,6 +37,9 @@ #include #include #include +#include +#include +#include =20 #include "xilinx_axienet.h" =20 @@ -46,6 +49,9 @@ #define TX_BD_NUM_MIN (MAX_SKB_FRAGS + 1) #define TX_BD_NUM_MAX 4096 #define RX_BD_NUM_MAX 4096 +#define DMA_NUM_APP_WORDS 5 +#define LEN_APP 4 +#define RX_BUF_NUM_DEFAULT 128 =20 /* Must be shorter than length of ethtool_drvinfo.driver field to fit */ #define DRIVER_NAME "xaxienet" @@ -54,6 +60,16 @@ =20 #define AXIENET_REGS_N 40 =20 +struct axi_skbuff { + struct scatterlist sgl[MAX_SKB_FRAGS + 1]; + struct dma_async_tx_descriptor *desc; + dma_addr_t dma_address; + struct sk_buff *skb; + int sg_len; +} __packed; + +static int axienet_rx_submit_desc(struct net_device *ndev); + /* Match table for of_platform binding */ static const struct of_device_id axienet_of_match[] =3D { { .compatible =3D "xlnx,axi-ethernet-1.00.a", }, @@ -726,6 +742,108 @@ static inline int axienet_check_tx_bd_space(struct ax= ienet_local *lp, return 0; } =20 +/** + * axienet_dma_tx_cb - DMA engine callback for TX channel. + * @data: Pointer to the axi_skbuff structure + * @result: error reporting through dmaengine_result. + * This function is called by dmaengine driver for TX channel to notify + * that the transmit is done. + */ +static void axienet_dma_tx_cb(void *data, const struct dmaengine_result *r= esult) +{ + struct axi_skbuff *axi_skb =3D data; + + struct net_device *netdev =3D axi_skb->skb->dev; + struct axienet_local *lp =3D netdev_priv(netdev); + + u64_stats_update_begin(&lp->tx_stat_sync); + u64_stats_add(&lp->tx_bytes, axi_skb->skb->len); + u64_stats_add(&lp->tx_packets, 1); + u64_stats_update_end(&lp->tx_stat_sync); + + dma_unmap_sg(lp->dev, axi_skb->sgl, axi_skb->sg_len, DMA_TO_DEVICE); + dev_kfree_skb_any(axi_skb->skb); + kmem_cache_free(lp->skb_cache, axi_skb); +} + +/** + * axienet_start_xmit_dmaengine - Starts the transmission. + * @skb: sk_buff pointer that contains data to be Txed. + * @ndev: Pointer to net_device structure. + * + * Return: NETDEV_TX_OK, on success + * NETDEV_TX_BUSY, if any memory failure or SG error. + * + * This function is invoked from xmit to initiate transmission. The + * function sets the skbs , call back API, SG etc. + * Additionally if checksum offloading is supported, + * it populates AXI Stream Control fields with appropriate values. + */ +static netdev_tx_t +axienet_start_xmit_dmaengine(struct sk_buff *skb, struct net_device *ndev) +{ + struct dma_async_tx_descriptor *dma_tx_desc =3D NULL; + struct axienet_local *lp =3D netdev_priv(ndev); + u32 app[DMA_NUM_APP_WORDS] =3D {0}; + struct axi_skbuff *axi_skb; + u32 csum_start_off; + u32 csum_index_off; + int sg_len; + int ret; + + sg_len =3D skb_shinfo(skb)->nr_frags + 1; + axi_skb =3D kmem_cache_zalloc(lp->skb_cache, GFP_KERNEL); + if (!axi_skb) + return NETDEV_TX_BUSY; + + sg_init_table(axi_skb->sgl, sg_len); + ret =3D skb_to_sgvec(skb, axi_skb->sgl, 0, skb->len); + if (ret < 0) + goto xmit_error_skb_sgvec; + + ret =3D dma_map_sg(lp->dev, axi_skb->sgl, sg_len, DMA_TO_DEVICE); + if (!ret) + goto xmit_error_skb_sgvec; + + /*Fill up app fields for checksum */ + if (skb->ip_summed =3D=3D CHECKSUM_PARTIAL) { + if (lp->features & XAE_FEATURE_FULL_TX_CSUM) { + /* Tx Full Checksum Offload Enabled */ + app[0] |=3D 2; + } else if (lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) { + csum_start_off =3D skb_transport_offset(skb); + csum_index_off =3D csum_start_off + skb->csum_offset; + /* Tx Partial Checksum Offload Enabled */ + app[0] |=3D 1; + app[1] =3D (csum_start_off << 16) | csum_index_off; + } + } else if (skb->ip_summed =3D=3D CHECKSUM_UNNECESSARY) { + app[0] |=3D 2; /* Tx Full Checksum Offload Enabled */ + } + + dma_tx_desc =3D lp->tx_chan->device->device_prep_slave_sg(lp->tx_chan, ax= i_skb->sgl, + sg_len, DMA_MEM_TO_DEV, + DMA_PREP_INTERRUPT, (void *)app); + + if (!dma_tx_desc) + goto xmit_error_prep; + + axi_skb->skb =3D skb; + axi_skb->sg_len =3D sg_len; + dma_tx_desc->callback_param =3D axi_skb; + dma_tx_desc->callback_result =3D axienet_dma_tx_cb; + dmaengine_submit(dma_tx_desc); + dma_async_issue_pending(lp->tx_chan); + + return NETDEV_TX_OK; + +xmit_error_prep: + dma_unmap_sg(lp->dev, axi_skb->sgl, sg_len, DMA_TO_DEVICE); +xmit_error_skb_sgvec: + kmem_cache_free(lp->skb_cache, axi_skb); + return NETDEV_TX_BUSY; +} + /** * axienet_tx_poll - Invoked once a transmit is completed by the * Axi DMA Tx channel. @@ -910,7 +1028,42 @@ axienet_start_xmit(struct sk_buff *skb, struct net_de= vice *ndev) if (!lp->use_dmaengine) return axienet_start_xmit_legacy(skb, ndev); else - return NETDEV_TX_BUSY; + return axienet_start_xmit_dmaengine(skb, ndev); +} + +/** + * axienet_dma_rx_cb - DMA engine callback for RX channel. + * @data: Pointer to the axi_skbuff structure + * @result: error reporting through dmaengine_result. + * This function is called by dmaengine driver for RX channel to notify + * that the packet is received. + */ +static void axienet_dma_rx_cb(void *data, const struct dmaengine_result *r= esult) +{ + struct axi_skbuff *axi_skb =3D data; + struct sk_buff *skb =3D axi_skb->skb; + struct net_device *netdev =3D skb->dev; + struct axienet_local *lp =3D netdev_priv(netdev); + size_t meta_len, meta_max_len, rx_len; + u32 *app; + + app =3D dmaengine_desc_get_metadata_ptr(axi_skb->desc, &meta_len, &meta_= max_len); + dma_unmap_single(lp->dev, axi_skb->dma_address, lp->max_frm_size, + DMA_FROM_DEVICE); + /* TODO: Derive app word index programmatically */ + rx_len =3D (app[LEN_APP] & 0xFFFF); + skb_put(skb, rx_len); + skb->protocol =3D eth_type_trans(skb, netdev); + skb->ip_summed =3D CHECKSUM_NONE; + + netif_rx(skb); + kmem_cache_free(lp->skb_cache, axi_skb); + u64_stats_update_begin(&lp->rx_stat_sync); + u64_stats_add(&lp->rx_packets, 1); + u64_stats_add(&lp->rx_bytes, rx_len); + u64_stats_update_end(&lp->rx_stat_sync); + axienet_rx_submit_desc(netdev); + dma_async_issue_pending(lp->rx_chan); } =20 /** @@ -1146,6 +1299,108 @@ static irqreturn_t axienet_eth_irq(int irq, void *_= ndev) =20 static void axienet_dma_err_handler(struct work_struct *work); =20 +/** + * axienet_rx_submit_desc - Submit the descriptors with required data + * like call backup API, skb buffer.. etc to dmaengine. + * + * @ndev: net_device pointer + * + *Return: 0, on success. + * non-zero error value on failure + */ +static int axienet_rx_submit_desc(struct net_device *ndev) +{ + struct dma_async_tx_descriptor *dma_rx_desc =3D NULL; + struct axienet_local *lp =3D netdev_priv(ndev); + struct axi_skbuff *axi_skb; + struct sk_buff *skb; + dma_addr_t addr; + int ret; + + axi_skb =3D kmem_cache_alloc(lp->skb_cache, GFP_KERNEL); + + if (!axi_skb) + return -ENOMEM; + skb =3D netdev_alloc_skb(ndev, lp->max_frm_size); + if (!skb) { + ret =3D -ENOMEM; + goto rx_bd_init_skb; + } + + sg_init_table(axi_skb->sgl, 1); + addr =3D dma_map_single(lp->dev, skb->data, lp->max_frm_size, DMA_FROM_DE= VICE); + sg_dma_address(axi_skb->sgl) =3D addr; + sg_dma_len(axi_skb->sgl) =3D lp->max_frm_size; + dma_rx_desc =3D dmaengine_prep_slave_sg(lp->rx_chan, axi_skb->sgl, + 1, DMA_DEV_TO_MEM, + DMA_PREP_INTERRUPT); + if (!dma_rx_desc) { + ret =3D -EINVAL; + goto rx_bd_init_prep_sg; + } + + axi_skb->skb =3D skb; + axi_skb->dma_address =3D sg_dma_address(axi_skb->sgl); + axi_skb->desc =3D dma_rx_desc; + dma_rx_desc->callback_param =3D axi_skb; + dma_rx_desc->callback_result =3D axienet_dma_rx_cb; + dmaengine_submit(dma_rx_desc); + + return 0; + +rx_bd_init_prep_sg: + dma_unmap_single(lp->dev, addr, lp->max_frm_size, DMA_FROM_DEVICE); + dev_kfree_skb(skb); +rx_bd_init_skb: + kmem_cache_free(lp->skb_cache, axi_skb); + return ret; +} + +/** + * axienet_init_dmaengine - init the dmaengine code. + * @ndev: Pointer to net_device structure + * + * Return: 0, on success. + * non-zero error value on failure + * + * This is the dmaengine initialization code. + */ +static inline int axienet_init_dmaengine(struct net_device *ndev) +{ + struct axienet_local *lp =3D netdev_priv(ndev); + int i, ret; + + lp->tx_chan =3D dma_request_chan(lp->dev, "tx_chan0"); + if (IS_ERR(lp->tx_chan)) { + ret =3D PTR_ERR(lp->tx_chan); + return dev_err_probe(lp->dev, ret, "No Ethernet DMA (TX) channel found\n= "); + } + + lp->rx_chan =3D dma_request_chan(lp->dev, "rx_chan0"); + if (IS_ERR(lp->rx_chan)) { + ret =3D PTR_ERR(lp->rx_chan); + dev_err_probe(lp->dev, ret, "No Ethernet DMA (RX) channel found\n"); + goto err_dma_request_rx; + } + lp->skb_cache =3D kmem_cache_create("ethernet", sizeof(struct axi_skbuff), + 0, 0, NULL); + if (!lp->skb_cache) { + ret =3D -ENOMEM; + goto err_kmem; + } + /* TODO: Instead of BD_NUM_DEFAULT use runtime support*/ + for (i =3D 0; i < RX_BUF_NUM_DEFAULT; i++) + axienet_rx_submit_desc(ndev); + dma_async_issue_pending(lp->rx_chan); + + return 0; +err_kmem: + dma_release_channel(lp->rx_chan); +err_dma_request_rx: + dma_release_channel(lp->tx_chan); + return ret; +} + /** * axienet_init_legacy_dma - init the dma legacy code. * @ndev: Pointer to net_device structure @@ -1237,7 +1492,24 @@ static int axienet_open(struct net_device *ndev) =20 phylink_start(lp->phylink); =20 - if (!lp->use_dmaengine) { + if (lp->use_dmaengine) { + /* Enable interrupts for Axi Ethernet core (if defined) */ + if (lp->eth_irq > 0) { + ret =3D request_irq(lp->eth_irq, axienet_eth_irq, IRQF_SHARED, + ndev->name, ndev); + if (ret) + goto error_code; + } + + ret =3D axienet_init_dmaengine(ndev); + + if (ret < 0) { + if (lp->eth_irq > 0) + free_irq(lp->eth_irq, ndev); + goto error_code; + } + + } else { ret =3D axienet_init_legacy_dma(ndev); if (ret) goto error_code; @@ -1285,6 +1557,14 @@ static int axienet_stop(struct net_device *ndev) free_irq(lp->tx_irq, ndev); free_irq(lp->rx_irq, ndev); axienet_dma_bd_release(ndev); + } else { + dmaengine_terminate_all(lp->tx_chan); + dmaengine_terminate_all(lp->rx_chan); + + dma_release_channel(lp->rx_chan); + dma_release_channel(lp->tx_chan); + + kmem_cache_destroy(lp->skb_cache); } =20 axienet_iow(lp, XAE_IE_OFFSET, 0); @@ -2134,6 +2414,31 @@ static int axienet_probe(struct platform_device *pde= v) } netif_napi_add(ndev, &lp->napi_rx, axienet_rx_poll); netif_napi_add(ndev, &lp->napi_tx, axienet_tx_poll); + } else { + struct xilinx_vdma_config cfg; + struct dma_chan *tx_chan; + + lp->eth_irq =3D platform_get_irq_optional(pdev, 0); + tx_chan =3D dma_request_chan(lp->dev, "tx_chan0"); + + if (IS_ERR(tx_chan)) { + ret =3D PTR_ERR(tx_chan); + dev_err_probe(lp->dev, ret, "No Ethernet DMA (TX) channel found\n"); + goto cleanup_clk; + } + + cfg.reset =3D 1; + /* As name says VDMA but it has support for DMA channel reset*/ + ret =3D xilinx_vdma_channel_set_config(tx_chan, &cfg); + + if (ret < 0) { + dev_err(&pdev->dev, "Reset channel failed\n"); + dma_release_channel(tx_chan); + goto cleanup_clk; + } + + dma_release_channel(tx_chan); + lp->use_dmaengine =3D 1; } =20 /* Check for Ethernet core IRQ (optional) */ --=20 2.25.1