From nobody Mon Feb 9 10:40:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40935EB64DD for ; Thu, 29 Jun 2023 08:30:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232196AbjF2Iau (ORCPT ); Thu, 29 Jun 2023 04:30:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232613AbjF2IaL (ORCPT ); Thu, 29 Jun 2023 04:30:11 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E17C1991; Thu, 29 Jun 2023 01:29:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1688027398; x=1719563398; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=K/3KO+Sn7iAB26kNDVGJP0twzMITJyOfWkzd9A2nZjo=; b=Z5RrB10osG7RXQ4YCqwFl13sLX+HkEGH4mxHfiRv8l8UaWobMRqIL0qR Hlzls+HkKWbcrx5CUzHOTKASnG9Kf5n/VcwNNELuo57C9O2w8/RGIbAya AUlbp1NvBOz3CvJQE7k43lQ5RnJWMCqBY927sKTpdcnbrs+SuwsmljhzE Ea/BQcYxf9nsgaxObMiiGiRsKO99kSKRUKNZgWGoAccDGQP1jnkXnVdSg xZY14WSNjTaX5mbig8QqdaZZlr9JfWJgJ5uTTxWQ/nx6VvMyj2cuv4JRn w6oEw9GJ+M76Tru9T1wY3EgxSyZTffhKhzXrnxrwHwkBj8krTq/X9hMTR w==; X-IronPort-AV: E=Sophos;i="6.01,168,1684825200"; d="scan'208";a="218155930" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Jun 2023 01:29:57 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 29 Jun 2023 01:29:50 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 29 Jun 2023 01:29:48 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , Subject: [PATCH v2 01/10] RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Date: Thu, 29 Jun 2023 09:28:47 +0100 Message-ID: <20230629-fruit-syndrome-74e32af9c8ad@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> References: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2434; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=UJAC/sZOfHsqO8ubaZdFS5UN7qeloghiBAOtP5WmH0o=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDClzHQ6un8fYz/RnncHnE2n3TnRc3rF78ubp2sESpiVe/10u l4YGdZSyMIhxMMiKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BeAiGxj+aX2XvMTf3Ln2caF4mP0cA5 n9uWomvG2yhUv6nyxb3cWay8iw/Gbwad/JV+tO+l85I/4g9WjVnH81ZwIkm1aLrFsw+XssAwA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner When filling hwcap the kernel already expects the isa string to start with rv32 if CONFIG_32BIT and rv64 if CONFIG_64BIT. So when recreating the runtime isa-string we can also just go the other way to get the correct starting point for it. Signed-off-by: Heiko Stuebner Reviewed-by: Andrew Jones Co-developed-by: Conor Dooley Signed-off-by: Conor Dooley Reviewed-by: Evan Green --- Changes in v2: - Delete the whole else & pull print_mmu() above it, since that's common code now --- arch/riscv/kernel/cpu.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index a2fc952318e9..2fb5e8e1df52 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -253,13 +253,16 @@ static void print_isa_ext(struct seq_file *f) */ static const char base_riscv_exts[13] =3D "imafdqcbkjpvh"; =20 -static void print_isa(struct seq_file *f, const char *isa) +static void print_isa(struct seq_file *f) { int i; =20 seq_puts(f, "isa\t\t: "); - /* Print the rv[64/32] part */ - seq_write(f, isa, 4); + if (IS_ENABLED(CONFIG_32BIT)) + seq_write(f, "rv32", 4); + else + seq_write(f, "rv64", 4); + for (i =3D 0; i < sizeof(base_riscv_exts); i++) { if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a')) /* Print only enabled the base ISA extensions */ @@ -316,27 +319,21 @@ static int c_show(struct seq_file *m, void *v) unsigned long cpu_id =3D (unsigned long)v - 1; struct riscv_cpuinfo *ci =3D per_cpu_ptr(&riscv_cpuinfo, cpu_id); struct device_node *node; - const char *compat, *isa; + const char *compat; =20 seq_printf(m, "processor\t: %lu\n", cpu_id); seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); + print_isa(m); + print_mmu(m); =20 if (acpi_disabled) { node =3D of_get_cpu_node(cpu_id, NULL); - if (!of_property_read_string(node, "riscv,isa", &isa)) - print_isa(m, isa); =20 - print_mmu(m); if (!of_property_read_string(node, "compatible", &compat) && strcmp(compat, "riscv")) seq_printf(m, "uarch\t\t: %s\n", compat); =20 of_node_put(node); - } else { - if (!acpi_get_riscv_isa(NULL, cpu_id, &isa)) - print_isa(m, isa); - - print_mmu(m); } =20 seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid); --=20 2.40.1 From nobody Mon Feb 9 10:40:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D242EB64DC for ; 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X-IronPort-AV: E=Sophos;i="6.01,168,1684825200"; d="scan'208";a="218155941" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Jun 2023 01:29:58 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 29 Jun 2023 01:29:53 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 29 Jun 2023 01:29:50 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , Subject: [PATCH v2 02/10] RISC-V: drop a needless check in print_isa_ext() Date: Thu, 29 Jun 2023 09:28:48 +0100 Message-ID: <20230629-tightly-filtrate-a0b8656035b6@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> References: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1275; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=6yGCLTHTWBR9QgFp49drRvDK9QX9Ej+dLrWhdW/gWbA=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDClzHQ7O/5jZKX5wYerZcy4XN1QdYwg7sGWDftNq5dLY9NAA EZn4jlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAExkzmxGhgOJoZGnTaWeGas0vN1o9v SYa3bTDhtfo/SrnC1zfaYmczP8lY9LiLpzerPj2fzdbFM01+z9fsvW0VOhOWRGysxDUt69nAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" isa_ext_arr cannot be empty, as some of the extensions within it are always built into the kernel. When this code was first added, back in commit a9b202606c69 ("RISC-V: Improve /proc/cpuinfo output for ISA extensions"), the array was empty and needed a dummy item & thus there could be no extensions present. When the first multi-letter ones did get added, it was Sscofpmf - which didn't have a Kconfig symbol to disable it. Remove this check, as it has been redundant since Sscofpmf was added. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- Changes in v2: - Reword commit message to explain why this can be dropped --- arch/riscv/kernel/cpu.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 2fb5e8e1df52..ddd7634e4c1d 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -233,10 +233,6 @@ static void print_isa_ext(struct seq_file *f) =20 arr_sz =3D ARRAY_SIZE(isa_ext_arr) - 1; =20 - /* No extension support available */ - if (arr_sz <=3D 0) - return; - for (i =3D 0; i <=3D arr_sz; i++) { edata =3D &isa_ext_arr[i]; if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) --=20 2.40.1 From nobody Mon Feb 9 10:40:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E8FCEB64DC for ; Thu, 29 Jun 2023 08:31:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232649AbjF2Ibg (ORCPT ); Thu, 29 Jun 2023 04:31:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232607AbjF2IaL (ORCPT ); Thu, 29 Jun 2023 04:30:11 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E624730EC; Thu, 29 Jun 2023 01:29:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1688027400; x=1719563400; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ACgufHXcPiL8rifI6fkEhENDFzTA51H/eccA5b+cTgc=; b=VN6qcp6qKs1mhR8+p1O9yVpEotuMuQJJ/VnLz9BTHsh4dy3cLZzaqE60 6bnLfkraxAFCjBvt4AGjxs37OYCRRB8s2wJ/nyaDXbQ1lZTooS+z5jq6W 76pD4q+jS+dVtByXyXvLJILWh89+tAr9a8unOzTE3wBIMAgiQG10Opbrk HMyZJFdDIHzagAGWVr2XbgjC8qvmm5Y9s7sXg26h1EogXzXDLPhy7l5EC 0E550v7EjPHD60PFCS5ieRwSrgAEJ3THawA9E3etKzhY3y/sOQAZcB8ga n89IxDn8k903BGO6SqSyiryEsphdwvBBe375nY/eK0U6T69h14WmGPnKV w==; X-IronPort-AV: E=Sophos;i="6.01,168,1684825200"; d="scan'208";a="218155948" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Jun 2023 01:29:58 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 29 Jun 2023 01:29:55 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 29 Jun 2023 01:29:53 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , Subject: [PATCH v2 03/10] RISC-V: shunt isa_ext_arr to cpufeature.c Date: Thu, 29 Jun 2023 09:28:49 +0100 Message-ID: <20230629-museum-playhouse-6dbe7e573f2c@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> References: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=8733; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=ACgufHXcPiL8rifI6fkEhENDFzTA51H/eccA5b+cTgc=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDClzHQ46MVg8it3Hec768kOv1nWfWsu2hDApSb9OyFy5+OGZ 4u8KHaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZhIyRWGPxxuqz/snvVtrq/arQaL98 2l1U+tn4nc/X7lePsFx2zvexMZGdZNKd/O+vjMEeUDJ6M5ec7laNZvdF0bp6/n/UbE6kdJGT8A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To facilitate using one struct to define extensions, rather than having several, shunt isa_ext_arr to cpufeature.c, where it will be used for probing extension presence also. As that scope of the array as widened, prefix it with riscv & drop the type from the variable name. Since the new array is const, print_isa() needs a wee bit of cleanup to avoid complaints about losing the const qualifier. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley Reviewed-by: Evan Green --- Changes in v2: - Drop the empty element from the end of the array, it was adding a bug anyway as I was not decrementing the result of ARRAY_SIZE() by one. Likely I meant to drop it originally and forgot, as dropping the decrement was intentional. --- arch/riscv/include/asm/hwcap.h | 3 ++ arch/riscv/kernel/cpu.c | 75 +--------------------------------- arch/riscv/kernel/cpufeature.c | 67 ++++++++++++++++++++++++++++++ 3 files changed, 72 insertions(+), 73 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index f041bfa7f6a0..7a57e6109aef 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -76,6 +76,9 @@ struct riscv_isa_ext_data { unsigned int isa_ext_id; }; =20 +extern const struct riscv_isa_ext_data riscv_isa_ext[]; +extern const size_t riscv_isa_ext_count; + unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); =20 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index ddd7634e4c1d..269a32ceb595 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -160,81 +160,10 @@ arch_initcall(riscv_cpuinfo_init); =20 #ifdef CONFIG_PROC_FS =20 -#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ - { \ - .uprop =3D #UPROP, \ - .isa_ext_id =3D EXTID, \ - } - -/* - * The canonical order of ISA extension names in the ISA string is defined= in - * chapter 27 of the unprivileged specification. - * - * Ordinarily, for in-kernel data structures, this order is unimportant but - * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo. - * - * The specification uses vague wording, such as should, when it comes to - * ordering, so for our purposes the following rules apply: - * - * 1. All multi-letter extensions must be separated from other extensions = by an - * underscore. - * - * 2. Additional standard extensions (starting with 'Z') must be sorted af= ter - * single-letter extensions and before any higher-privileged extensions. - - * 3. The first letter following the 'Z' conventionally indicates the most - * closely related alphabetical extension category, IMAFDQLCBKJTPVH. - * If multiple 'Z' extensions are named, they must be ordered first by - * category, then alphabetically within a category. - * - * 3. Standard supervisor-level extensions (starting with 'S') must be lis= ted - * after standard unprivileged extensions. If multiple supervisor-level - * extensions are listed, they must be ordered alphabetically. - * - * 4. Standard machine-level extensions (starting with 'Zxm') must be list= ed - * after any lower-privileged, standard extensions. If multiple - * machine-level extensions are listed, they must be ordered - * alphabetically. - * - * 5. Non-standard extensions (starting with 'X') must be listed after all - * standard extensions. If multiple non-standard extensions are listed,= they - * must be ordered alphabetically. - * - * An example string following the order is: - * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux - * - * New entries to this struct should follow the ordering rules described a= bove. - */ -static struct riscv_isa_ext_data isa_ext_arr[] =3D { - __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), - __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), - __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), - __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), - __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), - __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), - __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), - __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), - __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), - __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), - __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), - __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), - __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), - __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), - __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), - __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), - __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), - __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), -}; - static void print_isa_ext(struct seq_file *f) { - struct riscv_isa_ext_data *edata; - int i =3D 0, arr_sz; - - arr_sz =3D ARRAY_SIZE(isa_ext_arr) - 1; - - for (i =3D 0; i <=3D arr_sz; i++) { - edata =3D &isa_ext_arr[i]; + for (int i =3D 0; i < riscv_isa_ext_count; i++) { + const struct riscv_isa_ext_data *edata =3D &riscv_isa_ext[i]; if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) continue; seq_printf(f, "_%s", edata->uprop); diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index bdcf460ea53d..fb476153fffc 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -99,6 +99,73 @@ static bool riscv_isa_extension_check(int id) return true; } =20 +#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ + { \ + .uprop =3D #UPROP, \ + .isa_ext_id =3D EXTID, \ + } + +/* + * The canonical order of ISA extension names in the ISA string is defined= in + * chapter 27 of the unprivileged specification. + * + * Ordinarily, for in-kernel data structures, this order is unimportant but + * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo. + * + * The specification uses vague wording, such as should, when it comes to + * ordering, so for our purposes the following rules apply: + * + * 1. All multi-letter extensions must be separated from other extensions = by an + * underscore. + * + * 2. Additional standard extensions (starting with 'Z') must be sorted af= ter + * single-letter extensions and before any higher-privileged extensions. + * + * 3. The first letter following the 'Z' conventionally indicates the most + * closely related alphabetical extension category, IMAFDQLCBKJTPVH. + * If multiple 'Z' extensions are named, they must be ordered first by + * category, then alphabetically within a category. + * + * 3. Standard supervisor-level extensions (starting with 'S') must be lis= ted + * after standard unprivileged extensions. If multiple supervisor-level + * extensions are listed, they must be ordered alphabetically. + * + * 4. Standard machine-level extensions (starting with 'Zxm') must be list= ed + * after any lower-privileged, standard extensions. If multiple + * machine-level extensions are listed, they must be ordered + * alphabetically. + * + * 5. Non-standard extensions (starting with 'X') must be listed after all + * standard extensions. If multiple non-standard extensions are listed,= they + * must be ordered alphabetically. + * + * An example string following the order is: + * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux + * + * New entries to this struct should follow the ordering rules described a= bove. + */ +const struct riscv_isa_ext_data riscv_isa_ext[] =3D { + __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), + __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), + __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), + __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), + __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), + __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), + __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), + __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), + __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), + __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), + __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), + __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), + __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), + __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), + __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), + __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), + __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), +}; + +const size_t riscv_isa_ext_count =3D ARRAY_SIZE(riscv_isa_ext); + void __init riscv_fill_hwcap(void) { struct device_node *node; --=20 2.40.1 From nobody Mon Feb 9 10:40:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FD02EB64DC for ; Thu, 29 Jun 2023 08:31:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232602AbjF2IbY (ORCPT ); Thu, 29 Jun 2023 04:31:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232645AbjF2IaW (ORCPT ); Thu, 29 Jun 2023 04:30:22 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88169131; Thu, 29 Jun 2023 01:30:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1688027410; x=1719563410; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bIs6kqMED+8WeRtoxXsVzTKb8hUL0V34cciMGbaTy6Y=; b=BG0tf0G+aFVFpt0jAusByz4CPoEmvRuBHnycalTGo6+mDEjd4elNtLEp XtI30XWaFQiqxjF+4CK1ipLtImr9J1z/ctQTGZH4w2Dldqf0K/2YSk3JT KAW1LlOw1TsWaxFd30hycojN8L6hOBbn2UuDk4EU0ofgegLj7Ovg1ehWd ykPoEkPqiJ1mFtKdCf2eSmMirVJpq0GlzSE1cpH/lzKQkyi+PEz6180iv lQASahrXbstbTE6k9LPaY3PcdbRHd5W/oV04pjnv+Y3Ozp6QpIS8rl3jH myhLrRAQeoRsWd90cGxneTS7UnxF2OAcgQ/Nz2UwuNeAvkmijM79eBfqX A==; X-IronPort-AV: E=Sophos;i="6.01,168,1684825200"; d="scan'208";a="159104686" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Jun 2023 01:30:09 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 29 Jun 2023 01:29:58 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 29 Jun 2023 01:29:56 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , Subject: [PATCH v2 04/10] RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap() Date: Thu, 29 Jun 2023 09:28:50 +0100 Message-ID: <20230629-lair-thinner-349e8d9f0e89@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> References: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3700; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=bIs6kqMED+8WeRtoxXsVzTKb8hUL0V34cciMGbaTy6Y=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDClzHQ7V1O9/urQ6ewEnQ+vNl5feWW7avabv1Zbm7nUrz4fd jeBd0VHKwiDGwSArpsiSeLuvRWr9H5cdzj1vYeawMoEMYeDiFICJ3A9kZJhS9dCBN0zb5VdwyCfH77 O+7X3afe3gqqe7P9/f8aPHw3wOwz+r3WknI/w4BRTTYuWu+DIdN97y1mrG3wR2xolaN424M3kA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In riscv_fill_hwcap() riscv_isa_ext array can be looped over, rather than duplicating the list of extensions with individual SET_ISA_EXT_MAP() usage. While at it, drop the statement-of-the-obvious comments from the struct, rename uprop to something more suitable for its new use & constify the members. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- Changes in v2: - Delete the now unused definition --- arch/riscv/include/asm/hwcap.h | 7 ++----- arch/riscv/kernel/cpu.c | 5 +++-- arch/riscv/kernel/cpufeature.c | 26 +++++++------------------- 3 files changed, 12 insertions(+), 26 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 7a57e6109aef..2460ac2fc7ed 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -55,7 +55,6 @@ #define RISCV_ISA_EXT_ZIHPM 42 =20 #define RISCV_ISA_EXT_MAX 64 -#define RISCV_ISA_EXT_NAME_LEN_MAX 32 =20 #ifdef CONFIG_RISCV_M_MODE #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA @@ -70,10 +69,8 @@ unsigned long riscv_get_elf_hwcap(void); =20 struct riscv_isa_ext_data { - /* Name of the extension displayed to userspace via /proc/cpuinfo */ - char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; - /* The logical ISA extension ID */ - unsigned int isa_ext_id; + const unsigned int id; + const char *name; }; =20 extern const struct riscv_isa_ext_data riscv_isa_ext[]; diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 269a32ceb595..c89abf8ef6de 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -164,9 +164,10 @@ static void print_isa_ext(struct seq_file *f) { for (int i =3D 0; i < riscv_isa_ext_count; i++) { const struct riscv_isa_ext_data *edata =3D &riscv_isa_ext[i]; - if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) + if (!__riscv_isa_extension_available(NULL, edata->id)) continue; - seq_printf(f, "_%s", edata->uprop); + + seq_printf(f, "_%s", edata->name); } } =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index fb476153fffc..6d8cd45af723 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -99,11 +99,10 @@ static bool riscv_isa_extension_check(int id) return true; } =20 -#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ - { \ - .uprop =3D #UPROP, \ - .isa_ext_id =3D EXTID, \ - } +#define __RISCV_ISA_EXT_DATA(_name, _id) { \ + .name =3D #_name, \ + .id =3D _id, \ +} =20 /* * The canonical order of ISA extension names in the ISA string is defined= in @@ -366,20 +365,9 @@ void __init riscv_fill_hwcap(void) set_bit(nr, isainfo->isa); } } else { - /* sorted alphabetically */ - SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA); - SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA); - SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); - SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); - SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); - SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT); - SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); - SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA); - SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB); - SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS); - SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); - SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ); - SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); + for (int i =3D 0; i < riscv_isa_ext_count; i++) + SET_ISA_EXT_MAP(riscv_isa_ext[i].name, + riscv_isa_ext[i].id); } #undef SET_ISA_EXT_MAP } --=20 2.40.1 From nobody Mon Feb 9 10:40:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B01B5EB64DC for ; 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X-IronPort-AV: E=Sophos;i="6.01,168,1684825200"; d="scan'208";a="221156087" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Jun 2023 01:30:08 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 29 Jun 2023 01:30:00 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 29 Jun 2023 01:29:58 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , Subject: [PATCH v2 05/10] RISC-V: add missing single letter extension definitions Date: Thu, 29 Jun 2023 09:28:51 +0100 Message-ID: <20230629-disengage-cornbread-3876ec5b9e96@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> References: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1204; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=HPRtOyIqm/BcHFGgw0cl0PQB3rNvTkemYLiSjsKMtC8=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDClzHQ7l626WmZpff9hgpUqIwsNvnc17glU4/tntZbpiHPBh YvKNjlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAEzksg0jw2WVLce/L9aw9RHdfex1V2 rOlk/Tz/k+WP1ztVFgodn540AVz840NX8qvsLX+sm97Faa3GYfTTaxRBXutvvbRC/PWDuZFQA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To facilitate adding single letter extensions to riscv_isa_ext, add definitions for the extensions present in base_riscv_exts that do not already have them. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- arch/riscv/include/asm/hwcap.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 2460ac2fc7ed..a20e4ade1b53 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -14,12 +14,17 @@ #include =20 #define RISCV_ISA_EXT_a ('a' - 'a') +#define RISCV_ISA_EXT_b ('b' - 'a') #define RISCV_ISA_EXT_c ('c' - 'a') #define RISCV_ISA_EXT_d ('d' - 'a') #define RISCV_ISA_EXT_f ('f' - 'a') #define RISCV_ISA_EXT_h ('h' - 'a') #define RISCV_ISA_EXT_i ('i' - 'a') +#define RISCV_ISA_EXT_j ('j' - 'a') +#define RISCV_ISA_EXT_k ('k' - 'a') #define RISCV_ISA_EXT_m ('m' - 'a') +#define RISCV_ISA_EXT_p ('p' - 'a') +#define RISCV_ISA_EXT_q ('q' - 'a') #define RISCV_ISA_EXT_s ('s' - 'a') #define RISCV_ISA_EXT_u ('u' - 'a') #define RISCV_ISA_EXT_v ('v' - 'a') --=20 2.40.1 From nobody Mon Feb 9 10:40:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 609F8C0015E for ; Thu, 29 Jun 2023 08:31:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232492AbjF2IbF (ORCPT ); Thu, 29 Jun 2023 04:31:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232646AbjF2IaW (ORCPT ); Thu, 29 Jun 2023 04:30:22 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8D5D132; Thu, 29 Jun 2023 01:30:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1688027411; x=1719563411; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=r0ERhmqbd2oRPwjcE5btDtDW/JjDE/JzZQK8UiDqJyo=; b=ledMLAo8TwYyWqkFfwWaLfpSDiGwyBeUZb6xwWTHuEsnPKg0TAPAoDOB O9q8ms86rVV2SfXJR0+87zb+eW6slkh2qCPRfLNoGlFWsRnK5yejMV7B3 bKI6X44kd3gMx61tFPyb+KOJet2Y7VsaIrabYL1KR6wTYYOeMZGkD9AR9 NcJTuVldAXaROh8VGPsCPqbnJg5ZgtigmROK1YEwH6qwAm3vLRh/yff6Z VUI4bQUxIvUp8s3wQJdiaBsADQ0Tcji1uS3VYOveFHUvYLBgeBJMYV7rO 1b6wiYGg7WxRKwcbzLlxXrg18NpN8zB7B9bUt76DvxKLy1wEwK/gWaXLM g==; X-IronPort-AV: E=Sophos;i="6.01,168,1684825200"; d="scan'208";a="159104698" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Jun 2023 01:30:10 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 29 Jun 2023 01:30:03 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 29 Jun 2023 01:30:01 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , Subject: [PATCH v2 06/10] RISC-V: add single letter extensions to riscv_isa_ext Date: Thu, 29 Jun 2023 09:28:52 +0100 Message-ID: <20230629-uprising-harbor-439b85492132@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> References: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3714; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=r0ERhmqbd2oRPwjcE5btDtDW/JjDE/JzZQK8UiDqJyo=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDClzHQ7xqHjnlcbxGS1mNHGsavkiMGXzdyGv342hJZpPbLwO +TZ2lLIwiHEwyIopsiTe7muRWv/HZYdzz1uYOaxMIEMYuDgFYCJH/jP8j799dseFzfKbHPo4S24uXy Q71XbZyxy/xGq7rQ8rD/6f/5zhv0fF1gXfb5bt7bQIi3fIeDDnwq+AZx2WM/nr1yyMerk5iRkA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" So that riscv_fill_hwcap() can use riscv_isa_ext to probe for single letter extensions, add them to it. As a result, what gets spat out in /proc/cpuinfo will become borked, as single letter extensions will be printed as part of the base extensions and while printing from riscv_isa_arr. Take the opportunity to unify the printing of the isa string, using the new member of riscv_isa_ext_data in the process. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley Reviewed-by: Evan Green --- Changes in v2: - Drop the multi_letter member, in exchange for calling strnlen() in two places. --- arch/riscv/kernel/cpu.c | 37 ++++++++++------------------------ arch/riscv/kernel/cpufeature.c | 13 ++++++++++++ 2 files changed, 24 insertions(+), 26 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index c89abf8ef6de..d0dfd88221df 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -160,41 +160,26 @@ arch_initcall(riscv_cpuinfo_init); =20 #ifdef CONFIG_PROC_FS =20 -static void print_isa_ext(struct seq_file *f) -{ - for (int i =3D 0; i < riscv_isa_ext_count; i++) { - const struct riscv_isa_ext_data *edata =3D &riscv_isa_ext[i]; - if (!__riscv_isa_extension_available(NULL, edata->id)) - continue; - - seq_printf(f, "_%s", edata->name); - } -} - -/* - * These are the only valid base (single letter) ISA extensions as per the= spec. - * It also specifies the canonical order in which it appears in the spec. - * Some of the extension may just be a place holder for now (B, K, P, J). - * This should be updated once corresponding extensions are ratified. - */ -static const char base_riscv_exts[13] =3D "imafdqcbkjpvh"; - static void print_isa(struct seq_file *f) { - int i; - seq_puts(f, "isa\t\t: "); + if (IS_ENABLED(CONFIG_32BIT)) seq_write(f, "rv32", 4); else seq_write(f, "rv64", 4); =20 - for (i =3D 0; i < sizeof(base_riscv_exts); i++) { - if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a')) - /* Print only enabled the base ISA extensions */ - seq_write(f, &base_riscv_exts[i], 1); + for (int i =3D 0; i < riscv_isa_ext_count; i++) { + if (!__riscv_isa_extension_available(NULL, riscv_isa_ext[i].id)) + continue; + + /* Only multi-letter extensions are split by underscores */ + if (strnlen(riscv_isa_ext[i].name, 2) !=3D 1) + seq_puts(f, "_"); + + seq_printf(f, "%s", riscv_isa_ext[i].name); } - print_isa_ext(f); + seq_puts(f, "\n"); } =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 6d8cd45af723..bf7e8e8852f0 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -144,6 +144,19 @@ static bool riscv_isa_extension_check(int id) * New entries to this struct should follow the ordering rules described a= bove. */ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { + __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i), + __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m), + __RISCV_ISA_EXT_DATA(a, RISCV_ISA_EXT_a), + __RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f), + __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d), + __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), + __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c), + __RISCV_ISA_EXT_DATA(b, RISCV_ISA_EXT_b), + __RISCV_ISA_EXT_DATA(k, RISCV_ISA_EXT_k), + __RISCV_ISA_EXT_DATA(j, RISCV_ISA_EXT_j), + __RISCV_ISA_EXT_DATA(p, RISCV_ISA_EXT_p), + __RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v), + __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), --=20 2.40.1 From nobody Mon Feb 9 10:40:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 827DDEB64D9 for ; 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X-IronPort-AV: E=Sophos;i="6.01,168,1684825200"; d="scan'208";a="159104706" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Jun 2023 01:30:11 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 29 Jun 2023 01:30:06 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 29 Jun 2023 01:30:03 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , Subject: [PATCH v2 07/10] RISC-V: split riscv_fill_hwcap() in 3 Date: Thu, 29 Jun 2023 09:28:53 +0100 Message-ID: <20230629-hazy-creative-cd4e936f6d99@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> References: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=11968; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=iGe+YwVNmPq1+zqO9UyiaCBbCGF6aB1MOiyT8TFuwhg=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDClzHQ4LM/6OtAp34fj85oLWvKcLvr55Ix0nsrr0QWHO1wVv PpnGdZSyMIhxMMiKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAitXcY/tfI7WhwKOthvOXFECvB+y 8y9ceqfOecoPgVVVP2furf1cHwPyzNYv2ZJY9X9JgGOpv7Gfqtvn3vi8VNxeuH9wlF3lPbyAsA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Before adding more complexity to it, split riscv_fill_hwcap() into 3 distinct sections: - riscv_fill_hwcap() still is the top level function, into which the additional complexity will be added. - riscv_fill_hwcap_from_isa_string() handles getting the information from the riscv,isa/ACPI equivalent across harts & the various quirks there - riscv_parse_isa_string() does what it says on the tin. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- Changes in v2: - Drop unused variables --- arch/riscv/kernel/cpufeature.c | 345 +++++++++++++++++---------------- 1 file changed, 177 insertions(+), 168 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index bf7e8e8852f0..41aedeaecb61 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -178,29 +178,172 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { =20 const size_t riscv_isa_ext_count =3D ARRAY_SIZE(riscv_isa_ext); =20 -void __init riscv_fill_hwcap(void) +static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struc= t riscv_isainfo *isainfo, + unsigned long *isa2hwcap, const char *isa) +{ + /* + * For all possible cpus, we have already validated in + * the boot process that they at least contain "rv" and + * whichever of "32"/"64" this kernel supports, and so this + * section can be skipped. + */ + isa +=3D 4; + + while (*isa) { + const char *ext =3D isa++; + const char *ext_end =3D isa; + bool ext_long =3D false, ext_err =3D false; + + switch (*ext) { + case 's': + /* + * Workaround for invalid single-letter 's' & 'u'(QEMU). + * No need to set the bit in riscv_isa as 's' & 'u' are + * not valid ISA extensions. It works until multi-letter + * extension starting with "Su" appears. + */ + if (ext[-1] !=3D '_' && ext[1] =3D=3D 'u') { + ++isa; + ext_err =3D true; + break; + } + fallthrough; + case 'S': + case 'x': + case 'X': + case 'z': + case 'Z': + /* + * Before attempting to parse the extension itself, we find its end. + * As multi-letter extensions must be split from other multi-letter + * extensions with an "_", the end of a multi-letter extension will + * either be the null character or the "_" at the start of the next + * multi-letter extension. + * + * Next, as the extensions version is currently ignored, we + * eliminate that portion. This is done by parsing backwards from + * the end of the extension, removing any numbers. This may be a + * major or minor number however, so the process is repeated if a + * minor number was found. + * + * ext_end is intended to represent the first character *after* the + * name portion of an extension, but will be decremented to the last + * character itself while eliminating the extensions version number. + * A simple re-increment solves this problem. + */ + ext_long =3D true; + for (; *isa && *isa !=3D '_'; ++isa) + if (unlikely(!isalnum(*isa))) + ext_err =3D true; + + ext_end =3D isa; + if (unlikely(ext_err)) + break; + + if (!isdigit(ext_end[-1])) + break; + + while (isdigit(*--ext_end)) + ; + + if (tolower(ext_end[0]) !=3D 'p' || !isdigit(ext_end[-1])) { + ++ext_end; + break; + } + + while (isdigit(*--ext_end)) + ; + + ++ext_end; + break; + default: + /* + * Things are a little easier for single-letter extensions, as they + * are parsed forwards. + * + * After checking that our starting position is valid, we need to + * ensure that, when isa was incremented at the start of the loop, + * that it arrived at the start of the next extension. + * + * If we are already on a non-digit, there is nothing to do. Either + * we have a multi-letter extension's _, or the start of an + * extension. + * + * Otherwise we have found the current extension's major version + * number. Parse past it, and a subsequent p/minor version number + * if present. The `p` extension must not appear immediately after + * a number, so there is no fear of missing it. + * + */ + if (unlikely(!isalpha(*ext))) { + ext_err =3D true; + break; + } + + if (!isdigit(*isa)) + break; + + while (isdigit(*++isa)) + ; + + if (tolower(*isa) !=3D 'p') + break; + + if (!isdigit(*++isa)) { + --isa; + break; + } + + while (isdigit(*++isa)) + ; + + break; + } + + /* + * The parser expects that at the start of an iteration isa points to the + * first character of the next extension. As we stop parsing an extension + * on meeting a non-alphanumeric character, an extra increment is needed + * where the succeeding extension is a multi-letter prefixed with an "_". + */ + if (*isa =3D=3D '_') + ++isa; + +#define SET_ISA_EXT_MAP(name, bit) \ + do { \ + if ((ext_end - ext =3D=3D sizeof(name) - 1) && \ + !strncasecmp(ext, name, sizeof(name) - 1) && \ + riscv_isa_extension_check(bit)) \ + set_bit(bit, isainfo->isa); \ + } while (false) \ + + if (unlikely(ext_err)) + continue; + if (!ext_long) { + int nr =3D tolower(*ext) - 'a'; + + if (riscv_isa_extension_check(nr)) { + *this_hwcap |=3D isa2hwcap[nr]; + set_bit(nr, isainfo->isa); + } + } else { + for (int i =3D 0; i < riscv_isa_ext_count; i++) + SET_ISA_EXT_MAP(riscv_isa_ext[i].name, + riscv_isa_ext[i].id); + } +#undef SET_ISA_EXT_MAP + } +} + +static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwc= ap) { struct device_node *node; const char *isa; - char print_str[NUM_ALPHA_EXTS + 1]; - int i, j, rc; - unsigned long isa2hwcap[26] =3D {0}; + int rc; struct acpi_table_header *rhct; acpi_status status; unsigned int cpu; =20 - isa2hwcap['i' - 'a'] =3D COMPAT_HWCAP_ISA_I; - isa2hwcap['m' - 'a'] =3D COMPAT_HWCAP_ISA_M; - isa2hwcap['a' - 'a'] =3D COMPAT_HWCAP_ISA_A; - isa2hwcap['f' - 'a'] =3D COMPAT_HWCAP_ISA_F; - isa2hwcap['d' - 'a'] =3D COMPAT_HWCAP_ISA_D; - isa2hwcap['c' - 'a'] =3D COMPAT_HWCAP_ISA_C; - isa2hwcap['v' - 'a'] =3D COMPAT_HWCAP_ISA_V; - - elf_hwcap =3D 0; - - bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); - if (!acpi_disabled) { status =3D acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); if (ACPI_FAILURE(status)) @@ -232,158 +375,7 @@ void __init riscv_fill_hwcap(void) } } =20 - /* - * For all possible cpus, we have already validated in - * the boot process that they at least contain "rv" and - * whichever of "32"/"64" this kernel supports, and so this - * section can be skipped. - */ - isa +=3D 4; - - while (*isa) { - const char *ext =3D isa++; - const char *ext_end =3D isa; - bool ext_long =3D false, ext_err =3D false; - - switch (*ext) { - case 's': - /* - * Workaround for invalid single-letter 's' & 'u'(QEMU). - * No need to set the bit in riscv_isa as 's' & 'u' are - * not valid ISA extensions. It works until multi-letter - * extension starting with "Su" appears. - */ - if (ext[-1] !=3D '_' && ext[1] =3D=3D 'u') { - ++isa; - ext_err =3D true; - break; - } - fallthrough; - case 'S': - case 'x': - case 'X': - case 'z': - case 'Z': - /* - * Before attempting to parse the extension itself, we find its end. - * As multi-letter extensions must be split from other multi-letter - * extensions with an "_", the end of a multi-letter extension will - * either be the null character or the "_" at the start of the next - * multi-letter extension. - * - * Next, as the extensions version is currently ignored, we - * eliminate that portion. This is done by parsing backwards from - * the end of the extension, removing any numbers. This may be a - * major or minor number however, so the process is repeated if a - * minor number was found. - * - * ext_end is intended to represent the first character *after* the - * name portion of an extension, but will be decremented to the last - * character itself while eliminating the extensions version number. - * A simple re-increment solves this problem. - */ - ext_long =3D true; - for (; *isa && *isa !=3D '_'; ++isa) - if (unlikely(!isalnum(*isa))) - ext_err =3D true; - - ext_end =3D isa; - if (unlikely(ext_err)) - break; - - if (!isdigit(ext_end[-1])) - break; - - while (isdigit(*--ext_end)) - ; - - if (tolower(ext_end[0]) !=3D 'p' || !isdigit(ext_end[-1])) { - ++ext_end; - break; - } - - while (isdigit(*--ext_end)) - ; - - ++ext_end; - break; - default: - /* - * Things are a little easier for single-letter extensions, as they - * are parsed forwards. - * - * After checking that our starting position is valid, we need to - * ensure that, when isa was incremented at the start of the loop, - * that it arrived at the start of the next extension. - * - * If we are already on a non-digit, there is nothing to do. Either - * we have a multi-letter extension's _, or the start of an - * extension. - * - * Otherwise we have found the current extension's major version - * number. Parse past it, and a subsequent p/minor version number - * if present. The `p` extension must not appear immediately after - * a number, so there is no fear of missing it. - * - */ - if (unlikely(!isalpha(*ext))) { - ext_err =3D true; - break; - } - - if (!isdigit(*isa)) - break; - - while (isdigit(*++isa)) - ; - - if (tolower(*isa) !=3D 'p') - break; - - if (!isdigit(*++isa)) { - --isa; - break; - } - - while (isdigit(*++isa)) - ; - - break; - } - - /* - * The parser expects that at the start of an iteration isa points to t= he - * first character of the next extension. As we stop parsing an extensi= on - * on meeting a non-alphanumeric character, an extra increment is needed - * where the succeeding extension is a multi-letter prefixed with an "_= ". - */ - if (*isa =3D=3D '_') - ++isa; - -#define SET_ISA_EXT_MAP(name, bit) \ - do { \ - if ((ext_end - ext =3D=3D sizeof(name) - 1) && \ - !strncasecmp(ext, name, sizeof(name) - 1) && \ - riscv_isa_extension_check(bit)) \ - set_bit(bit, isainfo->isa); \ - } while (false) \ - - if (unlikely(ext_err)) - continue; - if (!ext_long) { - int nr =3D tolower(*ext) - 'a'; - - if (riscv_isa_extension_check(nr)) { - this_hwcap |=3D isa2hwcap[nr]; - set_bit(nr, isainfo->isa); - } - } else { - for (int i =3D 0; i < riscv_isa_ext_count; i++) - SET_ISA_EXT_MAP(riscv_isa_ext[i].name, - riscv_isa_ext[i].id); - } -#undef SET_ISA_EXT_MAP - } + riscv_parse_isa_string(&this_hwcap, isainfo, isa2hwcap, isa); =20 /* * Linux requires the following extensions, so we may as well @@ -420,6 +412,23 @@ void __init riscv_fill_hwcap(void) =20 if (!acpi_disabled && rhct) acpi_put_table((struct acpi_table_header *)rhct); +} + +void __init riscv_fill_hwcap(void) +{ + char print_str[NUM_ALPHA_EXTS + 1]; + int i, j; + unsigned long isa2hwcap[26] =3D {0}; + + isa2hwcap['i' - 'a'] =3D COMPAT_HWCAP_ISA_I; + isa2hwcap['m' - 'a'] =3D COMPAT_HWCAP_ISA_M; + isa2hwcap['a' - 'a'] =3D COMPAT_HWCAP_ISA_A; + isa2hwcap['f' - 'a'] =3D COMPAT_HWCAP_ISA_F; + isa2hwcap['d' - 'a'] =3D COMPAT_HWCAP_ISA_D; + isa2hwcap['c' - 'a'] =3D COMPAT_HWCAP_ISA_C; + isa2hwcap['v' - 'a'] =3D COMPAT_HWCAP_ISA_V; + + riscv_fill_hwcap_from_isa_string(isa2hwcap); =20 /* We don't support systems with F but without D, so mask those out * here. */ --=20 2.40.1 From nobody Mon Feb 9 10:40:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33D45EB64D9 for ; Thu, 29 Jun 2023 08:31:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232739AbjF2Ib4 (ORCPT ); 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X-IronPort-AV: E=Sophos;i="6.01,168,1684825200"; d="scan'208";a="159104711" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Jun 2023 01:30:12 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 29 Jun 2023 01:30:08 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 29 Jun 2023 01:30:06 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , Subject: [PATCH v2 08/10] RISC-V: enable extension detection from new properties Date: Thu, 29 Jun 2023 09:28:54 +0100 Message-ID: <20230629-defiling-salary-a51c0d89d31c@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> References: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4499; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=GCIGwsCwU5RS5bMsoRtWcou0pn3VgTFaZMXbVrYz4DA=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDClzHQ67sVyPKlafLH/ipn3L2WtuubbyvM48Grl7RYzCd2Wc s03sKGVhEONgkBVTZEm83dcitf6Pyw7nnrcwc1iZQIYwcHEKwESOBDAydM15+H/L1GPSk82kpmZ56K y7+eTxzZvhe9rmMS6QZZya7crIsNNM4OAdoz3rAxPnSezj3yj92CPXNo9vzt6YedPmPpwuyg8A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for parsing the new riscv,isa-extensions property in riscv_fill_hwcap(), by means of a new "property" member of the riscv_isa_ext_data struct. For now, this shadows the name of the extension for all users, however this may not be the case for all extensions, based on how the dt-binding is written. For the sake of backwards compatibility, fall back to the old scheme if the new properties are not detected. For now, just inform, rather than warn, when that happens. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- Changes in v2: - Pick a more suitable function name than fill_hwcap_new() - Actually use the property member to read from the DT --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 76 ++++++++++++++++++++++++++++++++-- 2 files changed, 73 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index a20e4ade1b53..e3cda14a486b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -76,6 +76,7 @@ unsigned long riscv_get_elf_hwcap(void); struct riscv_isa_ext_data { const unsigned int id; const char *name; + const char *property; }; =20 extern const struct riscv_isa_ext_data riscv_isa_ext[]; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 41aedeaecb61..2c4503fa984f 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -101,6 +101,7 @@ static bool riscv_isa_extension_check(int id) =20 #define __RISCV_ISA_EXT_DATA(_name, _id) { \ .name =3D #_name, \ + .property =3D #_name, \ .id =3D _id, \ } =20 @@ -414,11 +415,67 @@ static void __init riscv_fill_hwcap_from_isa_string(u= nsigned long *isa2hwcap) acpi_put_table((struct acpi_table_header *)rhct); } =20 +static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) +{ + unsigned int cpu; + + for_each_possible_cpu(cpu) { + unsigned long this_hwcap =3D 0; + struct device_node *cpu_node; + DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); + + cpu_node =3D of_cpu_device_node_get(cpu); + if (!cpu_node) { + pr_warn("Unable to find cpu node\n"); + continue; + } + + if (!of_property_present(cpu_node, "riscv,isa-extensions")) + continue; + + for (int i =3D 0; i < riscv_isa_ext_count; i++) { + if (of_property_match_string(cpu_node, "riscv,isa-extensions", + riscv_isa_ext[i].property) < 0) + continue; + + if (!riscv_isa_extension_check(riscv_isa_ext[i].id)) + continue; + + /* Only single letter extensions get set in hwcap */ + if (strnlen(riscv_isa_ext[i].name, 2) =3D=3D 1) + this_hwcap |=3D isa2hwcap[riscv_isa_ext[i].id]; + + set_bit(riscv_isa_ext[i].id, this_isa); + } + + of_node_put(cpu_node); + + /* + * All "okay" harts should have same isa. Set HWCAP based on + * common capabilities of every "okay" hart, in case they don't. + */ + if (elf_hwcap) + elf_hwcap &=3D this_hwcap; + else + elf_hwcap =3D this_hwcap; + + if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) + bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX); + else + bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX); + } + + if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) + return -ENOENT; + + return 0; +} + void __init riscv_fill_hwcap(void) { char print_str[NUM_ALPHA_EXTS + 1]; - int i, j; unsigned long isa2hwcap[26] =3D {0}; + int i, j; =20 isa2hwcap['i' - 'a'] =3D COMPAT_HWCAP_ISA_I; isa2hwcap['m' - 'a'] =3D COMPAT_HWCAP_ISA_M; @@ -428,10 +485,21 @@ void __init riscv_fill_hwcap(void) isa2hwcap['c' - 'a'] =3D COMPAT_HWCAP_ISA_C; isa2hwcap['v' - 'a'] =3D COMPAT_HWCAP_ISA_V; =20 - riscv_fill_hwcap_from_isa_string(isa2hwcap); + if (!acpi_disabled) { + riscv_fill_hwcap_from_isa_string(isa2hwcap); + } else { + int ret =3D riscv_fill_hwcap_from_ext_list(isa2hwcap); =20 - /* We don't support systems with F but without D, so mask those out - * here. */ + if (ret) { + pr_info("Falling back to deprecated \"riscv,isa\"\n"); + riscv_fill_hwcap_from_isa_string(isa2hwcap); + } + } + + /* + * We don't support systems with F but without D, so mask those out + * here. + */ if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)= ) { pr_info("This kernel does not support systems with F but not D\n"); elf_hwcap &=3D ~COMPAT_HWCAP_ISA_F; --=20 2.40.1 From nobody Mon Feb 9 10:40:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F141EEB64DC for ; Thu, 29 Jun 2023 08:32:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232802AbjF2IcM (ORCPT ); Thu, 29 Jun 2023 04:32:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232660AbjF2Ia1 (ORCPT ); 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29 Jun 2023 01:30:22 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 29 Jun 2023 01:30:11 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 29 Jun 2023 01:30:09 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , Subject: [PATCH v2 09/10] RISC-V: try new extension properties in of_early_processor_hartid() Date: Thu, 29 Jun 2023 09:28:55 +0100 Message-ID: <20230629-steersman-denim-9427eca04e44@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> References: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1585; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=19N0qNDtQxBiEwr1QgI1H4EeYKq+lA8J3+dC/I8+GXA=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDClzHQ5fdzgSvfBCmtG03eGaVsov3W68mr3acflL3j9PJf9V HFRr7ChlYRDjYJAVU2RJvN3XIrX+j8sO5563MHNYmUCGMHBxCsBEmLMYGe4/vs2m+q2M53vonZ1z41 9LXy1heD698LP9JtG7C99d/pLB8FdcJptxm9PcM9pasUcc48L8M8TYm+a7LVBjX1Z3Nj/8GB8A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To fully deprecate the kernel's use of "riscv,isa", of_early_processor_hartid() needs to first try using the new properties, before falling back to "riscv,isa". Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- arch/riscv/kernel/cpu.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index d0dfd88221df..9a4f4a23afcd 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -61,8 +61,29 @@ int riscv_early_of_processor_hartid(struct device_node *= node, unsigned long *har return -ENODEV; } =20 + if (of_property_read_string(node, "riscv,isa-base", &isa)) + goto old_interface; + + if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32i", 5)) + return -ENODEV; + + if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64i", 5)) + return -ENODEV; + + if (!of_property_present(node, "riscv,isa-extensions")) + return -ENODEV; + + if (of_property_match_string(node, "riscv,isa-extensions", "i") < 0 || + of_property_match_string(node, "riscv,isa-extensions", "m") < 0 || + of_property_match_string(node, "riscv,isa-extensions", "a") < 0) + return -ENODEV; + + return 0; + +old_interface: if (of_property_read_string(node, "riscv,isa", &isa)) { - pr_warn("CPU with hartid=3D%lu has no \"riscv,isa\" property\n", *hart); + pr_warn("CPU with hartid=3D%lu has no \"riscv,isa-base\" or \"riscv,isa\= " property\n", + *hart); return -ENODEV; } =20 --=20 2.40.1 From nobody Mon Feb 9 10:40:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 623BEEB64D9 for ; Thu, 29 Jun 2023 08:32:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232770AbjF2IcF (ORCPT ); Thu, 29 Jun 2023 04:32:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232656AbjF2Ia0 (ORCPT ); Thu, 29 Jun 2023 04:30:26 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 480C72703; Thu, 29 Jun 2023 01:30:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1688027415; x=1719563415; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FyhCBQzwfA+WMj8JPqh8q7RSGYDMWs5+f1Cx9CBdUeU=; b=pTmqSUC7tUzftDcBj6G2Yo/YQOU+fGmpVSVCVPHBhWWbnjCN0Z/wVY2z ig7a+gsi+e0JTP2GccymgKu5EHEPQfBfDjxfMkVSxIUmPD412GEzGEzP8 EPeI0R4aVmkA3Fhz6aRMQD/bNN24PE0H9uSYyCNHCNULX8uPofuYUVk6b DsfWxbRcqC9ZtrEng6EMD+wpfmF1kuF/pq8wqHvo0cMTOtFLY5jGH06Xa +U+x06SlXq496rhqUgeYOUXvcMTp9AtBZv2Ire41K2y9uCVt8Wy45AGIp FNdGfRev6Zwb1TWLXdUygQasbv4gezxX5iZRD+ppxOOZ2bME04Api1Wk8 Q==; X-IronPort-AV: E=Sophos;i="6.01,168,1684825200"; d="scan'208";a="220461307" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Jun 2023 01:30:14 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 29 Jun 2023 01:30:14 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 29 Jun 2023 01:30:11 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , "Evan Green" , Sunil V L , , , , Palmer Dabbelt Subject: [PATCH v2 10/10] RISC-V: provide a Kconfig option to disable parsing "riscv,isa" Date: Thu, 29 Jun 2023 09:28:56 +0100 Message-ID: <20230629-resilient-grievance-d782163b09d6@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> References: <20230629-rebuttal-vagueness-a699deb7c7b3@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2700; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=FyhCBQzwfA+WMj8JPqh8q7RSGYDMWs5+f1Cx9CBdUeU=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDClzHY7obVavUtw9NyBe5vWxwFOv+ZZa9B6d4MElaLi3sH39 L1GJjlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAEzkIx8jw5rVnnHmXF8XyF8z4PaQEv qXySfEuc0x/uets2oXG2dcf8/IcKJg2Z2Q6tpjEw6/avzHMm3O+rCfdR9mrtNeXVv+6JC5DzMA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As it says on the tin, provide a Kconfig option to disabling parsing the "riscv,isa" devicetree property. Hide the option behind NONPORTABLE so that only those willing to keep the pieces enable it, and make sure the default kernel contains the fallback code. Suggested-by: Palmer Dabbelt Signed-off-by: Conor Dooley --- arch/riscv/Kconfig | 16 ++++++++++++++++ arch/riscv/kernel/cpu.c | 3 +++ arch/riscv/kernel/cpufeature.c | 2 +- 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 1d39efe2b940..0e1909ac5947 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -291,6 +291,22 @@ config NONPORTABLE =20 If unsure, say N. =20 +config NO_RISCV_ISA_FALLBACK + bool "Permit falling back to parsing riscv,isa for extension support" + depends on NONPORTABLE + help + Parsing the "riscv,isa" devicetree property has been deprecated and + replaced by a list of explicitly defined strings. For compatibility + with existing platforms, the kernel will fall back to parsing the + "riscv,isa" property if the replacements are not found. + + Selecting Y here will result in a kernel without this fallback, and + will not work on platforms where the devicetree does not contain the + replacement properties of "riscv,isa-base" and + "riscv,isa-extensions". Please see the dt-binding, located at + Documentation/devicetree/bindings/riscv/extensions.yaml for details + on the replacement properties. + choice prompt "Base ISA" default ARCH_RV64I diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 9a4f4a23afcd..86a1d98b8b3b 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -81,6 +81,9 @@ int riscv_early_of_processor_hartid(struct device_node *n= ode, unsigned long *har return 0; =20 old_interface: + if (IS_ENABLED(CONFIG_NO_RISCV_ISA_FALLBACK)) + return -ENODEV; + if (of_property_read_string(node, "riscv,isa", &isa)) { pr_warn("CPU with hartid=3D%lu has no \"riscv,isa-base\" or \"riscv,isa\= " property\n", *hart); diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 2c4503fa984f..f6fb18d2af84 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -490,7 +490,7 @@ void __init riscv_fill_hwcap(void) } else { int ret =3D riscv_fill_hwcap_from_ext_list(isa2hwcap); =20 - if (ret) { + if (ret && !IS_ENABLED(CONFIG_NO_RISCV_ISA_FALLBACK)) { pr_info("Falling back to deprecated \"riscv,isa\"\n"); riscv_fill_hwcap_from_isa_string(isa2hwcap); } --=20 2.40.1