From nobody Thu Nov 14 06:11:35 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 071BAEB64DC for ; Tue, 27 Jun 2023 21:46:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230163AbjF0Vqb (ORCPT ); Tue, 27 Jun 2023 17:46:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230431AbjF0Vq1 (ORCPT ); Tue, 27 Jun 2023 17:46:27 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0EB3E272D; Tue, 27 Jun 2023 14:46:27 -0700 (PDT) Received: from notapiano.myfiosgateway.com (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 6AD66660716B; Tue, 27 Jun 2023 22:46:23 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1687902385; bh=Ud2ruCQMrs0y4/oeVi64N6XaZrL6MD3Lu7ndY/b2YiA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OX4G7uSaFVf1Rp+S5iCmBZuljKzbtG39+f4Fu4sgj7vuOZ7zbTVP7mIOXjSiMkzkx KnTEnsqh7eKb7K1um2WAEez1k6/QVYbHo+OMfYILQnycfc5DrPJLt7Nbjx6C0E5fwR t5ADZ0wYP8AvqGKNNINOQxQPSD4Z4Elyv+MHgyuoqr3FrkgkcqSc8twxoX0cHzwKKz /crOOTx+3AnC3X2hajK3C8lWRr1o73oTf6aNm7EkGpWn3+MhEJYrvFFZFsdTDPvmXu NCaH3PGvFIPxu2pqu4Spj9YLyK3Oj/fb/qhZZNhYw6SLFf6bFIiO1mPLIJK9vlB4W/ /656KnuIXCOfQ== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger , Hans Verkuil Cc: kernel@collabora.com, AngeloGioacchino Del Regno , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Andrew-CT Chen , Conor Dooley , Krzysztof Kozlowski , Mauro Carvalho Chehab , Rob Herring , Tiffany Lin , Yunfei Dong , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 1/7] media: dt-bindings: mediatek,vcodec: Allow single clock for mt8183 Date: Tue, 27 Jun 2023 17:45:51 -0400 Message-ID: <20230627214615.1503901-2-nfraprado@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230627214615.1503901-1-nfraprado@collabora.com> References: <20230627214615.1503901-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org MT8173 and MT8183 have different clocks, and consequently clock-names. Relax the number of clocks and set clock-names based on compatible. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger Reviewed-by: Krzysztof Kozlowski Signed-off-by: N=C3=ADcolas F. R. A. Prado --- (no changes since v3) Changes in v3: - Reintroduced this commit from v1 since the active clock is no longer used. - Further constrained clocks as suggested in v1. .../media/mediatek,vcodec-decoder.yaml | 37 ++++++++++++++----- 1 file changed, 28 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-decode= r.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.ya= ml index fad59b486d5d..1506d2693f7d 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml @@ -27,18 +27,12 @@ properties: maxItems: 1 =20 clocks: + minItems: 1 maxItems: 8 =20 clock-names: - items: - - const: vcodecpll - - const: univpll_d2 - - const: clk_cci400_sel - - const: vdec_sel - - const: vdecpll - - const: vencpll - - const: venc_lt_sel - - const: vdec_bus_clk_src + minItems: 1 + maxItems: 8 =20 assigned-clocks: true =20 @@ -88,6 +82,15 @@ allOf: required: - mediatek,scp =20 + properties: + clocks: + minItems: 1 + maxItems: 1 + + clock-names: + items: + - const: vdec + - if: properties: compatible: @@ -99,6 +102,22 @@ allOf: required: - mediatek,vpu =20 + properties: + clocks: + minItems: 8 + maxItems: 8 + + clock-names: + items: + - const: vcodecpll + - const: univpll_d2 + - const: clk_cci400_sel + - const: vdec_sel + - const: vdecpll + - const: vencpll + - const: venc_lt_sel + - const: vdec_bus_clk_src + additionalProperties: false =20 examples: --=20 2.41.0 From nobody Thu Nov 14 06:11:35 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C8D4C001B3 for ; Tue, 27 Jun 2023 21:46:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230128AbjF0Vqh (ORCPT ); Tue, 27 Jun 2023 17:46:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44166 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230465AbjF0Vqa (ORCPT ); Tue, 27 Jun 2023 17:46:30 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A070F2706; Tue, 27 Jun 2023 14:46:29 -0700 (PDT) Received: from notapiano.myfiosgateway.com (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 2B29A660716C; Tue, 27 Jun 2023 22:46:26 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1687902388; bh=9a46aNnESj501/E03oYlm9sAjEXaazXllJOV13stIS8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oJZYJJHlniKS48gum0sgefsmbP8xR8Oa/MOZCbnM02KPe/5T9EJyWJr1G00Xj7kmG oXP0mPaRlV/gUGtbzvXWB5Rwjf4jDWxTjh6kA3u7cb1w5NQ2Z2+042i4tSmRiv+msf 8Fhc/oRhY4vpUYckZukQOQlWoSpuOvYMyUeBxBU6DRJKFmyRpxMVtEXMYPdf6uH7VF X2RW78Ua55vZSEaHEjG6PvTOp39EEWQVE8N7A2TeHvizyWTBi/qmC9OvNwsZrujzjO e13JzXrZTVwrdwxD9nsE8N6QaY2JTP7Vyw4DcN78NoGKfJoy3db5Ku25x6hqS/97fh LjJOChpCdgz0w== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger , Hans Verkuil Cc: kernel@collabora.com, AngeloGioacchino Del Regno , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Andrew-CT Chen , Conor Dooley , Krzysztof Kozlowski , Mauro Carvalho Chehab , Rob Herring , Tiffany Lin , Yunfei Dong , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 2/7] media: dt-bindings: mediatek,vcodec: Don't require assigned-clocks Date: Tue, 27 Jun 2023 17:45:52 -0400 Message-ID: <20230627214615.1503901-3-nfraprado@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230627214615.1503901-1-nfraprado@collabora.com> References: <20230627214615.1503901-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On MT8183 it's not necessary to configure the parent for the clocks. Remove the assigned-clocks and assigned-clock-parents from the required list. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Matthias Brugger Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- (no changes since v1) .../devicetree/bindings/media/mediatek,vcodec-decoder.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-decode= r.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.ya= ml index 1506d2693f7d..1e56ece44aee 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml @@ -67,8 +67,6 @@ required: - clocks - clock-names - iommus - - assigned-clocks - - assigned-clock-parents =20 allOf: - if: --=20 2.41.0 From nobody Thu Nov 14 06:11:35 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2A47EB64DC for ; Tue, 27 Jun 2023 21:46:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230205AbjF0Vql (ORCPT ); Tue, 27 Jun 2023 17:46:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230496AbjF0Vqf (ORCPT ); Tue, 27 Jun 2023 17:46:35 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63EE42976; Tue, 27 Jun 2023 14:46:32 -0700 (PDT) Received: from notapiano.myfiosgateway.com (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id DDAE8660716D; Tue, 27 Jun 2023 22:46:28 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1687902391; bh=6/vcaD7vHgxFo563mcGSzADfJpcIhcKqIWXtcXlmyyg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QRX7Y7FJczspzvg1lbr4hdqkL2V2n45ngk1lc9CQScHa7bQQYNO6BXWJjQ4mdUwxJ /9TsURMA8BOHYMi0/Fu7ThKFO5dXWGl02FiKipJReDlL/oU340MrHwcADXNhUXbN/R Ar7nAy7hwB1n1fFG9oX9YJpKbYno+7ObS6bmEJ7NFPjGR+Q/RZB5dHbw+Oc4zx4OZf SRs4akW6zCFzxlDCOOtajVTuPnyjEhgqqkQP13tDy9KBzV7UfY0ncA2U/xN6KHret8 F4QmMtU7qTp035vpOCTPfbJKxor8dFaC9NlV0UgyerJSZhXuNjSgFzwVjB+KshnJ1C jn/wsh0jiqtcQ== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger , Hans Verkuil Cc: kernel@collabora.com, AngeloGioacchino Del Regno , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Andrew-CT Chen , Conor Dooley , Krzysztof Kozlowski , Mauro Carvalho Chehab , Rob Herring , Tiffany Lin , Yunfei Dong , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 3/7] media: dt-bindings: mediatek,vcodec: Remove VDEC_SYS register space Date: Tue, 27 Jun 2023 17:45:53 -0400 Message-ID: <20230627214615.1503901-4-nfraprado@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230627214615.1503901-1-nfraprado@collabora.com> References: <20230627214615.1503901-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The binding expects the first register space to be VDEC_SYS. However this register space is already assigned to a different node on both MT8173 and MT8183: a clock-controller node called 'vdecsys' which is also a syscon. In order to resolve the overlapping address ranges, remove the VDEC_SYS register space from the video decoder, and add a new property to hold the phandle to the syscon, so that iospace can still be handled. Also add reg-names to be able to tell that this new register schema is used, so the driver can keep backward compatibility. Signed-off-by: N=C3=ADcolas F. R. A. Prado --- Changes in v4: - Removed VDEC_SYS reg from mt8173 as well - Reworded commit Changes in v3: - Removed the active clock - Added a mediatek,vdecsys syscon property Changes in v2: - Merged with patch 1 (media: dt-bindings: mediatek,vcodec: Allow single clock for mt8183) to avoid changing number of clocks twice - Added maxItems to reg-names - Constrained clocks for each compatible - Reordered properties for each compatible .../media/mediatek,vcodec-decoder.yaml | 28 ++++++++++++++++--- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-decode= r.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.ya= ml index 1e56ece44aee..b401c67e3ba0 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml @@ -21,7 +21,22 @@ properties: - mediatek,mt8183-vcodec-dec =20 reg: - maxItems: 12 + minItems: 11 + maxItems: 11 + + reg-names: + items: + - const: misc + - const: ld + - const: top + - const: cm + - const: ad + - const: av + - const: pp + - const: hwd + - const: hwq + - const: hwb + - const: hwg =20 interrupts: maxItems: 1 @@ -60,6 +75,10 @@ properties: description: Describes point to scp. =20 + mediatek,vdecsys: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the vdecsys syscon node. + required: - compatible - reg @@ -67,6 +86,7 @@ required: - clocks - clock-names - iommus + - mediatek,vdecsys =20 allOf: - if: @@ -126,10 +146,9 @@ examples: #include #include =20 - vcodec_dec: vcodec@16000000 { + vcodec_dec: vcodec@16020000 { compatible =3D "mediatek,mt8173-vcodec-dec"; - reg =3D <0x16000000 0x100>, /*VDEC_SYS*/ - <0x16020000 0x1000>, /*VDEC_MISC*/ + reg =3D <0x16020000 0x1000>, /*VDEC_MISC*/ <0x16021000 0x800>, /*VDEC_LD*/ <0x16021800 0x800>, /*VDEC_TOP*/ <0x16022000 0x1000>, /*VDEC_CM*/ @@ -150,6 +169,7 @@ examples: <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; mediatek,vpu =3D <&vpu>; + mediatek,vdecsys =3D <&vdecsys>; power-domains =3D <&scpsys MT8173_POWER_DOMAIN_VDEC>; clocks =3D <&apmixedsys CLK_APMIXED_VCODECPLL>, <&topckgen CLK_TOP_UNIVPLL_D2>, --=20 2.41.0 From nobody Thu Nov 14 06:11:35 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC66EEB64D9 for ; Tue, 27 Jun 2023 21:46:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230265AbjF0Vqp (ORCPT ); Tue, 27 Jun 2023 17:46:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44260 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229915AbjF0Vqg (ORCPT ); Tue, 27 Jun 2023 17:46:36 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A12512D44; Tue, 27 Jun 2023 14:46:34 -0700 (PDT) Received: from notapiano.myfiosgateway.com (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 9E1786607165; Tue, 27 Jun 2023 22:46:31 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1687902393; bh=qe7GxwnSjbAfRY/6FkdfYaxWhyQir3XZsikITphI9wM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bdHidwzklkAhbmUpYjA44CW3qrHkIZZVA7RjXR3Z/QIt8traaERt3QwwvkUyb/Qev 5+rBFDjPiEs2wxzb32LmsViFA7e7zWPYwjfG2eBADE8bo82zAOPEENI+KtscCjgJ+L NGhFrfHi5IgwvM+ADyCynZARqJZNPYsRVyb9szXItCjrHoNjnTRHf8LZrlgmEkejRu 8SN2h6ryZrVMAoPN2ZK8PireVNbcbJIr+g8E0ARgNd49Xm+n3TlBJKf+56iM5sVmzq hof9n+5xgFAkeVJl+7JG+DxhCLvbEXi51oN5go1ZVErKVx6wcC76A44ADqcocuIWvR B8JuhVQMWVSaw== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger , Hans Verkuil Cc: kernel@collabora.com, AngeloGioacchino Del Regno , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Andrew-CT Chen , Mauro Carvalho Chehab , Tiffany Lin , Yunfei Dong , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 4/7] media: mediatek: vcodec: Define address for VDEC_HW_ACTIVE Date: Tue, 27 Jun 2023 17:45:54 -0400 Message-ID: <20230627214615.1503901-5-nfraprado@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230627214615.1503901-1-nfraprado@collabora.com> References: <20230627214615.1503901-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The VDEC_HW_ACTIVE bit is located at offset 0, bit 4 of the VDECSYS iospace. Only the mask was previously defined, with the address being implicit. Explicitly define the address, and append a '_MASK' suffix to the mask, to make accesses to this bit clearer. This commit brings no functional change. Signed-off-by: N=C3=ADcolas F. R. A. Prado --- Changes in v4: - Made use of BIT() macro for mask Changes in v3: - Added this commit drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c | 4 ++-- drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.c | 4 ++-- drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.h | 3 ++- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c b/= drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c index d41f2121b94f..83780d29a9cf 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c @@ -50,8 +50,8 @@ static irqreturn_t mtk_vcodec_dec_irq_handler(int irq, vo= id *priv) ctx =3D mtk_vcodec_get_curr_ctx(dev, MTK_VDEC_CORE); =20 /* check if HW active or not */ - cg_status =3D readl(dev->reg_base[0]); - if ((cg_status & VDEC_HW_ACTIVE) !=3D 0) { + cg_status =3D readl(dev->reg_base[0] + VDEC_HW_ACTIVE_ADDR); + if ((cg_status & VDEC_HW_ACTIVE_MASK) !=3D 0) { mtk_v4l2_err("DEC ISR, VDEC active is not 0x0 (0x%08x)", cg_status); return IRQ_HANDLED; diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.c b/d= rivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.c index e1cb2f8dca33..41aa66c7295b 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.c @@ -75,8 +75,8 @@ static irqreturn_t mtk_vdec_hw_irq_handler(int irq, void = *priv) ctx =3D mtk_vcodec_get_curr_ctx(dev->main_dev, dev->hw_idx); =20 /* check if HW active or not */ - cg_status =3D readl(dev->reg_base[VDEC_HW_SYS]); - if (cg_status & VDEC_HW_ACTIVE) { + cg_status =3D readl(dev->reg_base[VDEC_HW_SYS] + VDEC_HW_ACTIVE_ADDR); + if (cg_status & VDEC_HW_ACTIVE_MASK) { mtk_v4l2_err("vdec active is not 0x0 (0x%08x)", cg_status); return IRQ_HANDLED; diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.h b/d= rivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.h index 36faa8d9d681..ff250e3be78e 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.h @@ -12,7 +12,8 @@ =20 #include "mtk_vcodec_drv.h" =20 -#define VDEC_HW_ACTIVE 0x10 +#define VDEC_HW_ACTIVE_ADDR 0x0 +#define VDEC_HW_ACTIVE_MASK BIT(4) #define VDEC_IRQ_CFG 0x11 #define VDEC_IRQ_CLR 0x10 #define VDEC_IRQ_CFG_REG 0xa4 --=20 2.41.0 From nobody Thu Nov 14 06:11:35 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 435ADEB64DC for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1687902395; bh=7Yv0RLEqwrkwHViyfVu6oNggvzTGRKyaB317MVjZZKA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bCt6Wnh0qQyBkJ/zP4lYYrsd7dAsxqaPhyFzzqJyrmx4f3SCG0p+aO2Gi+Boqi+G0 JHlT68vKq1OFsrCtXIBuC3Cc4eoE+qXCr/R4nX1PjopFMYi3cmhveCut23B9hS7ONa mNpn162Q2W8XWmDjPvLYBTq6ijOaeqs5o8xCCIOUC+9/aYQuzNsr63I1IDMPyjzzeB PWZJyzhx5Soz2uoxEW/Pz+BrYHEW1Iue0+yu7H+4krGsiZ12wS8WHvBRs+nuKmapWW LSNdFYyUb3qKWwBajZ7pPwroP0kjmwTEQDmMq2cKk59WgvtSUo+m8/5s3+vDb0+8IZ nbZq0gVinZAtg== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger , Hans Verkuil Cc: kernel@collabora.com, AngeloGioacchino Del Regno , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Andrew-CT Chen , Mauro Carvalho Chehab , Tiffany Lin , Yunfei Dong , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 5/7] media: mediatek: vcodec: Read HW active status from syscon Date: Tue, 27 Jun 2023 17:45:55 -0400 Message-ID: <20230627214615.1503901-6-nfraprado@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230627214615.1503901-1-nfraprado@collabora.com> References: <20230627214615.1503901-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Remove the requirement of a VDEC_SYS reg iospace for both MT8173 and MT8183. To achieve that, rely on a vdecsys syscon to be passed through the DT, and use it to directly read the VDEC_HW_ACTIVE bit during IRQ handling to check whether the HW is active. Also update the VP8 stateful decoder to use the syscon, if present, for writes to VDEC_SYS. The old behavior is still present when reg-names aren't supplied, as to keep backward compatibility. Signed-off-by: N=C3=ADcolas F. R. A. Prado --- Changes in v4: - Added new helper and updated VP8 stateful decoder to use it, so the syscon can also be used by mt8173 - Made handling cleaner - Reworded commit Changes in v3: - Switched handling of VDEC_HW_ACTIVE to use a syscon instead of the 'active' clock - Reworded commit - Removed changes to subdev part of driver, since they aren't used by MT8183 .../mediatek/vcodec/mtk_vcodec_dec_drv.c | 76 ++++++++++++++++--- .../platform/mediatek/vcodec/mtk_vcodec_drv.h | 1 + .../mediatek/vcodec/mtk_vcodec_util.c | 15 ++++ .../mediatek/vcodec/mtk_vcodec_util.h | 2 + .../mediatek/vcodec/vdec/vdec_vp8_if.c | 10 +-- 5 files changed, 86 insertions(+), 18 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c b/= drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c index 83780d29a9cf..d83c2eb6f118 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c @@ -8,10 +8,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -38,22 +40,30 @@ static int mtk_vcodec_get_hw_count(struct mtk_vcodec_de= v *dev) } } =20 +static bool mtk_vcodec_is_hw_active(struct mtk_vcodec_dev *dev) +{ + u32 cg_status; + + if (dev->vdecsys_regmap) + return !regmap_test_bits(dev->vdecsys_regmap, VDEC_HW_ACTIVE_ADDR, + VDEC_HW_ACTIVE_MASK); + + cg_status =3D readl(dev->reg_base[VDEC_SYS] + VDEC_HW_ACTIVE_ADDR); + return !FIELD_GET(VDEC_HW_ACTIVE_MASK, cg_status); +} + static irqreturn_t mtk_vcodec_dec_irq_handler(int irq, void *priv) { struct mtk_vcodec_dev *dev =3D priv; struct mtk_vcodec_ctx *ctx; - u32 cg_status =3D 0; unsigned int dec_done_status =3D 0; void __iomem *vdec_misc_addr =3D dev->reg_base[VDEC_MISC] + VDEC_IRQ_CFG_REG; =20 ctx =3D mtk_vcodec_get_curr_ctx(dev, MTK_VDEC_CORE); =20 - /* check if HW active or not */ - cg_status =3D readl(dev->reg_base[0] + VDEC_HW_ACTIVE_ADDR); - if ((cg_status & VDEC_HW_ACTIVE_MASK) !=3D 0) { - mtk_v4l2_err("DEC ISR, VDEC active is not 0x0 (0x%08x)", - cg_status); + if (!mtk_vcodec_is_hw_active(dev)) { + mtk_v4l2_err("DEC ISR, VDEC active is not 0x0"); return IRQ_HANDLED; } =20 @@ -82,6 +92,33 @@ static int mtk_vcodec_get_reg_bases(struct mtk_vcodec_de= v *dev) { struct platform_device *pdev =3D dev->plat_dev; int reg_num, i; + struct resource *res; + bool has_vdecsys_reg; + static const char * const mtk_dec_reg_names[] =3D { + "misc", + "ld", + "top", + "cm", + "ad", + "av", + "pp", + "hwd", + "hwq", + "hwb", + "hwg" + }; + + /* + * If we have reg-names in devicetree, this means that we're on a new + * register organization, which implies that the VDEC_SYS iospace gets + * R/W through a syscon (regmap). + * Here we try to get the "misc" iostart only to check if we have reg-nam= es + */ + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "misc"); + if (res) + has_vdecsys_reg =3D false; + else + has_vdecsys_reg =3D true; =20 /* Sizeof(u32) * 4 bytes for each register base. */ reg_num =3D of_property_count_elems_of_size(pdev->dev.of_node, "reg", @@ -91,12 +128,29 @@ static int mtk_vcodec_get_reg_bases(struct mtk_vcodec_= dev *dev) return -EINVAL; } =20 - for (i =3D 0; i < reg_num; i++) { - dev->reg_base[i] =3D devm_platform_ioremap_resource(pdev, i); - if (IS_ERR(dev->reg_base[i])) - return PTR_ERR(dev->reg_base[i]); + if (has_vdecsys_reg) { + for (i =3D 0; i < reg_num; i++) { + dev->reg_base[i] =3D devm_platform_ioremap_resource(pdev, i); + if (IS_ERR(dev->reg_base[i])) + return PTR_ERR(dev->reg_base[i]); + + mtk_v4l2_debug(2, "reg[%d] base=3D%p", i, dev->reg_base[i]); + } + } else { + for (i =3D 0; i < reg_num; i++) { + dev->reg_base[i+1] =3D devm_platform_ioremap_resource_byname(pdev, mtk_= dec_reg_names[i]); + if (IS_ERR(dev->reg_base[i+1])) + return PTR_ERR(dev->reg_base[i+1]); =20 - mtk_v4l2_debug(2, "reg[%d] base=3D%p", i, dev->reg_base[i]); + mtk_v4l2_debug(2, "reg[%d] base=3D%p", i+1, dev->reg_base[i+1]); + } + + dev->vdecsys_regmap =3D syscon_regmap_lookup_by_phandle(pdev->dev.of_nod= e, + "mediatek,vdecsys"); + if (IS_ERR(dev->vdecsys_regmap)) { + dev_err(&pdev->dev, "Missing mediatek,vdecsys property"); + return PTR_ERR(dev->vdecsys_regmap); + } } =20 return 0; diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h index f17d67e781c9..0b430936f67d 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h @@ -489,6 +489,7 @@ struct mtk_vcodec_dev { void __iomem *reg_base[NUM_MAX_VCODEC_REG_BASE]; const struct mtk_vcodec_dec_pdata *vdec_pdata; const struct mtk_vcodec_enc_pdata *venc_pdata; + struct regmap *vdecsys_regmap; =20 struct mtk_vcodec_fw *fw_handler; =20 diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.c b/dri= vers/media/platform/mediatek/vcodec/mtk_vcodec_util.c index f214e6f67005..8aaa5eb45444 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.c @@ -8,6 +8,7 @@ #include #include #include +#include =20 #include "mtk_vcodec_dec_hw.h" #include "mtk_vcodec_drv.h" @@ -34,6 +35,20 @@ void __iomem *mtk_vcodec_get_reg_addr(struct mtk_vcodec_= ctx *data, } EXPORT_SYMBOL(mtk_vcodec_get_reg_addr); =20 +int mtk_vcodec_write_vdecsys(struct mtk_vcodec_ctx *ctx, unsigned int reg, + unsigned int val) +{ + struct mtk_vcodec_dev *dev =3D ctx->dev; + + if (dev->vdecsys_regmap) + return regmap_write(dev->vdecsys_regmap, reg, val); + + writel(val, dev->reg_base[VDEC_SYS] + reg); + + return 0; +} +EXPORT_SYMBOL(mtk_vcodec_write_vdecsys); + int mtk_vcodec_mem_alloc(struct mtk_vcodec_ctx *data, struct mtk_vcodec_mem *mem) { diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.h b/dri= vers/media/platform/mediatek/vcodec/mtk_vcodec_util.h index 88d389b65f13..c8bb4fc5153f 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.h @@ -70,6 +70,8 @@ extern int mtk_vcodec_dbg; =20 void __iomem *mtk_vcodec_get_reg_addr(struct mtk_vcodec_ctx *data, unsigned int reg_idx); +int mtk_vcodec_write_vdecsys(struct mtk_vcodec_ctx *ctx, unsigned int reg, + unsigned int val); int mtk_vcodec_mem_alloc(struct mtk_vcodec_ctx *data, struct mtk_vcodec_mem *mem); void mtk_vcodec_mem_free(struct mtk_vcodec_ctx *data, diff --git a/drivers/media/platform/mediatek/vcodec/vdec/vdec_vp8_if.c b/dr= ivers/media/platform/mediatek/vcodec/vdec/vdec_vp8_if.c index 88c046731754..2592fa37b4c8 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec/vdec_vp8_if.c +++ b/drivers/media/platform/mediatek/vcodec/vdec/vdec_vp8_if.c @@ -91,7 +91,6 @@ struct vdec_vp8_vsi { =20 /** * struct vdec_vp8_hw_reg_base - HW register base - * @sys : base address for sys * @misc : base address for misc * @ld : base address for ld * @top : base address for top @@ -100,7 +99,6 @@ struct vdec_vp8_vsi { * @hwb : base address for hwb */ struct vdec_vp8_hw_reg_base { - void __iomem *sys; void __iomem *misc; void __iomem *ld; void __iomem *top; @@ -170,7 +168,6 @@ static void get_hw_reg_base(struct vdec_vp8_inst *inst) inst->reg_base.top =3D mtk_vcodec_get_reg_addr(inst->ctx, VDEC_TOP); inst->reg_base.cm =3D mtk_vcodec_get_reg_addr(inst->ctx, VDEC_CM); inst->reg_base.hwd =3D mtk_vcodec_get_reg_addr(inst->ctx, VDEC_HWD); - inst->reg_base.sys =3D mtk_vcodec_get_reg_addr(inst->ctx, VDEC_SYS); inst->reg_base.misc =3D mtk_vcodec_get_reg_addr(inst->ctx, VDEC_MISC); inst->reg_base.ld =3D mtk_vcodec_get_reg_addr(inst->ctx, VDEC_LD); inst->reg_base.hwb =3D mtk_vcodec_get_reg_addr(inst->ctx, VDEC_HWB); @@ -222,17 +219,16 @@ static void read_hw_segmentation_data(struct vdec_vp8= _inst *inst) static void enable_hw_rw_function(struct vdec_vp8_inst *inst) { u32 val =3D 0; - void __iomem *sys =3D inst->reg_base.sys; void __iomem *misc =3D inst->reg_base.misc; void __iomem *ld =3D inst->reg_base.ld; void __iomem *hwb =3D inst->reg_base.hwb; void __iomem *hwd =3D inst->reg_base.hwd; =20 - writel(0x1, sys + VP8_RW_CKEN_SET); + mtk_vcodec_write_vdecsys(inst->ctx, VP8_RW_CKEN_SET, 0x1); writel(0x101, ld + VP8_WO_VLD_SRST); writel(0x101, hwb + VP8_WO_VLD_SRST); =20 - writel(1, sys); + mtk_vcodec_write_vdecsys(inst->ctx, 0, 0x1); val =3D readl(misc + VP8_RW_MISC_SRST); writel((val & 0xFFFFFFFE), misc + VP8_RW_MISC_SRST); =20 @@ -241,7 +237,7 @@ static void enable_hw_rw_function(struct vdec_vp8_inst = *inst) writel(0x71201100, misc + VP8_RW_MISC_FUNC_CON); writel(0x0, ld + VP8_WO_VLD_SRST); writel(0x0, hwb + VP8_WO_VLD_SRST); - writel(0x1, sys + VP8_RW_DCM_CON); + mtk_vcodec_write_vdecsys(inst->ctx, VP8_RW_DCM_CON, 0x1); writel(0x1, misc + VP8_RW_MISC_DCM_CON); writel(0x1, hwd + VP8_RW_VP8_CTRL); } --=20 2.41.0 From nobody Thu Nov 14 06:11:35 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8222C001B0 for ; Tue, 27 Jun 2023 21:47:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231139AbjF0VrH (ORCPT ); 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b=BEmknKh9uXv6AKN+kRQcmsKlfxopmDPOGU9wtjVeDOZByqNTKWgbBrpoNoUI/tJ/o JpCg6mqBUt8NpYy0cSQujxUuCgPiNI3k/w+SlZjOFZQA73DrJK7NKQNNUvLNnzMKIh okq1nDuFjUBiz8c3QC38vE2njRckaIzgmn5iKFiGOlClmGv1JXBoem+gJEo8SmLlgt s6UXFaOjHpIM10NU4NDzidkVlCX00STy5mojjPJmz999jEU4XsYr84LXg81DzHNPs8 VzyCm1mPcA+vQlPjma5/jMcJoS0Ec11mnN6yePr+MifjF3aj6FVbQMbvN3tdkBo7lr kvPOrsasFsA7g== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger , Hans Verkuil Cc: kernel@collabora.com, AngeloGioacchino Del Regno , =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 6/7] arm64: dts: mediatek: mt8173: Drop VDEC_SYS reg from decoder Date: Tue, 27 Jun 2023 17:45:56 -0400 Message-ID: <20230627214615.1503901-7-nfraprado@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230627214615.1503901-1-nfraprado@collabora.com> References: <20230627214615.1503901-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Remove the VDEC_SYS register space from the decoder, so that the node address becomes that of VDEC_MISC, solving the long-standing conflicting addresses between this node and the vdecsys clock-controller node: arch/arm64/boot/dts/mediatek/mt8173.dtsi:1365.38-1369.5: Warning (unique_un= it_address_if_enabled): /soc/clock-controller@16000000: duplicate unit-addr= ess (also used in node /soc/vcodec@16000000) The driver makes use of this register space, however, so also add a phandle to the VDEC_SYS syscon to maintain functionality. Signed-off-by: N=C3=ADcolas F. R. A. Prado --- Changes in v4: - Added this commit arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts= /mediatek/mt8173.dtsi index c47d7d900f28..cac4cd0a0320 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1368,10 +1368,9 @@ vdecsys: clock-controller@16000000 { #clock-cells =3D <1>; }; =20 - vcodec_dec: vcodec@16000000 { + vcodec_dec: vcodec@16020000 { compatible =3D "mediatek,mt8173-vcodec-dec"; - reg =3D <0 0x16000000 0 0x100>, /* VDEC_SYS */ - <0 0x16020000 0 0x1000>, /* VDEC_MISC */ + reg =3D <0 0x16020000 0 0x1000>, /* VDEC_MISC */ <0 0x16021000 0 0x800>, /* VDEC_LD */ <0 0x16021800 0 0x800>, /* VDEC_TOP */ <0 0x16022000 0 0x1000>, /* VDEC_CM */ @@ -1382,6 +1381,8 @@ vcodec_dec: vcodec@16000000 { <0 0x16027000 0 0x800>, /* VDEC_HWQ */ <0 0x16027800 0 0x800>, /* VDEC_HWB */ <0 0x16028400 0 0x400>; /* VDEC_HWG */ + reg-names =3D "misc", "ld", "top", "cm", "ad", "av", "pp", + "hwd", "hwq", "hwb", "hwg"; interrupts =3D ; iommus =3D <&iommu M4U_PORT_HW_VDEC_MC_EXT>, <&iommu M4U_PORT_HW_VDEC_PP_EXT>, @@ -1392,6 +1393,7 @@ vcodec_dec: vcodec@16000000 { <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; mediatek,vpu =3D <&vpu>; + mediatek,vdecsys =3D <&vdecsys>; power-domains =3D <&spm MT8173_POWER_DOMAIN_VDEC>; clocks =3D <&apmixedsys CLK_APMIXED_VCODECPLL>, <&topckgen CLK_TOP_UNIVPLL_D2>, --=20 2.41.0 From nobody Thu Nov 14 06:11:35 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86FF7EB64D9 for ; Tue, 27 Jun 2023 21:47:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231233AbjF0VrL (ORCPT ); Tue, 27 Jun 2023 17:47:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230522AbjF0VrD (ORCPT ); Tue, 27 Jun 2023 17:47:03 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76C642D60; Tue, 27 Jun 2023 14:46:41 -0700 (PDT) Received: from notapiano.myfiosgateway.com (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 405646607064; Tue, 27 Jun 2023 22:46:38 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1687902400; bh=dDGAXyQUfLadYEQWCBPnnvjplu6XpXRhFI0R4wZeknQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dSKXhDd1emsZa4HhNT1tcgAMDFHBcBmlnRvmDAd9gL2AaITNgAboDNXgt2YXunMAQ ZRAHCsLcxy7k1dy28NtOOUdRwjCvQTzU1I+GmkIB6tYXG+p2kzqW3x9wgZCuWApjxw 3yG+gAYCE0m+lny6J3QOrYMKZxTsqq5pzxijphIoP9otTEo0Y9D6vIzQofs07wr/wF IQremBG9SIWyWjQ+lqPDI3RRc0jhevbyjC/phJSG2DP9WC5YCSBV9fXsNgtNeAu1GA PjxYbtDMnhMhT7HBz0NVvBU9YFSX5I1i3icYyvGFAmrRS8apBBmA1LKNw4U/WHkPi5 /mleiZth/OsKw== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger , Hans Verkuil Cc: kernel@collabora.com, AngeloGioacchino Del Regno , Yunfei Dong , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 7/7] arm64: dts: mediatek: mt8183: Add decoder Date: Tue, 27 Jun 2023 17:45:57 -0400 Message-ID: <20230627214615.1503901-8-nfraprado@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230627214615.1503901-1-nfraprado@collabora.com> References: <20230627214615.1503901-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Yunfei Dong Add node for the hardware decoder present on the MT8183 SoC. Signed-off-by: Yunfei Dong Signed-off-by: Qianqian Yan Signed-off-by: Frederic Chen Signed-off-by: Alexandre Courbot Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- (no changes since v3) Changes in v3: - Dropped 'active' clock and added the 'mediatek,vdecsys' syscon phandle property instead Changes in v2: - Reformatted reg-names to fit in fewer lines arch/arm64/boot/dts/mediatek/mt8183.dtsi | 30 ++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts= /mediatek/mt8183.dtsi index 5169779d01df..4144f1ed3ff0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -2019,6 +2019,36 @@ vdecsys: syscon@16000000 { #clock-cells =3D <1>; }; =20 + vcodec_dec: video-codec@16020000 { + compatible =3D "mediatek,mt8183-vcodec-dec"; + reg =3D <0 0x16020000 0 0x1000>, /* VDEC_MISC */ + <0 0x16021000 0 0x800>, /* VDEC_VLD */ + <0 0x16021800 0 0x800>, /* VDEC_TOP */ + <0 0x16022000 0 0x1000>, /* VDEC_MC */ + <0 0x16023000 0 0x1000>, /* VDEC_AVCVLD */ + <0 0x16024000 0 0x1000>, /* VDEC_AVCMV */ + <0 0x16025000 0 0x1000>, /* VDEC_PP */ + <0 0x16026800 0 0x800>, /* VP8_VD */ + <0 0x16027000 0 0x800>, /* VP6_VD */ + <0 0x16027800 0 0x800>, /* VP8_VL */ + <0 0x16028400 0 0x400>; /* VP9_VD */ + reg-names =3D "misc", "ld", "top", "cm", "ad", "av", "pp", + "hwd", "hwq", "hwb", "hwg"; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_HW_VDEC_MC_EXT>, + <&iommu M4U_PORT_HW_VDEC_PP_EXT>, + <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, + <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, + <&iommu M4U_PORT_HW_VDEC_PPWRAP_EXT>; + mediatek,scp =3D <&scp>; + mediatek,vdecsys =3D <&vdecsys>; + power-domains =3D <&spm MT8183_POWER_DOMAIN_VDEC>; + clocks =3D <&vdecsys CLK_VDEC_VDEC>; + clock-names =3D "vdec"; + }; + larb1: larb@16010000 { compatible =3D "mediatek,mt8183-smi-larb"; reg =3D <0 0x16010000 0 0x1000>; --=20 2.41.0