From nobody Thu Nov 14 17:10:09 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47474C001B3 for ; Tue, 27 Jun 2023 06:40:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229578AbjF0Gkg (ORCPT ); Tue, 27 Jun 2023 02:40:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229790AbjF0GkG (ORCPT ); Tue, 27 Jun 2023 02:40:06 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B21C1FD7; Mon, 26 Jun 2023 23:40:04 -0700 (PDT) X-UUID: 6dd44a3c14b511eeb20a276fd37b9834-20230627 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=z8zL/tMj6ZU0jCH2maGtMUGXC5yMFUYAvn6bFT2xq0c=; b=pjt8zezOsnADgUhLOIx4MQncWyWZ761JO78e6jv8mD41fX/99fnOgCs1LL4S/16RBSR/QUN3n5RI/8/5ILEDx8Lw2k9ls0sAqDgvAkajpcXGT0EO27zYS/5h1GesLKIuVi/7+LfZ7Mzu7Jw5pN8L5UKqhqADuXCZs4DTGLKFNOc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.27,REQID:57e57ac1-bd99-45b2-9317-068945ba9b35,IP:0,U RL:0,TC:0,Content:-25,EDM:25,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACT ION:release,TS:95 X-CID-INFO: VERSION:1.1.27,REQID:57e57ac1-bd99-45b2-9317-068945ba9b35,IP:0,URL :0,TC:0,Content:-25,EDM:25,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACT ION:quarantine,TS:95 X-CID-META: VersionHash:01c9525,CLOUDID:cd5b5b82-5a99-42ae-a2dd-e4afb731b474,B ulkID:2306271439577U48IHVF,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:5,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0, OSI:0,OSA:0,AV:0,LES:1,SPR:NO X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SDM,TF_CID_SPAM_ASC,TF_CID_SPAM_FAS,TF_CID_SPAM_FSD, TF_CID_SPAM_SNR X-UUID: 6dd44a3c14b511eeb20a276fd37b9834-20230627 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1854773069; Tue, 27 Jun 2023 14:39:55 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 27 Jun 2023 14:39:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 27 Jun 2023 14:39:55 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel , Rob Herring CC: , , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Shawn Sung Subject: [PATCH v5 09/14] soc: mediatek: Support reset bit mapping in mmsys driver Date: Tue, 27 Jun 2023 14:39:41 +0800 Message-ID: <20230627063946.14935-10-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230627063946.14935-1-shawn.sung@mediatek.com> References: <20230627063946.14935-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" - Reset ID must starts from 0 and be consecutive, but the reset bits in our hardware design is not continuous, some bits are left unused, we need a map to solve the problem - Use old style 1-to-1 mapping if .rst_tb is not defined Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/soc/mediatek/mtk-mmsys.c | 9 +++++++++ drivers/soc/mediatek/mtk-mmsys.h | 3 +++ 2 files changed, 12 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mm= sys.c index af4235f7a35f..a7d2a21c11b2 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -310,6 +310,15 @@ static int mtk_mmsys_reset_update(struct reset_control= ler_dev *rcdev, unsigned l u32 offset; u32 reg; =20 + if (mmsys->data->rst_tb) { + if (id >=3D mmsys->data->num_resets) { + dev_err(rcdev->dev, "Invalid reset ID: %lu (>=3D%u)\n", + id, mmsys->data->num_resets); + return -EINVAL; + } + id =3D mmsys->data->rst_tb[id]; + } + offset =3D (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32); id =3D id % MMSYS_SW_RESET_PER_REG; reg =3D mmsys->data->sw0_rst_offset + offset; diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mm= sys.h index 964b5449d672..dfbb742eaa11 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -78,6 +78,8 @@ #define DSI_SEL_IN_RDMA 0x1 #define DSI_SEL_IN_MASK 0x1 =20 +#define MMSYS_RST_NR(bank, bit) (((bank) * 32) + (bit)) + struct mtk_mmsys_routes { u32 from_comp; u32 to_comp; @@ -119,6 +121,7 @@ struct mtk_mmsys_driver_data { const struct mtk_mmsys_routes *routes; const unsigned int num_routes; const u16 sw0_rst_offset; + const u8 *rst_tb; const u32 num_resets; const bool is_vppsys; const u8 vsync_len; --=20 2.18.0