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[83.9.3.103]) by smtp.gmail.com with ESMTPSA id g7-20020a19ac07000000b004fb259a5589sm1190508lfc.104.2023.06.27.09.24.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jun 2023 09:24:54 -0700 (PDT) From: Konrad Dybcio Date: Tue, 27 Jun 2023 18:24:23 +0200 Subject: [PATCH 07/11] dt-bindings: iommu: qcom_iommu: Allow 'tbu' clock MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230627-topic-more_bindings-v1-7-6b4b6cd081e5@linaro.org> References: <20230627-topic-more_bindings-v1-0-6b4b6cd081e5@linaro.org> In-Reply-To: <20230627-topic-more_bindings-v1-0-6b4b6cd081e5@linaro.org> To: cros-qcom-dts-watchers@chromium.org, Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov , Benjamin Li , James Willcox , Joseph Gates , Stephan Gerhold , Zac Crosby , Srinivas Kandagatla , Banajit Goswami , Liam Girdwood , Mark Brown , Lee Jones , Stephen Boyd , Joerg Roedel , Will Deacon , Robin Murphy , Greg Kroah-Hartman , Xu Yang , Peng Fan , Christian Marangi , Wesley Cheng , Jun Nie , Max Chen , Shawn Guo , Vivek Gautam Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vincent Knecht , Bryan O'Donoghue , Konrad Dybcio , alsa-devel@alsa-project.org, iommu@lists.linux.dev, linux-usb@vger.kernel.org, Krzysztof Kozlowski , Leo Yan , Rob Herring , Andy Gross , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1687883074; l=1161; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=dxmGowAABZGGJvN38BvE9OivxrhsE/2mFCf47Qi+lvI=; b=wzz2xUcbFtxUiSi4ThrPFbDIaElQBro5YtXx/lBo+PD1GGVfkejB8EYDpam4TZsF1HGcnDTRP unvzC8nqkCDCKapltiz8/h5Mv3Va5gUnt0oPVF9FgChKOoZXy8L9VnG X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some IOMMUs on some platforms (there doesn't seem to be a good denominator for this) require the presence of a third clock, specifically for accessing the IOMMU's Translation Buffer Unit (TBU). Allow it. Signed-off-by: Konrad Dybcio Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/iommu/qcom,iommu.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml b/Docu= mentation/devicetree/bindings/iommu/qcom,iommu.yaml index d9fabdf930d9..3b7acb459f8e 100644 --- a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml @@ -24,14 +24,18 @@ properties: - const: qcom,msm-iommu-v1 =20 clocks: + minItems: 2 items: - description: Clock required for IOMMU register group access - description: Clock required for underlying bus access + - description: Clock required for Translation Buffer Unit access =20 clock-names: + minItems: 2 items: - const: iface - const: bus + - const: tbu =20 power-domains: maxItems: 1 --=20 2.41.0