From nobody Tue Feb 10 06:08:31 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7A9BEB64D9 for ; Tue, 27 Jun 2023 20:15:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231537AbjF0UPZ (ORCPT ); Tue, 27 Jun 2023 16:15:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231156AbjF0UOg (ORCPT ); Tue, 27 Jun 2023 16:14:36 -0400 Received: from relay07.th.seeweb.it (relay07.th.seeweb.it [IPv6:2001:4b7a:2000:18::168]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD1AF272D for ; Tue, 27 Jun 2023 13:14:34 -0700 (PDT) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id 082913F77A; Tue, 27 Jun 2023 22:14:31 +0200 (CEST) From: Marijn Suijten Date: Tue, 27 Jun 2023 22:14:23 +0200 Subject: [PATCH v2 08/15] drm/msm/dpu: Add SM6125 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230627-sm6125-dpu-v2-8-03e430a2078c@somainline.org> References: <20230627-sm6125-dpu-v2-0-03e430a2078c@somainline.org> In-Reply-To: <20230627-sm6125-dpu-v2-0-03e430a2078c@somainline.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krishna Manikandan , Marijn Suijten , Loic Poulain , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Lux Aliaga X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add definitions for the display hardware used on the Qualcomm SM6125 platform. Signed-off-by: Marijn Suijten Reviewed-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 230 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 238 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h new file mode 100644 index 000000000000..7ab64b0c18b5 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023 Marijn Suijten . All = rights reserved. + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_5_4_SM6125_H +#define _DPU_5_4_SM6125_H + +static const struct dpu_caps sm6125_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0x6, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .max_linewidth =3D 2160, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, + .max_hdeci_exp =3D MAX_HORZ_DECIMATION, + .max_vdeci_exp =3D MAX_VERT_DECIMATION, +}; + +static const struct dpu_ubwc_cfg sm6125_ubwc_cfg =3D { + .ubwc_version =3D DPU_HW_UBWC_VER_10, + .highest_bank_bit =3D 0x1, + .ubwc_swizzle =3D 0x1, +}; + +static const struct dpu_mdp_cfg sm6125_mdp =3D { + .name =3D "top_0", + .base =3D 0x0, .len =3D 0x45c, + .features =3D 0, + .clk_ctrls =3D { + [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, + [DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, + [DPU_CLK_CTRL_DMA1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 8 }, + }, +}; + +static const struct dpu_ctl_cfg sm6125_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x1000, .len =3D 0x1e0, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x1200, .len =3D 0x1e0, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x1400, .len =3D 0x1e0, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x1600, .len =3D 0x1e0, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name =3D "ctl_4", .id =3D CTL_4, + .base =3D 0x1800, .len =3D 0x1e0, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name =3D "ctl_5", .id =3D CTL_5, + .base =3D 0x1a00, .len =3D 0x1e0, + .features =3D BIT(DPU_CTL_ACTIVE_CFG), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg sm6125_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, + .base =3D 0x4000, .len =3D 0x1f0, + .features =3D VIG_SM6125_MASK, + .sblk =3D &sm6125_vig_sblk_0, + .xin_id =3D 0, + .type =3D SSPP_TYPE_VIG, + .clk_ctrl =3D DPU_CLK_CTRL_VIG0, + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, + .base =3D 0x24000, .len =3D 0x1f0, + .features =3D DMA_SDM845_MASK, + .sblk =3D &sdm845_dma_sblk_0, + .xin_id =3D 1, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA0, + }, { + .name =3D "sspp_9", .id =3D SSPP_DMA1, + .base =3D 0x26000, .len =3D 0x1f0, + .features =3D DMA_SDM845_MASK, + .sblk =3D &sdm845_dma_sblk_1, + .xin_id =3D 5, + .type =3D SSPP_TYPE_DMA, + .clk_ctrl =3D DPU_CLK_CTRL_DMA1, + }, +}; + +static const struct dpu_lm_cfg sm6125_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, + .base =3D 0x44000, .len =3D 0x320, + .features =3D MIXER_QCM2290_MASK, + .sblk =3D &sdm845_lm_sblk, + .pingpong =3D PINGPONG_0, + .dspp =3D DSPP_0, + .lm_pair =3D LM_1, + }, { + .name =3D "lm_1", .id =3D LM_1, + .base =3D 0x45000, .len =3D 0x320, + .features =3D MIXER_QCM2290_MASK, + .sblk =3D &sdm845_lm_sblk, + .pingpong =3D PINGPONG_1, + .dspp =3D 0, + .lm_pair =3D LM_0, + }, +}; + +static const struct dpu_dspp_cfg sm6125_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, + .base =3D 0x54000, .len =3D 0x1800, + .features =3D DSPP_SC7180_MASK, + .sblk =3D &sm8150_dspp_sblk, + }, +}; + +static const struct dpu_pingpong_cfg sm6125_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, + .base =3D 0x70000, .len =3D 0xd4, + .features =3D PINGPONG_SM8150_MASK, + .merge_3d =3D 0, + .sblk =3D &sdm845_pp_sblk, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr =3D -1, + }, { + .name =3D "pingpong_1", .id =3D PINGPONG_1, + .base =3D 0x70800, .len =3D 0xd4, + .features =3D PINGPONG_SM8150_MASK, + .merge_3d =3D 0, + .sblk =3D &sdm845_pp_sblk, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + .intr_rdptr =3D -1, + }, +}; + +static const struct dpu_intf_cfg sm6125_intf[] =3D { + { + .name =3D "intf_0", .id =3D INTF_0, + .base =3D 0x6a000, .len =3D 0x280, + .features =3D INTF_SC7180_MASK, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + .intr_tear_rd_ptr =3D -1, + }, { + .name =3D "intf_1", .id =3D INTF_1, + .base =3D 0x6a800, .len =3D 0x2c0, + .features =3D INTF_SC7180_MASK, + .type =3D INTF_DSI, + .controller_id =3D 0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, +}; + +static const struct dpu_perf_cfg sm6125_perf_data =3D { + .max_bw_low =3D 4100000, + .max_bw_high =3D 4100000, + .min_core_ib =3D 2400000, + .min_llcc_ib =3D 0, /* No LLCC on this SoC */ + .min_dram_ib =3D 800000, + .min_prefill_lines =3D 24, + .danger_lut_tbl =3D {0xf, 0xffff, 0x0}, + .safe_lut_tbl =3D {0xfff8, 0xf000, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sm8150_qos_linear), + .entries =3D sm8150_qos_linear + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_macrotile), + .entries =3D sc7180_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +const struct dpu_mdss_cfg dpu_sm6125_cfg =3D { + .caps =3D &sm6125_dpu_caps, + .ubwc =3D &sm6125_ubwc_cfg, + .mdp =3D &sm6125_mdp, + .ctl_count =3D ARRAY_SIZE(sm6125_ctl), + .ctl =3D sm6125_ctl, + .sspp_count =3D ARRAY_SIZE(sm6125_sspp), + .sspp =3D sm6125_sspp, + .mixer_count =3D ARRAY_SIZE(sm6125_lm), + .mixer =3D sm6125_lm, + .dspp_count =3D ARRAY_SIZE(sm6125_dspp), + .dspp =3D sm6125_dspp, + .pingpong_count =3D ARRAY_SIZE(sm6125_pp), + .pingpong =3D sm6125_pp, + .intf_count =3D ARRAY_SIZE(sm6125_intf), + .intf =3D sm6125_intf, + .vbif_count =3D ARRAY_SIZE(sdm845_vbif), + .vbif =3D sdm845_vbif, + .perf =3D &sm6125_perf_data, + .mdss_irqs =3D BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF1_TEAR_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 3efa22429e5f..f529d1b988e3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -33,6 +33,9 @@ #define VIG_SC7180_MASK \ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4)) =20 +#define VIG_SM6125_MASK \ + (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE)) + #define VIG_SC7180_MASK_SDMA \ (VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) =20 @@ -332,6 +335,8 @@ static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0= =3D =20 static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =3D _VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED4); +static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 =3D + _VIG_SBLK("0", 3, DPU_SSPP_SCALER_QSEED3LITE); =20 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =3D _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4); @@ -632,6 +637,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { =20 #include "catalog/dpu_5_0_sm8150.h" #include "catalog/dpu_5_1_sc8180x.h" +#include "catalog/dpu_5_4_sm6125.h" =20 #include "catalog/dpu_6_0_sm8250.h" #include "catalog/dpu_6_2_sc7180.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 3b816e36d12d..1d150091da9c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -860,6 +860,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; extern const struct dpu_mdss_cfg dpu_sm8250_cfg; extern const struct dpu_mdss_cfg dpu_sc7180_cfg; extern const struct dpu_mdss_cfg dpu_sm6115_cfg; +extern const struct dpu_mdss_cfg dpu_sm6125_cfg; extern const struct dpu_mdss_cfg dpu_sm6350_cfg; extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; extern const struct dpu_mdss_cfg dpu_sm6375_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 882f20fc51cc..3b93b874394e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1305,6 +1305,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,sc8180x-dpu", .data =3D &dpu_sc8180x_cfg, }, { .compatible =3D "qcom,sc8280xp-dpu", .data =3D &dpu_sc8280xp_cfg, }, { .compatible =3D "qcom,sm6115-dpu", .data =3D &dpu_sm6115_cfg, }, + { .compatible =3D "qcom,sm6125-dpu", .data =3D &dpu_sm6125_cfg, }, { .compatible =3D "qcom,sm6350-dpu", .data =3D &dpu_sm6350_cfg, }, { .compatible =3D "qcom,sm6375-dpu", .data =3D &dpu_sm6375_cfg, }, { .compatible =3D "qcom,sm8150-dpu", .data =3D &dpu_sm8150_cfg, }, --=20 2.41.0