From nobody Tue Feb 10 09:57:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DA2EEB64DC for ; Tue, 27 Jun 2023 20:15:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231622AbjF0UPq (ORCPT ); Tue, 27 Jun 2023 16:15:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231289AbjF0UOq (ORCPT ); Tue, 27 Jun 2023 16:14:46 -0400 Received: from m-r2.th.seeweb.it (m-r2.th.seeweb.it [5.144.164.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF1052D50; Tue, 27 Jun 2023 13:14:41 -0700 (PDT) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id A7DB33F751; Tue, 27 Jun 2023 22:14:38 +0200 (CEST) From: Marijn Suijten Date: Tue, 27 Jun 2023 22:14:28 +0200 Subject: [PATCH v2 13/15] arm64: dts: qcom: sm6125: Add dispcc node MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230627-sm6125-dpu-v2-13-03e430a2078c@somainline.org> References: <20230627-sm6125-dpu-v2-0-03e430a2078c@somainline.org> In-Reply-To: <20230627-sm6125-dpu-v2-0-03e430a2078c@somainline.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krishna Manikandan , Marijn Suijten , Loic Poulain , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Lux Aliaga X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable and configure the dispcc node on SM6125 for consumption by MDSS later on. Signed-off-by: Marijn Suijten --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qco= m/sm6125.dtsi index edb03508dba3..a5cc0d43d2d9 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2021, Martin Botka */ =20 +#include #include #include #include @@ -1203,6 +1204,30 @@ sram@4690000 { reg =3D <0x04690000 0x10000>; }; =20 + dispcc: clock-controller@5f00000 { + compatible =3D "qcom,sm6125-dispcc"; + reg =3D <0x05f00000 0x20000>; + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + clock-names =3D "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk", + "cfg_ahb_clk", + "gcc_disp_gpll0_div_clk_src"; + power-domains =3D <&rpmpd SM6125_VDDCX>; + #clock-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + apps_smmu: iommu@c600000 { compatible =3D "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg =3D <0x0c600000 0x80000>; --=20 2.41.0