From nobody Mon Feb 9 01:11:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6EC6EB64DC for ; Mon, 26 Jun 2023 03:12:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231320AbjFZDMv (ORCPT ); Sun, 25 Jun 2023 23:12:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231138AbjFZDM1 (ORCPT ); Sun, 25 Jun 2023 23:12:27 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3459B1AA for ; Sun, 25 Jun 2023 20:12:24 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id C24362C0124; Mon, 26 Jun 2023 15:12:20 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1687749140; bh=eMOEgUa0E7z5p8qfBp+CWlp5a+uQqNd4H4SB3Ukp/sI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vIUNGZmGgGMYtCfI7k9W+Tkqud2W9P9ld6G9+cL2sKP5ipW3oVSGHltSOg51f24gc xm0j9dZueRrYl7qzbompeuTj/ugt+EU3kTjR1XOliLsejmwF8lSrqEb2xI6p1xxUHi EtRGCXXCnxyrBHHFCzlG/E3iw6Rj76SO29KuNJqtzpujmHPxbmId970OhZJalSt4GW 4EFAmZjTbD9TFXS1bWfjUJWD6+31xPJ/dRqpKwMIDc/GFXuAGoOBw1FkXY8HvQOXfv 6tQvCdgG5Gt05a3yqghMzDXkYdUjJ51g+k5flW5S2kLyFqLEHocUnp2e2zB6yvr57C tVADcqSF0AH1Q== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Mon, 26 Jun 2023 15:12:20 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id A0D8B13EE52; Mon, 26 Jun 2023 15:12:20 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 9F556281AA0; Mon, 26 Jun 2023 15:12:20 +1200 (NZST) From: Chris Packham To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, gregory.clement@bootlin.com, pierre.gondois@arm.com, arnd@arndb.de, f.fainelli@gmail.com Cc: linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chris Packham Subject: [PATCH v2 1/3] dt-bindings: mtd: Add AC5 specific binding Date: Mon, 26 Jun 2023 15:12:15 +1200 Message-ID: <20230626031217.870938-2-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230626031217.870938-1-chris.packham@alliedtelesis.co.nz> References: <20230626031217.870938-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 X-Patchwork-Bot: notify Content-Transfer-Encoding: quoted-printable X-SEG-SpamProfiler-Analysis: v=2.3 cv=NPqrBHyg c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=of4jigFt-DYA:10 a=uX4zeqIseCYJFCGchTMA:9 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add binding for AC5 SoC. This SoC only supports NAND SDR timings up to mode 3 so a specific compatible value is needed. Signed-off-by: Chris Packham Acked-by: Conor Dooley --- Notes: Changes in v2: - Keep compatibles in alphabetical order - Explain AC5 limitations in commit message .../devicetree/bindings/mtd/marvell,nand-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.= yaml b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml index a10729bb1840..1ecea848e8b9 100644 --- a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml +++ b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml @@ -16,6 +16,7 @@ properties: - const: marvell,armada-8k-nand-controller - const: marvell,armada370-nand-controller - enum: + - marvell,ac5-nand-controller - marvell,armada370-nand-controller - marvell,pxa3xx-nand-controller - description: legacy bindings --=20 2.41.0 From nobody Mon Feb 9 01:11:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F7F4EB64DC for ; Mon, 26 Jun 2023 03:12:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231255AbjFZDMp (ORCPT ); Sun, 25 Jun 2023 23:12:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230506AbjFZDM1 (ORCPT ); Sun, 25 Jun 2023 23:12:27 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34A7CE56 for ; Sun, 25 Jun 2023 20:12:24 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 039782C055E; Mon, 26 Jun 2023 15:12:21 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1687749141; bh=qyuUI+GTbigVnLlHtbXT9nNOWssZWdbxI7Bqwiieak8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TY67yQ5BxL4sg46haJEXGpozSvX91Y9otoDTdYdGTAgQK9k7JKEi0shHHL1nD0QBL lRpxpsXG4qUu/NhcZi2ZZUWUX+wIDDwc7duAFdNAqpxYokrq8Erf0u2VP4FFkIk5GT pnjMPpOv+Fwsqv+1XOA3QYQwDh1DM9GmUBWA82ejx04A0+7MDrx6qZmNppfaUJj0YC 0B5A+1nBwo/NFTK4U9lAuG1zac9mvZ8uWa8etqpX5a/CnimYlEERbuFq5IM/g6ygtr EffuJplMzPQZu48Q/K38rVjS7ecvNpGfKCKONNCzu+AqCQhx3laxdXtnWAjBvxJKHs bB3VYsojSPXRw== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Mon, 26 Jun 2023 15:12:20 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id A24D013EE63; Mon, 26 Jun 2023 15:12:20 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id A2BC6283B3E; Mon, 26 Jun 2023 15:12:20 +1200 (NZST) From: Chris Packham To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, gregory.clement@bootlin.com, pierre.gondois@arm.com, arnd@arndb.de, f.fainelli@gmail.com Cc: linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chris Packham Subject: [PATCH v2 2/3] arm64: dts: marvell: Add NAND flash controller to AC5 Date: Mon, 26 Jun 2023 15:12:16 +1200 Message-ID: <20230626031217.870938-3-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230626031217.870938-1-chris.packham@alliedtelesis.co.nz> References: <20230626031217.870938-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 X-Patchwork-Bot: notify Content-Transfer-Encoding: quoted-printable X-SEG-SpamProfiler-Analysis: v=2.3 cv=NPqrBHyg c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=of4jigFt-DYA:10 a=AWclJRrDGzD0f9BZm7oA:9 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The AC5/AC5X SoC has a NAND flash controller (NFC). Add this to the base SoC dtsi file as a disabled node. The NFC integration on the AC5/AC5X only supports SDR timing modes up to 3 so requires a dedicated compatible property so this limitation can be enforced. Signed-off-by: Chris Packham --- Notes: Changes in v2: - New. arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boo= t/dts/marvell/ac5-98dx25xx.dtsi index 8bce64069138..74d644e0c29e 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -296,6 +296,16 @@ spi1: spi@805a8000 { status =3D "disabled"; }; =20 + nand: nand-controller@805b0000 { + compatible =3D "marvell,ac5-nand-controller"; + reg =3D <0x0 0x805b0000 0x0 0x00000054>; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + interrupts =3D ; + clocks =3D <&cnm_clock>; + status =3D "disabled"; + }; + gic: interrupt-controller@80600000 { compatible =3D "arm,gic-v3"; #interrupt-cells =3D <3>; --=20 2.41.0 From nobody Mon Feb 9 01:11:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED977EB64DC for ; Mon, 26 Jun 2023 03:12:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231230AbjFZDMj (ORCPT ); Sun, 25 Jun 2023 23:12:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230514AbjFZDM1 (ORCPT ); Sun, 25 Jun 2023 23:12:27 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [IPv6:2001:df5:b000:5::4]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34A12E55 for ; Sun, 25 Jun 2023 20:12:24 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 077602C0591; Mon, 26 Jun 2023 15:12:21 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1687749141; bh=T/cMMndfNf0ocqhn0QoQw6bUJBMlWygzKPKZTmLFFsw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CTVr0opj8KePIWa9Q2JSSU2d7A6S+qQDuxZb2ekXGAgLNaskLMeJOioDIzHpCEiCM liIVfFrr5ANCddL1Fpfxb9w6Ht3Vrm5IhcKmG6h93HeG9os+bOQIHl6BqkuCt/p34x jdnIWqi1jlAFQgs81qUQIxrBx/hRZW3ptWeUPVrRjO4zE3l7HO3Gz1jpbM3xDsCtUd TEtMMoOFYNMCtycXtYUczNBwkEneqTEJlf8nvFK//qtWa6b4r+e3NqrAjtuq2A06IS 0QxG/owF7Xp4pWDNO6ci8qmyfbrW/GL8ZcMU0LilHVxht2o6WecRHChya06A9Liatw UgTEDkJHJgyfg== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Mon, 26 Jun 2023 15:12:20 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id A497313EE7B; Mon, 26 Jun 2023 15:12:20 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id A590D283B1A; Mon, 26 Jun 2023 15:12:20 +1200 (NZST) From: Chris Packham To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, gregory.clement@bootlin.com, pierre.gondois@arm.com, arnd@arndb.de, f.fainelli@gmail.com Cc: linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chris Packham Subject: [PATCH v2 3/3] mtd: rawnand: marvell: add support for AC5 SoC Date: Mon, 26 Jun 2023 15:12:17 +1200 Message-ID: <20230626031217.870938-4-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230626031217.870938-1-chris.packham@alliedtelesis.co.nz> References: <20230626031217.870938-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 X-Patchwork-Bot: notify Content-Transfer-Encoding: quoted-printable X-SEG-SpamProfiler-Analysis: v=2.3 cv=NPqrBHyg c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=of4jigFt-DYA:10 a=FN2KoAgMzK-72ix3NDkA:9 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for the AC5/AC5X SoC from Marvell. The NFC on this SoC only supports SDR modes up to 3. Marvell's SDK includes some predefined values for the ndtr registers. These haven't been incorporated as the existing code seems to get good values based on measurements taken with an oscilloscope. Signed-off-by: Chris Packham --- Notes: Changes in v2: - None drivers/mtd/nand/raw/Kconfig | 2 +- drivers/mtd/nand/raw/marvell_nand.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index b523354dfb00..0f4cbb497010 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -160,7 +160,7 @@ config MTD_NAND_MARVELL including: - PXA3xx processors (NFCv1) - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2) - - 64-bit Aramda platforms (7k, 8k) (NFCv2) + - 64-bit Aramda platforms (7k, 8k, ac5) (NFCv2) =20 config MTD_NAND_SLC_LPC32XX tristate "NXP LPC32xx SLC NAND controller" diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/mar= vell_nand.c index 30c15e4e1cc0..b9a8dd324211 100644 --- a/drivers/mtd/nand/raw/marvell_nand.c +++ b/drivers/mtd/nand/raw/marvell_nand.c @@ -375,6 +375,7 @@ static inline struct marvell_nand_chip_sel *to_nand_sel= (struct marvell_nand_chip * BCH error detection and correction algorithm, * NDCB3 register has been added * @use_dma: Use dma for data transfers + * @max_mode_number: Maximum timing mode supported by the controller */ struct marvell_nfc_caps { unsigned int max_cs_nb; @@ -383,6 +384,7 @@ struct marvell_nfc_caps { bool legacy_of_bindings; bool is_nfcv2; bool use_dma; + unsigned int max_mode_number; }; =20 /** @@ -2376,6 +2378,9 @@ static int marvell_nfc_setup_interface(struct nand_ch= ip *chip, int chipnr, if (IS_ERR(sdr)) return PTR_ERR(sdr); =20 + if (nfc->caps->max_mode_number && nfc->caps->max_mode_number < conf->timi= ngs.mode) + return -EOPNOTSUPP; + /* * SDR timings are given in pico-seconds while NFC timings must be * expressed in NAND controller clock cycles, which is half of the @@ -3073,6 +3078,13 @@ static const struct marvell_nfc_caps marvell_armada_= 8k_nfc_caps =3D { .is_nfcv2 =3D true, }; =20 +static const struct marvell_nfc_caps marvell_ac5_caps =3D { + .max_cs_nb =3D 2, + .max_rb_nb =3D 1, + .is_nfcv2 =3D true, + .max_mode_number =3D 3, +}; + static const struct marvell_nfc_caps marvell_armada370_nfc_caps =3D { .max_cs_nb =3D 4, .max_rb_nb =3D 2, @@ -3121,6 +3133,10 @@ static const struct of_device_id marvell_nfc_of_ids[= ] =3D { .compatible =3D "marvell,armada-8k-nand-controller", .data =3D &marvell_armada_8k_nfc_caps, }, + { + .compatible =3D "marvell,ac5-nand-controller", + .data =3D &marvell_ac5_caps, + }, { .compatible =3D "marvell,armada370-nand-controller", .data =3D &marvell_armada370_nfc_caps, --=20 2.41.0