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Shenoy" , Mark Rutland , Peter Zijlstra , Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Krzysztof Kozlowski Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 2/6] riscv: add support for misaligned handling in S-mode Date: Sat, 24 Jun 2023 14:20:45 +0200 Message-Id: <20230624122049.7886-3-cleger@rivosinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230624122049.7886-1-cleger@rivosinc.com> References: <20230624122049.7886-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Misalignment handling is only supported for M-mode and uses direct accesses to user memory. in S-mode, this requires to use the get_user()/put_user() accessors. Implement load_u8(), store_u8() and get_insn() using these accessors. Also, use CSR_TVAL instead of hardcoded mtval in csr_read() call which will work for both S-mode and M-mode. When used in S-mode, we do not handle misaligned accesses that are triggered from kernel mode. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/kernel/Makefile | 2 +- arch/riscv/kernel/traps_misaligned.c | 111 +++++++++++++++++++++++---- 2 files changed, 99 insertions(+), 14 deletions(-) diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 153864e4f399..61bad09280a6 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -56,9 +56,9 @@ obj-y +=3D stacktrace.o obj-y +=3D cacheinfo.o obj-y +=3D patch.o obj-y +=3D probes/ +obj-y +=3D traps_misaligned.o obj-$(CONFIG_MMU) +=3D vdso.o vdso/ =20 -obj-$(CONFIG_RISCV_M_MODE) +=3D traps_misaligned.o obj-$(CONFIG_FPU) +=3D fpu.o obj-$(CONFIG_SMP) +=3D smpboot.o obj-$(CONFIG_SMP) +=3D smp.o diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index e7bfb33089c1..e4a273ab77c9 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -12,6 +12,7 @@ #include #include #include +#include =20 #define INSN_MATCH_LB 0x3 #define INSN_MASK_LB 0x707f @@ -151,21 +152,25 @@ #define PRECISION_S 0 #define PRECISION_D 1 =20 -static inline u8 load_u8(const u8 *addr) +#ifdef CONFIG_RISCV_M_MODE +static inline int load_u8(const u8 *addr, u8 *r_val) { u8 val; =20 asm volatile("lbu %0, %1" : "=3D&r" (val) : "m" (*addr)); + *r_val =3D val; =20 - return val; + return 0; } =20 -static inline void store_u8(u8 *addr, u8 val) +static inline int store_u8(u8 *addr, u8 val) { asm volatile ("sb %0, %1\n" : : "r" (val), "m" (*addr)); + + return 0; } =20 -static inline ulong get_insn(ulong mepc) +static inline int get_insn(ulong mepc, ulong *r_insn) { register ulong __mepc asm ("a2") =3D mepc; ulong val, rvc_mask =3D 3, tmp; @@ -194,9 +199,63 @@ static inline ulong get_insn(ulong mepc) : [addr] "r" (__mepc), [rvc_mask] "r" (rvc_mask), [xlen_minus_16] "i" (XLEN_MINUS_16)); =20 - return val; + *r_insn =3D val; + + return 0; +} +#else +static inline int load_u8(const u8 *addr, u8 *r_val) +{ + return __get_user(*r_val, addr); +} + +static inline int store_u8(u8 *addr, u8 val) +{ + return __put_user(val, addr); } =20 +static inline int get_insn(ulong mepc, ulong *r_insn) +{ + ulong insn =3D 0; + + if (mepc & 0x2) { + ulong tmp =3D 0; + u16 __user *insn_addr =3D (u16 __user *)mepc; + + if (__get_user(insn, insn_addr)) + return -EFAULT; + /* __get_user() uses regular "lw" which sign extend the loaded + * value make sure to clear higher order bits in case we "or" it + * below with the upper 16 bits half. + */ + insn &=3D GENMASK(15, 0); + if ((insn & __INSN_LENGTH_MASK) !=3D __INSN_LENGTH_32) { + *r_insn =3D insn; + return 0; + } + insn_addr++; + if (__get_user(tmp, insn_addr)) + return -EFAULT; + *r_insn =3D (tmp << 16) | insn; + + return 0; + } else { + u32 __user *insn_addr =3D (u32 __user *)mepc; + + if (__get_user(insn, insn_addr)) + return -EFAULT; + if ((insn & __INSN_LENGTH_MASK) =3D=3D __INSN_LENGTH_32) { + *r_insn =3D insn; + return 0; + } + insn &=3D GENMASK(15, 0); + *r_insn =3D insn; + + return 0; + } +} +#endif + union reg_data { u8 data_bytes[8]; ulong data_ulong; @@ -207,10 +266,21 @@ int handle_misaligned_load(struct pt_regs *regs) { union reg_data val; unsigned long epc =3D regs->epc; - unsigned long insn =3D get_insn(epc); - unsigned long addr =3D csr_read(mtval); + unsigned long insn; + unsigned long addr; int i, fp =3D 0, shift =3D 0, len =3D 0; =20 + /* + * When running in supervisor mode, we only handle misaligned accesses + * triggered from user mode. + */ + if (!IS_ENABLED(CONFIG_RISCV_M_MODE) && !user_mode(regs)) + return -1; + + if (get_insn(epc, &insn)) + return -1; + + addr =3D csr_read(CSR_TVAL); regs->epc =3D 0; =20 if ((insn & INSN_MASK_LW) =3D=3D INSN_MATCH_LW) { @@ -274,8 +344,10 @@ int handle_misaligned_load(struct pt_regs *regs) } =20 val.data_u64 =3D 0; - for (i =3D 0; i < len; i++) - val.data_bytes[i] =3D load_u8((void *)(addr + i)); + for (i =3D 0; i < len; i++) { + if (load_u8((void *)(addr + i), &val.data_bytes[i])) + return -1; + } =20 if (fp) return -1; @@ -290,10 +362,21 @@ int handle_misaligned_store(struct pt_regs *regs) { union reg_data val; unsigned long epc =3D regs->epc; - unsigned long insn =3D get_insn(epc); - unsigned long addr =3D csr_read(mtval); + unsigned long insn; + unsigned long addr; int i, len =3D 0; =20 + /* + * When running in supervisor mode, we only handle misaligned accesses + * triggered from user mode. + */ + if (!IS_ENABLED(CONFIG_RISCV_M_MODE) && !user_mode(regs)) + return -1; + + if (get_insn(epc, &insn)) + return -1; + + addr =3D csr_read(CSR_TVAL); regs->epc =3D 0; =20 val.data_ulong =3D GET_RS2(insn, regs); @@ -327,8 +410,10 @@ int handle_misaligned_store(struct pt_regs *regs) return -1; } =20 - for (i =3D 0; i < len; i++) - store_u8((void *)(addr + i), val.data_bytes[i]); + for (i =3D 0; i < len; i++) { + if (store_u8((void *)(addr + i), val.data_bytes[i])) + return -1; + } =20 regs->epc =3D epc + INSN_LEN(insn); =20 --=20 2.40.1