From nobody Sat Feb 7 19:04:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9948CEB64D7 for ; Fri, 23 Jun 2023 22:20:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232455AbjFWWU4 (ORCPT ); Fri, 23 Jun 2023 18:20:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52600 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232413AbjFWWUt (ORCPT ); Fri, 23 Jun 2023 18:20:49 -0400 Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E326D2950 for ; Fri, 23 Jun 2023 15:20:40 -0700 (PDT) Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-6687466137bso743178b3a.0 for ; Fri, 23 Jun 2023 15:20:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1687558840; x=1690150840; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9tOWF5jVjkcJnGVSJRQXmOufijKMT1TZldHmns4l6jA=; b=j7Uv46y88tuBgLQu6gWfP6l1YvmyaedR9YtQXaYX46hKRc81vhJsaHPRG1Hs0/l1cO mMgV7FKk6FmtZeBkWeoBHnN5QVus9+Evd9TD3kHi/hYRUNQ0OTND9lFox6aBOGTWphkk XBBaNdslGJb3bfB42fhGE/9DRzBk8QTwfYx3ndmbP6POwft9BGYyYr6IqiaPAM2VEGEK C0033CwonW4UvCgbYXCOU9Oht1NYmh8GN6hf0jOzrLWmAfNzxnXV+yOClk5ojLOAdPtC 0ksRmXof7Rn+WvlBXTH18FhEhVv0XBM8fyIuAps2575BxtugwqY2VZa9iu7VODrQhcDa 6iXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687558840; x=1690150840; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9tOWF5jVjkcJnGVSJRQXmOufijKMT1TZldHmns4l6jA=; b=Z5gbl55V7TO/dqY1cw2i+11FNvH2LR/oaMjSs7zMMiHjYHeMxhG0R2DwFfjwvUaLon yTm+Fv9eTZniyXDNXjhdnuHTKUv78MZe1oIgIgAst5fa3UN5SJ63NeuuWUdbe3rczsvj 3/wILoemyrTEKjXHyyBfU4n42mlO9Ue0K582JwOB+tCXTTK7OJQ6mJeg9ywgEOpKufU4 79OmDIb4L2gED6NVk/vL82XMU/c2y7KZm2HSf2fLueIVpAJY4G7j60Qszk+uiTd+/wsM 9qaq/sWyEGHSjZLRCtbEJqgES9bN5IR3xE+tyW/0fkZV1Kwn4hEyG/q/1Yf9goHFDw8E 5U1w== X-Gm-Message-State: AC+VfDyyhNtzC74+07Dor3XkkBzP53xHRIS2oiHYibwAx0CD/11ZnUGd 6BuINxhR2fuKbSa1Q2xaEQDxYQ== X-Google-Smtp-Source: ACHHUZ5jseNwiCBYx3Vp2Jt1EnuGruMwwk6GbcJvwh8JVNPX3obSZyczhHcgUYVl3ZCui0U1efkKGQ== X-Received: by 2002:a05:6a20:729f:b0:118:e70:6f7d with SMTP id o31-20020a056a20729f00b001180e706f7dmr18899903pzk.10.1687558840398; Fri, 23 Jun 2023 15:20:40 -0700 (PDT) Received: from evan.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id ju20-20020a170903429400b001a80ad9c599sm35535plb.294.2023.06.23.15.20.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 15:20:39 -0700 (PDT) From: Evan Green To: Palmer Dabbelt Cc: Simon Hosie , Evan Green , Albert Ou , Alexandre Ghiti , Andrew Jones , Andy Chiu , Anup Patel , Conor Dooley , Greentime Hu , Guo Ren , Heiko Stuebner , Jisheng Zhang , Jonathan Corbet , Ley Foon Tan , Li Zhengyu , Masahiro Yamada , Palmer Dabbelt , Paul Walmsley , Sia Jee Heng , Sunil V L , Xianting Tian , Yangyu Chen , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 1/2] RISC-V: Probe for unaligned access speed Date: Fri, 23 Jun 2023 15:20:15 -0700 Message-Id: <20230623222016.3742145-2-evan@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230623222016.3742145-1-evan@rivosinc.com> References: <20230623222016.3742145-1-evan@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Rather than deferring misaligned access speed determinations to a vendor function, let's probe them and find out how fast they are. If we determine that a misaligned word access is faster than N byte accesses, mark the hardware's misaligned access as "fast". Fix the documentation as well to reflect this bar. Previously the only SoC that returned "fast" was the THead C906. The change to the documentation is more a clarification, since the C906 is fast in the sense of the corrected documentation. Signed-off-by: Evan Green --- Documentation/riscv/hwprobe.rst | 8 +-- arch/riscv/include/asm/cpufeature.h | 2 + arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/copy-noalign.S | 71 ++++++++++++++++++++++++++ arch/riscv/kernel/copy-noalign.h | 13 +++++ arch/riscv/kernel/cpufeature.c | 78 +++++++++++++++++++++++++++++ arch/riscv/kernel/smpboot.c | 2 + 7 files changed, 171 insertions(+), 4 deletions(-) create mode 100644 arch/riscv/kernel/copy-noalign.S create mode 100644 arch/riscv/kernel/copy-noalign.h diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.= rst index 19165ebd82ba..710325751766 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -88,12 +88,12 @@ The following keys are defined: always extremely slow. =20 * :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned accesses are supp= orted - in hardware, but are slower than the cooresponding aligned accesses - sequences. + in hardware, but are slower than N byte accesses, where N is the native + word size. =20 * :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned accesses are supp= orted - in hardware and are faster than the cooresponding aligned accesses - sequences. + in hardware and are faster than N byte accesses, where N is the native + word size. =20 * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses a= re not supported at all and will generate a misaligned address fault. diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index 23fed53b8815..b8e917176616 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -30,4 +30,6 @@ DECLARE_PER_CPU(long, misaligned_access_speed); /* Per-cpu ISA extensions. */ extern struct riscv_isainfo hart_isa[NR_CPUS]; =20 +void check_misaligned_access(int cpu); + #endif diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index a42951911067..f934d7ab7840 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -34,6 +34,7 @@ extra-y +=3D vmlinux.lds obj-y +=3D head.o obj-y +=3D soc.o obj-$(CONFIG_RISCV_ALTERNATIVE) +=3D alternative.o +obj-y +=3D copy-noalign.o obj-y +=3D cpu.o obj-y +=3D cpufeature.o obj-y +=3D entry.o diff --git a/arch/riscv/kernel/copy-noalign.S b/arch/riscv/kernel/copy-noal= ign.S new file mode 100644 index 000000000000..3807fc2324b2 --- /dev/null +++ b/arch/riscv/kernel/copy-noalign.S @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2023 Rivos Inc. */ + +#include +#include + + .text + +/* void __copy_words_unaligned(void *, const void *, size_t) */ +/* Performs a memcpy without aligning buffers, using word loads and stores= . */ +/* Note: The size is truncated to a multiple of 8 * SZREG */ +ENTRY(__copy_words_unaligned) + andi a4, a2, ~((8*SZREG)-1) + beqz a4, 2f + add a3, a1, a4 +1: + REG_L a4, 0(a1) + REG_L a5, SZREG(a1) + REG_L a6, 2*SZREG(a1) + REG_L a7, 3*SZREG(a1) + REG_L t0, 4*SZREG(a1) + REG_L t1, 5*SZREG(a1) + REG_L t2, 6*SZREG(a1) + REG_L t3, 7*SZREG(a1) + REG_S a4, 0(a0) + REG_S a5, SZREG(a0) + REG_S a6, 2*SZREG(a0) + REG_S a7, 3*SZREG(a0) + REG_S t0, 4*SZREG(a0) + REG_S t1, 5*SZREG(a0) + REG_S t2, 6*SZREG(a0) + REG_S t3, 7*SZREG(a0) + addi a0, a0, 8*SZREG + addi a1, a1, 8*SZREG + bltu a1, a3, 1b + +2: + ret +END(__copy_words_unaligned) + +/* void __copy_bytes_unaligned(void *, const void *, size_t) */ +/* Performs a memcpy without aligning buffers, using only byte accesses. */ +/* Note: The size is truncated to a multiple of 8 */ +ENTRY(__copy_bytes_unaligned) + andi a4, a2, ~(8-1) + beqz a4, 2f + add a3, a1, a4 +1: + lb a4, 0(a1) + lb a5, 1(a1) + lb a6, 2(a1) + lb a7, 3(a1) + lb t0, 4(a1) + lb t1, 5(a1) + lb t2, 6(a1) + lb t3, 7(a1) + sb a4, 0(a0) + sb a5, 1(a0) + sb a6, 2(a0) + sb a7, 3(a0) + sb t0, 4(a0) + sb t1, 5(a0) + sb t2, 6(a0) + sb t3, 7(a0) + addi a0, a0, 8 + addi a1, a1, 8 + bltu a1, a3, 1b + +2: + ret +END(__copy_bytes_unaligned) diff --git a/arch/riscv/kernel/copy-noalign.h b/arch/riscv/kernel/copy-noal= ign.h new file mode 100644 index 000000000000..99fbb9c763e0 --- /dev/null +++ b/arch/riscv/kernel/copy-noalign.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos, Inc. + */ +#ifndef __RISCV_KERNEL_COPY_NOALIGN_H +#define __RISCV_KERNEL_COPY_NOALIGN_H + +#include + +void __copy_words_unaligned(void *dst, const void *src, size_t size); +void __copy_bytes_unaligned(void *dst, const void *src, size_t size); + +#endif /* __RISCV_KERNEL_COPY_NOALIGN_H */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index bdcf460ea53d..3f7200dcc00c 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -19,11 +19,21 @@ #include #include #include +#include #include #include #include =20 +#include "copy-noalign.h" + #define NUM_ALPHA_EXTS ('z' - 'a' + 1) +#define MISALIGNED_ACCESS_JIFFIES_LG2 1 +#define MISALIGNED_BUFFER_SIZE 0x4000 +#define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80) + +#define MISALIGNED_COPY_MBS(_count) \ + ((HZ * (_count) * MISALIGNED_COPY_SIZE) >> \ + (20 + MISALIGNED_ACCESS_JIFFIES_LG2)) =20 unsigned long elf_hwcap __read_mostly; =20 @@ -396,6 +406,74 @@ unsigned long riscv_get_elf_hwcap(void) return hwcap; } =20 +void check_misaligned_access(int cpu) +{ + unsigned long j0, j1; + struct page *page; + void *dst; + void *src; + long word_copies =3D 0; + long byte_copies =3D 0; + long speed =3D RISCV_HWPROBE_MISALIGNED_SLOW; + + page =3D alloc_pages(GFP_NOWAIT, get_order(MISALIGNED_BUFFER_SIZE)); + if (!page) { + pr_warn("Can't alloc pages to measure memcpy performance"); + return; + } + + /* Make a misaligned destination buffer. */ + dst =3D (void *)((unsigned long)page_address(page) | 0x1); + /* Misalign src as well, but differently (off by 1 + 2 =3D 3). */ + src =3D dst + (MISALIGNED_BUFFER_SIZE / 2); + src +=3D 2; + /* Do a warmup. */ + __copy_words_unaligned(dst, src, MISALIGNED_COPY_SIZE); + preempt_disable(); + j0 =3D jiffies; + while ((j1 =3D jiffies) =3D=3D j0) + cpu_relax(); + + while (time_before(jiffies, + j1 + (1 << MISALIGNED_ACCESS_JIFFIES_LG2))) { + + __copy_words_unaligned(dst, src, MISALIGNED_COPY_SIZE); + word_copies +=3D 1; + } + + __copy_bytes_unaligned(dst, src, MISALIGNED_COPY_SIZE); + j0 =3D jiffies; + while ((j1 =3D jiffies) =3D=3D j0) + cpu_relax(); + + while (time_before(jiffies, + j1 + (1 << MISALIGNED_ACCESS_JIFFIES_LG2))) { + __copy_bytes_unaligned(dst, src, MISALIGNED_COPY_SIZE); + byte_copies +=3D 1; + } + + preempt_enable(); + if (word_copies >=3D byte_copies) + speed =3D RISCV_HWPROBE_MISALIGNED_FAST; + + pr_info("cpu%d: Unaligned word copy %ld MB/s, byte copy %ld MB/s, misalig= ned accesses are %s\n", + cpu, + MISALIGNED_COPY_MBS(word_copies), + MISALIGNED_COPY_MBS(byte_copies), + (speed =3D=3D RISCV_HWPROBE_MISALIGNED_FAST) ? "fast" : "slow"); + + per_cpu(misaligned_access_speed, cpu) =3D speed; + __free_pages(page, get_order(MISALIGNED_BUFFER_SIZE)); +} + +static int check_misaligned_access0(void) +{ + check_misaligned_access(0); + return 0; +} + +arch_initcall(check_misaligned_access0); + #ifdef CONFIG_RISCV_ALTERNATIVE /* * Alternative patch sites consider 48 bits when determining when to patch diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index bb0b76e1a6d4..e34a71b4786b 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -244,6 +245,7 @@ asmlinkage __visible void smp_callin(void) notify_cpu_starting(curr_cpuid); numa_add_cpu(curr_cpuid); set_cpu_online(curr_cpuid, 1); + check_misaligned_access(curr_cpuid); probe_vendor_features(curr_cpuid); =20 if (has_vector()) { --=20 2.34.1 From nobody Sat Feb 7 19:04:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1DB5EB64D7 for ; Fri, 23 Jun 2023 22:21:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232429AbjFWWVE (ORCPT ); Fri, 23 Jun 2023 18:21:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232449AbjFWWUy (ORCPT ); Fri, 23 Jun 2023 18:20:54 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC9B4270A for ; Fri, 23 Jun 2023 15:20:46 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1b543f7e53aso8862415ad.1 for ; Fri, 23 Jun 2023 15:20:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1687558846; x=1690150846; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TSNCaOQLase6R78rglYt4Rjd26nSgMIZzTltF0nRgNc=; b=LtPhohUcJlv52xMIVRCXAw8B7ne2l6il1uC9q65UIsvfKhdD+DnCmBqlyRJ7IjCx06 lXXBEHo7vIuBXEDbWmEIUUPUkMhEarommF1dNcFAnTJSl+7r9U9RQmW9NxB3fL79aVf5 zlDLpUNch5Yo47NMDGXMKT21peJBH6tcJnj36E7VwxJHkaeJ3bEIJiRT4mf04z58jZao Ofb2oDPuahkTvwln68mT6vUJ791BrJ+E+aZUbkeMNgDEA9z/vBjE1a0RHqQqwPQKmBgB XXUq2qeBHRqew7g5lhHx3UQwF+Uqe7eOCfLp619JdlpEAU4rg93u1+O3pl/9+SKrODtF whjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687558846; x=1690150846; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TSNCaOQLase6R78rglYt4Rjd26nSgMIZzTltF0nRgNc=; b=aXm4WPfmWSB64dQdbBvpJh8hJpQ2cKMRGBo6Vg/CcmRG1b6QqdlQn+Xhjlth8f0tvJ ydX89taF8N4azYRk983YwkWxxkrGOhCcB5vLEfZ2NGJ7hKWg0uBLah/MknQyxgICqzSi 3uJMikS/CMyPzS/Y1kMYpkPpaXyugBQTynQT2H7SkDJ1W7Ab7DKRWkzr1M9ZJf6iNSr5 opgOuR6a69TCaReiVOuy3ymjnCNgMP7FRzpVKIzKtN8SBgbJcQmfzPfANS49+XAx+qKz H2Pkqjg+MGNmUltbba0dc9vj1doFVjAEfifCj6ShnfPW/WPDYUudOCDKwyJOfEotERS5 CHkg== X-Gm-Message-State: AC+VfDxw9QodGW/w/LQvmlg899RMMxJx5gCKX4rHdAv8lFWcXmLgi3kc w1yBYHSUCr8nvt67SQBla3Wlfw== X-Google-Smtp-Source: ACHHUZ4EVHfJqU1ilq3/qiO6Tc2JAY6CRZISTiee+Hg9pywoB1Cb8B91JQTqGo3XNM9XY6iZaCII+A== X-Received: by 2002:a17:903:1cb:b0:1b6:8120:3fb0 with SMTP id e11-20020a17090301cb00b001b681203fb0mr487586plh.5.1687558845792; Fri, 23 Jun 2023 15:20:45 -0700 (PDT) Received: from evan.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id ju20-20020a170903429400b001a80ad9c599sm35535plb.294.2023.06.23.15.20.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 15:20:45 -0700 (PDT) From: Evan Green To: Palmer Dabbelt Cc: Simon Hosie , Evan Green , Albert Ou , Andrew Jones , Anup Patel , Conor Dooley , Greentime Hu , Guo Ren , Heiko Stuebner , Jisheng Zhang , Ley Foon Tan , Palmer Dabbelt , Paul Walmsley , Randy Dunlap , Samuel Holland , Sunil V L , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 2/2] RISC-V: alternative: Remove feature_probe_func Date: Fri, 23 Jun 2023 15:20:16 -0700 Message-Id: <20230623222016.3742145-3-evan@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230623222016.3742145-1-evan@rivosinc.com> References: <20230623222016.3742145-1-evan@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that we're testing unaligned memory copy and making that determination generically, there are no more users of the vendor feature_probe_func(). While I think it's probably going to need to come back, there are no users right now, so let's remove it until it's needed. Signed-off-by: Evan Green Reviewed-by: Conor Dooley --- arch/riscv/errata/thead/errata.c | 8 -------- arch/riscv/include/asm/alternative.h | 5 ----- arch/riscv/kernel/alternative.c | 19 ------------------- arch/riscv/kernel/smpboot.c | 1 - 4 files changed, 33 deletions(-) diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/err= ata.c index c259dc925ec1..bf42857c977f 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -117,11 +117,3 @@ void thead_errata_patch_func(struct alt_entry *begin, = struct alt_entry *end, if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) local_flush_icache_all(); } - -void thead_feature_probe_func(unsigned int cpu, - unsigned long archid, - unsigned long impid) -{ - if ((archid =3D=3D 0) && (impid =3D=3D 0)) - per_cpu(misaligned_access_speed, cpu) =3D RISCV_HWPROBE_MISALIGNED_FAST; -} diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/= alternative.h index 6a41537826a7..58ccd2f8cab7 100644 --- a/arch/riscv/include/asm/alternative.h +++ b/arch/riscv/include/asm/alternative.h @@ -30,7 +30,6 @@ #define ALT_OLD_PTR(a) __ALT_PTR(a, old_offset) #define ALT_ALT_PTR(a) __ALT_PTR(a, alt_offset) =20 -void probe_vendor_features(unsigned int cpu); void __init apply_boot_alternatives(void); void __init apply_early_boot_alternatives(void); void apply_module_alternatives(void *start, size_t length); @@ -53,15 +52,11 @@ void thead_errata_patch_func(struct alt_entry *begin, s= truct alt_entry *end, unsigned long archid, unsigned long impid, unsigned int stage); =20 -void thead_feature_probe_func(unsigned int cpu, unsigned long archid, - unsigned long impid); - void riscv_cpufeature_patch_func(struct alt_entry *begin, struct alt_entry= *end, unsigned int stage); =20 #else /* CONFIG_RISCV_ALTERNATIVE */ =20 -static inline void probe_vendor_features(unsigned int cpu) { } static inline void apply_boot_alternatives(void) { } static inline void apply_early_boot_alternatives(void) { } static inline void apply_module_alternatives(void *start, size_t length) {= } diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternativ= e.c index 6b75788c18e6..85056153fa23 100644 --- a/arch/riscv/kernel/alternative.c +++ b/arch/riscv/kernel/alternative.c @@ -27,8 +27,6 @@ struct cpu_manufacturer_info_t { void (*patch_func)(struct alt_entry *begin, struct alt_entry *end, unsigned long archid, unsigned long impid, unsigned int stage); - void (*feature_probe_func)(unsigned int cpu, unsigned long archid, - unsigned long impid); }; =20 static void riscv_fill_cpu_mfr_info(struct cpu_manufacturer_info_t *cpu_mf= r_info) @@ -43,7 +41,6 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufactur= er_info_t *cpu_mfr_info cpu_mfr_info->imp_id =3D sbi_get_mimpid(); #endif =20 - cpu_mfr_info->feature_probe_func =3D NULL; switch (cpu_mfr_info->vendor_id) { #ifdef CONFIG_ERRATA_SIFIVE case SIFIVE_VENDOR_ID: @@ -53,7 +50,6 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufactur= er_info_t *cpu_mfr_info #ifdef CONFIG_ERRATA_THEAD case THEAD_VENDOR_ID: cpu_mfr_info->patch_func =3D thead_errata_patch_func; - cpu_mfr_info->feature_probe_func =3D thead_feature_probe_func; break; #endif default: @@ -143,20 +139,6 @@ void riscv_alternative_fix_offsets(void *alt_ptr, unsi= gned int len, } } =20 -/* Called on each CPU as it starts */ -void probe_vendor_features(unsigned int cpu) -{ - struct cpu_manufacturer_info_t cpu_mfr_info; - - riscv_fill_cpu_mfr_info(&cpu_mfr_info); - if (!cpu_mfr_info.feature_probe_func) - return; - - cpu_mfr_info.feature_probe_func(cpu, - cpu_mfr_info.arch_id, - cpu_mfr_info.imp_id); -} - /* * This is called very early in the boot process (directly after we run * a feature detect on the boot CPU). No need to worry about other CPUs @@ -211,7 +193,6 @@ void __init apply_boot_alternatives(void) /* If called on non-boot cpu things could go wrong */ WARN_ON(smp_processor_id() !=3D 0); =20 - probe_vendor_features(0); _apply_alternatives((struct alt_entry *)__alt_start, (struct alt_entry *)__alt_end, RISCV_ALTERNATIVES_BOOT); diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index e34a71b4786b..054f2d4474d0 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -246,7 +246,6 @@ asmlinkage __visible void smp_callin(void) numa_add_cpu(curr_cpuid); set_cpu_online(curr_cpuid, 1); check_misaligned_access(curr_cpuid); - probe_vendor_features(curr_cpuid); =20 if (has_vector()) { if (riscv_v_setup_vsize()) --=20 2.34.1