From nobody Sat Feb 7 13:41:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3933DEB64DD for ; Fri, 23 Jun 2023 17:32:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231888AbjFWRcF (ORCPT ); Fri, 23 Jun 2023 13:32:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229451AbjFWRb7 (ORCPT ); Fri, 23 Jun 2023 13:31:59 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2E452129 for ; Fri, 23 Jun 2023 10:31:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687541517; x=1719077517; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Xg06mLwyuYOnrVMaZvi1VkV9aKC889ZSsBT8Qaml1Wk=; b=XdqigKSK5vb72UJ2G6P7PujaG63PnSFDluPNDxGNHmPQOruouu5oonL6 IIas9IGV4lboCvg66bRfXZHidvHkoX6e9fqZW23sf9kN5n50EzSwzqjDs 9tcjBdg2MqilXSUMG8oRDLf/Ble0GC2OuIgRey6fOULIlquZCZ2aWtXF+ q2JSp9INrO3hkQqGXu/gQZE5p2ay3g2NJNpEj9aTYxe2RTgdSvqSu+Ix8 petvS6SZhjWzYwXdQnUKr97mQV7J3GaoRJeCsALOD2f4CyISNLtgQBHXB b3CVpYQEwab5v1Jyi6QraMG40REC7G8qajDi/U+vOkUqe4gutDxg8zRu9 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10750"; a="340414839" X-IronPort-AV: E=Sophos;i="6.01,152,1684825200"; d="scan'208";a="340414839" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2023 10:31:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10750"; a="665557857" X-IronPort-AV: E=Sophos;i="6.01,152,1684825200"; d="scan'208";a="665557857" Received: from rbanda1x-mobl1.amr.corp.intel.com (HELO dsneddon-desk.sneddon.lan) ([10.212.18.180]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2023 10:31:00 -0700 From: Daniel Sneddon To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)) Cc: pawan.kumar.gupta@linux.intel.com, Daniel Sneddon , "H. Peter Anvin" , linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)) Subject: [PATCH] x86/msr-index: Fix MSR_IA32_ARCH_CAPABILITIES bit ordering Date: Fri, 23 Jun 2023 10:30:29 -0700 Message-Id: <20230623173029.822153-1-daniel.sneddon@linux.intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When the definition of ARCH_CAP_XAPIC_DISABLE was added to MSR_IA32_ARCH_CAPABILITIES it was incorrectly placed at the bottom of the list instead of being inserted by bit order. This means ARCH_CAP_XAPIC_DISABLE and ARCH_CAP_PBRSB_NO are now swapped and any future additions may look out of place. Move ARCH_CAP_XAPIC_DISABLE to its correct position. No functional change. Signed-off-by: Daniel Sneddon --- arch/x86/include/asm/msr-index.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 3aedae61af4fc..76b154e9aebaa 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -151,15 +151,14 @@ * are restricted to targets in * kernel. */ -#define ARCH_CAP_PBRSB_NO BIT(24) /* - * Not susceptible to Post-Barrier - * Return Stack Buffer Predictions. - */ - #define ARCH_CAP_XAPIC_DISABLE BIT(21) /* * IA32_XAPIC_DISABLE_STATUS MSR * supported */ +#define ARCH_CAP_PBRSB_NO BIT(24) /* + * Not susceptible to Post-Barrier + * Return Stack Buffer Predictions. + */ =20 #define MSR_IA32_FLUSH_CMD 0x0000010b #define L1D_FLUSH BIT(0) /* --=20 2.25.1