From nobody Mon Feb 9 13:58:26 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9962EB64D8 for ; Thu, 22 Jun 2023 04:20:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230305AbjFVEUE (ORCPT ); Thu, 22 Jun 2023 00:20:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229608AbjFVET6 (ORCPT ); Thu, 22 Jun 2023 00:19:58 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA42B10CE; Wed, 21 Jun 2023 21:19:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687407596; x=1718943596; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UtwbdSn3PxBMhABoZLMkSt6Wfnm48v4gql/S1jq6XPg=; b=WFSKNX3PIbuGIYpNud4Pq7ujruS71JAs/eyB+UvOBByu4QIhb/Al0KPl Qgdt9uIrpxymD7gnjwdPf/doe3O47q/cwa+kinzr9rxj4KGjRiiqoC/PX 4gFOr1Gl6HiO8rd3TJxdEpEwef/4aPG44QWrJ0gpc6kA1eEmMSs+WNXQv 4eGh97zMbVK9hqTteXolHUB8hSRzMVafSh+mOouGO1l6dMjq1uZDe6HcS 0/m0sNHgiGi5TLKo2cgepX/Qnd7AL3Z5mFRDmDvC+uo2Js+oQ3YifpWQj aOwh1A1cDTtuKIUGwersWeWN6hTidwE3itfdXSrRAWIOQGAQCkJ/rLbny w==; X-IronPort-AV: E=McAfee;i="6600,9927,10748"; a="363811776" X-IronPort-AV: E=Sophos;i="6.00,262,1681196400"; d="scan'208";a="363811776" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jun 2023 21:19:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10748"; a="744453742" X-IronPort-AV: E=Sophos;i="6.00,262,1681196400"; d="scan'208";a="744453742" Received: from yongliang-ubuntu20-ilbpg12.png.intel.com ([10.88.229.33]) by orsmga008.jf.intel.com with ESMTP; 21 Jun 2023 21:19:44 -0700 From: Choong Yong Liang To: Rajneesh Bhardwaj , David E Box , Hans de Goede , Mark Gross , Jose Abreu , Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?UTF-8?q?Marek=20Beh=C3=BAn?= , Jean Delvare , Guenter Roeck , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Philipp Zabel , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , Wong Vee Khee , Jon Hunter , Jesse Brandeburg , Revanth Kumar Uppala , Shenwei Wang , Andrey Konovalov , Jochen Henneberg Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, platform-driver-x86@vger.kernel.org, linux-hwmon@vger.kernel.org, bpf@vger.kernel.org, Voon Wei Feng , Tan@vger.kernel.org, Tee Min , Michael Sit Wei Hong , Lai Peter Jun Ann Subject: [PATCH net-next 1/6] platform/x86: intel_pmc_core: Add IPC mailbox accessor function and add SoC register access Date: Thu, 22 Jun 2023 12:19:00 +0800 Message-Id: <20230622041905.629430-2-yong.liang.choong@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230622041905.629430-1-yong.liang.choong@linux.intel.com> References: <20230622041905.629430-1-yong.liang.choong@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "David E. Box" - Exports intel_pmc_core_ipc() for host access to the PMC IPC mailbox - Add support to use IPC command allows host to access SoC registers through PMC firmware that are otherwise inaccessible to the host due to security policies. Signed-off-by: David E. Box Signed-off-by: Chao Qin Signed-off-by: Choong Yong Liang --- MAINTAINERS | 1 + drivers/platform/x86/intel/pmc/adl.c | 2 +- drivers/platform/x86/intel/pmc/cnp.c | 2 +- drivers/platform/x86/intel/pmc/core.c | 63 ++++++++++++++++++- drivers/platform/x86/intel/pmc/icl.c | 2 +- drivers/platform/x86/intel/pmc/mtl.c | 2 +- drivers/platform/x86/intel/pmc/spt.c | 2 +- drivers/platform/x86/intel/pmc/tgl.c | 2 +- .../core.h =3D> include/linux/intel_pmc_core.h | 27 +++++++- 9 files changed, 95 insertions(+), 8 deletions(-) rename drivers/platform/x86/intel/pmc/core.h =3D> include/linux/intel_pmc_= core.h (95%) diff --git a/MAINTAINERS b/MAINTAINERS index cb14589d14ab..bdb08a79a5f8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10581,6 +10581,7 @@ L: platform-driver-x86@vger.kernel.org S: Maintained F: Documentation/ABI/testing/sysfs-platform-intel-pmc F: drivers/platform/x86/intel/pmc/ +F: include/linux/intel_pmc_core* =20 INTEL PMIC GPIO DRIVERS M: Andy Shevchenko diff --git a/drivers/platform/x86/intel/pmc/adl.c b/drivers/platform/x86/in= tel/pmc/adl.c index 5cbd40979f2a..b6a376c536c0 100644 --- a/drivers/platform/x86/intel/pmc/adl.c +++ b/drivers/platform/x86/intel/pmc/adl.c @@ -8,7 +8,7 @@ * */ =20 -#include "core.h" +#include =20 /* Alder Lake: PGD PFET Enable Ack Status Register(s) bitmap */ const struct pmc_bit_map adl_pfear_map[] =3D { diff --git a/drivers/platform/x86/intel/pmc/cnp.c b/drivers/platform/x86/in= tel/pmc/cnp.c index 7fb38815c4eb..504034cc5ec3 100644 --- a/drivers/platform/x86/intel/pmc/cnp.c +++ b/drivers/platform/x86/intel/pmc/cnp.c @@ -8,7 +8,7 @@ * */ =20 -#include "core.h" +#include =20 /* Cannon Lake: PGD PFET Enable Ack Status Register(s) bitmap */ const struct pmc_bit_map cnp_pfear_map[] =3D { diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/i= ntel/pmc/core.c index da6e7206d38b..0d60763c5144 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -26,7 +27,9 @@ #include #include =20 -#include "core.h" +#define PMC_IPCS_PARAM_COUNT 7 + +static const struct x86_cpu_id *pmc_cpu_id; =20 /* Maximum number of modes supported by platfoms that has low power mode c= apability */ const char *pmc_lpm_modes[] =3D { @@ -53,6 +56,63 @@ const struct pmc_bit_map msr_map[] =3D { {} }; =20 +int intel_pmc_core_ipc(struct pmc_ipc_cmd *ipc_cmd, u32 *rbuf) +{ + struct acpi_buffer buffer =3D { ACPI_ALLOCATE_BUFFER, NULL }; + union acpi_object params[PMC_IPCS_PARAM_COUNT] =3D { + {.type =3D ACPI_TYPE_INTEGER,}, + {.type =3D ACPI_TYPE_INTEGER,}, + {.type =3D ACPI_TYPE_INTEGER,}, + {.type =3D ACPI_TYPE_INTEGER,}, + {.type =3D ACPI_TYPE_INTEGER,}, + {.type =3D ACPI_TYPE_INTEGER,}, + {.type =3D ACPI_TYPE_INTEGER,}, + }; + struct acpi_object_list arg_list =3D { PMC_IPCS_PARAM_COUNT, params }; + union acpi_object *obj; + int status; + + if (!pmc_cpu_id || !ipc_cmd || !rbuf) + return -EINVAL; + + /* + * 0: IPC Command + * 1: IPC Sub Command + * 2: Size + * 3-6: Write Buffer for offset + */ + params[0].integer.value =3D ipc_cmd->cmd; + params[1].integer.value =3D ipc_cmd->sub_cmd; + params[2].integer.value =3D ipc_cmd->size; + params[3].integer.value =3D ipc_cmd->wbuf[0]; + params[4].integer.value =3D ipc_cmd->wbuf[1]; + params[5].integer.value =3D ipc_cmd->wbuf[2]; + params[6].integer.value =3D ipc_cmd->wbuf[3]; + + status =3D acpi_evaluate_object(NULL, "\\IPCS", &arg_list, &buffer); + if (ACPI_FAILURE(status)) + return -ENODEV; + + obj =3D buffer.pointer; + /* Check if the number of elements in package is 5 */ + if (obj && obj->type =3D=3D ACPI_TYPE_PACKAGE && obj->package.count =3D= =3D 5) { + const union acpi_object *objs =3D obj->package.elements; + + if ((u8)objs[0].integer.value !=3D 0) + return -EINVAL; + + rbuf[0] =3D objs[1].integer.value; + rbuf[1] =3D objs[2].integer.value; + rbuf[2] =3D objs[3].integer.value; + rbuf[3] =3D objs[4].integer.value; + } else { + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL(intel_pmc_core_ipc); + static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset) { return readl(pmcdev->regbase + reg_offset); @@ -1130,6 +1190,7 @@ static int pmc_core_probe(struct platform_device *pde= v) mutex_init(&pmcdev->lock); core_init(pmcdev); =20 + pmc_cpu_id =3D cpu_id; =20 if (lpit_read_residency_count_address(&slp_s0_addr)) { pmcdev->base_addr =3D PMC_BASE_ADDR_DEFAULT; diff --git a/drivers/platform/x86/intel/pmc/icl.c b/drivers/platform/x86/in= tel/pmc/icl.c index 2f11b1a6daeb..f18048ff9382 100644 --- a/drivers/platform/x86/intel/pmc/icl.c +++ b/drivers/platform/x86/intel/pmc/icl.c @@ -8,7 +8,7 @@ * */ =20 -#include "core.h" +#include =20 const struct pmc_bit_map icl_pfear_map[] =3D { {"RES_65", BIT(0)}, diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/in= tel/pmc/mtl.c index e8cc156412ce..7897f5fe9881 100644 --- a/drivers/platform/x86/intel/pmc/mtl.c +++ b/drivers/platform/x86/intel/pmc/mtl.c @@ -9,7 +9,7 @@ */ =20 #include -#include "core.h" +#include =20 const struct pmc_reg_map mtl_reg_map =3D { .pfear_sts =3D ext_tgl_pfear_map, diff --git a/drivers/platform/x86/intel/pmc/spt.c b/drivers/platform/x86/in= tel/pmc/spt.c index e16982236778..95ce490cf5d6 100644 --- a/drivers/platform/x86/intel/pmc/spt.c +++ b/drivers/platform/x86/intel/pmc/spt.c @@ -8,7 +8,7 @@ * */ =20 -#include "core.h" +#include =20 const struct pmc_bit_map spt_pll_map[] =3D { {"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0}, diff --git a/drivers/platform/x86/intel/pmc/tgl.c b/drivers/platform/x86/in= tel/pmc/tgl.c index c245ada849d0..a1719d809497 100644 --- a/drivers/platform/x86/intel/pmc/tgl.c +++ b/drivers/platform/x86/intel/pmc/tgl.c @@ -8,7 +8,7 @@ * */ =20 -#include "core.h" +#include =20 #define ACPI_S0IX_DSM_UUID "57a6512e-3979-4e9d-9708-ff13b2508972" #define ACPI_GET_LOW_MODE_REGISTERS 1 diff --git a/drivers/platform/x86/intel/pmc/core.h b/include/linux/intel_pm= c_core.h similarity index 95% rename from drivers/platform/x86/intel/pmc/core.h rename to include/linux/intel_pmc_core.h index 9ca9b9746719..82810e8b92a2 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/include/linux/intel_pmc_core.h @@ -250,7 +250,16 @@ enum ppfear_regs { #define MTL_LPM_STATUS_OFFSET 0x1700 #define MTL_LPM_LIVE_STATUS_OFFSET 0x175C =20 -extern const char *pmc_lpm_modes[]; +#define IPC_SOC_REGISTER_ACCESS 0xAA +#define IPC_SOC_SUB_CMD_READ 0x00 +#define IPC_SOC_SUB_CMD_WRITE 0x01 + +struct pmc_ipc_cmd { + u32 cmd; + u32 sub_cmd; + u32 size; + u32 wbuf[4]; +}; =20 struct pmc_bit_map { const char *name; @@ -427,4 +436,20 @@ static const struct file_operations __name ## _fops = =3D { \ .release =3D single_release, \ } =20 +#if IS_ENABLED(CONFIG_INTEL_PMC_CORE) +/** + * intel_pmc_core_ipc() - PMC IPC Mailbox accessor + * @ipc_cmd: struct pmc_ipc_cmd prepared with input to send + * @rbuf: Allocated u32[4] array for returned IPC data + * + * Return: 0 on success. Non-zero on mailbox error + */ +int intel_pmc_core_ipc(struct pmc_ipc_cmd *ipc_cmd, u32 *rbuf); +#else +static inline int intel_pmc_core_ipc(struct pmc_ipc_cmd *ipc_cmd, u32 *rbu= f) +{ + return -ENODEV; +} +#endif /* CONFIG_INTEL_PMC_CORE */ + #endif /* PMC_CORE_H */ --=20 2.25.1