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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000042A8.mail.protection.outlook.com (10.167.243.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6521.17 via Frontend Transport; Thu, 22 Jun 2023 03:53:38 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 21 Jun 2023 22:53:36 -0500 From: Terry Bowman To: , , , , , , , CC: , , , Subject: [PATCH v6 07/27] cxl/core/regs: Add @dev to cxl_register_map Date: Wed, 21 Jun 2023 22:51:06 -0500 Message-ID: <20230622035126.4130151-8-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230622035126.4130151-1-terry.bowman@amd.com> References: <20230622035126.4130151-1-terry.bowman@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A8:EE_|DM4PR12MB6160:EE_ X-MS-Office365-Filtering-Correlation-Id: d45ebc84-c78b-49ee-c877-08db72d442c8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jun 2023 03:53:38.0426 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d45ebc84-c78b-49ee-c877-08db72d442c8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6160 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Robert Richter The corresponding device of a register mapping is used for devm operations and logging. For operations with struct cxl_register_map the device needs to be kept track separately. To simpify the involved function interfaces, add @dev to cxl_register_map. While at it also reorder function arguments of cxl_map_device_regs() and cxl_map_component_regs() to have the object @cxl_register_map first. In a result a bunch of functions are available to be used with a @cxl_register_map object. This patch is in preparation of reworking the component register setup code. Signed-off-by: Robert Richter Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron --- drivers/cxl/core/hdm.c | 4 ++-- drivers/cxl/core/regs.c | 18 ++++++++++++------ drivers/cxl/cxl.h | 10 ++++++---- drivers/cxl/pci.c | 23 +++++++++++------------ 4 files changed, 31 insertions(+), 24 deletions(-) diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 7889ff203a34..5abfa9276dac 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -85,6 +85,7 @@ static int map_hdm_decoder_regs(struct cxl_port *port, vo= id __iomem *crb, struct cxl_component_regs *regs) { struct cxl_register_map map =3D { + .dev =3D &port->dev, .resource =3D port->component_reg_phys, .base =3D crb, .max_size =3D CXL_COMPONENT_REG_BLOCK_SIZE, @@ -97,8 +98,7 @@ static int map_hdm_decoder_regs(struct cxl_port *port, vo= id __iomem *crb, return -ENODEV; } =20 - return cxl_map_component_regs(&port->dev, regs, &map, - BIT(CXL_CM_CAP_CAP_ID_HDM)); + return cxl_map_component_regs(&map, regs, BIT(CXL_CM_CAP_CAP_ID_HDM)); } =20 static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info) diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 6c4b33133918..713e4a9ca35a 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -199,9 +199,11 @@ void __iomem *devm_cxl_iomap_block(struct device *dev,= resource_size_t addr, return ret_val; } =20 -int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *= regs, - struct cxl_register_map *map, unsigned long map_mask) +int cxl_map_component_regs(struct cxl_register_map *map, + struct cxl_component_regs *regs, + unsigned long map_mask) { + struct device *dev =3D map->dev; struct mapinfo { struct cxl_reg_map *rmap; void __iomem **addr; @@ -231,10 +233,10 @@ int cxl_map_component_regs(struct device *dev, struct= cxl_component_regs *regs, } EXPORT_SYMBOL_NS_GPL(cxl_map_component_regs, CXL); =20 -int cxl_map_device_regs(struct device *dev, - struct cxl_device_regs *regs, - struct cxl_register_map *map) +int cxl_map_device_regs(struct cxl_register_map *map, + struct cxl_device_regs *regs) { + struct device *dev =3D map->dev; resource_size_t phys_addr =3D map->resource; struct mapinfo { struct cxl_reg_map *rmap; @@ -302,7 +304,11 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_r= egloc_type type, u32 regloc_size, regblocks; int regloc, i; =20 - map->resource =3D CXL_RESOURCE_NONE; + *map =3D (struct cxl_register_map) { + .dev =3D &pdev->dev, + .resource =3D CXL_RESOURCE_NONE, + }; + regloc =3D pci_find_dvsec_capability(pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_REG_LOCATOR); if (!regloc) diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 754cfe59ae37..bd68d5fabf21 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -231,6 +231,7 @@ struct cxl_device_reg_map { =20 /** * struct cxl_register_map - DVSEC harvested register block mapping parame= ters + * @dev: device for devm operations and logging * @base: virtual base of the register-block-BAR + @block_offset * @resource: physical resource base of the register block * @max_size: maximum mapping size to perform register search @@ -239,6 +240,7 @@ struct cxl_device_reg_map { * @device_map: cxl_reg_maps for device registers */ struct cxl_register_map { + struct device *dev; void __iomem *base; resource_size_t resource; resource_size_t max_size; @@ -253,11 +255,11 @@ void cxl_probe_component_regs(struct device *dev, voi= d __iomem *base, struct cxl_component_reg_map *map); void cxl_probe_device_regs(struct device *dev, void __iomem *base, struct cxl_device_reg_map *map); -int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *= regs, - struct cxl_register_map *map, +int cxl_map_component_regs(struct cxl_register_map *map, + struct cxl_component_regs *regs, unsigned long map_mask); -int cxl_map_device_regs(struct device *dev, struct cxl_device_regs *regs, - struct cxl_register_map *map); +int cxl_map_device_regs(struct cxl_register_map *map, + struct cxl_device_regs *regs); =20 enum cxl_regloc_type; int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 0872f2233ed0..0a89b96e6a8d 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -274,9 +274,9 @@ static int cxl_pci_setup_mailbox(struct cxl_dev_state *= cxlds) return 0; } =20 -static int cxl_map_regblock(struct pci_dev *pdev, struct cxl_register_map = *map) +static int cxl_map_regblock(struct cxl_register_map *map) { - struct device *dev =3D &pdev->dev; + struct device *dev =3D map->dev; =20 map->base =3D ioremap(map->resource, map->max_size); if (!map->base) { @@ -288,18 +288,17 @@ static int cxl_map_regblock(struct pci_dev *pdev, str= uct cxl_register_map *map) return 0; } =20 -static void cxl_unmap_regblock(struct pci_dev *pdev, - struct cxl_register_map *map) +static void cxl_unmap_regblock(struct cxl_register_map *map) { iounmap(map->base); map->base =3D NULL; } =20 -static int cxl_probe_regs(struct pci_dev *pdev, struct cxl_register_map *m= ap) +static int cxl_probe_regs(struct cxl_register_map *map) { struct cxl_component_reg_map *comp_map; struct cxl_device_reg_map *dev_map; - struct device *dev =3D &pdev->dev; + struct device *dev =3D map->dev; void __iomem *base =3D map->base; =20 switch (map->reg_type) { @@ -346,12 +345,12 @@ static int cxl_setup_regs(struct pci_dev *pdev, enum = cxl_regloc_type type, if (rc) return rc; =20 - rc =3D cxl_map_regblock(pdev, map); + rc =3D cxl_map_regblock(map); if (rc) return rc; =20 - rc =3D cxl_probe_regs(pdev, map); - cxl_unmap_regblock(pdev, map); + rc =3D cxl_probe_regs(map); + cxl_unmap_regblock(map); =20 return rc; } @@ -688,7 +687,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const st= ruct pci_device_id *id) if (rc) return rc; =20 - rc =3D cxl_map_device_regs(&pdev->dev, &cxlds->regs.device_regs, &map); + rc =3D cxl_map_device_regs(&map, &cxlds->regs.device_regs); if (rc) return rc; =20 @@ -703,8 +702,8 @@ static int cxl_pci_probe(struct pci_dev *pdev, const st= ruct pci_device_id *id) =20 cxlds->component_reg_phys =3D map.resource; =20 - rc =3D cxl_map_component_regs(&pdev->dev, &cxlds->regs.component, - &map, BIT(CXL_CM_CAP_CAP_ID_RAS)); + rc =3D cxl_map_component_regs(&map, &cxlds->regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS)); if (rc) dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); =20 --=20 2.34.1