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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9CD.mail.protection.outlook.com (10.167.241.140) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6521.24 via Frontend Transport; Wed, 21 Jun 2023 23:55:44 +0000 Received: from ruby-95f9host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 21 Jun 2023 18:55:42 -0500 From: Suravee Suthikulpanit To: , , CC: , , , , , , , , , , , , , , , "Suravee Suthikulpanit" Subject: [RFC PATCH 01/21] iommu/amd: Declare helper functions as extern Date: Wed, 21 Jun 2023 18:54:48 -0500 Message-ID: <20230621235508.113949-2-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> References: <20230621235508.113949-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CD:EE_|IA1PR12MB7568:EE_ X-MS-Office365-Filtering-Correlation-Id: 3efdd915-31d2-4947-eabf-08db72b306ff X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 23:55:44.4267 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3efdd915-31d2-4947-eabf-08db72b306ff X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7568 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To allow reuse from other files. There is no functional change. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 18 ++++++++++++++++++ drivers/iommu/amd/init.c | 6 +++--- drivers/iommu/amd/io_pgtable.c | 18 +++++++++--------- drivers/iommu/amd/iommu.c | 14 +++++++------- 4 files changed, 37 insertions(+), 19 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index e98f20a9bdd8..827d065bbe8e 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -11,6 +11,24 @@ =20 #include "amd_iommu_types.h" =20 +extern void iommu_feature_enable(struct amd_iommu *iommu, u8 bit); +extern void iommu_feature_disable(struct amd_iommu *iommu, u8 bit); +extern u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end); +extern void set_dte_entry(struct amd_iommu *iommu, u16 devid, + struct protection_domain *domain, + bool ats, bool ppr); +extern int iommu_flush_dte(struct amd_iommu *iommu, u16 devid); +extern struct protection_domain *to_pdomain(struct iommu_domain *dom); +extern struct iommu_domain *amd_iommu_domain_alloc(unsigned int type); +extern void amd_iommu_domain_free(struct iommu_domain *dom); +extern int amd_iommu_v1_map_pages(struct io_pgtable_ops *ops, unsigned lon= g iova, + phys_addr_t paddr, size_t pgsize, size_t pgcount, + int prot, gfp_t gfp, size_t *mapped); +extern unsigned long amd_iommu_v1_unmap_pages(struct io_pgtable_ops *ops, + unsigned long iova, + size_t pgsize, size_t pgcount, + struct iommu_iotlb_gather *gather); + extern irqreturn_t amd_iommu_int_thread(int irq, void *data); extern irqreturn_t amd_iommu_int_handler(int irq, void *data); extern void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid); diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 329a406cc37d..886cf55e75e2 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -432,7 +432,7 @@ static void iommu_set_device_table(struct amd_iommu *io= mmu) } =20 /* Generic functions to enable/disable certain features of the IOMMU. */ -static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) +void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) { u64 ctrl; =20 @@ -441,7 +441,7 @@ static void iommu_feature_enable(struct amd_iommu *iomm= u, u8 bit) writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); } =20 -static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) +void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) { u64 ctrl; =20 @@ -490,7 +490,7 @@ static void iommu_disable(struct amd_iommu *iommu) * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMM= U in * the system has one. */ -static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end) +u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end) { if (!request_mem_region(address, end, "amd_iommu")) { pr_err("Can not reserve memory region %llx-%llx for mmio\n", diff --git a/drivers/iommu/amd/io_pgtable.c b/drivers/iommu/amd/io_pgtable.c index 1b67116882be..9b398673208d 100644 --- a/drivers/iommu/amd/io_pgtable.c +++ b/drivers/iommu/amd/io_pgtable.c @@ -360,9 +360,9 @@ static void free_clear_pte(u64 *pte, u64 pteval, struct= list_head *freelist) * supporting all features of AMD IOMMU page tables like level skipping * and full 64 bit address spaces. */ -static int iommu_v1_map_pages(struct io_pgtable_ops *ops, unsigned long io= va, - phys_addr_t paddr, size_t pgsize, size_t pgcount, - int prot, gfp_t gfp, size_t *mapped) +int amd_iommu_v1_map_pages(struct io_pgtable_ops *ops, unsigned long iova, + phys_addr_t paddr, size_t pgsize, size_t pgcount, + int prot, gfp_t gfp, size_t *mapped) { struct protection_domain *dom =3D io_pgtable_ops_to_domain(ops); LIST_HEAD(freelist); @@ -435,10 +435,10 @@ static int iommu_v1_map_pages(struct io_pgtable_ops *= ops, unsigned long iova, return ret; } =20 -static unsigned long iommu_v1_unmap_pages(struct io_pgtable_ops *ops, - unsigned long iova, - size_t pgsize, size_t pgcount, - struct iommu_iotlb_gather *gather) +unsigned long amd_iommu_v1_unmap_pages(struct io_pgtable_ops *ops, + unsigned long iova, + size_t pgsize, size_t pgcount, + struct iommu_iotlb_gather *gather) { struct amd_io_pgtable *pgtable =3D io_pgtable_ops_to_data(ops); unsigned long long unmapped; @@ -524,8 +524,8 @@ static struct io_pgtable *v1_alloc_pgtable(struct io_pg= table_cfg *cfg, void *coo cfg->oas =3D IOMMU_OUT_ADDR_BIT_SIZE, cfg->tlb =3D &v1_flush_ops; =20 - pgtable->iop.ops.map_pages =3D iommu_v1_map_pages; - pgtable->iop.ops.unmap_pages =3D iommu_v1_unmap_pages; + pgtable->iop.ops.map_pages =3D amd_iommu_v1_map_pages; + pgtable->iop.ops.unmap_pages =3D amd_iommu_v1_unmap_pages; pgtable->iop.ops.iova_to_phys =3D iommu_v1_iova_to_phys; =20 return &pgtable->iop; diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 4a314647d1f7..bbd10698851f 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -177,7 +177,7 @@ static struct amd_iommu *rlookup_amd_iommu(struct devic= e *dev) return __rlookup_amd_iommu(seg, PCI_SBDF_TO_DEVID(devid)); } =20 -static struct protection_domain *to_pdomain(struct iommu_domain *dom) +struct protection_domain *to_pdomain(struct iommu_domain *dom) { return container_of(dom, struct protection_domain, domain); } @@ -450,7 +450,7 @@ static void amd_iommu_uninit_device(struct device *dev) * *************************************************************************= ***/ =20 -static void dump_dte_entry(struct amd_iommu *iommu, u16 devid) +void dump_dte_entry(struct amd_iommu *iommu, u16 devid) { int i; struct dev_table_entry *dev_table =3D get_dev_table(iommu); @@ -1192,7 +1192,7 @@ static int iommu_completion_wait(struct amd_iommu *io= mmu) return ret; } =20 -static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) +int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) { struct iommu_cmd cmd; =20 @@ -1553,8 +1553,8 @@ static void free_gcr3_table(struct protection_domain = *domain) free_page((unsigned long)domain->gcr3_tbl); } =20 -static void set_dte_entry(struct amd_iommu *iommu, u16 devid, - struct protection_domain *domain, bool ats, bool ppr) +void set_dte_entry(struct amd_iommu *iommu, u16 devid, + struct protection_domain *domain, bool ats, bool ppr) { u64 pte_root =3D 0; u64 flags =3D 0; @@ -2118,7 +2118,7 @@ static struct protection_domain *protection_domain_al= loc(unsigned int type) return NULL; } =20 -static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) +struct iommu_domain *amd_iommu_domain_alloc(unsigned int type) { struct protection_domain *domain; =20 @@ -2140,7 +2140,7 @@ static struct iommu_domain *amd_iommu_domain_alloc(un= signed type) return &domain->domain; } =20 -static void amd_iommu_domain_free(struct iommu_domain *dom) +void amd_iommu_domain_free(struct iommu_domain *dom) { struct protection_domain *domain; =20 --=20 2.34.1